JPS62183161A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To contrive both reduction in erasing time and stabilization of operation of the semiconductor integrated circuit device having a nonvolatile memory function by a method wherein the second well region is provided in the first well region formed on a semiconductor substrate, and a semiconductor element is provided in the second well region. CONSTITUTION:The n-type well region 3 in a resin A is provided in an n-type well region 2. This well region 2 is formed deeper and wider than the well region 3. The circumferential part of the region 3 in the region 2 reaches the surface of the semiconductor substrate 1, and the Al conductive layer 33 is passed through a connection hole 34 and connected to the surface of an n<+> type semiconductor region 41 on the surface of the region 2 of the substrate 1. As for the conductive layer 33, when the power source potential Vcc is applied to the region 2, an inverted bias is generated between the regions 2 and 3, the electrons injected into the region 3 from an n-channel MISFET (metal insulation semiconductor field effect transistor) are flowed into the region 2, and the electrons are adsorbed by the power source potential Vcc from the region 2. Also, as the hole (positive hole) injected into the substrate 1 from a p-channel MISFET through the region 2 can not pass the barrier located between the substrate 1 and the region 2, no current runs between the p-channel MISFET of the substrate 1 and the p-channel MISFET.

Description

[Detailed description of the invention]

[Industrial Application Field] The present invention relates to a semiconductor integrated circuit device, and particularly to a technique that is effective when applied to a semiconductor integrated circuit device having a nonvolatile memory function. [Prior art] EEPROM (Electrical
ly Erasable and Progra
The memory cells of the ROM (mmable ROM) are provided in the well region. This is because information is erased by applying a circuit ground potential VsS, for example Ov, to the gate electrode and applying a high potential VPP, for example 15V, to the well region. The technology related to EEPROM is described, for example, in Nikkei Electronics J, June 4, 19B4 issue, published by Nikkei McGraw-Hill, p.197-p.
208. [Problems to be solved by the invention] When applying a high potential to the well region, it is necessary to apply a potential equal to or higher than the potential VPP to the substrate to maintain a reverse bias state between the well region and the substrate. It is. The inventor of the present invention investigated erasing information from memory cells and found that erasing information takes a long time. When erasing information, the entire substrate is brought to a potential higher than the program potential VPP. However, since the volume of the board is large,
This is because it takes a long time to boost the substrate potential. Also, by applying a potential higher than the potential VPP to the substrate, the MISFET provided on the substrate due to the substrate effect
There is a problem in that the threshold value fluctuates greatly and peripheral circuits tend to malfunction. An object of the present invention is to provide a technique for improving the electrical characteristics of a semiconductor integrated circuit device. Another object of the present invention is to shorten the erasing time of a semiconductor integrated circuit device having a nonvolatile memory function. Another object of the present invention is to stabilize and facilitate the operation of a semiconductor integrated circuit device having a nonvolatile memory function. The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings. [Means for Solving the Problems] A brief overview of one typical invention disclosed in this application is as follows. That is, a first well region is provided in the semiconductor substrate. A second well region is provided within this first well region, and a semiconductor element is provided within this second well region. [Function] According to the above-described means, by providing the first well region, the potential of the substrate can be set regardless of the potential of the second well region where the semiconductor element is provided, so that the above-described object can be achieved. The configuration of the present invention will be explained below along with examples. [Example 2] Example I is an example in which the present invention is applied to an EEFROM memory cell. 1A and 1B are diagrams for explaining the general operation of a memory cell made possible by the present invention.
Figure A shows the selection operation during a byte write operation, and Figure 1B shows the selection operation during a byte erase operation. In addition, in FIG. 1A and FIG. 1B, the memory cell M
One byte of the same cell is prepared for each of 4, and these cells perform a write or erase operation all at once. In FIG. 1A and FIG. 1B, M t ”−M + is a memory cell, and the selection MISFETQs and MNOS
(Met a l 1tride Oxid
a Sem1 conductor) type MISFET
The 0 selection word line WLs connected to the gate electrode of the 1 selection MISFET Qs is the selection word line WLs connected in series with the selection MISFETQs. selected by the decoder. A high level (power supply potential Vcc, for example 5V) or a low level (circuit ground potential Vss, for example Ov) is applied to the word line WLs by an X decoder. The selected word line WLg is connected to the gate electrode of the MNOS, with a high voltage word line WL extending in parallel with the first selected word line WLs extending in the lateral (X) direction in FIG. . The high voltage word line WL is selected by an X decoder (or high voltage decoder) not shown. The word line WL, 4 is provided with a program potential VPP by an X decoder.
For example, 15V or the circuit ground potential V gs is applied. The data IIADL extends in a direction intersecting the selected word aWLs and the high voltage word line WL, 4, that is, in the vertical (Y) direction in the first Wi. The data line DL is
It is connected to the source region of the selection MISFETQs of each memory cell. Data line DL is selected by a Y decoder (not shown). The data line DL is controlled by the Y decoder.
A potential Vss is applied or a floating state is applied. A write block line or source line PL is connected to the source region of MNO5Q. Write block line PL extends parallel to data line DL, that is, in the Y direction in FIG. , write block line PL are selected by a Y decoder (or write block circuit) not shown. The write block line PL has a Y decoder number; therefore, the potential V
ss or VPP is supplied. Each selected word line W
Memory cells are provided in respective areas corresponding to L s , high voltage words II & WLM, data line DL, and write block line PL, and a plurality of memory cells are arranged in the X and Y directions to form a memory cell array. P-Well is a p-type well region, and a memory cell is provided within this p-type well region P-Welf. When the memory cell array is divided into multiple mats, the p-type well region P-Well may be provided for each mat. You can make it larger. The p-type well region P-Well is an n-type well region N-Welf.
It is provided inside. When the P-type well region P-Well is provided separately for each mat, the n-type well region N-Well is divided for each mat corresponding to the P-type well region P-Well region. Alternatively, it may be made large enough to accommodate all the p-type well regions P-Well. Next, the electrical operation of the memory cell will be explained. FIG. 1A shows a case where information is written to a memory cell M in writing information. A selected word line WLs connected to a memory cell M into which information is to be written is selected by an X decoder (not shown), and a power supply potential Vc is applied to the selected word line WLs.
c, for example, 5V (high level) is applied to the selected word line WLs other than the selected word line WLs connected to the selected memory cell M1, the ground potential of one circuit Vss,
For example, it is set to Ov (low level). A program potential VPP, for example 15V, is applied to the high voltage word line WL connected to the gate electrode of MNO8Q of the selected memory cell M1. The other high voltage word lines WL are set to the ground potential VsS of one circuit. The data line DL connected to the selected memory cell MI is at the ground potential V of the circuit.
ss, for example Ov (low level). The other data lines DL are left open (floating). At this time, the actual potential is set to about 3V by, for example, a precharge operation of the data line in advance (the same applies to the open state described below). The ground potential Vss of the circuit is applied to the write blocking line PL connected to the selected memory cell M1, and is used as a source line. Program potential VPP, for example 15V, is applied to the other write block lines PL. In writing, all the P-type well regions P-Well in which memory cells are provided are set to the circuit ground potential Vss+eg, λ, Ov. Further, all the n-type well regions N-Well are set to the circuit ground potential Vss, for example, Ov. When the above circuit conditions are set, one selected memory cell M
Minority carriers (i!
child) is injected and information is written. Since high voltage VPP is not applied to memory cell M2 at all, no writing is performed. A high voltage VPP is applied to the memory cell M3 from a write blocking line PL in order to prevent writing. This substantially reduces the potential difference between the gate electrode and the channel region and no writing is performed. In memory cell M4, since the potential of the drain or channel region is higher than the potential of the gate electrode, writing does not occur (it does not enter the erased state either). In the write operation, since the P-type well region P-Welf is set to the ground potential Vss, the potential of the p--type substrate l can also be held at the ground potential. Furthermore, since the n-wall region NWell to which a fixed potential (for example, ground potential) is applied is provided between these, even if the potential of the p-type well region P-Well changes, the substrate l
The potential of does not change. Therefore, the peripheral circuits of the memory cell array can operate reliably. Next, the information erasing operation will be explained. In FIG. 1B, information is erased from memory cell M! This shows the case where this is done. A selected word wAW Ls connected to a memory cell M whose information is to be erased is selected by an X decoder (not shown), and a power supply potential Vcc, for example 5V, is applied to the selected word line WLs. The other selected word lines WLs are at the circuit ground potential Vs.
Make it s. The high voltage word line WL connected to MNO3Q of the selected memory cell MI is connected to the circuit ground potential ■
ss, for example Ov. Other high voltage word lines WL
, 4 apply a program potential VPP, for example 15V. In erasing information, all write block lines PL are set to the program potential VPP. In addition, all data lines DL are in an open state (Floa
ting). A program potential VPP, for example 15V, is applied to the p-type well region P-Wall in which the selected memory cell MI is provided. Other p-type well regions P-W
ell is set to the circuit ground potential Vss, for example Ov. The n-type well region N-Well in which the selected memory cell MI is provided is at a potential Vpp+α (for example, 16
V), that is, the potential is higher than the program potential VPP. It is designed to satisfy the reverse bias condition between the P-type well region P-Well and the P-well region P-Well. p-type well region P-Well other than p-type well region P-W e11 in which selected memory cell MI is provided and this p-type well region P-W
The n-type well area N-Wall that includes the ELL is 1
The ground potential of the circuit is set to VsS. When such circuit conditions are set, carriers in the gate insulating film of only the memory cell M1 whose information is to be erased are released, and the information is erased. Memory cell M2
And M3 is not erased because there is no potential difference between the gate electrode and the channel region. Memory cell M4 is in the same state as memory cell M3 in FIG. 1A and is not erased (or written to). As mentioned above, in the erase operation, the n- and p-type well regions N-Welf and P- on the unselected memory cell side are
The potentials of both wells are set to ground potential. Therefore, the potential of the substrate 1 is not affected, while the n- and p-type well regions N-
Well and P-Well (7) potentials are Hu'z, VP
P ten (! and Vpp. Set α to an appropriate value (0,7V
above), the area N-Well and P
-Wall can be reverse biased. Also,
Since the n-type region N-Well is provided, the potential of the substrate 1 can be maintained at the ground potential Vss, and the potential of the substrate 1 can be maintained at the ground potential Vss.
It can be stabilized without being affected by potential fluctuations in the well. Therefore, the peripheral circuits of the memory cell array can operate reliably. These well regions N-Well and P-Well
The potential is given by a bias voltage generation circuit and its control circuit (not shown). The bias voltage generation circuit is constituted by various known booster circuits, and has a power supply voltage Vcc.
A boosted voltage VPp or VPP+α is generated from the voltage VPp or VPP+α. Voltage VPP for the word line and write block line is also generated thereby. Only during erasing, the control circuit (erase circuit) generates voltage VPP+α, and
A voltage VP is applied to the type well regions N-Wall and P-Well.
P and VPP+α are applied respectively. During erasing, the potential of the entire substrate 1 is set to a high potential VPP or VPP.
Rather than boosting to +α, the n-type and p-type well regions,
In particular, in the case of the byte erase shown in FIG. 1B, it is only necessary to boost the voltage of one n-type and p-type well region in which the memory cell (M, ) to be erased is formed. Therefore, the burden on the bias voltage generation circuit is reduced. One circuit can be miniaturized and power consumption can be reduced. In addition, the time required for boosting the voltage is short, and the erasing operation can be performed at high speed. The potentials of the word line, data line, write block line, and well may be set so as to cause this. Even in this case, J
! This is more advantageous than increasing the pressure of the entire sheet metal in the above points. Next, the specific configuration of the device will be explained. Figure 2 is a plan view of an EEPROM memory cell, and Figure 3 is a cross-sectional view of an EEPROM chip. Area A is a cross-sectional copy of peripheral circuits such as an address decoder, clock circuit, and sense amplifier, and area B is a memory cell. FIG. 3 is a schematic diagram of a cross section of a cell. Note that insulating films other than the field insulating film are not shown in FIG. 2 in order to make the configuration easier to see. In FIGS. 2 and 3, reference numeral 1 denotes a semiconductor substrate made of p-type single crystal silicon, and a field insulating film 6 made of a silicon oxide film is provided on the surface. In region A, field insulating film 6 defines an element region of a semiconductor element such as a MISFET. In region B, a pattern of memory cells is defined. A p-type channel stopper region 5 is provided under the field insulating film 6 on the surface of the semiconductor substrate 1 except for the n-type well region 2, which will be described later, and on the surface of the n-type well region 3. As shown in the area diagram of FIG. 3, a deep n-type well region 2 is provided in the memory cell array region of the semiconductor substrate 1. Note that the n-type well region 2 is not shown in FIG. 2 in order to make the configuration easier to see. An n-type well region 3 shallower than the n-type well region 2 is provided on the main surface of the n-type well region 2 . n-type well region 2
is formed deeper and wider than the n-type well region 3. That is, the P-type well region 3 is the same as the N-type well region 2.
The 6n type well region 2 and the n type well region 3 provided so as to be included in the 6n type well region 2 and the n type well region 3 are formed so as to encompass each mat or byte of the memory cell array, or even the entire memory cell array. Therefore, the n-type well region 2 is not provided over the entire main surface of the semiconductor substrate 1, but is at most the size of the memory cell array region. Therefore, the volume of the n-type well region 2 is smaller than that of the semiconductor substrate 1.
It is much smaller than that of . n-type well region 2
A part of the peripheral portion of the P-type well region 3 reaches the surface of the semiconductor substrate 1. A layer 19 connects a conductor made of a first aluminum layer to the surface of the n-type well region 2 reaching the surface of the semiconductor substrate l around the n-type well region 3 through a contact hole 20 . The conductive layer 19 applies a potential higher than the program potential VPP to the n-type well region 2 when erasing information. That is, the n-type well region 2 is
When erasing information, a reverse bias condition with respect to the n-type well region 3 is satisfied. In addition, the conductive layer 19 is
For purposes other than erasing information, a circuit ground potential Vss, for example O■, is applied to the n-type well region 2. n-type well region 2
An rl" type semiconductor region 26 is provided on the surface of the portion where the conductive layer 19 is connected. That is, the conductive layer 19 is
It is connected to the surface of the n' type semiconductor region 26. A conductive layer 17 made of a first aluminum layer is connected to a predetermined portion of the surface of the n-type well region 3 through a connection hole 1B. Through this conductive layer 17, a program potential VPP is applied to the n-type well region 3 when erasing information, and a circuit ground potential Vss is applied except when erasing information. On the surface of the part of the P-type well region 3 to which the conductive layer 17 is connected,
A p° type semiconductor region 25 is provided. That is, the conductive layer 17 is connected to the surface of the p' type semiconductor region 25. As described above, the n-type well region 2 is boosted to a potential higher than the program potential VPP when erasing information. However, the volume of the n-type well region 2 is extremely smaller than the volume of the semiconductor substrate 1. Therefore, n-type well region 2 is charged faster than when charging semiconductor substrate 1. That is, the r1 type well region 2 is quickly boosted to the program potential VPP when erasing information. Selection MISFET Q of memory cell M shown in FIG.
s is a gate made of a polycrystalline silicon layer, as shown in region B of FIGS. 2 and 3. It consists of an i-pole (11°), an rl' type semiconductor region (24°) which is a source and drain region, and a gate isolation R film (7) made of a silicon oxide film. The goo 1-electrode 11 is formed integrally with the selected word line W[, S, and extends over the gate insulating film 7 and the field insulating film 6. Above the field insulating film 6 is the selected word line WLs, and above the insulating films 1 to 7 is the gate electrode 11. An insulating film 36 made of a silicon oxide film covers the side and top surfaces of the gate 1 electrode 11 and the selected word line WLs. The n''' type semiconductor region 24 is provided on the surface of both sides of the gate electrode 11 of the p type well region 3.
The n4 type semiconductor region 24, which is the drain region of TQs, is
It is formed integrally with the drain region of the selected M I S F E T Q s adjacent to the same connection hole 16 of the data line 15 . The n″″ type semiconductor region 24, which is the source region of the selected MISFETQs, is an MNO
3Q1. It is formed integrally with the drain region of l. Note that the gate electrode 11 and the selected word line WLs are not limited to polycrystalline silicon films, but are made of, for example, Mo, WLs.
-Ta-T may be formed by a high melting point metal film or a silicide film of the high melting point metal. Alternatively, it may be a two-layer film in which the high-melting point metal film or silicide film is provided on a single-crystal silicon layer. MNO8Q1. of memory cell M shown in FIG. l is a first silicon oxide film made of an extremely thin silicon oxide film of about 20λ on a predetermined surface of the p-type well region 3, as shown in region B of FIGS. 2 and 3.
A gate insulating film (UTO) 8 , a second gate insulating film 9 made of a silicon nitride film deposited on the first gate insulating film 8 , and a second gate insulating film 9 deposited on the second gate insulating film 9 A gate voltage tfilo made of a polycrystalline silicon film is provided on both sides of the gate electrode 10 on the surface of the p-type well region 3.
The first gate insulating film 8 is provided only on the surface of the p-type well region 3 exposed from the field insulating film 6.The second gate insulating film 9 is , is provided not only on the first gate insulating film 8 but also on the field insulating film 6. The gate electrode 10 is formed integrally with the high voltage word line WL. That is, the field insulating film 6 Above is the high voltage word line WL, and above the surface of the P-type well region 3 excluding the field insulating film 6 is the gate electrode 10.The gate electrode 10 and the high voltage word line WL are connected to the gate electrode 11.
and extends parallel to the selected word line WLs. MN
O8Q. The 11' type μ conductor region 24, which is the drain region of the transistor, is formed integrally with the source region of the selected MISFETQs. Further, the n° type semiconductor region 24 which is the source region of MNO8QM is connected to the MNO8Q of another memory cell to which the same write block w&13 is connected through the same connection hole 14.
, and is formed integrally with the source region of . Note that the gate electrode 10 is not limited to a polycrystalline silicon layer, but may be a high dew point metal film such as Mo, W, Ta, or Ti or a silicide film thereof, or a high melting point metal film on a polycrystalline silicon layer. A layer or a silicide film thereof may be provided. A write block line 13 (PL) made of a first aluminum layer is connected to the surface of an 11'' type semiconductor region 24, which is a source region of MNO3Q, through a connection hole 14.The write block line 13 is selected. The write block line 13 intersects with and extends above the word line WLs and the high voltage word line WL.The side of the write block line 13 is parallel to the data line WLs and the high voltage word line WL. The data line 15 extends over the selected word line WLS and the high voltage word line WL, and also extends over the n-type semiconductor region 24 which is the source region of the selected MISFET Qs. It is connected to the surface through a connection hole 16.The data line 15, the write block line 13, and the selected word line W
Ls and the high voltage word RWL, 4 are insulated by an insulating film 35 made of, for example, phosphosilicate glass (PSG). Peripheral circuits such as the address decoder, sense amplifier, main amplifier, and clock circuit are complementary MIS consisting of an n-channel MI 5FET and a p-channel MISFET.
It is composed of FET. The p-channel MISFE
As shown in FIG. 3, T is formed in a shallow r1 type well region 4 provided on the main surface of the semiconductor substrate l. In the n-channel MISF, the impurity concentration of the n-type well region 4 is 111;
The ET is formed on the main surface of a shallow p-type well region 3 provided on the main surface of the conductor substrate 1 . p-type well region 3. It is provided within the deep n-type well region 2. The impurity concentration in the n-type well region 2 is higher than that in the semiconductor substrate 1. The impurity concentration of the p-type well region 3 is higher than that of the n-type well region 2. Here, first, the configuration of the p-channel MI S FET will be explained. P-channel MISF that constitutes the peripheral circuit
ET is a gate insulating film 7 made of a silicon oxide film on the surface of the n-type well region 4. Goo 1-1 consisting of a polycrystalline silicon layer on the gate insulating film 7! The electrode 12 is composed of a p-type semiconductor region 38 which is a source and drain region on the surface of both sides of the gate electrode 12 of the n-type well region 4. The planar shape of the n-channel MISFET is defined by a field insulating film 7 made of a silicon oxide film. A conductive layer 21 made of a first aluminum layer is connected to the surface of the P' type semiconductor region 38 which is a source region through a contact hole 23 . The conductive layer 21 is connected to the surface of the n-type well region 4 through the connection hole 22 . A t+7 type semiconductor region 37 is provided in a portion of the surface of the n-type well region 4 to which the conductive layer 21 is connected. That is, the conductive layer 21 is

[Connected to the surface of the 50-type semiconductor region 37. The conductive layer 21 applies a power supply potential VcC5, for example, 5V, to the source region of the P-channel MISFET. p-channel MISF
On the surface of the P type semiconductor region 38, which is the 1-rain region of YET, there is a conductive layer 2 made of a first aluminum layer.
7 is connected. One end of the conductive layer 27 is. It is connected to the drain region of an n-channel MISFET, which will be described later. r] The channel MTSFET includes a gate insulating film 7 on the surface of the P-type well region 3, a goo 1-electrode 12 . n' type semiconductor regions 3 which are source and drain regions on both sides of the gate pole 12 of the P type well region 3;
It consists of 9. The planar shape of the n-channel MI S FET is defined by the field insulating film 6. A conductive layer 27 forms a contact hole 29 on the surface of a diamond-type semiconductor region 39 which is a drain region.
connected through. A conductive layer 30 made of a first aluminum layer is connected to the surface of the n3 type semiconductor region 39 serving as a source region through a contact hole 31 . The conductive layer 30 is connected to the surface of the n-type well region 3 through a connection hole 32 . The conductivity fI of the surface of the n-type well region 3! A p11 type semiconductor region 40 is provided in a portion where the layer 30 is connected. That is, the conductive layer 30 has a P′-type semicircular region 40.
connected to the surface of Conductive M30 is an n-channel M
n4 type semiconductor region 3 which is the source region of I S FET
The ground potential Vss of the circuit, for example 0■, is applied to 9. In addition, P-channel MISFET and n-channel MISFET
In FET, gate 1! The pole 12 is not limited to a polycrystalline silicon layer, but can be made of Mo, W, Ta, T.
It may be a high melting point metal film such as i or its silicide film, or it may be a 2Fg film in which the high melting point metal film or silicide film is provided on a polycrystalline silicon layer. The n-type well region 3 in region A is the n-type well region 2
It is located inside. The n-type well region 2 is formed deeper and wider than the n-type well region 3. A peripheral portion of the n-type well region 3 of the n-type well region 2 reaches the surface of the semiconductor substrate l. A conductive layer 33 made of a first aluminum layer is connected to a portion of the n-type well region 2 exposed on the surface of the semiconductor substrate 1 through a connection hole 34 . The conductivity T1. of the surface of the n-type well region 2. A 04 type semiconductor region 41 is provided in a portion where Wj33 is connected. That is, the conductive layer 33 is connected to the surface of the n-type semiconductor region 41. The conductor N33 connects the n-type well region 2 to the power supply potential Vc.
c, for example, 5V is applied. That is, a reverse bias is applied between the n-type well region 2 and the n-type well region 3. Electrons injected from the n-channel MISFET into the n-type well region 3
f from the n-type well region 2 by flowing into the
It is absorbed by the fi source potential Vcc. On the other hand, holes injected from the p-channel MI S FET into the semiconductor substrate 1 through the n-type well region 2 cannot cross the barrier between the semiconductor substrate 1 and the n-type well region 2. That is, the p-channel M I S of the semiconductor substrate 1
No current flows between the FET and the n-channel MISFET. [Example 2] FIG. 4 is a plan view of a complementary MISFET of Example 2, and FIG. 5 is a sectional view taken along the line AA in FIG. 4. Note that insulating films other than the field insulating film 6 are not shown in FIG. 4 in order to make the configuration of the complementary MISFET easier to see. In Example 2, a P-type well region 42 is provided on the main surface of a p-type semiconductor substrate l, and an n-type well region f! is provided within this n-type well region 42. ji 43 is provided, and a P-channel MIS FET is configured in this n-type well region 43 to provide a complementary MIS.
This prevents FET latch-up. In FIGS. 4 and 5, the n-channel MISFET consists of a gate insulating film 7° on the surface of a semiconductor substrate l, a gate j1!2 electrode 12 on the gate insulating film 7, and a gate f of the semiconductor substrate 1.
! ! It is composed of rl' type semiconductors which are source and drain regions provided on the surfaces of both sides of the pole 12. The surface of the n-type semiconductor region 39, which is the source region, has a conductive F! made of a first aluminum layer. j46
are connected through the connection hole 47. Conductive PI 46 provides the circuit's ground potential Vss. A conductive layer 48 made of a first aluminum layer is connected to the surface of the rl'' type semiconductor region 39 which is a drain region through a connection hole 49. is connected to the conductor made of the first aluminum layer through the contact hole 57. A deep P-type well region 42 is provided in the region of the semiconductor substrate 1 where the p-channel MISFET is provided. A shallow n-type well region 43 is provided within the n-type well region 42. On the surface of the semiconductor substrate 1 and the P-type well region 42 under the field #!l edge film 6 excluding the n-type well region 43,
A p-type channel stopper region 5 is provided. Here, the configuration of the P-channel MISFET will be explained. p
The channel MISFET includes a gate insulating film 7 on the surface of the n-type well region 43, a gate electrode 12 on the gate insulating film 7,
The n-type well region 43 is composed of P1-type half regions 38, which are source and drain regions, on the surfaces of both sides of the gate electrode 12. On the surface of the p-type semiconductor region 38, which is the drain region,
One end of the conductive layer 48 is connected through a connection hole 50. The surface of the p-type semiconductor region 38, which is the source region, is made of a first aluminum layer and has a power supply potential Vcc.
, for example 5V, continues through the connection hole 51 . The conductive layer 52 is connected to the surface of the n-type well region 43 through a connection hole 53. Gate electrode 12
A conductive layer 58 made of a first aluminum layer is connected to the end portion of the field insulating film 6 through a connection hole 59 . An n + -type semiconductor region 45 is provided in a portion of the n-type well region 43 to which the conductive layer [52] is connected. That is, the conductive layer 52 is connected to the surface of the n'-type semiconductor region 45. The impurity concentration of the p-type well region 42 is the same as that of the semiconductor substrate l.
It's higher than the one inside. Namely. The resistance value of the n-type well region 42 is smaller than that of the semiconductor substrate 1. The impurity concentration of the n-type well region 43 is higher than that of the n-type well region 42. n
The type well region 43 has a P-channel MISFE on its surface.
The peripheral portion of T is exposed between the field insulating films 6. The n-type well region 42 is formed deeper and wider than the n-type well region 43. n of the n-type well region 42
The surface of the peripheral portion of the mold well region 43 is exposed on the surface of the semiconductor substrate 1 . A P'''' type semiconductor region 44 is provided on the surface of the P type well region 42, surrounding the n type well region 43. The surface of the p+ type semiconductor region 44 is exposed between the field insulating films 6. The planar shape of the p4 type half region 44 is defined by the field isolation film 6. A conductor made of a first aluminum layer is formed on a predetermined portion of the surface of the P-type semiconductor region 44.
4 are connected through the connection hole 55. The p-type semiconductor region 44 is used to approximately uniformly apply a circuit ground potential Vss, eg, Ov, applied through the conductive layer 54 to the n-type well region 42. Complementary MISFET latch-up is caused by P-channel MISFET
A parasitic transistor whose emitter is the p-type semiconductor region 38, which is the drain region of the SFET, whose base is the n-type well region 43, and whose collector is the p-type semiconductor substrate 1, is conductive, and the collector current is the source region of the n-channel MISFET. This is caused by flowing into the n-type semiconductor region 39. However, a p-type well region 42 having a lower resistance than the semiconductor substrate 1 is provided around the n-type well region 43, and this p-type well region 42 is connected to a conductive layer 54 to which the circuit ground potential Vss is applied.
, the collector current of the parasitic transistor flows to the outside of the semiconductor substrate 1 through the conductive layer 54. Therefore, the P channel M I S of the semiconductor substrate 1
No current flows between the FET and the n-channel MISFET. In this embodiment, the n-channel MISFET is formed on the main surface of the semiconductor substrate.
The ET may be configured within the P-type well region. According to the new technology disclosed in this application, the following effects can be obtained. (1) By providing a p-type well region having a memory cell on its main surface within a larger n-type well region, the n-type well region is extremely smaller than the entire semiconductor substrate. The potential of the n-type well region can be increased at high speed. (2) According to (1) above, the current required to boost the voltage in the n-type well region is reduced, so the MISFET that constitutes the booster circuit can be made smaller, and power consumption can be reduced. (3), n-channel M forming complementary MISFET
An I S FET is provided in the p-type well region, and
By providing the type well region within the n-type well region,
The n-channel MISFET is shielded by the n-type well region, so that latch-up can be prevented from occurring between the p-channel MISFET and the n-channel MISFET. (4) According to (3) above, complementary MI S FET
It is possible to improve the electrical characteristics of. (5), p-channel M forming complementary MISFET
The collector current of the parasitic transistor is is absorbed by the P-well region, so the P-channel MISFET and n
It is possible to prevent latch-up from occurring between channel MISFETs. (6) Since the peripheral circuits of the memory cell array can operate stably even when writing or erasing information to the memory cells, it becomes possible to form the EEPROM on the same chip as a microcomputer chip or the like. The present invention has been specifically explained above using examples, but
It goes without saying that the present invention is not limited to the embodiments described above, and can be modified in various ways without departing from the spirit thereof. For example, a memory cell may include one MNO5 type device or an MNO5 type device.
It may consist of one 8-type element and two MISFETs (switch elements on the data line side and the write element line side). Or M I where the memory cell has a floating gate
It may also consist of an S FET. The present invention can be widely applied to various semiconductor devices including semiconductor devices that electrically write and erase information in memory cells. [Effects of the Invention] The effects obtained by typical inventions disclosed in this application are briefly explained below. By forming the well region within the well region of the same or opposite conductivity type, the electrical characteristics of the semiconductor device can be improved, and in particular, its operating speed and reliability can be improved.

[Brief explanation of drawings]

1A and 1B are circuit diagrams for writing and erasing memory cells of an EEPROM. FIG. 2 is a plan view of the memory cell. Figure 3 shows MISFE that constitutes the peripheral circuit of EEPROM.
4 is a plan view of the complementary MISFET, and FIG. 5 is a sectional view taken along the line AA in FIG. 4. 1... Semiconductor substrate, 2.3.4.42-43... Well region, 5, 24.25.26.38.39.40.
41.44.45...Semiconductor region, 6...Field insulating film, 7.8.9.35.36...Insulating film. 10. 11. 12, 13, 15, 17. 19.2
1.27.30.33.46.48.52.54゜56
．． 58-- Conductive layer, 14.16.18.20°22.
23.28.29.31.32.34.47.49.5
0.51.53.55.57.59... Connection hole. Agent Patent Attorney Katsuma Ogawa''- Figure 1A Figure IB

Claims (1)

[Claims] 1. A first well region of a first conductivity type or a second conductivity type is provided on the main surface of a semiconductor substrate of a first conductivity type, and a first well region of a second conductivity type or a first conductivity type is provided in the first well region. 1. A semiconductor integrated circuit device, characterized in that a second well region of a conductive type is provided, and a semiconductor element is provided on a main surface of the second well region. 2. The semiconductor element is a MISFET that stores non-volatile information and electrically erases the non-volatile information, the first well region is applied with an erase potential when erasing information, and the second well region is Claim 1, characterized in that a potential higher than the erase potential is applied when erasing information.
The semiconductor integrated circuit device described in . 3. The semiconductor element is a p-channel MISFET or an n-channel MISFET constituting a complementary MISFET.
Claim 1, wherein the second well region is an element isolation region that electrically isolates the semiconductor element on the main surface of the first well region from other semiconductor elements. The semiconductor integrated circuit device described.