JP2006339554A - Nonvolatile semiconductor memory and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve a disadvantage that a high voltage is required for data deleting operation for eliminating electric charges accumulated on a floating gate (FG) in an EEPROM. <P>SOLUTION: A memory cell is configured by a combination of a p-MOSFET 20 and an n-MOSFET 22. The FETs 20, 22 have a common FG. In a data writing operation, a current is applied to a channel of the FET 22 to generate hot electrons in the vicinity of a drain region, and the hot electrons are implanted into the FG by applying a positive voltage to a control gate electrode (CG). In a data deleting operation, a current is applied to a channel of the FET 20 to generate hot holes, and the hot holes are implanted into the FG by applying a negative voltage to the control CG. Thus, the data deleting operation can be realized without using an FN tunnel current requiring a high voltage. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a nonvolatile semiconductor memory device, and more particularly to an EEPROM (Electrically Erasable Programmable Read-Only Memory).

FIG. 5 is a schematic diagram showing a cross-sectional structure of an EEPROM memory cell which is a kind of semiconductor memory. This memory cell has a structure that is common to MOS (Metal Oxide Semiconductor) type field effect transistors in terms of basic points. The transistor 1 shown in FIG. 5 is an n-channel, and the source region 4 and the drain region 6 of the n ⁺ diffusion layer are formed on the surface of the p-type semiconductor substrate 2, respectively. A floating gate electrode 10 (floating gate: FG) is disposed on the channel region 8 between the source region 4 and the drain region 6 via a gate oxide film (not shown). A control gate electrode 12 (control gate: CG) is disposed thereon via an interlayer insulating layer (not shown) such as an oxide film.

  The source region 4, the drain region 6, and the CG 12 are each connected to a wiring, and a voltage can be applied from the outside of the memory cell via the wiring. On the other hand, the FG 10 is formed as an isolated electrode that is completely surrounded by an insulating film and is not connected to the outside of the memory cell. The threshold voltage of the transistor 1 shifts according to the amount of charge accumulated in the FG 10, and 1-bit data is stored in the transistor 1 by associating the two states with the logical data “1” and “0”, respectively. Remembered. Since the FG 10 is an isolated electrode as described above, the amount of charge in the FG 10 is maintained even when the power supplied to the transistor 1 is turned off, thereby realizing data non-volatility.

  Writing and erasing data in the memory cell is performed by injecting electrons into the FG 10 and removing the electrons. Conventionally, electrons are injected into the FG 10 by hot carrier injection. Specifically, when a high voltage is applied to the drain region 6 and CG 12 of the transistor 1, electrons moving from the source region 4 toward the drain region 6 obtain high energy in the vicinity of the drain region 6 to generate hot electrons. Become. Electrons are injected into the FG 10 by drawing hot electrons that can exceed the potential barrier of the gate oxide film between the semiconductor substrate surface and the FG 10 with a high voltage of the CG 12.

  On the other hand, the removal of electrons from the FG 10 is performed using an FN (Fowler-Nordheim) tunnel current. For example, when the CG 12 is set to a low voltage while the drain region 6 is floated, and a high voltage is applied to the source region 4, the tunnel current between the FG 10 and the source region 4 increases, and thus the FG 10 accumulates. The extracted electrons are extracted to the source region 4.

  FIG. 6 is a schematic diagram for explaining data writing, erasing, and reading operations in the transistor 1, and shows an example of voltages applied to the source (S), the drain (D), and CG. FIG. 4A shows the data write operation. When the source is grounded and +4 V is applied to the drain, for example, electrons move from the source region toward the drain region, and some of them become hot electrons in the vicinity of the drain region. When, for example, +6 V is applied to CG as a voltage higher than the drain, the generated hot electrons can be injected into FG10. As electrons are accumulated in the FG 10, the threshold voltage Vt of the transistor 1 rises from the reference voltage vα to vβ.

  FIG. 4B shows the data erasing operation. When the source is opened, the drain is grounded, and -6 V, for example, is applied to CG, electrons move from FG 10 toward the drain region through the FN tunneling process. Thereby, the electrons accumulated in the FG 10 by the write operation are removed, and the threshold voltage Vt of the transistor 1 returns to vα.

  FIG. 4C shows the data read operation (read operation). At the time of reading, it is not necessary to move electrons beyond the gate oxide film, so that the operation can be performed at a lower voltage than the above two operations. For example, the drain can be + 1.5V with respect to the grounded source. A value between vα and vβ is selected as the voltage of CG, and, for example, + 1.5V is applied. In the state where electrons are accumulated in FG10 and the threshold voltage is vβ, the drain current Id does not flow. On the other hand, in the state where electrons are not accumulated in FG10 and the threshold voltage is vα, the drain current Id flows. By detecting this difference in drain current, it is detected whether the data stored in the transistor 1 is “0” or “1”.

There are several hot carrier generation mechanisms. Basically, hot carriers are generated due to a high electric field in the vicinity of the drain region 6. Incidentally, in recent years, with the miniaturization of transistors, hot carriers are easily generated even when the source-drain voltage Vds is relatively low. In addition, the gate voltage applied to the CG 12 at the time of hot carrier injection basically has only to work to direct the moving direction of the hot carrier generated according to Vds to the FG 10, and further to the hot carrier whose direction is changed to the FG 10. Giving energy is not so important. That is, even a potential difference is relatively small values of the drain and the gate (the delta _HC), hot carrier injection into FG10 may occur.

On the other hand, the magnitude of the FN tunnel current is determined according to the tunnel phenomenon at the potential barrier of the gate oxide film, and the amount of current changes exponentially according to the electric field applied to the gate oxide film. In other words, between the semiconductor substrate surface and CG12 such drain regions, when not applied to large voltage delta _FN compared to delta _HC as shown in FIG. 6, FN tunnel current does not flow substantially by the current FG10 It may happen that the charge cannot be removed from.

Incidentally, it is possible to easily generate the FN tunnel current by reducing the thickness Tox of the gate oxide film. In the current EEPROM, Tox is set to a very small value of about 10 nm in the vicinity of the drain region, for example. The operation voltage at the time of erasing data is reduced. Incidentally, FIG. 6 described above is an example of the operating voltage in such a configuration. However, it is not always easy to satisfactorily form such a thin gate oxide film. Therefore, from the viewpoint of the yield or the like is convenient to avoid hard too small Tox, in which case, delta _FN may become greater. Further, although only a part of the vicinity of the drain region is thinly formed, the process becomes complicated.

  As described above, conventionally, removal from the FG 10 at the time of data erasure is performed by the FN tunnel current, and at that time, it is required to apply a relatively high voltage between the semiconductor substrate and the CG 12. there were. That is, a power supply that generates a relatively high voltage is required for the erase operation. For example, it is necessary to mount a booster circuit that generates the voltage in the semiconductor chip. As described above, the conventional memory cell may cause a problem that the complexity and difficulty in process and design increase in the formation of the gate oxide film and the power supply circuit.

  In particular, the memory cell is not only configured as a single memory device in which only the memory cell is integrated, but also, for example, in order to hold parameters necessary for the operation of other semiconductor devices, it is desired to be incorporated in the chip of the semiconductor device. There may be cases. In this case, the memory capacity required is often a relatively small amount. In that case, a booster circuit is provided in the chip for the small amount of memory portion, or a thin gate oxide film is provided in the process of the semiconductor device. Adding a process such as forming with high accuracy or forming only a part of the gate oxide film (for example, in the vicinity of the drain region) thin has the problem that the effect of increasing the chip area and reducing the yield may increase. .

  The present invention has been made in order to solve the above-described problems. Data writing and erasing can be performed at a relatively low voltage without reducing the thickness of the gate oxide film, or data can be reduced while reducing the thickness of the gate oxide film. An object of the present invention is to provide a nonvolatile semiconductor memory device that can perform writing and erasing of data at a lower voltage.

  In the nonvolatile semiconductor memory device according to the present invention, a field effect transistor which is formed on a semiconductor substrate and constitutes a memory cell includes a floating gate electrode between a channel and a control gate electrode, and the accumulated charge amount of the floating gate electrode is reduced. In response, the memory cell is a first conductivity type field effect transistor having a first floating gate electrode and a second conductivity type field effect. And a second transistor having a second floating gate electrode, and the first floating gate electrode and the second floating gate electrode are electrically connected to each other.

  In another nonvolatile semiconductor memory device according to the present invention, the first transistor and the second transistor have the common control gate electrode.

  In another nonvolatile semiconductor memory device according to the present invention, the first floating gate electrode and the second floating gate electrode are formed of an integral conductive material.

  An operation method of the nonvolatile semiconductor memory device according to the present invention is such that a channel current is passed through the first transistor, the generated hot carriers are injected into the first floating gate electrode, and the floating gate electrode potential is written from a reference potential. A transition is made to a data holding potential corresponding to data, a data current is written to the memory cell, a channel current is passed through the second transistor, and hot carriers having a polarity opposite to that at the time of the data writing are generated. And an operation of erasing the data by injecting the floating gate electrode to change the floating gate electrode potential from the data holding potential to the reference potential.

  According to another operation method of the nonvolatile semiconductor memory device of the present invention, the data stored in the memory cell is detected based on a difference between a drain current of the first transistor and a drain current of the second transistor. To do.

  According to the present invention, each memory cell includes two field effect transistors (FETs). Each of these two FETs has a floating gate electrode, one being an n-channel transistor and the other being a p-channel transistor. The n-channel FET can inject hot electrons generated in the channel by applying a voltage between the drain and source into the floating gate electrode by the voltage applied to the control gate electrode. The p-channel FET can inject hot holes generated in the channel by applying a voltage between the drain and the source into the floating gate electrode by the voltage applied to the control gate electrode. Here, the floating gate electrodes of both FETs are electrically connected to each other, and the charge accumulated in the floating gate electrode by one of hot electron injection and hot hole injection is neutralized by the other injection. Can be removed. By selectively injecting these electrons and holes, the amount of charge in the floating gate electrode is controlled to change the threshold voltage of each FET, thereby realizing data writing and erasing in the memory cell. That is, according to the present invention, both data writing and erasing are performed by hot carrier injection, so that a memory that operates at a relatively low voltage is configured with a relatively easy process compared to the case of using the FN tunnel current. can do.

  Hereinafter, embodiments of the present invention (hereinafter referred to as embodiments) will be described with reference to the drawings.

  FIG. 1 is a circuit diagram showing a schematic configuration of an EEPROM memory cell according to the embodiment. The memory cell includes a p-channel MOSFET 20 and an n-channel MOSFET 22. The MOSFETs 20 and 22 have a floating gate electrode FG between each channel and the control gate electrode CG, and the dotted line between the two FGs in FIG. 1 indicates that the FGs are electrically connected to each other. In FIG. 1, φsp and φdp represent the source terminal and drain terminal of the MOSFET 20, and φsn and φdn represent the source terminal and drain terminal of the MOSFET 22. The CGs of the MOSFETs 20 and 22 are connected to a common terminal φcg.

FIG. 2 is a diagram schematically showing the vertical sectional structure of the MOSFETs 20 and 22. Here, a structure in which the MOSFETs 20 and 22 are formed on the surface of a p-type silicon substrate (P-sub) 30 is shown. The substrate surface to form a MOSFET20 of p-channel, n-type impurity region 32 is formed, the source region 34 and a drain region of the p-type impurity made of p ⁺ diffusion layer introduced at a high concentration n-type impurity region 32 36 is formed. The FG 40 is disposed so as to cover the channel region 38 between the source region 34 and the drain region 36, and the CG 42 is further disposed thereon.

On the other hand, as the source region 44 and drain region 46 of the n-channel MOSFET 22, an n ⁺ diffusion layer in which an n-type impurity is introduced at a high concentration is formed on the surface of the P-sub 30. An FG 50 is disposed so as to cover a channel region 48 between the source region 44 and the drain region 46, and a CG 52 is further disposed thereon.

  For example, the FGs 40 and 50 are made of a conductive material such as polysilicon. In FIG. 2, for convenience, the FG 40 and the FG 50 are shown separately. However, as shown in a plan view later, they are formed as one continuous electrode. Similarly, the CGs 42 and 52 are formed of a conductive material such as polysilicon, and are formed as integral electrodes continuous with each other as shown in a plan view later.

  A gate oxide film 54 made of a silicon oxide film or the like is formed between the channel region 38 and the FG 40 and between the channel region 48 and the FG 50. An interlayer insulating layer 56 is also formed between FG 40 and CG 42 and between FG 50 and CG 52. The thickness Tox of the gate oxide film 54 is set so that hot carriers that can be generated in the vicinity of the drain region can be injected into the FGs 40 and 50. Specifically, it is determined in consideration of the relationship between the source-drain voltage Vds and the voltage applied to the CGs 42 and 52 when the hot carrier injection operation is performed. From the viewpoint of reducing these voltages, it is basically preferable to set Tox to be small. However, in addition to this viewpoint, the viewpoint of the process for forming the gate oxide film 54 and the durability and stability of the formed gate oxide film In view of the above, Tox should be determined comprehensively. Since this memory cell does not perform data erasure due to the FN tunnel current, it is not required to consider that the tunnel phenomenon can easily occur when determining Tox. In addition, it is preferable that the thickness of the interlayer insulating layer 56 is basically set to be small from the viewpoint of reducing operating voltage in data writing and erasing operations and data reading operations.

  The substrate regions of the MOSFETs 20 and 22 are separated from adjacent elements by surrounding the periphery with a local oxide film (LOCOS) 58 formed on the substrate surface. The FGs 40 and 50 are surrounded by a gate oxide film 54 and an interlayer insulating layer 56, and are in an electrically floating state. The source regions 34 and 44 and the drain regions 36 and 46 are connected to a wiring 60 made of aluminum (Al) or the like through a contact hole opened in a layer above it. The CGs 42 and 52 are connected to a wiring made of an Al layer or the like through a contact hole at a position not shown in FIG.

  FIG. 3 is a schematic plan view of the present memory cell. FIG. 3 shows only the patterns related to the main manufacturing process. MOSFET 20 is formed in active region 80, and MOSFET 22 is formed in active region 82. An FG 84 common to both MOSFETs is disposed so as to cross the respective active regions 80 and 82 formed in a rectangular shape, and a CG 86 common to both MOSFETs is disposed on top of the FG 84. A portion of FG 84 located on active region 80 corresponds to FG 40 shown in FIG. 2, and a portion located on active region 82 corresponds to FG 50. The FG 84 is not connected to any wiring. On the other hand, the CG 86 is connected to the wiring 90 via the contact 88. The voltage applied to the terminal φcg is supplied to the CG 86 via the wiring 90. Incidentally, a portion of the CG 86 located on the active region 80 corresponds to the CG 42 shown in FIG. 2, and a portion located on the active region 82 corresponds to the CG 52.

  A LOCOS 38 is formed outside the active regions 80 and 82. An n-type impurity is introduced into the active region 80 to form an n-type impurity region 32. In the active region 80, the n-type impurity region 32 under the FG 84 becomes a channel region 38, p-type impurities are introduced into regions located on both sides of the channel region 38, and the source region 34 and the drain region 36 are It is formed. The source region 34 is connected to a wiring 94 made of an Al layer or the like through a contact 92, and the wiring is connected to a terminal φsp. The drain region 36 is connected to the wiring 98 through the contact 96, and the wiring is connected to the terminal φdp.

  On the other hand, in the active region 82, the channel region 48 located under the FG 84 is made of P-sub30. An n-type impurity is introduced into regions located on both sides of the channel region 48, and a source region 44 and a drain region 46 are formed. The source region 44 is connected to the wiring 102 through the contact 100, and the wiring is connected to the terminal φsn. The drain region 46 is connected to the wiring 106 through the contact 104, and the wiring is connected to the terminal φdn.

  One memory cell shown in FIG. 3 can be arranged one-dimensionally or two-dimensionally. For example, in the case of two-dimensional arrangement, a plurality of memory cells connected to common terminals φsp, φdp, φsn, φdn (that is, wirings 94, 98, 102, 106) are arranged in the horizontal direction in FIG. The CGs of these memory cells are connected to wirings connected to different terminals φcg. Further, in the vertical direction in FIG. 3, memory cells connected to a common terminal φcg (that is, wiring 90) and connected to a set of different terminals φsp, φdp, φsn, and φdn are arranged. Which of the two-dimensionally arranged memory cells is selected to write, erase, or read data is selectively applied to a plurality of terminals φcg and a plurality of terminals φsp, φdp, This can be determined by selectively applying a predetermined pattern of voltage to either of the set of φsn and φdn.

  Next, data writing, erasing, and reading operations for the memory cell will be described by taking specific voltages that can be compared with the conventional operation shown in FIG. 6 as an example. Here, a case where electrons are injected into the FG in the write operation and holes are injected in the erase operation will be described. FIG. 4 is a schematic diagram illustrating voltage examples applied to the source (S), drain (D), and CG in each operation. FIG. 4A shows a data write operation. When the source terminal φsn is grounded and, for example, +4 V is applied to the drain terminal φdn, electrons move from the source region to the drain region of the n−MOSFET 22, and some of them become hot electrons near the drain region. The MOSFET 22 is configured such that hot electrons can be injected into the FG 84 beyond the gate oxide film by applying, for example, + 6V, which is 2V higher than the drain voltage, to the CG terminal φcg. By accumulating electrons in the FG 84, the threshold voltage Vtn of the MOSFET 22 increases from the reference voltage vα to vβ, and the threshold voltage Vtp of the MOSFET 20 decreases from the reference voltage vα ′ to vβ ′.

  At this time, the p-MOSFET 20 has both the source terminal φsp and the drain terminal φdp at +4 V, so that no current flows between the source and the drain, neither hot carrier injection nor tunneling current occurs, and the charge amount of the FG 84 is affected. Not give.

  FIG. 4B shows the data erasing operation. By applying +4 V to the source terminal φsp and grounding the drain terminal φdp, holes move from the source region to the drain region of the p-MOSFET 20, and some of them become hot holes near the drain region. For example, the p-MOSFET 20 can be basically similar to the n-MOSFET 22 except for the difference in conductivity type. In that case, for example, by applying −2 V, which is 2 V lower than the drain voltage, to the CG terminal φcg, hot holes can be injected into the FG 84 from the vicinity of the drain region over the gate oxide film. By injecting holes into the FG 84, the electrons injected into the FG 84 in the above write operation are neutralized, the threshold voltage Vtn of the MOSFET 22 is returned from vβ to vα, and the threshold voltage Vtp of the MOSFET 20 is changed from vβ ′ to vα ′. Can be returned.

  At this time, the n-MOSFET 22 grounds both the source terminal φsn and the drain terminal φdn, so that no source-drain current flows, neither hot carrier injection nor tunneling current occurs, and the FG 84 charge amount is affected. Don't give.

  FIG. 4C shows a data read operation (read operation). Here, the operation of reading the data stored in the memory cell based on the difference in the drain current of the MOSFET 22 in accordance with the accumulated charge amount of the FG 84 will be described. At the time of reading, it is not necessary to move electrons beyond the gate oxide film, so that the operation can be performed at a lower voltage than the above two operations. In order to allow the drain current to flow through the MOSFET 22, for example, the drain is set to +1.5 V with respect to the grounded source. Further, a value between vα and vβ is selected as the voltage of CG, and, for example, + 1.5V is applied. In the state where electrons are accumulated in FG84 and the threshold voltage is vβ, the drain current Id does not flow, while in the state where electrons are not accumulated in FG84 and the threshold voltage is vα, the drain current Id flows. By detecting this difference in drain current, it is detected whether the data stored in the memory cell is “0” or “1”.

  At this time, the p-MOSFET 20 is set so that the source-drain current does not flow by grounding the source terminal φsp and the drain terminal φdp together. On the other hand, the storage data can be detected based on the drain current of the p-MOSFET 20 and can be set so that no current flows through the n-MOSFET 22. Further, when the voltage of the CG can be set to a value between vα and vβ and between vα ′ and vβ ′, each source can be supplied so that a drain current can flow in each of the MOSFETs 20 and 22. A voltage and a drain voltage can be set, and data can be detected based on a difference between both drain currents. Furthermore, such a configuration for detecting data based on the difference in drain current can be realized regardless of the mutual relationship between the threshold voltages Vtp and Vtn of both MOSFETs if the CG voltages of the MOSFETs 20 and 22 can be controlled independently. It is.

  Comparing the operation example of the present memory cell in FIG. 4 with the conventional operation example in FIG. 6, in the conventional configuration in which data erasure is performed by the FN tunnel current, a power supply of −6 V is used at the time of erasure. In the configuration of this memory cell, a power supply of −2V is sufficient at the time of erasing. Thus, according to this memory cell, the operating voltage is reduced when the thickness of the gate oxide film is the same as the conventional one. In addition, since a margin for an increase in operating voltage when the gate oxide film thickness Tox is increased is obtained, Tox can be increased to improve the reliability of the gate oxide film formation process.

FIG. 2 is a circuit diagram showing a schematic configuration of a memory cell of the EEPROM according to the embodiment. It is a schematic diagram explaining the vertical cross-sectional structure of the memory cell which concerns on embodiment. 2 is a schematic plan view of a memory cell according to an embodiment. FIG. It is a schematic diagram showing an example of an applied voltage in each operation of the memory cell according to the embodiment. It is a schematic diagram which shows the cross-section of the memory cell of EEPROM. It is a schematic diagram which shows the example of the applied voltage in each operation | movement of the conventional memory cell.

Explanation of symbols

  20 p-MOSFET, 22 n-MOSFET, 30 P-sub, 32 n-type impurity region, 34, 44 source region, 36, 46 drain region, 38, 48 channel region, 40, 50, 84 Floating gate electrode (FG) , 42, 52, 86 Control gate electrode (CG), 54 Gate oxide film, 56 Interlayer insulating film, 58 LOCOS, 60 wiring, 80, 82 Active region, 90, 94, 98, 102, 106 wiring.

Claims (5)

A non-volatile semiconductor memory device in which a field-effect transistor formed on a semiconductor substrate and constituting a memory cell has a floating gate electrode between a channel and a control gate electrode, and stores data according to the amount of charge stored in the floating gate electrode In
The memory cell is
A first conductivity type field effect transistor comprising a first floating gate electrode;
A field effect transistor of the second conductivity type, and a second transistor having a second floating gate electrode,
The first floating gate electrode and the second floating gate electrode are electrically connected to each other;
A non-volatile semiconductor memory device. The nonvolatile semiconductor memory device according to claim 1,
The first transistor and the second transistor have the common control gate electrode;
A non-volatile semiconductor memory device. The nonvolatile semiconductor memory device according to claim 1 or 2,
The first floating gate electrode and the second floating gate electrode are formed of an integral conductive material;
A non-volatile semiconductor memory device. An operation method for the nonvolatile semiconductor memory device according to claim 1,
A channel current is passed through the first transistor, the generated hot carriers are injected into the first floating gate electrode, and the floating gate electrode potential is changed from a reference potential to a data holding potential corresponding to write data, to the memory cell. Writing data,
A channel current is passed through the second transistor, hot carriers having a polarity opposite to that of the generated data write are injected into the second floating gate electrode, and the floating gate electrode potential is changed from the data holding potential to the reference. Transition to a potential and erasing the data;
A method for operating a nonvolatile semiconductor memory device, comprising: The operation method of the nonvolatile semiconductor memory device according to claim 4,
An operation method of a nonvolatile semiconductor memory device, wherein the data stored in the memory cell is detected based on a difference between a drain current of the first transistor and a drain current of the second transistor.

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