JP2009239161A - Nonvolatile semiconductor memory device and usage method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory device which does not cause significant increase in the cell area but solves the problem of disturbance. <P>SOLUTION: The nonvolatile semiconductor memory includes a p-type first well formed in a semiconductor substrate and connected to a first terminal; a first NMOS transistor and a second NMOS transistor formed in a first well and connected in series between a second terminal and a third terminal; an n-type second well formed in the semiconductor substrate and connected to a fourth terminal; a first PMOS transistor and a second PMOS transistor, formed in the second well and connected in series between a fifth terminal and a sixth terminal, wherein the gate of the first NMOS transistor constitutes a seventh terminal, the first PMOS transistor constitutes an eighth terminal, the gates of the second NMOS transistor and the second PMOS transistor are connected in common and are in a floating state. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

The present invention relates to an electrically writable nonvolatile semiconductor memory element and a nonvolatile semiconductor memory device including the same.

Necessity of redundancy (redundancy) due to increase in capacity of built-in SRAM, necessity of individual tuning after mounting a board such as an LCD driver, personal identification information (ID code, decryption key, and IC card With the expansion of various applications such as numbers, the need for low-cost fuses is increasing. Conventionally, fuse memories that can be formed by a standard CMOS process include those having a polysilicon or wiring metal layer that is blown by a laser or current, and those having an insulating gate film that is broken by a voltage.

However, a fuse memory having such a fusing part or a dielectric breakdown part can be programmed only once, and therefore is not suitable for applications requiring rewriting as described above. On the other hand, if it is a floating gate type non-volatile memory element, an electrically erasable / writeable fuse can be created, but in order to form a floating gate, a standard CMOS process similar to a conventional flash memory is used. Since it is necessary to introduce an additional process, it is not worth the cost. Therefore, various proposals have been made for realizing a floating gate type nonvolatile memory element by a standard CMOS process (single-layer poly).

FIG. 59 shows a floating gate type nonvolatile memory element realized by a standard CMOS process (single-layer poly) disclosed in US Pat. No. 7,221,596 (Patent Document 1).

59 includes PMOS transistors M0, M1, Ms0, Ms1, M0c, M1c, M0t, and M1t, of which the PMOS transistors M0c, M1c, M0t, and M1t have a common source and drain, respectively. It functions as a connected MOS capacitor. Comparing the capacitance C0c of the MOS capacitor consisting of the PMOS transistor M0c with the capacitance C0t of the MOS capacitor consisting of the PMOS transistor M0t, C0c is larger than C0t. Similarly, when comparing the capacitance C1c of the MOS capacitor composed of the PMOS transistor M1c with the capacitance C1t of the MOS capacitor composed of the PMOS transistor M1t, C1c is larger than C1t.

The PMOS transistors Ms0 and Ms1 function as selection transistors, and their gates are driven by a signal Vrow. The gates of the PMOS transistors M0, M0c, and M0t are commonly connected to form a floating gate Fg0, and the gates of the PMOS transistors M1, M1c, and M1t are commonly connected to form a floating gate Fg1.

Electron injection into the floating gate Fg1 is performed by applying 0V to V0 and 10V to V1, and at the same time, electrons are extracted from the floating gate Fg0. Electron injection into the floating gate Fg0 is performed by applying 10V to V0 and 0V to V1, and at the same time, electrons are extracted from the floating gate Fg1.

In this nonvolatile memory element, the FN tunnel phenomenon over the entire channel region of the transistor is used to put electrons into and out of the floating gate. In order to implement the FN tunneling phenomenon at a low voltage, it is necessary to efficiently transmit the voltage of the control gate to the floating gate (= improve the coupling ratio). For this reason, a large MOS type is required between the control gate and the floating gate. Capacity is required. As a result, there is a problem that the cell area becomes large as follows.

The memory cells in FIG. 59 are all composed of PMOS, but each N well needs to be divided into three (V, V0, V1), and an N well isolation region is required in terms of layout. There is a problem that the area becomes large.

In addition, since electrons are taken in and out by the FN tunnel phenomenon through the gate oxide film of the FN tunneling MOS capacitor C1t, the coupling MOS is used to efficiently adjust the potential of the floating gate Fg1 (improve the coupling ratio). It is necessary to make the capacitance C1c relatively larger than C1t. For example, in order to set the coupling ratio to 0.9, C1c needs a capacity about nine times that of C1t, which causes an increase in the memory cell area.

A floating gate type nonvolatile memory element realized by a standard CMOS process (single-layer poly) disclosed in Japanese Patent Application Laid-Open No. 2006-0666529 (Patent Document 2) is shown in FIGS.

As shown in FIG. 60, this nonvolatile memory element is formed to extend to a P well 23 formed in a P-type substrate and an N well 24 adjacent thereto. In the P-well 23, a selection transistor comprising an n-type diffusion layer 29 and an n-type diffusion layer 30 (RBL) and a gate 26 (RWL) disposed on the channel 32 therebetween via a gate insulating film 25. ST is formed. In the N well 24, an n-type diffusion layer 33 (PWL / Vss) and a p-type diffusion layer 28 (PBL) are formed. A floating gate 27 is formed on the channel extending in the region between the p-type diffusion layer 28 and the n-type diffusion layer 29 via the gate insulating film 25. The floating gate 27, the N well 24 and the n-type diffusion layer 29 on the P well 23 constitute a memory transistor MT, and the N well 24 and the floating gate 27 constitute a capacitor C2. Each node of PBL and PWL constitutes an injector (CJ).

An equivalent circuit of the nonvolatile memory element of FIG. 60 is shown in FIG. FIG. 62 shows voltage application conditions for each node in each operation of standby (STBY), program (PGM), erase (ERS), and read (READ).

In this nonvolatile memory element, a BTBT-HE (Hot Electron) mode generated in an overlap region 31 between the p-type diffusion layer 28 and the floating gate 27 is used as an electron injection operation to the floating gate 27, and the floating gate 27 As an electron extracting operation from the FN tunnel mode, an FN tunnel mode in an overlap region between the n-type diffusion layer 29 and the floating gate 27 is used. Both operations use a phenomenon that occurs not in the entire channel region of the MOS transistor but in the overlap region of the diffusion layer and the floating gate, so that a large MOS type capacitor for improving the coupling ratio is not required, and the cell area is reduced. There is an advantage that it can be made smaller. However, the array operation has a problem that it becomes severe from the viewpoint of the operation margin because disturb stress is applied to the non-selected cells at the time of data writing.

FIG. 63 shows an example in which the nonvolatile memory elements of FIG. 60 are configured in an array. When the upper left cell is selected, 0V is applied to RWL <0>, VCC is applied to PWL <0>, 0V is applied to RWL <1>, and 0V is applied to PWL <1>. -4V is applied to 0>, 0V is applied to RBL <0>, 0V is applied to PBL <1>, and 0V is applied to RBL <1>.

In this state, VCC + 4V is applied as a junction reverse bias to C2 of the selected cell, which contributes to the program operation. On the other hand, a memory cell belonging to the same row as the selected cell has a so-called gate disturb problem, and VCC, which is a junction reverse bias, is applied to C2 and belongs to the same column as the selected cell. A so-called drain disturb problem occurs in the memory cell, and a junction reverse bias of 4 V is applied to C2. These cells are placed in a so-called half-selected state, and disturb stress remains (weak BTBT-HE mode).

US Pat. No. 7,221,596 JP 2006-0666529 A

An object of the present invention is to provide a nonvolatile memory element that solves the above problems and does not cause a significant increase in cell area, but solves the disturb problem.

In order to solve the above problems, in the present invention, a semiconductor substrate, a p-type first well formed on the semiconductor substrate and connected to the first terminal, a second well formed on the first well, and the second terminal A first NMOS transistor and a second NMOS transistor connected in series between the first terminal and the third terminal; an n-type second well formed on the semiconductor substrate and connected to the fourth terminal; And a first PMOS transistor and a second PMOS transistor connected in series between the fifth terminal and the sixth terminal. The gate of the first NMOS transistor is the seventh terminal. The first PMOS transistor constitutes the eighth terminal, the gates of the second NMOS transistor and the second PMOS transistor are connected in common and are in a floating state. To provide a nonvolatile semiconductor memory device which comprises a memory cell (Figure 1).

The nonvolatile semiconductor memory device of the present invention may further include a third well formed on the semiconductor substrate and including the first well and the second well (FIG. 2).

In the nonvolatile semiconductor memory device of the present invention, the fourth well formed in the semiconductor substrate, the fourth well, the ninth terminal, the gate of the second NMOS transistor, and the second PMOS are further formed. A nonvolatile semiconductor memory device including a capacitor connected between the gate of the transistor and the fourth well is a p-type well connected to the ninth terminal; The capacitive element may be an NMOS transistor having a source and a drain commonly connected to the fifth terminal, and a gate connected to the gate of the second NMOS transistor and the gate of the second PMOS transistor (FIG. 40).

In the nonvolatile semiconductor memory device of the present invention, the first NMOS transistor, the second NMOS transistor, the first PMOS transistor, and the second PMOS transistor all have a symmetrical structure of the source and drain diffusion layers. And may have an asymmetric structure. One of the source and drain diffusion layers of the second NMOS transistor and the second PMOS transistor may have an impurity concentration higher than the other of the source and drain.

In the nonvolatile semiconductor memory device of the present invention, the gate of the second NMOS transistor is formed of an n-type polysilicon film, the gate of the second PMOS transistor is formed of a p-type polysilicon film, and the n-type polysilicon film is formed. The area of the polysilicon film and the area of the p-type polysilicon film may be equal, or the areas may be different. The area of the n-type polysilicon film may be larger or smaller than the area of the p-type polysilicon film (FIG. 8).

Furthermore, in the present invention, a memory cell pair comprising a first memory cell and a second memory cell is formed by combining two memory cells, and the seventh terminal of the first memory cell and the second memory cell The seventh terminal of the first memory cell is commonly connected, the eighth terminal of the first memory cell and the eighth terminal of the second memory cell are commonly connected, and the first terminal of the first memory cell That the first terminals of the two memory cells are connected in common, and the fourth terminal of the first memory cell and the fourth terminal of the second memory cell are connected in common to form a memory cell pair. A non-volatile semiconductor memory device is provided. The ninth terminal of the first memory cell and the ninth terminal of the second memory cell may be connected in common (FIG. 22).

Further, in the present invention, a plurality of memory cells are arranged in a matrix, the seventh terminals of the memory cells belonging to the same row are connected in common, and the eighth terminals of the memory cells belonging to the same row are connected. Connected in common, the second terminals of the memory cells belonging to the same column are connected in common, the fifth terminals of the memory cells belonging to the same column are connected in common, and belong to multiple rows and multiple columns The third terminals of the memory cells are connected in common, the sixth terminals of the memory cells belonging to multiple rows and multiple columns are connected in common, and the first terminals of the memory cells belonging to multiple rows and multiple columns are connected in common. A nonvolatile semiconductor memory device is provided in which a memory cell array is configured by commonly connecting the fourth terminals of memory cells belonging to a plurality of rows and a plurality of columns (FIG. 11). The ninth terminals of the memory cells belonging to the same row may be connected in common (FIG. 45).

In the present invention, a plurality of memory cell pairs are arranged in a matrix, the seventh terminals of the memory cell pairs belonging to the same row are connected in common, and the eighth terminals of the memory cell pairs belonging to the same row are connected. May be connected in common (FIG. 27), or the ninth terminals of memory cell pairs belonging to the same row may be connected in common (FIG. 52). ).

The nonvolatile semiconductor memory device of the present invention may further include a sense amplifier that compares the current flowing from the second terminal to the third terminal with a reference current to determine data, and from the sixth terminal A sense amplifier that compares the current flowing to the fifth terminal with a reference current to determine data may be included (FIGS. 17 and 18). Further, data is discriminated by comparing the current flowing from the second terminal of the first memory cell to the third terminal and the current flowing from the second terminal of the second memory cell to the third terminal. A sense amplifier may be included, and a current flowing from the sixth terminal of the first memory cell to the fifth terminal is compared with a current flowing from the sixth terminal of the second memory cell to the fifth terminal. Thus, a sense amplifier for discriminating data may be included (FIGS. 35 and 37).

To achieve the above object, according to the present invention, in a method of using a nonvolatile semiconductor memory device, the nonvolatile semiconductor memory device includes a semiconductor substrate and a p-type first formed on the semiconductor substrate and connected to the first terminal. And a first NMOS transistor and a second NMOS transistor formed in the first well and connected in series between the second terminal and the third terminal, and the fourth well formed in the semiconductor substrate. An n-type second well connected to the terminal, and a first PMOS transistor and a second PMOS transistor formed in the second well and connected in series between the fifth terminal and the sixth terminal The gate of the first NMOS transistor constitutes the seventh terminal, the first PMOS transistor constitutes the eighth terminal, and the second NMOS transistor and the second PMOS transistor The gate includes a memory cell characterized in that the gates are connected in common and are in a floating state, and electrons generated by BTBT-HE in the vicinity of the drain and the gate of the second PMOS transistor are transferred to the second PMOS. Provided is a method of using a nonvolatile semiconductor memory device characterized by being injected into a gate of a transistor.

In the method of using the nonvolatile semiconductor memory device of the present invention, the BTBT-HE injection may be performed while applying a positive voltage to the fourth terminal.

In the method of using the nonvolatile semiconductor memory device of the present invention, the nonvolatile semiconductor memory device includes a semiconductor substrate, a p-type first well formed on the semiconductor substrate and connected to a first terminal, and a first well. A first NMOS transistor and a second NMOS transistor connected in series between the second terminal and the third terminal, and an n-type transistor formed on the semiconductor substrate and connected to the fourth terminal. A first well including a first PMOS transistor and a second PMOS transistor formed in the second well and connected in series between the fifth terminal and the sixth terminal; The gate of the transistor constitutes the seventh terminal, the first PMOS transistor constitutes the eighth terminal, and the gates of the second NMOS transistor and the second PMOS transistor are connected in common. Includes memory cells, characterized in that a floating state, may be performed electrons are extracted by the second FN tunnel current to the drain from the gate of the NMOS transistor.

In the method of using the nonvolatile semiconductor memory device according to the present invention, the gate of the second PMOS transistor of the memory cell is configured in a memory cell array configuration including a plurality of the memory cells in accordance with write data to each memory cell. The injection of electrons into the memory cell and the extraction of electrons from the gate of the second NMOS transistor of the memory cell may be performed simultaneously, or may be performed in separate steps.

To achieve the above object, according to the present invention, in a method of using a nonvolatile semiconductor memory device, the nonvolatile semiconductor memory device includes a semiconductor substrate, and a p-type first semiconductor device formed on the semiconductor substrate and connected to the first terminal. A first NMOS transistor and a second NMOS transistor formed in the first well and connected in series between the second terminal and the third terminal; N-type second well connected to the first terminal, and a first PMOS transistor and a second PMOS formed in the second well and connected in series between the fifth terminal and the sixth terminal The first NMOS transistor constitutes a seventh terminal, the first PMOS transistor constitutes an eighth terminal, the second NMOS transistor and the second PMOS transistor. The memory cell pair includes a plurality of memory cells connected in common and in a floating state, and a memory cell pair including a first memory cell and a second memory cell by combining two memory cells The seventh terminal of the first memory cell and the seventh terminal of the second memory cell are connected in common, and the eighth terminal of the first memory cell and the eighth terminal of the second memory cell are configured. The terminals are connected in common, the first terminal of the first memory cell and the first terminal of the second memory cell are connected in common, the fourth terminal of the first memory cell and the second memory cell Are connected in common to form a memory cell pair, and electrons generated by BTBT-HE in the vicinity of the drain and gate of the second PMOS transistor of the first memory cell are connected to the second terminal. Injected into the gate of the PMOS transistor, The second FN tunnel current to the drain from the gate of the NMOS transistor of the second memory cell provides for the use of a non-volatile semiconductor memory device which is characterized in that the electron withdrawal.

In the method of using the nonvolatile semiconductor memory device of the present invention, electrons are injected into the gate of the second PMOS transistor of the first memory cell and electrons from the gate of the second NMOS transistor of the second memory cell. The drawing may be performed simultaneously or in a separate step.

In the method of using the nonvolatile semiconductor memory device of the present invention, the nonvolatile semiconductor memory device is further formed in the fourth well formed in the semiconductor substrate, the fourth well, the ninth terminal, and the second terminal. And a capacitive element connected between the gate of the NMOS transistor and the gate of the second PMOS transistor.

Thus, the feature of the present invention is that it is possible to realize a configuration in which no disturb stress is applied as an array operation while using the operation mechanism similar to that of Patent Document 2 described above. In addition, since BTBT-HE injection and FN tunnel electron extraction in the present invention can be performed simultaneously, Data “1” and Data “0” can be written simultaneously. This means that an EEPROM capable of rewriting data in byte units can be realized by a standard CMOS process. Since both the BTBT-HE mode and the FN tunnel mode have a small operating current, it is possible to realize an optimum configuration for a system that requires low power consumption.

In the present invention, the write disturb characteristic can be improved while reducing the cell area. By using the pair configuration, the sense margin is increased and the reliability is improved.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. Note that, in the embodiments, the same components are denoted by the same reference numerals, and redundant description among the embodiments is omitted.

A first embodiment of the present invention will be described with reference to FIGS.

As shown in FIG. 1, a memory cell 120 of a nonvolatile semiconductor memory device according to Example 1 of the present invention includes a semiconductor substrate 100, and a p formed on the semiconductor substrate 100 and connected to VPW through a P + diffusion layer 103. A type well (P-well) 101 and an n-type well (N-well) 102 connected to the VNW through an N + diffusion layer 107 are formed.

The NMOS transistor 111 and the NMOS transistor 112 are formed in the well 101 and are connected in series between VDN and VSN. The N + diffusion layer 106 is connected to VDN, and an NMOS transistor 111 is formed between the N + diffusion layer 106 and the N + diffusion layer 105. The N + diffusion layer 104 is connected to the VSN, and an NMOS transistor 112 is formed between the N + diffusion layer 104 and the N + diffusion layer 105.

The PMOS transistor 113 and the PMOS transistor 114 are formed in the well 102 and are connected in series between VDP and VSP. The P + diffusion layer 110 is connected to VDP, and a PMOS transistor 114 is formed between the P + diffusion layer 110 and the P + diffusion layer 109. The P + diffusion layer 108 is connected to VSP, and a PMOS transistor 113 is formed between the P + diffusion layer 108 and the P + diffusion layer 109.

The gate of the NMOS transistor 111 is connected to VGN, the gate of the PMOS transistor 114 is connected to VGP, the gates of the NMOS transistor 112 and the PMOS transistor 113 are commonly connected (short), and the floating gate FG is in a floating state. Function. Data is stored according to the accumulation state of electrons in the floating gate FG.

Electrons are injected into the floating gate FG in bit units from the diffusion layer 109 which is the drain of the PMOS transistor 113 by the BTBT-HE operation. Extraction of electrons from the floating gate FG is performed in units of bits using the FN tunnel current to the diffusion layer 105 which is the drain of the NMOS transistor 112. The potential of VPW is the same as the P-sub potential (GND).

Each diffusion layer of the BTBT-HE injection region (P + diffusion layer 109) and the FN tunnel region (N + diffusion layer 105) has the same structure as the other diffusion layer region (P + diffusion layer 108 and N + diffusion layer 104). Also good. In this case, there exists an effect that manufacture is easy.

Each diffusion layer in the BTBT-HE injection region (P + diffusion layer 109) and the FN tunnel region (N + diffusion layer 105) has a different structure from the other diffusion layer region (P + diffusion layer 108 and N + diffusion layer 104). It is desirable. In this case, in order to improve the BTBT-HE injection efficiency and the FN tunnel efficiency, optimization such as increasing the impurity concentration is possible.

A modification of the first embodiment of the present invention will be described with reference to FIG.

As shown in FIG. 2, the memory cell 120 of the nonvolatile semiconductor memory device according to the modification of the first embodiment of the present invention includes a semiconductor substrate 100 and an n-type well (Bottom N-well) formed in the semiconductor substrate 100. ) 121 and p-type well (P-well) 101 formed in well 121 and connected to VPW through P + diffusion layer 103, and connected to VNW through N + diffusion layer 107. The n-type well (N-well) 102 is formed. That is, the memory cell 120 of Example 2 is formed in a triple well.

An equivalent circuit of the memory cell of Example 1 is shown in FIG. VDN and VDP are terminals connected to a sense amplifier or a write driver, and VSN and VSP are terminals connected to a source line. A selection NMOS transistor (NMOS transistor 111 in FIGS. 1 and 2) whose gate is connected to VGN and an FG-NMOS transistor (NMOS transistor 112 in FIGS. 1 and 2) are connected in series between VDN and VSN. Yes. The selection NMOS transistor and the FG-NMOS transistor are connected to a common well, and the terminal thereof is VPW. A selection PMOS transistor (PMOS transistor 114 in FIGS. 1 and 2) whose gate is connected to VGP and an FG-PMOS transistor (PMOS transistor 113 in FIGS. 1 and 2) are connected in series between VDP and VSP. Yes. The selection PMOS transistor and the FG-PMOS transistor are connected to a common well, and the terminal thereof is VNW. That is, this memory cell is an 8-terminal element of VGN, VGP, VDN, VDP, VSN, VSP, VPW and VNW.

FIG. 4 shows a layout diagram of the memory cell of the first embodiment. VGN, VGP and FG are all formed of the first polysilicon layer (G1), and VPW, VSN, VSP and VNW are all formed of the first metal layer (M1). VDN and VDP that run orthogonal to VPW, VSN, VSP, and VNW are formed of a second metal layer. The layout shown in FIG. 4 is compact, can be highly integrated, and can be realized by a standard CMOS process with one polysilicon layer.

As a transistor constituting the nonvolatile memory element, a transistor having a gate oxide film having a certain thickness is used among transistors that can be realized by a standard CMOS process. For example, an I / O transistor (for example, gate oxide film thickness = about 7 nm) is used.

As described above, the electron injection operation to the floating gate includes the BTBT-HE (Hot Electron) mode generated in the P + diffusion / gate overlap region of the P-type MOS transistor, and the electron extraction operation from the floating gate includes the N-type MOS. The FN tunnel mode in the N + diffusion / gate overlap region of the transistor is used. Since both BTBT-HE injection and FN tunnel electron extraction use a phenomenon that occurs not in the channel region of the MOS transistor but in the overlap region of the diffusion layer and the floating gate, a large MOS type capacitor for improving the coupling ratio is used. There is an advantage that it becomes unnecessary and the cell area can be reduced.

Since the BTBT-HE injection and the FN tunnel electron extraction operation can be executed for each memory cell, it means that data “1” and data “0” can be written for each bit, and the EEPROM can be replaced.

Both BTBT-HE injection and FN tunnel electron extraction are characterized by a small operating current, and an optimal configuration can be realized for a system that requires low power consumption.

For the data, the sense amplifier circuit determines the current value of the N-type MOS transistor MN or the P-type MOS transistor MP determined by the FG potential.

5 to 7 show a data write method for the memory cell according to the first embodiment of the present invention.

FIG. 5 shows an example of an applied voltage when the BTBT-HE injection operation is used. VDN, VGN, VPW, and VSN are all 0V, VDP, and VGP are all negative voltages such as -7V, VNW is 0V, and VSP is 0V or in a high impedance state. As a result, BTBT-HE (Hot Electron) generated in the P + diffusion / gate overlap region of the FG-PMOS can be injected into the floating gate FG.

FIG. 6 is an example of an applied voltage when using the Back Bias assisted BTBT-HE (B4-HE) injection operation. VDN, VGN, VPW, and VSN are all set to 0V, VDP is set to 0V, VGP is set to a negative voltage such as −2V, VNW is set to 6V, VSP is set to 0V, VCC, or a high impedance state. As a result, BTBT-HE (Hot Electron) generated in the P + diffusion / gate overlap region of the FG-PMOS can be injected into the floating gate FG.

FIG. 7 is an example of an applied voltage when electrons are extracted from the FG by the FN tunnel current. VDN and VGN are both 7V, VPW is 0V, VSN is in a high impedance state, VDP, VGP and VNW are 0V, and VSP is 0V or in a high impedance state. As a result, electrons can be extracted from the floating gate FG in the FN tunnel mode in the N + diffusion / gate overlap region of FG-NMO.

FG is commonly connected to FG-NMOS and FG-PMOS. However, in general, the polysilicon constituting the gate of the NMOS transistor is doped with n-type impurities (N + poly), and the polysilicon constituting the gate of the PMOS transistor is doped with p-type impurities (P + poly). FIGS. 8A to 8C show an example of distribution of N + poly and P + poly. FIG. 8A shows an example in which the areas of N + poly and P + poly are substantially equal, and the boundary between N + poly and P + poly comes to the boundary between P well and N well. FIG. 8B shows an example in which the area of P + poly is larger than N + poly, and the P + poly portion protrudes up to the N well. FIG. 8C shows an example in which the area of P + poly is larger than N + poly, and the P + poly portion protrudes up to the N well. Since the retention characteristics of the memory cell are affected by the material of the FG, the structures shown in FIGS. 8A to 8C should be used properly in order to optimize the balance between the characteristics of the FG-NMOS and the FG-PMOS and improve the retention characteristics. Is desirable.

FIG. 9A illustrates the definition of data in the memory cell in the first embodiment. The threshold voltage Vth_M of the FG-NMOS is defined as Data “1” when the threshold voltage Vth_M is lower than the reference voltage Vref (or reference current Iref) on the vertical axis, and Data “0” when higher.

FIG. 9B shows a comparison with the voltage display of FIG. 9A when sensing by the current value.

FIG. 10 shows a data rewrite operation (write operation). Rewriting from data “1” to data “0” raises the threshold of FG-NMOS using BTBT-HE, and rewriting from data “0” to data “1” uses FN. -Lower the NMOS threshold. As described above, data “0” is written by injecting electrons into the floating gate in the BTBT-HE mode generated in the P + diffusion / gate overlap region of FG-PMOS, and data “1” is N + diffusion of FG-NMOS. / Write by extracting electrons from the floating gate in the FN tunnel mode in the gate overlap region. This eliminates the need for an erasing operation like a flash memory, and enables writing of data “0” and data “1” for each bit, thereby realizing a so-called EEPROM specification.

FIG. 11 shows an array configuration of the memory cell of the first embodiment. In this memory array, a plurality of memory cells according to the first embodiment are arranged in a matrix as a cell unit, VGNs of memory cells belonging to the same row are connected in common, and VGPs of memory cells belonging to the same row are respectively connected. The VDNs of memory cells belonging to the same column are connected in common. Further, VDPs of memory cells belonging to the same column are commonly connected, VSNs of memory cells belonging to a plurality of rows and multiple columns are commonly connected, and VSPs of memory cells belonging to a plurality of rows and multiple columns are commonly connected, A memory cell array is configured by commonly connecting VPWs of memory cells belonging to a plurality of rows and columns and connecting VNWs of memory cells belonging to a plurality of rows and columns. VSN, VSP, VPW and VNW are driven as a common signal for memory cells belonging to a plurality of rows and columns.

FIG. 12A is a table showing each potential applied to each terminal in each operation mode of the nonvolatile semiconductor memory device according to the first embodiment. FIG. 12B shows inequalities representing the relationship between the potentials. Here, as a writing method, an example of simultaneously writing Data “0” and Data “1” (simultaneous writing mode, shown in the fifth and sixth columns from the right in the table), Data “0” and Data An example of writing “1” in another step (in different step writing mode, shown in the third and fourth columns from the right in the table) is shown. In addition, two types of reading are also shown: READ (1) sensed from the NMOS side and READ (2) sensed from the PMOS side.

FIG. 13 is a specific example of each potential applied to each terminal in each operation mode of the nonvolatile semiconductor memory device according to the first embodiment. The power supply voltage VCC is 1.8V. In the figure, HiZ indicates a high impedance state.

FIG. 14 shows voltages applied to the respective terminals in the simultaneous write mode and voltages that are simultaneously applied to the rows other than the selected cell at the time of the memory array operation according to the first embodiment. 7 V is applied to VGN of the selected row, −7 V is applied to VGP, and 0 V is applied to VGN and VGP of the other rows, and data “1” of the selected row is written to the cell to be written. In this case, 7 V is applied to VDN and 0 V is applied to VDP, and 0 V is applied to VDN and −7 V is applied to VDP in a cell in which Data “0” is written. VSN and VSP are commonly placed in HiZ, and VPW and VNW are commonly applied with 0V. Data “1” is written by extracting electrons from the floating gate in the FN tunnel mode in the N + diffusion / gate overlap region of the FG-NMOS. Data “0” is written by injecting electrons into the floating gate in the BTBT-HE mode generated in the P + diffusion / gate overlap region of the FG-PMOS. Here, no disturb stress is applied to the non-selected cells. Erasing operation like a flash memory becomes unnecessary, and writing of Data “0” and Data “1” can be realized for each bit, and the EEPROM specification can be realized. Note that two types of positive and negative high voltages are required at the same time, and two charge pump circuits are required.

FIG. 15 and FIG. 16 show voltages applied to the respective terminals in the different step write mode and voltages applied simultaneously to the rows other than the selected cell in the memory array operation in the first embodiment.

FIG. 15 shows voltages that are simultaneously applied to the selected cell and cells other than the selected cell in the writing step of Data “1”. 7V is applied to VGN of the selected row and 0V is applied to VGP, and 0V is applied to VGN and VGP of the other rows. In the column of the selected cell, 7V is applied to VDN and 0V is applied to VDP. In other columns, 0 V is applied to VDN and 0 V is applied to VDP. VSN is placed in HiZ, and 0 V is commonly applied to VSP, VPW, and VNW. Data “1” is written by extracting electrons from the floating gate in the FN tunnel mode in the N + diffusion / gate overlap region of the FG-NMOS. Here, no disturb stress is applied to the non-selected cells.

FIG. 16 shows voltages that are simultaneously applied to the selected cell and cells other than the selected cell in the writing step of Data “0”. 0 V is applied to VGN of the selected row, −7 V is applied to VGP, and 0 V is applied to VGN and VGP of the other rows. In the column of the selected cell, 0 V and VDP are applied to VDN. -7V is applied, and in the other columns, 0V is applied to VDN and 0V is applied to VDP. VSP is placed in HiZ, and 0 V is commonly applied to VSN, VPW, and VNW. Data “0” is written by injecting electrons into the floating gate in the BTBT-HE mode generated in the P + diffusion / gate overlap region of the FG-PMOS. Here, no disturb stress is applied to the non-selected cells.

Even in the separate step write mode as described above, the erase operation as in the flash memory becomes unnecessary, and the writing of Data “0” and Data “1” can be realized for each bit, and the EEPROM specification can be realized. In FIG. 15, only one type of positive high voltage is used, and in FIG. 16, only one type of negative high voltage is used.

FIG. 17 is a diagram showing an operation when reading from the NMOS side (Read (1)). A differential sense amplifier (differential SA) is added, and the current I_MN flowing in the NMOS section is read by comparing with the reference current Iref by this differential SA. A voltage of about 1 V is applied to VDN.

FIG. 18 is a diagram showing the operation when reading from the PMOS side (Read (2)). A differential sense amplifier (differential SA) is added, and the current I_MP flowing in the PMOS section is read and compared with the reference current Iref by this differential SA. A voltage of about 1 V is applied to VDP.

FIG. 19 is a diagram showing an example of the configuration of the differential sense amplifier shown in FIG. 17, and FIG. 20 is a diagram showing an example of the configuration of the differential sense amplifier shown in FIG. , I_MNT corresponds to I_MN, I_MNB corresponds to I_ref, I_MPT corresponds to I_MP, and I_MPB corresponds to I_ref). Both are composed of a current mirror circuit and a bias transistor, and their outputs NT and NB are amplified by a differential amplifier to obtain an output SAOUT.

FIG. 21 shows the entire circuit configuration of the nonvolatile semiconductor memory device using the memory cell of the first embodiment, which is another logic core (DSP, CPU, various drivers, controller logic) configured using standard CMOS. Etc.) is provided as a non-volatile semiconductor memory device macro.

The nonvolatile semiconductor memory device (macro) includes a memory cell array (Memory Array) having the array configuration shown in FIG. 11, a VG driver circuit (VG Driver) for driving VGP and VGN, and VNW, VPW, VSN, and VSP. Connected to VDN and VDP, column selection gate (YG), sense amplifier (Sense Amp) in FIG. 19 or 20, and voltage applied to VDN and VDP at the time of writing And a write driver. Furthermore, it comprises a control circuit (Control Circuit) for controlling these various circuits and a power circuit (Power Circuit) including a charge pump circuit for supplying positive and negative high voltages and the like. The power supply circuit (Power Circuit) may not be included in the macro, and may be shared with other logic cores.

A second embodiment of the present invention will be described with reference to FIGS. In the second embodiment, two memory cells described in the first embodiment are paired to form a memory cell pair, one being a T-side element (first memory cell) and the other being a B-side element (second memory cell). ), Data is written in a complementary manner. In the following description, those not particularly specified are the same as those in the first embodiment.

An equivalent circuit of the memory cell of Example 2 is shown in FIG. T-side elements VDN_T and VDP_T are terminals connected to the sense amplifier or write driver, B-side elements VDN_B and VDP_B are also connected to the sense amplifier or write driver, and VSN and VSP are common source lines. It is a terminal connected to. The MNT transistor and MPT transistor of the T side element share a floating gate FG_T. The MNB transistor and MPB transistor of the B side element share a floating gate FG_B. The N-type selection transistor and MNT transistor of the T-side element, the N-type selection transistor of the B-side element, and the MNB transistor share a common well, and their terminals are VPW. The P-type selection transistor and MPT transistor of the T-side element, the P-type selection transistor of the B-side element, and the MPB transistor share a well, and their terminals are VNW.

A layout diagram of the memory cell of Example 2 is shown in FIG. VGN, VGP, FG_T and FG_B are all formed by the first polysilicon layer (G1), and VPW, VSN, VSP and VNW are all formed by the first metal layer (M1). VDN_T, VDP_T, VDN_B, and VDP_B that run orthogonally to VPW, VSN, VSP, and VNW are formed of a second metal layer. The layout shown in FIG. 23 is compact, can be highly integrated, and can be realized by a standard CMOS process with one polysilicon layer.

The above is a memory cell configuration in which two nonvolatile memory elements (T-side element and B-side element) are connected using VSN, VSP, VPW, and VNW as common wiring, and the data includes the FG_T potential of the T-side element and the B-side element. The current difference between the N-type MOS transistors MNT and MNB caused by the difference in FG_B potential or the current difference between the P-type MOS transistors MPT and MPB is read out by the sense amplifier circuit.

In this way, the pair element configuration increases the sense margin and leads to higher reliability.

FIG. 24A illustrates the definition of data in the memory cell in the first embodiment. The FG-NMOS threshold voltage Vth_M is defined as Data “1” when the MNT threshold is lower than the MNB threshold on the vertical axis, and Data “0” when higher.

FIG. 24B shows a comparison with the voltage display of FIG. 24A when sensing by the current value.

FIG. 25 shows an increase in the margin of the second embodiment compared to the first embodiment. There are variations in the write characteristics of memory cells (variations between process lots, wafers, chips, and chips). Variations between process lots, wafers, and chips can be corrected by tuning the write voltage for each chip, but variations in the chip surface remain. Due to this variation, the write state Vth has a certain distribution width, and the sense margin is determined by the worst bit of each distribution. The sense margin in the first embodiment is Vth_A−Vref or Vref−Vth_B, but the sense margin in the second embodiment is larger than Vth_A−Vth_B. Here, since the pair element exists in a physically close place, the possibility that the Vth of the pair element becomes the worst bit of the in-chip variation is extremely small. Therefore, the sense margin is larger than Vth_A−Vth_B.

FIG. 26 shows a data rewrite operation (write operation). Rewriting from data “1” to data “0” raises the threshold of MNT using BTBT-HE and lowers the threshold of MNB using FN. Rewriting from data “0” to data “1” lowers the MNT threshold using FN and raises the MNB threshold using BTBT-HE. This eliminates the need for an erasing operation like a flash memory, and enables writing of data “0” and data “1” for each bit, thereby realizing a so-called EEPROM specification.

FIG. 27 shows an array configuration of the memory cell of the second embodiment. In this memory array, a plurality of memory cell pairs according to the second embodiment are arranged in a matrix as a cell unit, VGNs of memory cell pairs belonging to the same row are connected in common, and memory cell pairs belonging to the same row are connected. VGPs are connected in common, and VDN_T and VDN_B of memory cell pairs belonging to the same column are connected in common. Also, VDP_T and VDP_B of memory cells belonging to the same column are connected in common, VSNs of memory cells belonging to multiple rows and multiple columns are connected in common, and VSPs of memory cells belonging to multiple rows and multiple columns are connected in common A memory cell array is configured by commonly connecting VPWs of memory cells belonging to a plurality of rows and columns and connecting VNWs of memory cells belonging to a plurality of rows and columns. VSN, VSP, VPW and VNW are driven as a common signal for memory cells belonging to a plurality of rows and columns.

FIG. 28A is a table showing each potential applied to each terminal in each operation mode of the nonvolatile semiconductor memory device according to the second embodiment. FIG. 28B shows inequalities representing the relationship between the potentials. Here, as a writing method, an example of simultaneously writing Data “0” and Data “1” (shown in the seventh and eighth columns from the right in the table), Data “0” and Data “1”. An example of writing “1” in another step (in different step writing mode, shown in the third and sixth columns from the right in the table) is shown. In addition, two types of reading are also shown: READ (1) sensed from the NMOS side and READ (2) sensed from the PMOS side.

FIG. 29 is a specific example of each potential applied to each terminal in each operation mode of the nonvolatile semiconductor memory device according to the second embodiment. The power supply voltage VCC is 1.8V. In the figure, HiZ indicates a high impedance state.

FIG. 30 shows voltages applied to the respective terminals in the simultaneous write mode and voltages that are simultaneously applied to the rows other than the selected cell at the time in the memory array operation in the second embodiment. Here, no disturb stress is applied to the non-selected cells. Erasing operation like a flash memory becomes unnecessary, and writing of Data “0” and Data “1” can be realized for each bit, and the EEPROM specification can be realized. Note that two types of positive and negative high voltages are required at the same time, and two charge pump circuits are required.

FIG. 31 shows a time chart of the write operation shown in FIG.

32 and 33 show voltages applied to the respective terminals in the different step write mode and voltages applied simultaneously to the rows other than the selected cell at the time of the memory array operation in the second embodiment. FIG. 34 shows a time chart of this write operation.

FIG. 32 shows voltages that are simultaneously applied to the selected cell and cells other than the selected cell in the first write step. Here, no disturb stress is applied to the non-selected cells. FIG. 33 shows voltages that are simultaneously applied to the selected cell and cells other than the selected cell in the second write step. Again, no disturb stress is applied to the non-selected cells.

Even in the separate step write mode as described above, the erase operation as in the flash memory becomes unnecessary, and the writing of Data “0” and Data “1” can be realized for each bit, and the EEPROM specification can be realized. In FIG. 32, only one type of positive high voltage is used, and only one type of negative high voltage is used in FIG.

FIG. 35 shows the operation when reading from the NMOS side (Read (1)). A differential sense amplifier (differential SA) is added, and the currents I_MNT and I_MNB flowing through the NMOS parts of the memory cell pair are compared and read by the differential SA. A voltage of about 1 V is applied to VDN. A time chart at this time is shown in FIG.

FIG. 37 is a diagram showing the operation when reading from the PMOS side (Read (2)). A differential type sense amplifier (differential type SA) is added, and the currents I_MPT and I_MPB flowing through the PMOS portions of the memory cell pair are compared and read by the differential type SA. A voltage of about 1 V is applied to VDP. A time chart at this time is shown in FIG.

As the differential sense amplifier, the one shown in FIG. 19 or FIG. 20 is used.

FIG. 39 shows the entire circuit configuration of the nonvolatile semiconductor memory device using the memory cell of the first embodiment, which is another logic core (DSP, CPU, various drivers, controller logic) configured using standard CMOS. Etc.) is provided as a non-volatile semiconductor memory device macro. 21 is different from that shown in FIG. 21 in that a column selection gate (YG), a sense amplifier (Sense Amp), and a write driver (Write Driver) that applies a voltage at the time of writing are connected to VDN_T, VDP_T, VDN_B, and VDP_B. It is that you are.

A third embodiment of the present invention will be described with reference to FIGS. In the following description, those not particularly specified are the same as those in the first and second embodiments.

As shown in FIG. 40, the memory cell 120 of the nonvolatile semiconductor memory device according to the example 3 of the present invention includes a semiconductor substrate 100 and an n-type well (Bottom N-well) formed in the semiconductor substrate 100. ) 121 and p-type well (P-well) 101 formed in well 121 and connected to VPW through P + diffusion layer 103, and connected to VNW through N + diffusion layer 107. The n-type well (N-well) 102 is formed. That is, the memory cell 120 of Example 3 is formed in a triple well. This is partly in common with the structure shown in FIG. 2 as a modification of the first embodiment.

Furthermore, as shown in FIG. 40, an n-type well (Bottom N-well) 123 formed on the p-type semiconductor substrate 100 and connected to the VNWC via the N + diffusion layer 124, and a well 123 is formed. A p-type well (P-well) 122 connected to the VCG via a diffusion layer is formed. In this well 122, an NMOS transistor 127 is formed which includes N + diffusion layers 125 and 126 and a gate formed on the channel region between both via an insulating film. The gate of the NMOS transistor 127 is connected in common to the gate of the NMOS transistor 112 and the gate of the PMOS transistor 113, and functions as a floating gate FG in a floating state. Data is stored according to the accumulation state of electrons in the floating gate FG. The source and drain of the NMOS transistor 127 are commonly connected to VCG. As a result, the NMOS transistor 127 operates as a MOS capacitor (capacitance element).

As described above, an NMOS capacitor for controlling the floating gate potential is added. Since the VCG voltage is both positive and negative, it must be formed in a triple well. Although the cell area is increased, the floating gate potential can be arbitrarily set, so that there is an advantage that the writing speed can be easily increased. Compared with the case where the control gate is not used, it is only necessary to increase the electric field applied to the floating gate / drain overlap region by changing the floating gate potential by about ± 2V. Can be smaller than

FIG. 41 shows an equivalent circuit of the memory cell of the third embodiment. As in the first embodiment, VDN and VDP are terminals connected to a sense amplifier or a write driver, and VSN and VSP are terminals connected to a source line. A selection NMOS transistor (NMOS transistor 111 in FIG. 40) having a gate connected to VGN and an FG-NMOS transistor (NMOS transistor 112 in FIG. 40) are connected in series between VDN and VSN. The selection NMOS transistor and the FG-NMOS transistor are connected to a common well, and the terminal thereof is VPW. A selection PMOS transistor (PMOS transistor 114 in FIG. 40) and an FG-PMOS transistor (NMOS transistor 113 in FIG. 40) whose gates are connected to VGP are connected in series between VDP and VSP. The selection PMOS transistor and the FG-PMOS transistor are connected to a common well, and the terminal thereof is VNW. Further, an NMOS capacitor for control gate (NMOS transistor 127 in FIG. 40) is added, one end is connected to VCG and the other end is connected to FG.

42 to 44 show a data write method of the memory cell according to the third embodiment of the present invention.

FIG. 42 shows an example of applied voltage when the BTBT-HE injection operation is used. VDN, VGN, VPW, and VSN are all 0V, VDP, and VGP are all negative voltages such as -7V, VNW is 0V, and VSP is 0V or in a high impedance state. VCC is applied to VNWC and VCG. As a result, BTBT-HE (Hot Electron) generated in the P + diffusion / gate overlap region of the FG-PMOS can be injected into the floating gate FG.

FIG. 43 is an example of an applied voltage when using a Back Bias assisted BTBT-HE (B4-HE) injection operation. VDN, VGN, VPW, and VSN are all set to 0V, VDP is set to 0V, VGP is set to a negative voltage such as −2V, VNW is set to 6V, VSP is set to 0V, VCC, or a high impedance state. VCC is applied to VNWC and VCG. As a result, BTBT-HE (Hot Electron) generated in the P + diffusion / gate overlap region of the FG-PMOS can be injected into the floating gate FG.

FIG. 44 shows an example of applied voltage when electrons are extracted from FG by FN tunnel current. VDN and VGN are both 7V, VPW is 0V, VSN is in a high impedance state, VDP, VGP and VNW are 0V, and VSP is 0V or in a high impedance state. VCC is applied to VNWC and −2 V is applied to VCG. As a result, electrons can be extracted from the floating gate FG in the FN tunnel mode in the N + diffusion / gate overlap region of FG-NMO.

FIG. 45 shows an array configuration of the memory cell of the third embodiment. In this memory array, a plurality of memory cells of FIG. 40 are arranged in a matrix as a cell unit, VGNs of memory cells belonging to the same row are connected in common, and VGPs of memory cells belonging to the same row are respectively shared. And VDNs of memory cells belonging to the same column are commonly connected to each other. Further, VDPs of memory cells belonging to the same column are commonly connected, VSNs of memory cells belonging to a plurality of rows and multiple columns are commonly connected, and VSPs of memory cells belonging to a plurality of rows and multiple columns are commonly connected, A memory cell array is configured by commonly connecting VPWs of memory cells belonging to a plurality of rows and columns and connecting VNWs of memory cells belonging to a plurality of rows and columns. Further, the VCGs belonging to the same row are connected in common. VNWC, VSN, VSP, VPW and VNW are driven as a common signal for memory cells belonging to a plurality of rows and a plurality of columns.

FIG. 46A is a table showing each potential applied to each terminal in each operation mode of the nonvolatile semiconductor memory device of Example 3. FIG. 46B shows an inequality representing the relationship between the potentials. Two types of reading are shown: READ (1) sensed from the NMOS side and READ (2) sensed from the PMOS side.

FIG. 47 is a specific example of each potential applied to each terminal in each operation mode of the nonvolatile semiconductor memory device according to the third embodiment. The power supply voltage VCC is 1.8V. In the figure, HiZ indicates a high impedance state.

FIG. 48 shows voltages that are simultaneously applied to the selected cell and cells other than the selected cell in the writing step of Data “1”. 7 V is applied to VGN of the selected row, 0 V is applied to VGP, and −2 V is applied to VCG, and 0 V is applied to VGN, VGP, and VCG of the other rows. In the column of the selected cell, 7 V is applied to VDN and 0 V is applied to VDP, and in other columns, 0 V is applied to VDN and 0 V is applied to VDP. VSN is placed in HiZ, and 0 V is commonly applied to VSP, VPW, and VNW. Data “1” is written by extracting electrons from the floating gate in the FN tunnel mode in the N + diffusion / gate overlap region of the FG-NMOS. Here, no disturb stress is applied to cells belonging to another row among the non-selected cells. Of the non-selected cells belonging to the same row as the selected cell, a cell belonging to another column is subjected to a disturb stress of VCG = −2V.

As described above, the erase operation as in the flash memory becomes unnecessary, and the writing of Data “1” can be realized for each bit, and the EEPROM specification can be realized. In order to speed up the electron extraction from the floating gate by the FN tunnel, the selection VCG voltage is set to a negative voltage (for example, −2 V).

FIG. 49 shows voltages that are simultaneously applied to the selected cell and cells other than the selected cell in the writing step of Data “0”. 0 V is applied to VGN of the selected row, −7 V is applied to VGP, VCC is applied to VCG, 0 V is applied to VGN and VGP of the other rows, and VDN is selected in the column of the selected cell. In the other columns, 0V is applied to VDN and 0V is applied to VDP. VSP is placed in HiZ, and 0 V is commonly applied to VNWC, VSN, VPW, and VNW. Data “0” is written by injecting electrons into the floating gate in the BTBT-HE mode generated in the P + diffusion / gate overlap region of the FG-PMOS. Here, no disturb stress is applied to the non-selected cell belonging to another row from the selected cell, but among the non-selected cells belonging to the same row as the selected cell, the cell belonging to another column has VCG. = Disturbance stress for VCC.

As described above, the erase operation as in the flash memory becomes unnecessary, and the writing of Data “0” can be realized for each bit, and the EEPROM specification can be realized. In order to speed up the electron injection into the floating gate by BTBT-HE, the selection VCG voltage is set to a positive voltage (for example, VCC).

FIG. 50 shows the entire circuit configuration of the nonvolatile semiconductor memory device using the memory cell of the third embodiment. Compared with that shown in FIG. 21, a VNW driver (VNW Driver) for VNWC and a VCG driver ( VCG Driver) has been added.

A fourth embodiment of the present invention will be described with reference to FIGS. In the fourth embodiment, two memory cells described in the third embodiment are paired to form a memory cell pair, one being a T-side element (first memory cell) and the other being a B-side element (second memory cell). ), Data is written in a complementary manner. In the following description, those not particularly specified are the same as those in Examples 1, 2, and 3.

An equivalent circuit of the memory cell of Example 4 is shown in FIG. T-side elements VDN_T and VDP_T are terminals connected to the sense amplifier or write driver, B-side elements VDN_B and VDP_B are also connected to the sense amplifier or write driver, and VSN and VSP are common source lines. It is a terminal connected to. The MNT transistor and MPT transistor of the T side element share a floating gate FG_T. The MNB transistor and MPB transistor of the B side element share a floating gate FG_B. The N-type selection transistor and MNT transistor of the T-side element, the N-type selection transistor of the B-side element, and the MNB transistor share a common well, and their terminals are VPW. The P-type selection transistor and MPT transistor of the T-side element, the P-type selection transistor of the B-side element, and the MPB transistor share a well, and their terminals are VNW. Further, the VCG is commonly connected to the other ends of both the T-side and B-side capacitive elements.

The above is a memory cell configuration in which two nonvolatile memory elements (T-side element and B-side element) are connected using VSN, VSP, VPW, and VNW as common wiring, and the data includes the FG_T potential of the T-side element and the B-side element. The current difference between the N-type MOS transistors MNT and MNB caused by the difference in FG_B potential or the current difference between the P-type MOS transistors MPT and MPB is read out by the sense amplifier circuit.

In this way, the pair element configuration increases the sense margin and leads to higher reliability.

FIG. 52 shows an array configuration of the memory cell of the fourth embodiment. In this memory array, a plurality of memory cell pairs according to the third embodiment are arranged in a matrix as a cell unit, VGNs of memory cell pairs belonging to the same row are connected in common, and memory cell pairs belonging to the same row are connected. Each VGP is connected in common. VCGs belonging to the same row are connected in common. VDN_T and VDN_B of memory cell pairs belonging to the same column are connected in common. VDP_T and VDP_B of memory cells belonging to the same column are connected in common, VSNs of memory cells belonging to multiple rows and multiple columns are connected in common, VSPs of memory cells belonging to multiple rows and multiple columns are connected in common, A memory cell array is configured by commonly connecting VPWs of memory cells belonging to a plurality of rows and columns and connecting VNWs of memory cells belonging to a plurality of rows and columns. VNWC, VSN, VSP, VPW and VNW are driven as a common signal for memory cells belonging to a plurality of rows and a plurality of columns.

FIG. 53A is a table showing each potential applied to each terminal in each operation mode of the nonvolatile semiconductor memory device according to the fourth embodiment. FIG. 53B shows inequalities representing the relationship between the potentials. Here, two types of reading are shown: READ (1) sensed from the NMOS side and READ (2) sensed from the PMOS side.

FIG. 54 is a specific example of each potential applied to each terminal in each operation mode of the nonvolatile semiconductor memory device according to the fourth embodiment. The power supply voltage VCC is 1.8V. In the figure, HiZ indicates a high impedance state.

FIG. 55 shows voltages that are simultaneously applied to the selected cell and cells other than the selected cell in the first write step. Only the FN operation is performed as step 1 of the two-step method. In order to speed up the electron extraction from the floating gate by the FN tunnel, the selection VCG voltage is set to a negative voltage (for example, −2 V). Here, no disturb stress is applied to unselected cells belonging to a different row from the selected cell.

FIG. 56 shows voltages that are simultaneously applied to the selected cell and cells other than the selected cell in the second write step. Only the BTBT-HE operation is performed as step 2 of the 2-step method. In order to speed up the electron injection into the floating gate by BTBT-HE, the selection VCG voltage is set to a positive voltage (for example, VCC). Again, no disturb stress is applied to unselected cells belonging to a different row from the selected cell.

Even in the above writing method, the erase operation as in the flash memory is not required, and writing of Data “0” and Data “1” can be realized for each bit, and the EEPROM specification can be realized. In FIG. 55, only one type of positive high voltage is used, and in FIG. 56, only one type of negative high voltage is used. Therefore, it is possible to share a charge pump.

FIG. 57 shows the entire circuit configuration of a nonvolatile semiconductor memory device using the memory cell of Example 4, which is another logic core (DSP, CPU, various drivers, controller logic) configured using standard CMOS. Etc.) is provided as a non-volatile semiconductor memory device macro. The difference from FIG. 52 is that a column selection gate (YG), a sense amplifier (Sense Amp), and a write driver (Write Driver) that applies a voltage at the time of writing are connected to VDN_T, VDP_T, VDN_B, and VDP_B. .

FIG. 58 is a table showing a comparison between the conventional example and the embodiment of the present invention. Conventional Example 1 is a cell structure described in US Pat. No. 7,221,596 (Patent Document 1), and Conventional Example 2 is a cell structure described in Japanese Patent Application Laid-Open No. 2006-0666529 (Patent Document 2). Conventional Examples 1 and 2 and Examples 1 to 4 of the present invention were compared and examined in terms of cell configuration, cell area ratio, write method, write voltage, charge pump type, write speed, write disturb level, and sense margin. Also from this chart, it can be understood that in the present invention, the write disturb characteristic can be improved while reducing the cell area, and that the sense margin is increased and the reliability is improved by the pair configuration.

The present invention can be applied to a nonvolatile memory device and a logic product in which the nonvolatile memory device is embedded.

3 is a cross-sectional view of the memory cell of Example 1. FIG. 6 is a cross-sectional view of a memory cell according to a modification of Example 1. FIG. 3 is an equivalent circuit diagram of the memory cell of Example 1. FIG. 3 is a layout diagram of a memory cell according to Embodiment 1. FIG. 3 is an equivalent circuit diagram of the memory cell of Example 1. FIG. 3 is an example of a data write method for a memory cell according to the first embodiment. 3 is an example of a data write method for a memory cell according to the first embodiment. FIG. 5 is a layout diagram showing distribution of gate polysilicon layers of memory cells. It is the figure which showed the definition of data. It is the chart which showed contrast in current sense. It is a figure showing data rewrite operation (write operation). 3 is an array configuration diagram of a memory cell according to Embodiment 1. FIG. 3 is a table showing each potential applied to each terminal in each operation mode of the nonvolatile semiconductor memory device of Example 1. It is an inequality showing the relationship of each electric potential of FIG. 12A. 3 is a specific example of each potential applied to each terminal in each operation mode of the nonvolatile semiconductor memory device of Example 1. FIG. FIG. 6 is a diagram illustrating an operation when data “1” and “0” are simultaneously written in the first embodiment. FIG. 6 is a diagram illustrating an operation when data “1” is written in the first embodiment. FIG. 6 is a diagram illustrating an operation when data “0” is written in the first embodiment. It is the figure which showed the operation | movement at the time of the reading using the electric current which flows into NMOS. It is the figure which showed the operation | movement at the time of the reading using the electric current which flows into PMOS. It is the figure which showed an example of the structure of the differential type sense amplifier in the case of determining using the electric current which flows into NMOS. It is the figure which showed an example of the structure of the differential type sense amplifier in the case of determining using the electric current which flows into PMOS. 1 is an overall configuration diagram of a non-volatile semiconductor storage device macro using a memory cell of Example 1. FIG. 6 is an equivalent circuit diagram of the memory cell of Example 2. FIG. 6 is a layout diagram of a memory cell according to Embodiment 2. FIG. It is the figure which showed the definition of the data in a pair element structure. It is the chart which showed contrast in current sense. It is the figure which contrasted the sense margin of Example 1 and Example 2. FIG. It is the figure which showed the definition of data rewriting. 6 is an array configuration diagram of a memory cell according to Embodiment 2. FIG. 10 is a table showing each potential applied to each terminal in each operation mode of the nonvolatile semiconductor memory device of Example 2. It is an inequality showing the relationship of each electric potential of FIG. 28A. 6 is a specific example of each potential applied to each terminal in each operation mode of the nonvolatile semiconductor memory device according to the second embodiment. In Example 2, it is the figure which showed the operation | movement in the case of writing data "1" and "0" simultaneously. In Example 2, it is a time chart at the time of writing data "1" and "0" simultaneously. In Example 2, it is the figure which showed the write-in operation | movement by FN tunnel operation | movement. In Example 2, it is the figure which showed the write-in operation | movement by BTBT-HE operation | movement. In Example 2, it is a time chart in the case of implementing FN tunnel operation | movement and BTBT-HE operation | movement in write-in operation | movement separately. It is the figure which showed the operation | movement at the time of the reading using the electric current difference which flows into NMOS. It is a time chart at the time of reading using the current difference which flows into NMOS. It is the figure which showed the operation | movement at the time of the reading using the current difference which flows into PMOS. It is a time chart at the time of reading using the current difference which flows into PMOS. FIG. 6 is an overall configuration diagram of a nonvolatile semiconductor memory device macro using a memory cell of Example 2. 6 is a cross-sectional view of a memory cell of Example 3. FIG. 6 is an equivalent circuit diagram of the memory cell of Example 3. FIG. 10 is an example of a data writing method by a BTBT-HE operation of a memory cell according to Embodiment 3; 10 is an example of a data writing method by a BTBT-HE operation of a memory cell according to Embodiment 3; 10 is an example of a data writing method using an FN tunnel of a memory cell according to Embodiment 3; 6 is an array configuration diagram of a memory cell according to Embodiment 3. FIG. 12 is a table showing each potential applied to each terminal in each operation mode of the nonvolatile semiconductor memory device of Example 3. It is an inequality showing the relationship of each electric potential of FIG. 46A. 12 is a specific example of each potential applied to each terminal in each operation mode of the nonvolatile semiconductor memory device according to the third embodiment. FIG. 10 is a diagram illustrating an operation when data “1” is written in the third embodiment. FIG. 10 is a diagram illustrating an operation when data “0” is written in the third embodiment. FIG. 6 is an overall configuration diagram of a nonvolatile semiconductor memory device macro using a memory cell of Example 3. 6 is an equivalent circuit diagram of a memory cell according to Embodiment 4. FIG. FIG. 10 is an array configuration diagram of a memory cell according to a fourth embodiment. 10 is a table showing each potential applied to each terminal in each operation mode of the nonvolatile semiconductor memory device of Example 4. 53B is an inequality representing the relationship between the potentials in FIG. 53A. FIG. 10 is a specific example of each potential applied to each terminal in each operation mode of the nonvolatile semiconductor memory device of Example 4. FIG. In Example 4, it is the figure which showed the write-in operation | movement by FN tunnel operation | movement. In Example 4, it is the figure which showed the write-in operation | movement by BTBT-HE operation | movement. FIG. 6 is an overall configuration diagram of a nonvolatile semiconductor memory device macro using a memory cell of Example 4; It is the graph which showed the contrast in a conventional example and the effect of this invention. FIG. 6 is a diagram showing a configuration of a memory cell of Conventional Example 1. FIG. 10 is a diagram showing a configuration of a memory cell of Conventional Example 2. 10 is an equivalent circuit diagram of a memory cell of Conventional Example 2. FIG. FIG. 10 is a diagram showing a voltage application relationship during operation of the memory cell of Conventional Example 2. FIG. 10 is a diagram showing an operation at the time of writing in the memory cell of Conventional Example 2.

Explanation of symbols

100 Semiconductor substrate 101 p-type well (P-well)
102 n-type well (N-well)
103, 108, 109, 110 P + diffusion layers 104, 105, 106, 107 N + diffusion layers 111, 112 NMOS transistors 113, 114 PMOS transistors 120 Memory cells

Claims (30)

A semiconductor substrate;
A p-type first well formed on the semiconductor substrate and connected to a first terminal;
A first NMOS transistor and a second NMOS transistor formed in the first well and connected in series between a second terminal and a third terminal;
An n-type second well formed on the semiconductor substrate and connected to a fourth terminal;
A first PMOS transistor and a second PMOS transistor formed in the second well and connected in series between a fifth terminal and a sixth terminal;
The gate of the first NMOS transistor constitutes a seventh terminal, the first PMOS transistor constitutes an eighth terminal, and the gates of the second NMOS transistor and the second PMOS transistor are shared. A non-volatile semiconductor memory device comprising: a memory cell that is connected and is in a floating state. The nonvolatile semiconductor memory device according to claim 1, further comprising:
A non-volatile semiconductor memory device comprising: a third well formed on the semiconductor substrate and including the first well and the second well. The nonvolatile semiconductor memory device according to claim 1, further comprising:
A fourth well formed in the semiconductor substrate;
A nonvolatile element formed in the fourth well and connected between a ninth terminal and a gate of the second NMOS transistor and a gate of the second PMOS transistor; Semiconductor memory device.   4. The nonvolatile semiconductor memory device according to claim 3, wherein the fourth well is a p-type well connected to the ninth terminal, and the capacitive element has a source and a drain commonly connected to the fifth terminal. A non-volatile semiconductor memory device, characterized in that the gate is an NMOS transistor connected to the gate of the second NMOS transistor and the gate of the second PMOS transistor.   5. The nonvolatile semiconductor memory device according to claim 1, wherein each of the first NMOS transistor, the second NMOS transistor, the first PMOS transistor, and the second PMOS transistor is a source. A non-volatile semiconductor memory device, wherein the drain diffusion layer has a symmetrical structure.   5. The nonvolatile semiconductor memory device according to claim 1, wherein source and drain diffusion layers of the second NMOS transistor and the second PMOS transistor have an asymmetric structure. A nonvolatile semiconductor memory device.   7. The nonvolatile semiconductor memory device according to claim 6, wherein one of the source and drain diffusion layers of the second NMOS transistor and the second PMOS transistor has a higher impurity concentration than the other of the source and drain. A nonvolatile semiconductor memory device.   5. The nonvolatile semiconductor memory device according to claim 1, wherein a gate of the second NMOS transistor is formed of an n-type polysilicon film, and a gate of the second PMOS transistor is a p-type polysilicon. A nonvolatile semiconductor memory device comprising a silicon film, wherein an area of the n-type polysilicon film is equal to an area of the p-type polysilicon film.   5. The nonvolatile semiconductor memory device according to claim 1, wherein a gate of the second NMOS transistor is formed of an n-type polysilicon film, and a gate of the second PMOS transistor is a p-type polysilicon. A nonvolatile semiconductor memory device comprising a silicon film, wherein an area of the n-type polysilicon film is different from an area of the p-type polysilicon film.   10. The nonvolatile semiconductor memory device according to claim 9, wherein an area of the n-type polysilicon film is larger than an area of the p-type polysilicon film.   10. The nonvolatile semiconductor memory device according to claim 9, wherein an area of the n-type polysilicon film is smaller than an area of the p-type polysilicon film.   3. The nonvolatile semiconductor memory device according to claim 1, wherein two memory cells are combined to form a memory cell pair composed of a first memory cell and a second memory cell. The seventh terminal and the seventh terminal of the second memory cell are commonly connected, and the eighth terminal of the first memory cell and the eighth terminal of the second memory cell are connected to each other. Connected in common, the first terminal of the first memory cell and the first terminal of the second memory cell are connected in common, the fourth terminal of the first memory cell and the A non-volatile semiconductor memory device, wherein a memory cell pair is configured by commonly connecting the fourth terminals of second memory cells.   4. The nonvolatile semiconductor memory device according to claim 3, wherein two memory cells are combined to form a memory cell pair including a first memory cell and a second memory cell, and the first memory cell includes the first memory cell pair. 7 terminal and the seventh terminal of the second memory cell are connected in common, and the eighth terminal of the first memory cell and the eighth terminal of the second memory cell are connected in common. And connecting the first terminal of the first memory cell and the first terminal of the second memory cell in common, and connecting the fourth terminal of the first memory cell and the second terminal of the first memory cell. The fourth terminals of the memory cells are commonly connected, and the ninth terminal of the first memory cell and the ninth terminal of the second memory cell are commonly connected to form a memory cell pair. A non-volatile semiconductor memory device characterized by comprising.   3. The nonvolatile semiconductor memory device according to claim 1, wherein a plurality of the memory cells are arranged in a matrix, the seventh terminals of the memory cells belonging to the same row are connected in common, and the same row The eighth terminals of the memory cells belonging to the same column are commonly connected, the second terminals of the memory cells belonging to the same column are commonly connected, and the eighth terminals of the memory cells belonging to the same column are connected. 5 terminals are commonly connected, the third terminals of the memory cells belonging to multiple rows and multiple columns are commonly connected, and the sixth terminals of the memory cells belonging to the multiple rows and multiple columns are commonly connected. Connecting the first terminals of the memory cells belonging to the plurality of rows and columns to the memory cell array by commonly connecting the fourth terminals of the memory cells belonging to the plurality of rows and columns. Structure The nonvolatile semiconductor memory device, characterized in that the.   4. The non-volatile semiconductor memory device according to claim 3, wherein a plurality of the memory cells are arranged in a matrix, the seventh terminals of the memory cells belonging to the same row are connected in common, and belong to the same row. The eighth terminals of the memory cells are connected in common, the second terminals of the memory cells belonging to the same column are connected in common, and the fifth terminals of the memory cells belonging to the same column are connected. Respectively connecting the terminals in common, connecting the ninth terminals of the memory cells belonging to the same row in common, connecting the third terminals of the memory cells belonging to a plurality of rows and multiple columns in common, The sixth terminals of the memory cells belonging to the multiple rows and multiple columns are connected in common, the first terminals of the memory cells belonging to the multiple rows and multiple columns are connected in common, and the multiple rows and multiple columns are connected. Before belonging The nonvolatile semiconductor memory device, characterized in that to constitute a memory cell array by connecting the fourth terminal of the memory cell in common.   13. The nonvolatile semiconductor memory device according to claim 12, wherein a plurality of the memory cell pairs are arranged in a matrix, the seventh terminals of the memory cell pairs belonging to the same row are connected in common, and the same row A nonvolatile semiconductor memory device, wherein the eighth terminals of the memory cell pairs belonging to each are connected in common.   14. The nonvolatile semiconductor memory device according to claim 13, wherein a plurality of the memory cell pairs are arranged in a matrix, the seventh terminals of the memory cell pairs belonging to the same row are connected in common, and the same row A nonvolatile semiconductor memory device characterized in that the eighth terminals of the memory cell pairs belonging to each are connected in common and the ninth terminals of the memory cell pairs belonging to the same row are connected in common .   5. The nonvolatile semiconductor memory device according to claim 1, further comprising a sense amplifier that determines data by comparing a current flowing from the second terminal to the third terminal with a reference current. A non-volatile semiconductor memory device.   5. The nonvolatile semiconductor memory device according to claim 1, further comprising a sense amplifier that determines data by comparing a current flowing from the sixth terminal to the fifth terminal with a reference current. A non-volatile semiconductor memory device.   14. The nonvolatile semiconductor memory device according to claim 12, further comprising: a current flowing from the second terminal of the first memory cell to the third terminal; and a current of the second memory cell. A non-volatile semiconductor memory device, comprising: a sense amplifier that compares data flowing from the second terminal to the third terminal to determine data.   14. The nonvolatile semiconductor memory device according to claim 12, further comprising: a current flowing from the sixth terminal of the first memory cell to the fifth terminal; and the second memory cell. A non-volatile semiconductor memory device, comprising: a sense amplifier that compares data flowing from the sixth terminal to the fifth terminal to determine data. In a method of using a nonvolatile semiconductor memory device,
The non-volatile semiconductor memory device includes a semiconductor substrate, a p-type first well formed on the semiconductor substrate and connected to a first terminal, the first well, a second terminal, A first NMOS transistor and a second NMOS transistor connected in series between three terminals, an n-type second well formed on the semiconductor substrate and connected to a fourth terminal, and the second NMOS transistor And a first PMOS transistor and a second PMOS transistor connected in series between the fifth terminal and the sixth terminal, the gate of the first NMOS transistor being the seventh The first PMOS transistor constitutes an eighth terminal, the gates of the second NMOS transistor and the second PMOS transistor are connected in common, and It includes a memory cell, characterized in that in a grayed state,
A method of using a non-volatile semiconductor memory device, wherein electrons generated by BTBT-HE are injected into the gate of the second PMOS transistor in the vicinity of the drain and gate of the second PMOS transistor. The method for using the nonvolatile semiconductor memory device according to claim 22,
The method of using a nonvolatile semiconductor memory device, wherein the implantation is performed while applying a positive voltage to the fourth terminal. In a method of using a nonvolatile semiconductor memory device,
The non-volatile semiconductor memory device includes a semiconductor substrate, a p-type first well formed on the semiconductor substrate and connected to a first terminal, the first well, a second terminal, A first NMOS transistor and a second NMOS transistor connected in series between three terminals, an n-type second well formed on the semiconductor substrate and connected to a fourth terminal, and the second NMOS transistor And a first PMOS transistor and a second PMOS transistor connected in series between the fifth terminal and the sixth terminal, the gate of the first NMOS transistor being the seventh The first PMOS transistor constitutes an eighth terminal, the gates of the second NMOS transistor and the second PMOS transistor are connected in common, and It includes a memory cell, characterized in that in a grayed state,
A method of using a nonvolatile semiconductor memory device, wherein electrons are extracted from the gate to the drain of the second NMOS transistor by an FN tunnel current.   25. The method of using a nonvolatile semiconductor memory device according to claim 22, wherein in the memory cell array configuration including a plurality of the memory cells, the second PMOS of the memory cells in accordance with write data to each memory cell. A method of using a nonvolatile semiconductor memory device, wherein injection of electrons into the gate of a transistor and extraction of electrons from the gate of the second NMOS transistor of the memory cell are performed simultaneously.   25. The method of using a nonvolatile semiconductor memory device according to claim 22, wherein in the memory cell array configuration including a plurality of the memory cells, the second PMOS of the memory cells in accordance with write data to each memory cell. A method of using a nonvolatile semiconductor memory device, wherein injection of electrons into the gate of a transistor and extraction of electrons from the gate of the second NMOS transistor of the memory cell are performed in separate steps. In a method of using a nonvolatile semiconductor memory device,
The non-volatile semiconductor memory device includes a semiconductor substrate, a p-type first well formed on the semiconductor substrate and connected to a first terminal, the first well, a second terminal, A first NMOS transistor and a second NMOS transistor connected in series between three terminals, an n-type second well formed on the semiconductor substrate and connected to a fourth terminal, and the second NMOS transistor And a first PMOS transistor and a second PMOS transistor connected in series between the fifth terminal and the sixth terminal, the gate of the first NMOS transistor being the seventh The first PMOS transistor constitutes an eighth terminal, the gates of the second NMOS transistor and the second PMOS transistor are connected in common, and A plurality of memory cells, wherein two memory cells are combined to form a memory cell pair consisting of a first memory cell and a second memory cell, and the first memory cell The seventh terminal of the second memory cell and the seventh terminal of the second memory cell are connected in common, and the eighth terminal of the first memory cell and the eighth terminal of the second memory cell. Are connected in common, the first terminal of the first memory cell and the first terminal of the second memory cell are connected in common, and the fourth terminal of the first memory cell The fourth terminals of the second memory cells are connected in common to form a memory cell pair, and BTBT-HE is used in the vicinity of the drain and gate of the second PMOS transistor of the first memory cell. The generated electrons are converted into the second PM. It was injected into the gate of the transistor S,
A method of using a nonvolatile semiconductor memory device, wherein electrons are extracted from a gate to a drain of the second NMOS transistor of the second memory cell by an FN tunnel current.   28. The method of using a nonvolatile semiconductor memory device according to claim 27, wherein electrons are injected into a gate of the second PMOS transistor of the first memory cell, and the second NMOS transistor of the second memory cell. A method for using a nonvolatile semiconductor memory device, wherein electrons are extracted from a gate at the same time.   28. The method of using a nonvolatile semiconductor memory device according to claim 27, wherein electrons are injected into a gate of the second PMOS transistor of the first memory cell, and the second NMOS transistor of the second memory cell. A method of using a nonvolatile semiconductor memory device, wherein extraction of electrons from a gate is performed in a separate step. 30. The method of using a nonvolatile semiconductor memory device according to claim 29, wherein the nonvolatile semiconductor memory device is further formed in a fourth well formed in the semiconductor substrate and in the fourth well, A method of using a nonvolatile semiconductor memory device, comprising: a terminal; and a capacitor connected between the gate of the second NMOS transistor and the gate of the second PMOS transistor.