JP3417974B2 - Nonvolatile storage element and nonvolatile storage device using the same - Google Patents

Description

Detailed Description of the Invention

[0001]

The present invention relates to relates to the non-volatile storage equipment utilizing nonvolatile memory elements and the same.

[0002]

2. Description of the Related Art In recent years, with the development of the semiconductor industry, there has been a demand for integration of non-volatile memory devices which semi-permanently store information. In order to meet this demand, it is possible to improve the degree of integration of the memory cell circuit. Therefore, conventionally, so-called MONOS (metal oxide nitri) is used to store information by injecting and extracting charges.
A nonvolatile memory element having a de oxide silicon) structure has been proposed. A nonvolatile memory element having such a MONOS structure is disclosed in, for example, "A True Single-Transistor O
xide-Nitride-Oxide EEPROM Device (IEEE ELECTRON DEV
ICE LETTERS, VOL.EDL-8, NO.3, MARCH 1987 PP93-95) ''
Is disclosed in.

FIG. 8 is a schematic sectional view showing a structure of a nonvolatile memory element having a MONOS structure. As shown in FIG. 8, this non-volatile memory element has a P-type silicon substrate 10
An N ⁺ type source region 10b and an N ⁺ type drain region 10c, which are formed on the surface layer of the silicon substrate 10 with a predetermined space, and a source region 10b and a drain region 1.
ON and an ONO (oxide nitride oxide) film 11 formed on the channel region 10a.
The gate electrode 12 (W) formed on the O film 11 is provided.

The gate electrode 12 is covered with an interlayer insulating film 13, and a bit line 15 (B) is formed on the interlayer insulating film 13 through a contact hole 14 so that a drain region 1 is formed.
It is in contact with 0c. In addition, in the following description, the nonvolatile memory element is referred to as a “memory transistor”.

FIG. 9 is an equivalent circuit diagram showing an electrical configuration of a nonvolatile memory device using a memory transistor having a MONOS structure. As shown in FIG. 9, this nonvolatile memory device has the MONOS structure shown in FIG.
Memory transistors 1A, 1B, 1 having NO film M
Memory cells 2A, 2B, 2C, consisting of C and 1D only
The 2Ds are arranged in a matrix along the row direction X and the column direction Y.

[0006] Memory cells 2A are arranged along the row direction X, 2B and 2C, the memory transients scan data in 2D
1 A, 1B and 1C, the gate of 1D, and the word lines W1, W2 are connected, respectively, memory cells 2A are arranged along the column direction Y, 2C and 2B, 2
Memory transistors 1A, 1C and 1B, 1D in D
The bit lines B1 and B2 are connected to the drains of, respectively. Further, each memory cell 2A, 2B, 2C,
The source line S is used as the source of the memory transistors 1A, 1B, 1C and 1D in the 2D, and the substrate line S is used as the substrate.
The UBs are commonly connected.

FIG. 9 and Table 1 show each operation of writing, erasing and reading of information in the nonvolatile memory device.
Will be described with reference to. Note that Table 1 assumes the case where the memory cell 1A shown in FIG. 9 is selected during each of write, erase, and read operations.

[0008]

[Table 1]

<Write> In order to select the memory cell 2A by applying 0V to the source line S and the substrate line SUB respectively, and applying 10V to the word line W1 to which the memory cell 2A is connected. , 9V is applied to the bit line B1 to which the memory cell 2A is connected. Meanwhile, 0V is applied to the word line W2 connected to the unselected memory cells 2B and 2D, and 0V is applied to the bit line B2 connected to the unselected memory cells 2B and 2D.

Then, electrons are injected into the ONO film M of the memory transistor 1A in the memory cell 2A, and the memory cell 2A is in the information writing state. <Erase> 0 V is applied to the source line S and the substrate line SUB, and −6 V is applied to the word line W1 connected to the memory cell 2A,
To select the memory cell 2A, 9V is applied to the bit line B1 connected to the memory cell 2A, and 0 is applied to the other word lines W2 and B2.
Apply V.

Then, holes are injected into the ONO film M of the memory transistor 1A in the memory cell 2A.
As a result, the electrons accumulated in the ONO film M of the memory transistor 1A are neutralized and the memory cell 2A
The information stored in is erased. <Read> 0V is applied to the source line S and the substrate line SUB, respectively, and 3 is applied to the word line to which the memory cell 2A to be read is connected.
Since V is applied to select the memory cell 2A, 1V is applied to the bit line B1 to which the memory cell 2A is connected.
Then, 0V is applied to the bit line B2 connected to the unselected memory cells 2B and 2D, and 0V is applied to the word line W2 connected to the unselected memory cells 2C and 2D.

Then, if the information in which the electrons are accumulated in the ONO film M of the memory transistor 1A in the memory cell 2A is in the written state, the memory transistor 1
There is no conduction between the source and drain of A, and no current flows in the memory cell 2A. On the other hand, in the erased state of information in which electrons are not accumulated in the ONO film M of the memory transistor 1A in the memory cell 2A, the source-drain of the memory transistor 1A becomes conductive, and a current flows in the memory cell 2A. By sensing this state, the information stored in the memory cell 2A can be read.

In the following description, the memory transistors 1A, 1B, 1C and 1D are collectively referred to as "memory transistor 1". FIG. 10 is a diagram showing the operating principle of the memory transistor during writing, and FIG. 11 is a diagram showing the operating principle of the memory transistor during erasing. Figure 1
The information writing and erasing operations of the memory transistor 1 will be described in detail with reference to FIGS. <Writing> At the time of writing information, as shown in FIG. 10, 0 V is applied to the source region 10b of the memory transistor 1 and the silicon substrate 10, respectively, and 10 V is applied to the gate electrode 12 and 9 V to the drain region 10c. When each is applied, a positive saturated channel current flows between the source and the drain. In the pinch off region near the drain region 10c, electrons accelerated by the high electric field cause ionization (impact ionization),
Electrons having high energy, so-called hot electrons are generated, and these hot electrons are locally injected into the ONO film 11. As a result, the memory transistor 1 is in the written state. <Erase> When erasing information, as shown in FIG.
When 0V is applied to the source region 10b of the memory transistor 1 and the silicon substrate 30 respectively, and -6V is applied to the gate electrode 12 and 9V is applied to the drain region 10c, a negative saturated channel current is generated between the source and the drain. Flowing. Hot holes are generated near the drain region 10c, and these hot holes are injected into the ONO film 11. Then, in the ONO film 11, the accumulated electrons and the injected holes are electrically coupled, and the electrons are neutralized. As a result, the memory transistor 1 enters the erased state.

[0014]

FIG. 12 shows the write / erase characteristics of the above memory transistor. In FIG. 12, the vertical axis represents both the threshold voltage in the read state and the drain current, and the horizontal axis represents the write / erase count. As is apparent from FIG. 12, in the above memory transistor, since writing and erasing are locally performed, writing / writing
When the erase count (hereinafter referred to as “rewrite count”) is about 1000, no deterioration of the device is observed, but the rewrite count is 4
When it reaches about 0000 times, it is turned on due to stress
Due to the deterioration of the O film, the erased state or the on-state characteristic is lowered. Such device deterioration is caused by ONO
This can be prevented by reducing the stress on the film, and the number of rewritable times can be increased.

Therefore, in order to reduce the stress on the ONO film at the time of erasing, FN (Fowle) is applied between the gate and the substrate.
It is said that it is effective to generate an r-Nordheim) tunnel current and to inject holes into the entire ONO film by this FN tunnel current to perform erasing. By the way, the ONO film 11 is made of Si as shown in FIGS.
Trap nitride film 11b made of ₃ N ₄ and trapping charges
Is sandwiched by a bottom oxide film 11c made of SiO ₂ capable of tunneling charges and a top oxide film 11a preventing charge penetration, and has a so-called sandwich structure. That is, the ONO film 11 has a structure for confining the injected charges for a long time.

However, at the time of writing, as shown in FIG. 13, hot electrons generated near the drain region 10c are generated in the drain region 1 of the nitride film 11b.
It is locally injected to the 0c side. Therefore, one ONO
In the film 11, a writing area A into which electrons are injected,
The non-writing area B into which electrons are not injected is mixed. As described above, in the state where the writing area A and the non-writing area B are mixed, as described above, the gate 12-the substrate 1
When a high electric field is applied between 0 and holes are entirely injected into the ONO film by an FN tunnel current, erasing is performed.
As shown in FIG. 4, in the write region A, the nitride film 11b is formed.
The electrons accumulated in the area are neutralized by the holes to be in the erased state, but in the non-write area B, the holes are accumulated in the nitride film 11b, resulting in a so-called over-erased state. If this overerasure occurs, punch through
(punch through) Breakdown of breakdown voltage occurs.

[0017] The present invention has been made in view of the above, the prevent over erase, and aims <br/> provide nonvolatile storage equipment utilizing nonvolatile memory elements and which can be improved rewritable times To do.

[0018]

A non-volatile memory element according to the present invention for achieving the above object stores information by injecting and extracting electric charges, and is predetermined. A semiconductor substrate having a first conductivity type and a source region and a drain region having a second conductivity type opposite to the first conductivity type and formed at a predetermined distance in a surface layer of the semiconductor substrate. , A trap nitride film which is formed on the drain region side partial region of the channel region generated so as to be sandwiched between the source region and the drain region, and which stores the charge generated in the channel region.
A charge storage film having, formed on the remaining region of the channel region, a gate insulating film capable of tunneling the charges generated in the channel region, and a gate electrode formed on the gate insulating film and the charge storage film is Dressings containing. Well
In addition, the nonvolatile memory element according to the present invention has injected charges.
Information is stored by taking it out or taking it out.
And a semiconductor substrate having a predetermined first conductivity type
And formed on the surface layer of the semiconductor substrate with a predetermined gap
And a second conductivity type opposite to the first conductivity type described above.
Source region and drain region, and the above source region
And the channel region that occurs between the drain region
Formed on a part of the drain region side of the region
A charge storage film for storing charges generated in the region,
If it is provided in the entire channel region, one
Polarized charge is locally injected to write area and non-write area
And the charge of the other polarity is injected into the entire area during erase.
Causes the over-erased state in the non-written area.
Formed on the load storage film and the rest of the above channel region.
This allows the charge generated in the channel region to tunnel.
On the gate insulating film and the charge storage film.
The formed gate electrode is included. For the above charge storage film
Write information using hot electron or hot
It may be performed by injecting holes.

In the non-volatile memory device using the non-volatile memory element, the non-volatile memory elements are formed in a matrix on the semiconductor substrate along the row direction and the column direction, and along the row direction. A word line is connected to the gate electrode of each non-volatile memory element arranged in a row, and a bit line is connected to the drain region of each non-volatile memory element arranged along the column direction. Source lines are commonly connected to the source regions of the memory elements, and common substrate lines are provided on the semiconductor substrate.

[0020] information during writing <br/> of the nonvolatile memory device, the source line and the substrate line leave the ground potential, high for the word line non-volatile memory element for writing is connected In order to apply the voltage and select the non-volatile memory element for writing, the write voltage is applied to the bit line to which the non-volatile memory element is connected and the non-selected non-volatile memory element is connected. It is only necessary to apply the write inhibit voltage to the bit line to which the non-selected nonvolatile memory element is connected, with the selected word line at the ground potential . Further, when erasing information, a high voltage is applied to the substrate line, by applying a different high voltage polarity to that at the time of writing the word line non-volatile storage elements to erase the information is connected Good.
Further, at the time of reading of the information, keep the ground potential source line and the substrate line, the sense voltage is applied to the word line non-volatile memory device for reading is connected, the non-volatile memory device for reading the by applying a read voltage to the bit line connected
Good .

At the time of writing the above information, a saturated channel current flows between the source and drain of the selected nonvolatile memory element. A high energy charge is generated in the vicinity of the drain region, and the high energy charge is injected. At this time, in the nonvolatile memory element, since the charge storage film is formed only on the drain region side partial region of the channel region, the charge storage region is narrow and the charges are uniformly stored in the charge storage film. .

At the time of erasing information, an FN tunnel current is generated between the gate electrode of the selected nonvolatile memory element and the substrate, and the FN tunnel current injects charges having a polarity different from that at the time of writing. At this time, the charges having different polarities injected by the FN tunnel current are combined with the charges stored in the charge storage film, and the stored information is erased. On the other hand, charges of different polarities injected into the gate insulating film tunnel through the gate insulating film and escape to the gate electrode. As a result, charges having different polarities are not accumulated in the nonvolatile memory element.

As described above, even if the information is erased by the FN tunnel current, the over-erase state does not occur, so that the punch-through breakdown voltage does not decrease. At the time of reading information, if electric charge is accumulated in the charge accumulating film of the non-volatile memory element, the drain and source become conductive and no channel is formed. As a result, no current flows in the nonvolatile memory element. On the other hand, when the charge is not stored in the charge storage film, the source-drain conducts and the channel is formed. As a result, a current flows through the nonvolatile memory element. By sensing this state, reading of the stored information is achieved.

[0024]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to FIGS. FIG. 1 is a sectional view showing a schematic configuration of a nonvolatile memory element according to an embodiment of the present invention. The configuration of the nonvolatile memory element according to this example will be described with reference to FIG.

As shown in FIG. 1, the nonvolatile memory element of this embodiment has a P-type silicon substrate 30 and a silicon substrate 30.
Of the N ⁺ type source region 30b and the N ⁺ type drain region 30c formed at predetermined intervals in the surface layer of the channel region 30a and the drain region 30c side of the channel region 30a formed so as to be sandwiched between the source region 30b and the drain region 30c. A charge storage film 31A formed on the partial region to store charges generated in the channel region 30a, a gate oxide film 31B formed on the remaining region of the channel region 30a, a charge storage film 31A and a gate oxide film 31B. The gate electrode 32 formed above is provided, and information is stored by injecting charges into or discharging charges from the charge storage film 31.

The charge storage film 31A has a so-called ONO structure in which a trap nitride film 31b for trapping charges is sandwiched by a bottom oxide film 31c capable of tunneling charges and a top oxide film 31a preventing penetration of charges. There is. The top oxide film 31a and the bottom oxide film 31c are S
The nitride film 31b is made of SiO ₂ , and is made of Si ₃ N ₄ .

The gate oxide film 31B is made of SiO ₂ , and charges generated in the channel region 30a are transferred to the gate electrode 3.
It is formed thinner than the charge storage film 31A so that it can be tunneled to 2. In addition, in the following description, the nonvolatile memory element is referred to as a “memory transistor”.

FIG. 2 shows the structure of the non-volatile memory device. FIG. 2 (a) is a plan view showing a state in which the passivation film is peeled off, and FIG. 2 (b) is a sectional view taken along line H-H of FIG. 2 (a). Figure,
FIG. 7C is a sectional view taken along the line I-I of FIG. Figure 2
The configuration of the nonvolatile memory element will be described with reference to (a), (b), and (c). The nonvolatile storage device is shown in FIG.
As shown in (a), the memory transistors 20A, 20B, 20C, 20D shown in FIG.
Are arranged in a matrix along the row direction X and the column direction Y.

As shown in FIG. 2C, the memory transistors 20C and 20D arranged in the row direction X are isolated from each other by the field oxide film 36 formed thickly on the surface layer on the silicon substrate 30. Has been done. The gate electrode 32 of the memory transistors 20C and 20D
Are formed along the row direction X such that the word line W2 is shared by the transistors 20C and 20D. Similarly, the memory transistors 20A and 20B arranged in the row direction X are also element-isolated by the field oxide film, and the gate electrode 32 is formed as shown in FIG.
As shown in (a), it is formed along the row direction X so that the word line W1 is shared by the transistors 20A and 20B.

The memory transistors 20A and 20C arranged in the column direction Y share a drain region 30c as shown in FIG. 2B, and the drain region 30c has a column direction Y. The bit line 35 (B1) formed along the contact is in contact through the contact hole 34 formed by opening the interlayer insulating film 33. In addition, the memory transistors 20B and 20D, which are similarly arranged in the column direction Y, share a drain region, and in this drain region, as shown in FIG.
Bit line 35 (B2) formed along the column direction
Are in contact with each other through the contact hole 34.

FIG. 3 shows the steps of the method for manufacturing the nonvolatile memory device.
FIG. 3 is a cross-sectional view sequentially showing one memory for convenience of explanation.
Only transistors are shown. With reference to FIG.
A method of manufacturing the nonvolatile memory device will be described. First,
A charge storage layer and a tunnel oxide film are formed. Sanawa
Then, as shown in FIG.
For example, SiO 2 with a film thickness of about 60Å is formed on the control substrate 30.₂Membrane 4
After growing 0, as shown in FIG.
PCVD (low pressure chemical vapor deposition) method
Alternatively, by thermal nitriding, SiO₂For example, the film thickness on the film 40
Si of about 140Å₃N_FourThe film 41 is grown thick. Next
In addition, as shown in FIG.₃N_FourPredetermined of membrane 41
After applying the resist 42 on the region of FIG.
As shown, HF was used to protrude from the resist 42.
Si₃N_FourEtch the film 41 to a film thickness of 30 Å
Remove it. Subsequently, the resist 42 was ashed.
After that, wet oxidation is performed for a predetermined time. Then, Figure 3
As shown in (e), etching is performed in the step of FIG.
Thin Si₃N_FourThe film 41 is eroded by oxygen. On the other hand, d
Si not etched₃N_FourThe film 41 remains and SiO
₂Covered with a membrane. As a result, on the silicon substrate 30
Is Si₃N _FourSiO film₂Sandwich sandwiched between membranes
Charge storage film 31A having a structure, and SiO₂Only from the membrane
The gate oxide film 31B is formed. This
At this time, the charge storage film (hereinafter referred to as “ONO film”) 31
The film thickness of the bottom oxide film 31a of A is, for example, 60Å,
The film thickness of the p-nitride film 31b is, for example, 110Å, the top oxide film
The film thickness of 31c is set to 60Å, for example. Well
In addition, the thickness of the gate oxide film 31B causes the charge to tunnel.
In order to obtain, for example, about 100 Å than ONO film 31A
It is set thin.

When the ONO film and tunnel oxide film forming steps are completed, a gate electrode is formed. That is,
As shown in FIG. 3F, for example, by the LPCVD method,
After depositing polysilicon on the ONO film 31A and the gate oxide film 31B, the polysilicon is doped with phosphorus in order to impart conductivity. Then, by photolithography, polysilicon is patterned along the row direction to form the gate electrodes 32 (W1, W2).

When the gate electrode forming step is completed, a source region and a drain region are formed. That is, as shown in FIG. 3G, phosphorus is ion-implanted by implantation using the gate electrode 32 as a mask to implant the N ⁺ -type source region 3 into the surface layer of the P-type silicon substrate 30.
0b and N ⁺ type drain region 30c are formed in a self-aligned manner.

After the formation process of the source region and the drain region is completed, an interlayer insulating film and a bit line are formed. That is, as shown in FIG. 3H, BPSG (boron phosfeid silica glass) is deposited on the entire surface by, eg, CVD (chemical vapor deposition) to form an interlayer insulating film 33. Next, the interlayer insulating film 3
3 is opened to form a contact hole 34 on the drain region 30c. Then, for example, PVD (physical vapo
A conductive material such as Al-Si is deposited by the r deposition method, and the conductive material is patterned in the column direction to form the bit lines 35 (B1, B2) in the contact holes 34.
Through the drain region 30c.

FIG. 4 is an equivalent circuit diagram showing the electrical configuration of the nonvolatile memory device. The electrical configuration of the nonvolatile memory device will be described with reference to FIG. As shown in FIG. 4, the nonvolatile memory device includes memory transistors 20A and 20A having the ONO film M only in a partial region shown in FIG.
B, 20C, 20D only memory cells 21A, 2
1B, 21C, and 21D are arranged in a matrix along the row direction X and the column direction Y.

At the gates of the memory transistors in the memory cells 21A and 21B arranged along the row direction X,
The word line W1 is connected, and the word line W2 is connected to the gates of the memory transistors in the memory cells 21C and 21D arranged in the row direction X. Memory cells 20 arranged in the column direction Y
A bit line B1 is connected to the drains of the memory transistors in A and 20C, and a bit line B2 is connected to the drains of the memory transistors in memory cells 20B and 20D arranged in the column direction Y. Has been done.

Further, each memory cell 20A, 20B, 20
A source line S is commonly connected to the sources of the memory transistors in C and 20D, and a substrate line SUB is commonly connected to the substrates. The operation of writing, reading, and erasing information in the nonvolatile memory device will be described with reference to FIG. Note that you assumed that selects the memory cell 21A shown in FIG. 4 in each operation of writing can inclusive and read.

[0038]

<Writing> When writing information,
First, 0 for the source line S and the substrate line SUB
V is applied respectively. Then, the memory cell 21A
Is applied to the word line W1 connected to the memory cell 2 to select the memory cell 21A.
9V is applied to the bit line B1 to which 1A is connected. Further, 0V is applied to the word line W2 to which the non-selected memory cells 21C and 21D are connected, and 0V is applied to the bit line B2 to which the non-selected memory cells 21B and 21D are connected.

Then, the selected memory cell 21A
In the inside, hot electrons are generated due to the high electric field generated near the drain of the memory transistor 20A, and these hot electrons are injected into the ONO film M,
Information is written in the memory cell 21A. on the other hand,
In the non-selected memory cells 21B, 21C, 21D,
No hot electrons are generated near the drains of the memory transistors 20B, 20C, and 20D, and hot electrons are not injected into the ONO film M, so that information is not written.

The gate voltage required for conduction between the source and drain changes between the state where electrons are accumulated in the ONO film and the state where electrons are not accumulated. That is, the threshold voltage V _TH for conducting between the source and the drain has a high threshold V1 (for example, 5 V) when electrons are injected into the ONO film, and is low when electrons are not injected. Value V2 (eg 2V)
Take In this way, by setting the threshold voltage V _TH to two types, binary data of “1” or “0” can be stored in the memory cell. <Erase> Information is erased collectively . A high voltage 7V applied to the base plate line SUB, respectively applied to -6V with respect to the word lines W1, W2.

Then, in all the memory cells,
An FN tunnel current is generated between the gate of the memory transistor and the substrate, and this FN tunnel current causes holes to become O.
It is injected into the NO film M. As a result, hot electrons accumulated in the ONO film M of the memory transistor are neutralized by coupling with the holes. As a result, the information stored in all the memory cells is erased at once.

Information may be erased by dividing it for each word line. That is, the bit lines B1 and B2
And advance by applying 0V to the source line S, the 7V is applied to the substrate line SUB, a memory cell 21A erasing the information, the word line W1 of 21B - 6
When V is applied and 0 V is applied to the word line W2 of the non-selected memory cells 20C and 20D, the information stored in the memory cells 21A and 21B arranged along the word line W1 is erased. <Reading> To read the information stored in the memory cell 21A, first, 0 V is applied to the source line S and the substrate line SUB. The sense voltage 3V is applied to the word line W1 to which the memory cell 21A is connected.
Is applied to select the memory cell 21A, the bit line B1 to which the memory cell 21A is connected is set to 1
Apply V. Furthermore, unselected memory cells 21C, 21
0V is applied to the word line W2 to which D is connected, and 0V is applied to the bit line B2 to which the non-selected memory cells 21B and 21D are connected.

Then, in the memory cell 21A, if the ONO film M of the memory transistor 20A is in a written state of information in which electrons are accumulated, the source-drain of the memory transistor 20A is not conductive,
No channel is formed. That is, no cell current flows in the memory cell 21A. On the other hand, the memory transistor 20
When the ONO film M of A is in the erased state of information in which electrons are not accumulated, the source-drain of the memory transistor 20A becomes conductive and a channel is formed. That is, a cell current flows in the memory cell 21A. If this state is sensed by a decoder and a sense amplifier (not shown) connected to the outside, the reading of the information stored in the memory cell 21A is achieved.

Further, the reading of information may be performed collectively. That is, the source line S and the substrate line SUB
0V is applied to all word lines W1, W2
If a sense voltage of 3V is applied to all the bit lines B1 and B2 and a voltage of 1V is applied to all the bit lines B1 and B2, the information stored in all the memory cells 21A, 21B, 21C and 21D can be collectively read.

Here, the sense voltage is an intermediate voltage between the two kinds of values of the threshold voltage V _TH , V1 and V2. Therefore, when this sense voltage is applied, it turns on.
Conduction / non-conduction between the source and drain is determined by whether or not electrons are accumulated in the O film. In the following description, the memory transistors 20A, 20B,
20C and 20D are collectively referred to as "memory transistor 20".

FIG. 5 is a diagram showing the operating principle of the memory transistor when writing information, FIG. 6 is a diagram showing the operating principle of the memory transistor when erasing information, and FIG. 7 is an operating principle of the memory transistor when reading information. FIG.
Each operation of writing, erasing and reading information of the memory transistor will be described with reference to FIGS. <Writing> When writing information to the memory transistor 20, FIG.
As shown in (a ), when 0V is applied to the source region 30b of the memory transistor 20 and the silicon substrate 30, 10V is applied to the gate electrode 32, and 9V is applied to the drain region 30c, a saturated channel is formed between the source and the drain. An electric current flows. Hot electrons are generated in the pinch-off region near the drain region 30c, and these hot electrons jump over the bottom oxide film 31c and are injected into the trap nitride film 31b.

Then, in the memory transistor 20, the ONO film 31A is formed only on a partial region of the channel region 30a on the drain region 30c side.
As the charge storage area becomes narrower, as shown in FIG.
Electrons are uniformly injected into the ONO film 31A. When erasing the information stored in the <Erase> memory transistor 20, as shown in FIG. 6 (a), divorced substrate 30 7
Applying a V, is applied to -6V to the gate electrode 32, occurs FN tunnel current between the gate electrode 32 substrate 30, holes through F N tunnel current this is injected into the trap nitride film 31b. Since holes are injected into the ONO film by the FN tunnel current as described above, stress on the ONO film at the time of erasing can be reduced, which leads to improvement in the number of rewritable times.

As shown in FIG. 6B, the holes injected by the FN tunnel current are combined with the hot electrons accumulated in the nitride film 31b and the electrons are neutralized. As a result, the information is erased. . On the other hand, the holes injected into the gate oxide film 31B tunnel through the gate oxide film 31B and pass through to the gate electrode 32.
Will not be accumulated in. As described above, even if the erasure is performed by the FN tunnel current, the over-erase state does not occur, so that the punch-through breakdown voltage does not decrease. <Read> When reading the information stored in the memory transistor 20, as shown in FIGS. 7A and 7B, 0 V is applied to the source region 30 b of the memory transistor 20 and the silicon substrate 30, and the gate electrode 32 is applied. When a sense voltage of 3V is applied and a voltage of 1V is applied to the drain region 30c, the surface of the silicon substrate 30 directly below the gate oxide film 31B is affected by the positive charge of the gate electrode 32 and is inverted (inverted).
on) As a result, the substrate 3 immediately below the gate oxide film 31B
On the surface of 0, the inversion layer IL occurs.

At this time, as shown in FIG. 7A, when the trap nitride film 31b is in a state of writing information in which electrons are accumulated, the positive charge of the gate electrode 32 affects the nitride film 31b. The electrons are blocked by the electrons accumulated in the ONO film and do not reach the surface of the silicon substrate 30 directly below the ONO film. As a result, there is no conduction between the source and drain and no channel is formed. That is, no current flows through the memory transistor 20. On the other hand, as shown in FIG. 7B, when the trap nitride film 31b is in the erased state of information in which electrons are not accumulated, the gate electrode 3
The influence of the positive charge of 2 also extends to the surface of the silicon substrate immediately below the ONO film, and the source-drain conducts, and the channel CH
Is formed. That is, a current flows through the memory transistor 20.

As described above, the memory transistor is
An ONO film for accumulating charges is formed on a partial region of the channel region on the drain region side, and a gate oxide film capable of tunneling charges is formed on the remaining region of the channel region. -Even if information is erased by generating FN tunnel current between the substrates and injecting holes by this FN tunnel current, excessive erasure does not occur.

Therefore, by using the memory transistor having the ONO film only in the partial region, it is possible to prevent over-erasure and improve the number of rewritable times of the nonvolatile memory device. The present invention is not limited to the above embodiment, and many modifications and changes can be made within the scope of the present invention.

For example, the memory transistor in the above embodiment may have a structure having an NO (nitride-oxide) film for accumulating charges in a partial region, or may use an N-type silicon substrate.

[0054]

As is apparent from the above description, according to the present invention, it is possible to prevent excessive erasure and to improve the number of rewritable times.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a schematic configuration of a nonvolatile memory element according to an embodiment of the present invention.

2A and 2B show a configuration of a nonvolatile memory device, FIG. 2A is a plan view showing a state in which a passivation film is removed, FIG. 2B is a sectional view taken along line HH of FIG. FIG. 7C is a sectional view taken along the line I-I of FIG.

FIG. 3 is a cross-sectional view showing the method of manufacturing the nonvolatile memory device in the order of steps.

FIG. 4 is an equivalent circuit diagram showing an electrical configuration of the nonvolatile memory device.

FIG. 5 is a diagram showing an operation principle of a nonvolatile memory element at the time of writing information.

FIG. 6 is a diagram showing an operating principle of a nonvolatile memory element when erasing information.

FIG. 7 is a diagram showing an operation principle of a nonvolatile memory element at the time of reading information.

FIG. 8 is a cross-sectional view showing a schematic configuration of a conventional nonvolatile memory element.

FIG. 9 is an equivalent circuit diagram showing an electrical configuration of a conventional nonvolatile memory device.

FIG. 10 is a diagram showing an operation principle of a nonvolatile memory element at the time of writing information.

FIG. 11 is a diagram showing an operating principle of a nonvolatile memory element when erasing information.

FIG. 12 is a diagram showing write / erase characteristics of a nonvolatile memory element.

FIG. 13 is a diagram showing a written state of an ONO film.

FIG. 14 is a diagram showing an over-erased state of an ONO film.

[Explanation of symbols]

20, 20A, 20B, 20C, 20D Nonvolatile storage element (memory transistor) 21A, 21B, 21C, 21D Memory cell 30a Channel region 30b Source region 30c Drain region 30 Silicon substrate 31a Top oxide film 31b Trap nitride film 31c Bottom oxide film 31A, MONO film (charge storage film) 31B Gate oxide film 32 Gate electrodes W1 and W2 Word lines B1 and B2 Bit line S Source line SUB Substrate line

─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Takanori Ozawa 21 ROHM Co., Ltd., Mizozaki-cho, Saiin, Ukyo-ku, Kyoto (56) References JP 62-113478 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 21/8247 G01C 16/02 H01L 27/115 H01L 29/788 H01L 29/792

Claims (4)

(57) [Claims] 1. A method for storing information by injecting and extracting electric charges, wherein a predetermined first conductivity type semiconductor substrate and a surface layer of the semiconductor substrate are provided with a predetermined distance. A source region and a drain region, which are formed apart from each other and have a second conductivity type opposite to the first conductivity type, and a partial region of the channel region which is formed so as to be sandwiched between the source region and the drain region on the drain region side. Traps formed on top of which trap the charge generated in the channel region.
A charge storage film having an oxide film, a gate insulating film formed on the remaining region of the channel region and capable of tunneling charges generated in the channel region, and a gate formed on the gate insulating film and the charge storage film A nonvolatile memory element including an electrode. 2. Injection and removal of electric charge
To store information by A semiconductor substrate having a predetermined first conductivity type; Formed on the surface layer of the semiconductor substrate with a predetermined gap.
A second conductivity type opposite to the first conductivity type above.
A source region and a drain region, Raw so that it is sandwiched between the source region and the drain region.
Formed on a part of the drain region side of the channel region.
And a charge storage film that stores the charges generated in the channel region
And when it is provided over the entire channel region,
At the time of imprinting, electric charges of one polarity are locally injected and the writing area
Area and non-write area are generated, and the electric charge of the other polarity is fully erased during erase
Overwriting in the non-write area by injecting into the body
A charge storage film in a leaving state, A channel formed on the remaining region of the channel region
Gate insulating film that can tunnel charges generated in the region
When, The gate formed on the gate insulating film and the charge storage film.
Including the electrode Characteristic nonvolatile storage element. 3. A hot electro device for the charge storage film.
Information can be written by injecting
The non-volatile according to claim 1 or 2, which is performed.
Foaming memory element. 4. The non-volatile memory element according to claim 1, wherein the non-volatile memory element is formed in a matrix on a semiconductor substrate along a row direction and a column direction, and arranged along the row direction. A word line is connected to the gate electrode of each nonvolatile memory element, a bit line is connected to the drain region of each nonvolatile memory element arranged in the column direction, and a source of each nonvolatile memory element is connected. A source line is commonly connected to the region, and a common substrate line is provided to the semiconductor substrate.