JP3067420B2 - Nonvolatile memory device and driving method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a nonvolatile memory device and a method of driving the same.

[0002]

2. Description of the Related Art Conventionally, as a non-volatile memory device for storing information semi-permanently (hereinafter referred to as "non-volatile memory"), as shown in FIG. 12, a memory transistor for storing information by accumulating electric charge is shown in FIG. 1 and a select transistor 2 for selecting the memory transistor 1 (hereinafter, referred to as “non-volatile memory cell”) are arranged in a matrix on the same semiconductor substrate. Have been.

In recent years, with the development of the semiconductor industry, high integration of nonvolatile memories has been required. In order to meet this demand, it is conceivable to improve the degree of integration of the memory cell circuit. However, since the nonvolatile memory cell shown in FIG. 12 has a so-called two-transistor / 1-cell structure, there is a limit in supporting high integration.

Therefore, as shown in FIG. 13, a nonvolatile memory in which a split gate type transistor 3 having a memory gate 3a for accumulating charges and a select gate 3b for selecting the memory gate 3a is used as a nonvolatile memory cell. Was proposed. In such a memory cell, although it can contribute to high integration to some extent,
As still because it has two transistor / one-cell structure was very similar to the structure to correspond to the higher integration is limited.

To cope with this, as shown in FIG. 14, the memory transistors 4A, 4B, 4C, and 4D are made into nonvolatile memory cells 5A, 5B, 5C, and 5D, and the memory cells 5A, 5B, 5C, and 5D are made. 2. Description of the Related Art A nonvolatile memory has been proposed which is formed in a matrix on the same semiconductor substrate. In this nonvolatile memory, word lines WL1 and WL2 are respectively connected to gates of memory transistors 4A and 4B and 4C and 4D arranged in a row direction. The bit lines BL1 and BL2 are connected to the drains of the memory transistors 4A and 4C and 4B and 4D, respectively, and the source line SL is commonly connected to the sources.

Although the above-mentioned nonvolatile memory has a one-transistor / one-cell structure, it contributes to higher integration to some extent. Since the isolation region exists between the memory transistors and the wiring is complicated, it has not been possible to contribute to higher integration by that much.

To cope with the above, as shown in FIG.
There has been proposed a nonvolatile memory in which nonvolatile memory cells 5A, 5B, 5C, and 5D having a transistor / 1 cell structure are arranged in a virtual ground array. That is, the memory transistors 4A, 4A,
Sources and drains of 4B, 4C and 4D are connected to each other, and bit lines are connected to the sources and drains of memory transistors 4A, 4C and 4B and 4D arranged in the column direction including the source-drain connection intermediate point. BL1, BL2, BL3 are connected respectively.

Referring to FIG. 15, the operation of writing and erasing information in a nonvolatile memory having a virtual ground array structure will be described. <Writing> When writing information to the nonvolatile memory cell 5A, the substrate is set to the ground potential, and a high voltage is applied only to the word line WL1 connected to the gate of the memory transistor 4A of the memory cell 5A to be written. To apply H and select a memory cell 5A to be written, a low voltage L is applied to the bit line BL1 connected to the source of the memory cell 5A, and to the other bit lines BL2 and BL3. High voltage H is applied.

Then, charges are injected into the gate insulating film of the memory transistor 4A in the memory cell 5A, and information is written to the memory cell 5A. <Erase> When erasing information stored in the nonvolatile memory cells 5A and 5B connected to the word line WL1, the word line WL1 is set to the ground potential and all the bit lines BL1, BL2 and BL3 are opened. In this state, a high voltage H is applied to the substrate and other word lines WL2.

Then, charges having different polarities from those at the time of writing are injected into the memory transistors 4A and 4B in the memory cells 5A and 5B, and the information stored in the memory cells 5A and 5B is erased. Here, the operation principle of writing and erasing information in the memory transistor will be described with reference to FIG.

As shown in FIG. 16, a memory transistor includes a P-type silicon substrate 10 having a channel region 10a and an N ⁺ type source region 10b and an N ⁺ type drain region 10c with the channel region 10a interposed therebetween. The gate insulating film 11 is formed on the channel region 10a so as to bridge the source region 10b and the drain region 10c and accumulates electric charges. The gate insulating film 11 is provided on the channel region 10a with the gate insulating film 11 interposed therebetween. And a gate electrode 12.

As shown in FIG. 17, the gate insulating film 11 is formed by forming a nitride film 11b for storing electric charges into a tunnel oxide film 11b.
It has a so-called sandwich structure sandwiched between c and the trap oxide film 11a. In the following description, the gate insulating film is referred to as “ONO (oxide nitride oxide)”.
Film ". <Write> At the time of writing information, FIG.
When the silicon substrate 10 is set to the ground potential and a high voltage H is applied to the drain region 10c and the gate electrode 12 and a low voltage L is applied to the source region 10b as shown in FIG. A saturated channel current flows, and a pinch-off region (pinch
In the off region, electrons accelerated by a high electric field have high energy and are called hot electrons.
ctron), and the hot electrons are generated by the ONO film 1
Injected into 1 and accumulated. <Erase> When information is erased, the source region 10b and the drain region 10c are opened (OPE) as shown in FIG.
N), the gate electrode 12 is set to the ground potential 0 V, and when a high voltage H is applied to the silicon substrate 10, holes are generated in the entire channel region 10a, and the holes are tunneled by FN (Fowler Nordheim) tunneling. ONO film 1
Injected into 1. Then, the electrons accumulated in the ONO film 11 are electrically neutralized by the holes.

[0013]

However, in the above-mentioned nonvolatile memory, information is written by injecting hot electrons into the ONO film.
At this time, the write current is increased to cause the accelerated electrons to collide with silicon near the drain region to generate hot electrons having high energy and to inject the hot electrons locally. The tunnel oxide film of the ONO film deteriorated, leading to a decrease in the number of rewrites.

Further, since the local writing is performed, the variation in the operating speed of the memory transistor causes the variation in FIG.
In one ONO film 11, the nitride film 11b
The write region A in which hot electrons are injected into the nitride film 11b and the non-write region B in which hot electrons are not injected into the nitride film 11b are mixed. Thus, in a state where the writing area A and the non-writing area B are mixed, FIG.
When erasing is performed by generating holes in the entire channel region and injecting the holes into the ONO film 11 through FN tunneling, the nitride film 1
Although the electrons accumulated in 1b are neutralized by holes to be in an erased state, in the non-writing region B, holes are accumulated in the nitride film 11b, resulting in a so-called excessively erased state. Thus, when excessive erasure occurs,
Punch through A decrease in withstand voltage occurs and power consumption increases.

SUMMARY OF THE INVENTION In view of the above, it is an object of the present invention to provide a nonvolatile memory device capable of improving the number of rewrites and reducing power consumption while further increasing the degree of integration, and a driving method thereof.

[0016]

According to the first aspect of the present invention, there is provided a semiconductor substrate having a channel region and a source region and a drain region formed with the channel region interposed therebetween. A gate insulating film formed on a channel region except a predetermined offset region adjacent to the source region on the semiconductor substrate;
On a channel region except for the offset region, provided via the gate insulating film, and a gate <br/> gate electrode connected to the word line, the storage of information by storing charges in the gate insulating film And a voltage is applied to the source region.
Is applied to the source region and the offset.
A non-volatile memory element that can be electrically connected to a channel region other than a flash region , wherein the non-volatile memory element is a non-volatile memory element adjacent to a row direction on the same semiconductor substrate. In the form of sharing the source and drain regions of
Are arranged in a matrix, the gate electrode of the nonvolatile memory elements arranged formed in the row direction, word lines are connected respectively, including shared portion between the source region and the drain region, formed and arranged in the column direction A bit line is connected to the source region and the drain region of the nonvolatile storage element in a state insulated from the word line, and the nonvolatile storage elements arranged in the column direction are connected to the gate electrode of the nonvolatile storage element. An element is isolated by interposing a field oxide film therebetween, and an end surface of the field oxide film on the source region side extends completely to the source region through the offset region. Is
A nonvolatile storage device characterized by the above-mentioned. Also, billing
The invention according to Item 2 is characterized in that the nonvolatile element is replaced with a channel.
Source region with its channel region
A semiconductor substrate on which a semiconductor substrate and a drain region are formed;
A predetermined offset adjacent to the source region on the body substrate
Gate insulating film formed on the channel region excluding the gate region
When, on the offset region lean rather channel region, wherein
Provided via a gate insulating film and connected to a word line
Gate electrode and a floating gate,
By accumulating charge in the floating gate,
Performs storage and applies a voltage to the source region
The source region and the offset region.
Non-volatile memory that can be electrically connected to the channel region
An element is provided.

Since the nonvolatile memory device according to the first or second aspect has a one-transistor / one-cell structure, it can contribute to higher integration. Claim 3
In the invention of the present invention , the channel region and the channel region
Semiconductor with source and drain regions formed between
Body substrate and a substrate adjacent to the source region on the semiconductor substrate.
Gate formed on the channel region excluding the region defined
On the insulating film and the channel region excluding the predetermined region
A gate electrode provided via the gate insulating film;
Information storage by accumulating charge in the gate insulating film.
The non-volatile memory element that performs storage is on the same semiconductor substrate,
The source region and drain of the nonvolatile memory element adjacent in the row direction
Arranged in a matrix in such a way as to share the
Of the non-volatile memory elements formed and arranged in the row direction.
Word lines are connected to the gate electrodes, respectively,
In the column direction, including the shared part of the source and drain regions
The source region and the source of the arrayed nonvolatile memory element
Bits in the rain area, insulated from word lines
Lines are connected to each other and
The volatile storage elements are connected to the gate of the nonvolatile storage element.
By interposing a field oxide film between the electrodes,
The device is isolated and the source region of the field oxide film is
The area side end face completely passes over the predetermined area
Driving a nonvolatile storage device extending to the source area
In writing information, the substrate is set to the ground potential at the time of writing information, and a high voltage is applied only to the word line connected to the gate electrode of the nonvolatile memory element to be written. In order to select a nonvolatile memory element to be performed, a bit line connected to a drain region of the nonvolatile memory element is set to a ground potential, a write inhibit voltage is applied to other bit lines, and when erasing information, In order to divide and erase the stored information for each word line, all the bit lines are left open, the word line connected to the nonvolatile memory element to be erased is set to the ground potential, and the substrate and other word lines are connected. When reading information, the substrate is set at the ground potential and connected to the gate electrode of the nonvolatile memory element for reading. That a sense voltage is applied to the word lines, for selecting the nonvolatile memory element to be read, a read voltage is applied to the bit line connected to the source region of the nonvolatile memory element, other JP to the word lines and bit lines and a ground potential
This is a method for driving a nonvolatile memory device . In addition,
5. The driving method according to claim 4, wherein the nonvolatile storage device is
Instead of the non-volatile element, a channel region and its
The source and drain regions sandwich the channel region
A formed semiconductor substrate, and a source region on the semiconductor substrate.
On the channel region except for the predetermined region adjacent to the region
The gate insulating film formed and the
Provided on the channel region via the gate insulating film.
A gate electrode; a floating gate;
Information storage by accumulating charge in the loading gate
That it has a nonvolatile memory element that performs
Features.

At the time of writing information, the gate region of the nonvolatile memory element connected to the word line to which a high voltage is applied, and the channel region excluding the lower part of the gate insulating film,
It is always an offset area. On the other hand, an FN current is generated between the gate electrode and the substrate of the nonvolatile memory element,
Electric charges are generated in the entire channel region excluding the offset region.

At this time, in the source region of the selected nonvolatile memory element, the depletion layer at the junction of the source region does not spread to the boundary of the offset region due to the write-protection voltage. Insulating film or
Injected into the floating gate . Therefore, a channel is formed from the drain region side of the nonvolatile memory element to the boundary of the offset region. On the other hand, in the drain region of the non-selected non-volatile memory element, the depletion layer at the junction of the drain region spreads to the boundary of the offset region due to the write-protection voltage.
Not injected into the gate insulating film or floating gate . Therefore, no channel is formed from the drain region side of the nonvolatile memory element to the boundary of the offset region.

As described above, in writing information, the entire writing can be performed on the gate insulating film or the floating gate . Therefore, deterioration of the gate insulating film can be prevented, and the number of rewrites can be increased.
Information can be written instantaneously. At the time of erasing information, a reverse bias is applied between the gate electrode of the nonvolatile memory element to be erased and the substrate at the time of writing, an FN current is generated, and at the time of writing to the entire channel region excluding the offset region. Charges of different polarities are generated.
The FN current causes charges having different polarities to be transferred to the gate insulating film or the floating gate of the nonvolatile memory element.
It is injected into the preparative, gate insulating film or the floating gate
The charge stored in the memory is neutralized, and information is divided and erased for each word line.

At this time, the electric charge is entirely stored in the gate insulating film or the floating gate by the whole writing, and the electric charge is stored in one gate insulating film or the floating gate.
Since the write region and the non-write region do not coexist in the gate, charges having different polarities are entirely deposited on the gate insulating film or the gate insulating film.
Excessive erasure does not occur even if it is implanted into the floating gate . Therefore, the punch-through breakdown voltage does not decrease. Therefore, power consumption can be reduced.

At the time of reading information, the depletion layer at the junction of the source region of the selected nonvolatile memory element extends to the boundary of the offset region. At this time, when charge is accumulated in the gate insulating film or the floating gate of the nonvolatile memory element, the depletion layer is connected to the channel formed at the time of writing, the channel is formed in the entire channel region, and the source region is formed. Conduction between the drain regions. On the other hand, when no charge is accumulated in the gate insulating film or the floating gate , no channel is formed at the time of writing, so that conduction between the source region and the drain region does not occur.

In the above nonvolatile storage device,
Since the end surface of the field oxide film on the source region side is laid out by extending to the predetermined region, that is, the source region by completely passing over the offset region, the boundary surface between the field oxide film and the gate electrode is formed. The offset length is the same distance as the actual offset length. Therefore, at the boundary between the field oxide film and the gate electrode, the depletion layer in the source region does not reach the gate electrode during writing, and conduction between the source region and the drain region does not occur. Therefore, writing of information is performed reliably.

According to a fifth aspect of the present invention, in the above driving method, all the word lines may be set to the ground potential, all the bit lines may be left open, and a high voltage may be applied to the substrate. In this case, reverse bias is applied to all the non-volatile storage elements, so that stored information can be erased collectively.

[0025]

1 to 11 show an embodiment of the present invention.
It will be described in detail based on. FIG. 1 is a plan view of a nonvolatile memory according to one embodiment of the present invention, FIG. 2 is a sectional view taken along line XX of FIG.
FIG. 2 is a sectional view taken along line YY of FIG. FIG. 1 shows a state in which the passivation film has been peeled off. 1 to 3
The structure of the nonvolatile memory according to the present embodiment will be described with reference to FIG.

As shown in FIG. 1, the nonvolatile memory of this embodiment is a memory transistor 21 for storing information by accumulating charges on the same P-type silicon substrate 20.
A, 21B, 21C and 21D are arranged in a matrix with a virtual ground array. In the following description, the memory transistors 21A, 21B,
21C and 21D are collectively referred to as “memory transistor 21”.

The surface layer of the P-type silicon substrate 20 has the structure shown in FIG.
As shown, a channel region 22 and an N + type source region 23 and an N + type drain region 24 are formed with the channel region 22 interposed therebetween. Memory transistor 21
Is the so-called MONOS (metal oxide nitride oxide
licon) structure and is formed on the channel region 22 except for a predetermined region (offset region) spaced a predetermined distance D (0.1 to 0.5 μm) from the source region 23 on the silicon substrate 20. ONO film 25 for storing electric charge
And a gate electrode 26 provided via an ONO film 25 on the channel region 22 excluding a predetermined region (offset region) . The memory transistors 21A, 21B and 21C, 21D adjacent in the row direction
Share a source region 23 and a drain region 24 with each other as shown in FIGS.

Gate electrodes 2 of memory transistors 21A and 21B and 21C and 21D arranged in a row direction
6, word lines WL1 and WL2 are connected to each other through contact holes 27 as shown in FIGS. 1, 2 and 3, and are arranged in a column direction including a shared portion between the source region 23 and the drain region 24. Memory transistor 2
Bit lines BL1, BL2, BL3 are connected to the source region 23 and the drain region 24 of 1A, 21C and 21B, 21D through contact holes 28, respectively. Then, the bit lines BL1, BL2,
BL3 is wired so as to be orthogonal to the word lines WL1 and WL2, and between the word lines WL1 and WL2 and the bit lines BL1, BL2 and BL3, as shown in FIG.
As in 3, the oxide insulating film 29 is interposed.

Source region 23 and drain region 24
Are bit lines BL1, BL2, BL3 as shown in FIG.
It is provided along. The ONO film 25 has a so-called sandwich structure in which a nitride film for storing charges is sandwiched between a tunnel oxide film and a trap film, and as shown in FIG.
2, BL3.

The memory transistors 2 arranged formed in the column direction 1 A, 2 1 C and 2 1 B, 2 1 gate of the D electrode 2
Between 6, as shown in FIG. 1 and 3, the film thickness is interposed the field oxide film 30 formed thickly, the field oxide film 30, the memory transistor 2 1 A, 2, which are arranged and formed in a column direction 1 C and 2 1 B, 2 1 D to each other are isolated.

The gate electrode 26 and the word line WL
1 and WL2, as shown in FIGS.
One is filled. Further, as shown in FIG. 4, the layout of the field oxide film 30 is such that the end face on the side of the source region 23 is completely passed over a predetermined region (offset region OS) at a predetermined distance D from the source region 23, and It extends to 23.

FIGS. 5 and 6 are sectional views showing a method of manufacturing a nonvolatile memory in the order of steps, and both figures (a) show XX of FIG.
Cross-section, both figures (b) show the Y-Y cross section of FIG. A method for manufacturing a nonvolatile memory will be described with reference to FIGS. First, as shown in 1- (a) and (b) in FIG. 5, a field oxide film 30 is formed along a column direction on a P-type silicon substrate 20 by a LOCOS (local oxidation of silicon) method such as steam oxidation. Form. The oxidation conditions at this time may be, for example, an oxidation temperature of 1000 ° C. and an oxidation time of 6 hours.

Then, as shown in 2- (a) and (b) in FIG. 5, after the ONO film 25 is formed on the entire surface by a conventionally known film forming method of a semiconductor process, 3- (a) ( As shown in b), the gate electrode 26 is formed. Next, in FIG.
(A) As shown in FIG.
Is applied, etching is performed in a stripe shape so that the ONO film 25 remains along the column direction.

Subsequently, as shown in 1- (a) and (b) of FIG. 6, the resist 40, the gate electrode 26, and the ONO film 25 are formed.
Is implanted obliquely from the drain region to the source region using the mask as a mask to implant and diffuse impurities, and then annealed to form the N ⁺ -type source region 23 and the N ⁺ -type drain region 24 in the column direction. To form a stripe. At this time, the source region 23 and the gate electrode 2
6 and the ONO film 25 are controlled by the thickness of the resist 40, and the distance can be easily set to 0.1 to 0.5 μm. As described above, the implantation angle of the impurity for setting the interval to 0.1 to 0.5 μm is, for example, 1 μm in thickness including the resist 40, the gate electrode 26, and the ONO film 25.
In this case, the inclination may be about 10 degrees with respect to a vertical line with the silicon substrate 20 as a reference. The annealing conditions may be, for example, an annealing temperature of 900 ° C. and an annealing time of 30 minutes.

After the entire surface is covered with an interlayer insulating film 31 made of SiO ₂ or the like as shown in FIGS. 6A and 6B, as shown in FIGS. , Gate electrode 26
A contact hole 27 is formed thereon, and for example, CVD (che
A conductive substance is deposited on the interlayer insulating film 31 by a mical vapor deposition method, and the conductive substance is connected through the contact hole 27. And by etching
The conductive material is patterned in stripes along the row direction to form word lines WL1 and WL2.

Next, as shown at 4- (a) and (b) in FIG.
An oxide insulating film 29 made of SiO ₂ or the like is formed on the entire surface, and a contact hole 28 (not shown) is formed on the source region 23 and the drain region 24. And, for example, CV
A conductive material is deposited on the oxide insulating film 29 by the method D, and the conductive material is connected through the contact holes 28. Then, the conductive material is patterned by etching into stripes along the column direction, thereby forming a bit. Line BL1,
BL2 and BL3 are formed.

FIG. 7 is an equivalent circuit diagram of the nonvolatile memory. The electrical configuration of the nonvolatile memory will be described with reference to FIG. The nonvolatile memory has a one-transistor / one-cell structure in which the memory transistors 21A, 21B, 21C, and 21D are nonvolatile memory cells 50A, 50B, 50C, and 50D.

Memory transistors 2 arranged in a row direction
Word lines WL1 and WL2 are connected to the gates of 1A, 21B and 21C and 21D, respectively, and the sources and drains of adjacent memory transistors 21A, 21B and 21C and 21D are connected to each of the word lines WL1 and WL2. Have been. The source and drain of the memory transistors 21A, 21C and 21B, 21D arranged in the column direction including the source-drain connection intermediate point are connected to bit lines BL1, BL2, B
L3 are connected respectively.

With reference to FIG. 7 and Table 1, operations of writing, erasing, and reading information in the nonvolatile memory will be described. Table 1 assumes that the nonvolatile memory cell 50B shown in FIG. 7 is selected.

[0040]

[Table 1]

<Write> At the time of writing information, the substrate is set to the ground potential of 0 V, and the memory transistor 21 in the memory cell 50B to be written is written.
A high voltage of 15 V is applied only to the word line WL1 connected to the gate of B, and the memory cell 50B to be written is selected, so that the bit connected to the drain of the memory transistor 21B in the memory cell 50B is selected. The line BL3 is set to the ground potential 0V, and the write inhibit voltage 7V is applied to the other bit lines BL1 and BL2.

Then, an FN current is generated due to a potential difference between the gate and the substrate of the memory transistor 21B, and electrons are injected into the ONO film by the FN current.
Information is written to the memory cell 50B. The gate voltage required for conducting between the source and the drain changes between the state where electrons are accumulated in the ONO film and the state where electrons are not accumulated in the ONO film. In other words, the threshold voltage V _TH for conducting between the source and the drain takes a high threshold value V1 (for example, 5 V) when electrons are accumulated in the ONO film, and is low when electrons are not accumulated. A threshold value V2 (for example, 2V) is taken. Thus, by setting the threshold voltage V _TH to two types, “1” is obtained.
Alternatively, binary data of “0” can be stored in a memory cell.

At the time of writing, if the bit lines to which the write inhibit voltage 7V is applied are sequentially changed in the direction of arrow W shown in FIG. 7, serial writing can be performed for each word line. <Erase> At the time of erasing information, all bit lines BL1, BL2, BL3 are set to the open state, and the word lines connected to the memory transistors 21A, 21B of the memory cells 50A, 50B to be erased. WL1 is set to a ground potential of 0 V, and a high voltage of 15 V is applied to the substrate and other word lines WL2. here,
The reason why the bit lines BL1, BL2, and BL3 are set in the open state is to prevent a current from flowing from the substrate toward the diffusion layer in the forward direction.

Then, the memory transistors 21A,
A reverse bias is applied between the gate and the substrate of 21B during writing, holes are injected into the ONO film by the FN current, and electrons accumulated in the ONO film are electrically neutralized. Therefore, the information stored in the memory cells 50A and 50B is erased. At the time of erasure,
If the word line to which the high voltage 15V is applied is changed, the information stored in the memory cell can be divided and erased for each word line. <Read (READ)> When reading information,
The substrate is set to the ground potential 0V, and the sense voltage 3 is applied to the word line WL1 connected to the gate of the memory transistor 21B in the memory cell 50B to be read.
In order to select the memory cell 50B to be read by applying V, a read voltage of 10 V is applied to the bit line BL2 connected to the source of the memory transistor 21B in the memory cell 50B, and another word line WL is applied.
2 and the bit lines BL1 and BL3 are set to the ground potential 0V.

Then, when electrons are accumulated in the memory transistor 21B, a channel is formed between the source and the drain of the memory transistor 21B, and the memory transistor 21B conducts. On the other hand, when electrons are not accumulated in the memory transistor 21B, no channel is formed between the source and the drain of the memory transistor 21B, and the memory transistor 2B
1B does not conduct. If the conduction / non-conduction of the memory transistor 21B is sensed by a decoder and a sense amplifier (not shown) connected to the outside, information stored in the memory cell 50B can be read.

Here, the sense voltage is an intermediate voltage between two values V1 and V2 of the threshold voltage _VTH . Therefore, when this sense voltage is applied,
The conduction / non-conduction between the source and the drain is determined by whether or not electrons are accumulated in the O film. At the time of reading, if the bit lines to which the reading voltage 7V is applied are sequentially changed in the direction of arrow W shown in FIG. 7, serial reading can be performed for each word line.

FIG. 8 is a diagram for explaining the operating principle of the memory transistor when writing information, FIG. 9 is a diagram for explaining the operating principle of the memory transistor when erasing information, and FIG. It is a figure explaining an operation principle. Here, the operating principle of writing, erasing, and reading of information of the memory transistor will be described. <Writing> At the time of writing information, as shown in FIG. 8A, the silicon substrate 20 is set to the ground potential 0 V, a high voltage 15 V is applied to the gate electrodes 26 of the memory transistors 21A and 21B, and the memory transistors 21A and 21
Assuming that a write inhibit voltage of 7 V is applied to a shared portion between the source region 23 and the drain region 24 of B, and the source region 23 of the memory transistor 21A and the drain region 24 of the memory transistor 21B are set to the ground potential of 0 V, the memory transistors 21A and 21B The gate region except for the gate electrode 26 and the lower portion of the ONO film 25 is always an offset region OS. On the other hand, an FN current is generated between the gate electrodes 26 of the memory transistors 21A and 21B and the silicon substrate 20, and electrons are injected into the entire channel region excluding the offset region OS.

At this time, in the source region 23 of the memory transistor 21B to which the write inhibit voltage 7V is applied, the depletion layer 60 at the PN junction of the source region 23 does not spread to the boundary of the offset region OS. FIG.
As shown in (b), electrons are injected into the ONO film 25 by the FN current. Therefore, the memory transistor 21
A channel (shaded in the figure) is formed from the drain region 24 side of B to the boundary of the offset region OS.

On the other hand, in the drain region 24 of the memory transistor 21A to which the write inhibit voltage 7V is applied, as shown in FIG. 8A, the depletion layer 60 at the PN junction of the drain region 24 is Since the depletion layer 60 spreads to the boundary, the depletion layer 60 blocks electrons, and FIG.
As shown in (b), it is not injected into the ONO film 25. Therefore, no channel is formed from the drain region 24 side of the memory transistor 21A to the boundary of the offset region OS.

As described above, in writing information, O
Since the entire writing can be performed on the NO film 25, deterioration of the ONO film (tunnel oxide film) can be prevented, and the number of times of rewriting can be increased. <Erasing> At the time of erasing information, as shown in FIG. 9A, the source region 23 and the drain region 24 of the memory transistors 21A and 21B are opened (OPEN), and the gate electrode 26 is opened.
Is set to the ground potential of 0 V, and a high voltage of 15 V is applied to the silicon substrate 20, the memory transistors 21A, 21
A bias is applied between the gate electrode 26 of B and the silicon substrate 20 in a direction opposite to that at the time of writing, an FN current is generated, and holes are generated in the entire channel region excluding the offset region OS. Then, by this FN current, FIG.
As shown in (b), the holes are formed in the memory transistors 21A and 2A.
The electrons injected into the 1B ONO film 25 and accumulated in the ONO film 25 are electrically neutralized. Actually, electrons in the ONO film 25 are extracted by the reverse bias, and when the bias is further increased, the substrate 2
From 0, holes are injected by FN.

At this time, the electrons are entirely accumulated in the ONO film 25 by the whole writing, and the writing region and the non-writing region are not mixed in one ONO film 25. Over-erasing does not occur even if it is injected into the ONO film 25 in the first step. Therefore, the punch-through breakdown voltage does not decrease. Therefore, power consumption can be reduced. <Reading> FIG.
As described above, the silicon substrate 20 is set to the ground potential 0 V,
A sense voltage of 3 V is applied to the gate electrodes 26 of the memory transistors 21A and 21B for reading, and a read voltage of 10 V is applied to a shared portion between the source region 23 and the drain region 24 of the memory transistors 21A and 21B. Assuming that the source region 23 and the drain region 24 of the memory transistor 21B have a ground potential of 0 V, the depletion layer 60 at the PN junction of the source region 23 of the memory transistor 21B extends to the boundary of the offset region OS.

At this time, the O of the memory transistor 21B is
When electrons are accumulated in the NO film 25,
The depletion layer 60 extends from the drain region 24 to the offset region OS
Connected to the channel (shaded in the figure)
As shown in FIG. 10B, a channel CH is formed in the entire channel region 22, and conduction between the source region 23 and the drain region 24 is established.

On the other hand, the ONO of the memory transistor 21B
When electrons are not accumulated in the film 25, a channel is not formed from the drain region 24 to the offset region OS, so that no conduction is made between the source region 23 and the drain region 24. By the way, as shown in FIG. 11A, the layout is such that the end surface on the source region 23 side of the field oxide film 30 that isolates the memory transistor in the column direction extends only to the middle of the offset region OS. When is, as shown in FIG. 11 (b), the offset length r ₂ at the boundary between the field oxide film 30 and the gate electrode 26, becomes shorter than the actual offset length r _1. For this reason, at the time of writing information, if a write inhibit voltage is applied to the source region 23,
In the boundary portion between the field oxide film 30 and the gate electrode 26 is shorter offset length r _2, it will reach the depletion layer of the source region 23 to the gate electrode 26, conduction between the source region 23-the drain region 24 I do. Therefore, injection of electrons may be cut off, and writing may not be performed.

To cope with this, in the present embodiment, as shown in FIG. 4, the end surface of the field oxide film 30 on the source region 23 side extends to the source region 23 by completely passing over the offset region OS. In this case, the offset length at the boundary between the field oxide film 30 and the gate electrode 26 is equal to the actual offset length. Therefore, at the boundary between the field oxide film 30 and the gate electrode 26, the depletion layer of the source region 23 does not reach the gate electrode 26, and conduction between the source region 23 and the drain region 24 does not occur.
Therefore, writing of information is reliably performed in the selected memory transistor.

It should be noted that the present invention is not limited to the above-described embodiment, and it goes without saying that many changes or modifications can be made within the scope of the present invention. For example, in the above embodiment, if all the word lines are set to the ground potential and all the bit lines are left open and a high voltage is applied to the substrate, all the memory transistors are reverse-biased, so that the data is stored. Information can be erased all at once.

[0056] Further, the present invention has been described when applied to a non-volatile memory of the type that store charge in a gate insulating film, a gate insulating film constituted of only the tunnel oxide film, floating gate charge The same effect can be obtained even if the present invention is applied to a non-volatile memory of the type that stores data.

[0057]

As is apparent from the above description, claim 1
To by the invention of the 5 lever, while achieving higher integration, thereby improving the number of times of rewriting, it is possible to lower the power consumption. In addition, since the end surface of the field oxide film on the source region side is completely extended over the predetermined offset region and extended to the source region, the offset length at the boundary between the field oxide film and the gate electrode is set. The distance is the same as the actual offset length. Therefore, at the boundary between the field oxide film and the gate electrode, the depletion layer of the source region does not reach the gate electrode at the time of writing, and conduction between the source region and the drain region does not occur. Will be

According to the driving method of the third or fourth aspect , at the time of erasing, stored information can be divided and erased for each word line. According to the driving method of claim 5 , at the time of erasing,
The stored information can be erased collectively.

[Brief description of the drawings]

FIG. 1 is a plan view of a nonvolatile memory according to one embodiment of the present invention.

FIG. 2 is a sectional view taken along line XX of FIG.

FIG. 3 is a sectional view taken along line YY of FIG. 1;

FIG. 4 is a diagram showing a layout of a field oxide film.

FIG. 5 is a sectional view illustrating a method for manufacturing a nonvolatile memory in the order of steps.

FIG. 6 is a sectional view showing a manufacturing method following FIG. 5 in the order of steps;

FIG. 7 is an equivalent circuit diagram of the nonvolatile memory.

FIG. 8 is a diagram illustrating an operation principle of a memory transistor at the time of writing information.

FIG. 9 is a diagram showing an operation principle of a memory transistor when erasing information.

FIG. 10 is a diagram illustrating the operation principle of a memory transistor when reading information.

11A is a diagram showing a state in which the field oxide film is laid out so as to extend only to an intermediate portion of the offset region, and FIG. 11B is an enlarged view of a portion Z in FIG. 11A. is there.

FIG. 12 is an equivalent circuit diagram of a conventional memory cell having a two-transistor / 1-cell structure.

FIG. 13 is an equivalent circuit diagram of a memory cell having a conventional split gate transistor.

FIG. 14 is an equivalent circuit diagram of a conventional nonvolatile memory using a memory cell having a one-transistor / one-cell structure.

FIG. 15 is an equivalent circuit diagram of a conventional nonvolatile memory in which memory cells having a one-transistor / 1-cell structure are arranged in a virtual ground array.

16A and 16B show the operation principle of the memory transistor shown in FIG. 15, and FIG. 16A shows a data writing operation;
FIG. 3B is a diagram showing an information erasing operation.

FIG. 17 is a diagram showing an over-erased state.

[Explanation of symbols]

 Reference Signs List 20 silicon substrate 21A, 21B, 21C, 21D memory transistor 22 channel region 23 source region 24 drain region 25 ONO film 26 gate electrode 30 field oxide film 50A, 50B, 50C, 50D memory cell WL1, WL2 word line BL1, BL2, BL3 Bit line

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-56-155574 (JP, A) JP-A-4-230079 (JP, A) JP-A-1-1522673 (JP, A) JP-A-60-1985 182174 (JP, A) JP-A-48-15434 (JP, A) JP-A-56-155574 (JP, A) JP-A-52-26129 (JP, A) JP-A-53-148256 (JP, A) JP-A-55-48973 (JP, A) JP-A-64-39070 (JP, A) JP-A-64-53464 (JP, A) JP-A-4-91471 (JP, A) (58) (Int.Cl. ⁷ , DB name) H01L 27/115 H01L 21/8247 H01L 29/788 H01L 29/792

Claims (5)

(57) [Claims] 1. A semiconductor substrate having a channel region, a source region and a drain region formed with the channel region interposed therebetween, and a semiconductor substrate formed on the channel region excluding a predetermined offset region adjacent to the source region on the semiconductor substrate. a gate insulating film, the channel region except for the offset region, provided via the gate insulating film, Wa
And a gate electrode connected to Dorain, when the storage of information by storing charges in the gate <br/> gate insulating film DOO
In particular, by applying a voltage to the source region,
A channel region excluding the source region and the offset region
And a non-volatile memory element in a state in which the non-volatile memory element is in a conductive state, and the non-volatile memory element shares a source region and a drain region of the non-volatile memory element adjacent in the row direction on the same semiconductor substrate. in, are arranged in a matrix, the gate electrode of the nonvolatile memory elements arranged formed in the row direction, word lines are connected respectively, including shared portion between the source region and the drain region, arranged in the column direction A bit line is connected to the source region and the drain region of the formed nonvolatile memory element in a state of being insulated from the word line, and the nonvolatile memory elements arranged and formed in the column direction are connected to each other. The device is isolated by interposing a field oxide film between the gate electrodes, and the end surface of the field oxide film on the source region side is Off
A non-volatile storage device, wherein the non-volatile storage device extends completely to a source region by completely passing over a set region. 2. A channel region instead of the nonvolatile element.
And a source region and a channel region therebetween.
A semiconductor substrate having a drain region formed thereon, and the semiconductor substrate
Upper, predetermined offset area adjacent to the source area
Gate insulating film formed on the channel region excluding
The gate is located on the channel region excluding the offset region.
A gate provided through an insulating film and connected to a word line
Plate electrode and float plate And a floating gate.
Storage of information by storing charge in
And applying a voltage to the source region.
Therefore, the channel excluding the source region and the offset region
Non-volatile memory element that can conduct to the tunnel region
The nonvolatile memory according to claim 1, wherein the nonvolatile memory is provided.
Sex storage device. 3. A channel region and the channel region.
With the source and drain regions formed
A conductive substrate, on the semiconductor substrate, adjacent to the source region;
The game formed on the channel region excluding the predetermined region
The gate insulating film and the channel region excluding the predetermined region.
A gate electrode provided via the gate insulating film;
Information storage by accumulating charge in the gate insulating film.
The non-volatile memory element that performs storage is on the same semiconductor substrate,
The source region and drain of the nonvolatile memory element adjacent in the row direction
Arranged in a matrix in such a way as to share the
Of the non-volatile memory elements formed and arranged in the row direction.
Word lines are connected to the gate electrodes, respectively,
In the column direction, including the shared part of the source and drain regions
The source region and the source of the arrayed nonvolatile memory element
Bits in the rain area, insulated from word lines
Lines are connected to each other and
The volatile storage elements are connected to the gate of the nonvolatile storage element.
By interposing a field oxide film between the electrodes,
The device is isolated and the source region of the field oxide film is
The area side end face completely passes over the predetermined area
A method for driving a nonvolatile memory device extending to a source region , wherein a substrate is set to a ground potential at the time of writing information and is connected to a gate electrode of a nonvolatile memory element to be written. In order to apply a high voltage only to the word line and select a nonvolatile memory element for writing, the bit line connected to the drain region of the nonvolatile memory element is set to the ground potential, and In order to erase the stored information by dividing it for each word line at the time of erasing the information, all the bit lines are opened and connected to the nonvolatile storage element for erasing. The word line is set to the ground potential, a high voltage is applied to the substrate and other word lines, and when reading information, the substrate is set to the ground potential and read. Out a sense voltage is applied to the word line connected to the gate electrode of the nonvolatile memory element which performs, for selecting the nonvolatile memory element to be read, is connected to the source region of the nonvolatile memory element A read voltage is applied to a given bit line, and other word lines and bit lines are set to a ground potential. 4. The non-volatile memory device according to claim 1, wherein
In place of the child, a channel region and its channel region
With the source and drain regions formed
A conductive substrate, on the semiconductor substrate, adjacent to the source region;
The game formed on the channel region excluding the predetermined region
The gate insulating film and the channel region excluding the predetermined region.
A gate electrode provided via the gate insulating film
And a floating gate.
Non-volatile storage of information by accumulating charge in the gate
Characterized by having a volatile memory element
The method for driving a nonvolatile memory device according to claim 3. 5. A method for driving a nonvolatile memory device according to claim 3 , wherein all word lines are set to the ground potential and all the word lines are set to the ground potential in order to collectively erase stored information instead of the divided erasure. A method for driving a nonvolatile memory device, wherein a bit line is left open and a high voltage is applied to a substrate.