JP3251699B2 - Non-volatile storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a flash EEPROM (Electric
rically Erasable Programable Read On ly Memory) etc., on a semiconductor substrate, or by injecting the charge, it performs storage of information by taking out a plurality of memory cells consisting of only the memory transistor, the row and column directions The present invention relates to a nonvolatile memory device which is arranged in a matrix along the line.

[0002]

2. Description of the Related Art With the recent development of the semiconductor industry, there is a demand for integration of a nonvolatile memory device for semi-permanently storing information and low-voltage driving. A nonvolatile storage device that meets this demand is disclosed in, for example, "1993 IEDM". FIG. 7 shows a configuration of the nonvolatile storage device,
FIG. 3A is a plan view showing a state in which the passivation film is peeled off, and FIG. 3B is a cross-sectional view taken along line II of FIG. As shown in FIG. 7A, this nonvolatile memory device includes a memory transistor 1 on a P-type silicon substrate 10.
A, 1B, 1C, 1D
B, 2C and 2D are arranged in a matrix along the row direction X and the column direction Y. That is, it has a one-transistor / one-cell structure.

Each of the memory transistors 1A, 1B, 1C,
1D, as shown in FIG. 7B (only the memory cells 2A and 2C appear), the N ⁺ -type source region 11 and the N-type source region 11 formed on the surface layer of the silicon substrate 10 at predetermined intervals. A drain region 12, a tunnel oxide film 14 formed on a channel region 13 formed between the source region 11 and the drain region 12, and a tunnel oxide film 14.
A floating gate 15 formed on the floating gate 15 and an ONO (oxide-nitrid
The semiconductor device includes an e-oxide film 16 and a control gate 17 formed on the ONO film 16.

[0004] The entire surface is covered with an interlayer insulating film 18, and a portion of the interlayer insulating film 18 corresponding to the drain region 12 includes:
A contact hole 19 is opened. Therefore, the floating gate 15 is connected to the tunnel oxide film 14, ON
It is surrounded by the O film 15 and the interlayer insulating film 18 and is not connected to the outside. The control gate 17 is shown in FIG.
As shown in FIG. 5, the memory cells 2A, 2B and 2C, 2D arranged in the row direction X are shared by the memory cells 2A, 2B and 2D to form word lines WL1, WL2.

As shown in FIG. 7B, the drain region 12 includes an N ⁺ layer 12a and an N ⁻ layer 12 surrounding the N ⁺ layer 12a.
b, which is a so-called double diffusion structure, and is shared by the memory transistors 1A, 1C and 1B , 1D adjacent in the column direction Y as shown in FIG. As shown in FIG. 7B, the bit lines BL1 and BL2 are formed through the contact holes 19 in the N ⁺ layer 12a.
Are in contact. Bit lines BL1 and BL2 are shown in FIG.
As shown in (a), the memory cells 2A, 2C, and 2 are extended in the column direction Y and arranged in the column direction Y.
B, 2D.

FIG. 8 is an equivalent circuit diagram showing an electrical configuration of the nonvolatile memory device. Referring to FIG. 7, a word line WL1 is connected to control gates CG of memory transistors 1A and 1B arranged along row direction X. Similarly, memory transistors 1C arranged along row direction X are similarly connected. , 1D is connected to a word line WL2.

Memory transistor 1 adjacent in column direction Y
A, the drains D of 1C are connected to each other.
The drains D of the memory transistors 1B and 1D adjacent in the column direction Y are connected to each other. Memory transistor 1
The bit line BL is located at the midpoint of the drain connection between A and 1C.
1 is connected, and a bit line BL2 is connected to a drain connection middle point of the memory transistors 1B and 1D.

Each of the memory transistors 1A, 1B, 1C,
A source line SL is commonly connected to the 1D source S. Here, with reference to FIG. 8 and Table 1, each operation of writing, erasing, and reading information in the nonvolatile storage device will be described.

[0009]

[Table 1]

<Write> In FIG. 8, it is assumed that information is written to memory cell 2A. First, when writing information, all memory cells 2A, 2B, 2C,
Electrons are collectively injected into the floating gates FG of the memory transistors 1A, 1B, 1C, and 1D in the 2D to be in an erased state. Then, open the source line SL
In addition to the (open) state, 0 V is applied to the substrate SUB. A voltage of -7 V is applied to the word line WL1 to which the memory cell 2A is connected, and 5 V is applied to the bit line BL1 to which the memory cell 2A is connected to select the memory cell 2A. Further, the word line W to which the unselected memory cells 2B and 2D are connected.
0 V is applied to L2 and the bit line BL2 to which the unselected memory cells 2C and 2D are connected.

Then, in the selected memory cell 2A, the electrons accumulated in the floating gate FG of the memory transistor 1A are converted to FN (F
owler-Nordheim) It is pulled out to the drain D side by tunneling. As a result, the memory cell 2A enters a state where information is written. <Erase (ERASE)> Information is erased collectively. That is, 0V is applied to all the bit lines BL1 and BL2, the source line SL, and the substrate SUB, and 20V is applied to all the word lines WL1 and WL2.

Then, all memory cells 2A, 2A
In B, 2C and 2D, the memory transistors 1A, 1B,
An FN tunnel current is generated between the control gates CG of the 1C and 1D and the substrate, and electrons are injected into the floating gate FG by the FN tunnel current.
As a result, all the memory cells 2A, 2B, 2C, 2D
Becomes an information erasing state. <Reading (READ)> In FIG. 8, it is assumed that information stored in the memory cell 2A is read. First, 0 V is applied to the source line SL and the substrate SUB. Word line WL to which memory cell 2A is connected
In order to apply 3V to 1 and select the memory cell 2A, the bit line BL to which the memory cell 2A is connected is
1V is applied to one. Also, 0V is applied to the word line WL2 to which the unselected memory cells 2C and 2D are connected, and the bit line BL2 to which the unselected memory cells 2B and 2D are connected is opened.

Then, in the memory cell 2A,
The floating gate F of the memory transistor 1A
In a write state where electrons are not accumulated in G, the source S-drain D of the memory transistor 1A conducts, and a channel is formed. That is, the memory cell 2
A current flows in A. On the other hand, when the memory transistor 1A is in an erased state in which electrons are accumulated in the floating gate FG, the source S-drain D of the memory transistor 1A does not conduct, and no channel is formed. That is, no current flows in the memory cell 2A. By sensing this state, reading of information stored in the memory cell 2A is achieved.

[0014]

The non-volatile memory device shown in FIGS. 7 and 8 uses FN tunneling when rewriting information, so that low-voltage driving is possible.
Power consumption can be reduced. As a result, the external supply voltage 3-5
A single power supply of V can be used, and the internal booster circuit can sufficiently cover it. Therefore, an external booster circuit becomes unnecessary,
The device becomes smaller. Further, since the memory transistor has a one-transistor / one-cell structure and the drain region is shared between memory transistors adjacent in the column direction, the cell area is reduced, which contributes to a higher degree of integration.

By the way, in order to support a next-generation device, further higher integration is required. However, in the above-mentioned nonvolatile memory device, since the bit line and the drain region are in contact with each other, it is necessary to secure a contact margin regardless of how fine the element is. That is, the cell area cannot be reduced by the amount of the contact margin, and it is not possible to support a next-generation device.

In order to cope with the above, in recent years, a so-called FAC that does not make contact with an impurity diffusion layer on a substrate is used.
An E (Flash Array Contactless EPROM) structure has been proposed. This FACE structure does not require a contact, and is said to be sufficiently compatible with next-generation devices.
Thus, if the nonvolatile storage device has a FACE structure, the configuration is as shown in FIG. 9A and 9B show a configuration of a nonvolatile memory device having a FACE structure. FIG. 9A is a plan view showing a state in which a passivation film is removed, and FIG. 9B is a plan view showing II-II in FIG. It is a line sectional view.
In this nonvolatile memory device, as shown in FIG. 9B (only the memory cells 2A and 2B appear), the source of the memory transistors adjacent to each other in the row direction X is formed on the surface layer of the P-type silicon substrate 10. N-type impurity diffusion layers 21, 22, and 23 serving as regions and drain regions are formed on the substrate 30 at predetermined intervals without making contact.

Each of the impurity diffusion layers 21, 22, 23 is formed as shown in FIG.
As shown in (a), the contact extends from the back side of the substrate 30 at a predetermined location and extends in the column direction Y. That is, the leftmost impurity diffusion layer 21 in the figure is the memory cells 2A, 2A arranged in the column direction Y.
The bit line BL1 is shared by C and a memory cell (not shown). The impurity diffusion layer 22 is shared by the memory cells 2A, 2C and 2B, 2D arranged along the column direction Y to form a bit line BL2. The rightmost impurity diffusion layer 23 is shared by the memory cells 2B and 2D arranged along the column direction Y and a memory cell (not shown) to form a bit line BL3. The other configuration is the same as that of the nonvolatile memory device shown in FIG.

FIG. 10 is an equivalent circuit diagram showing an electrical configuration of the nonvolatile memory device having the FACE structure. Referring to FIG. 7, a word line WL1 is connected to control gates CG of memory transistors 1A and 1B arranged along row direction X. Similarly, memory transistors 1C arranged along row direction X are similarly connected. , 1D is connected to a word line WL2.

The memory transistors arranged along the word line WL1 are connected in an array by connecting the sources S and drains D of adjacent memory transistors. Similarly, the memory transistors arranged along the word line WL2 are also connected in an array.
In the figure, the source S of the leftmost memory transistor 1A is shown.
And the connection point between the drain of the memory transistor (not shown) and the source S of the leftmost memory transistor 1C.
The bit line BL1 is connected to a connection middle point between the bit line BL1 and a drain of a memory transistor (not shown). A bit line BL2 is connected to a connection midpoint between the drain D of the memory transistor 1A and the source S of the memory transistor 1B and a connection midpoint between the drain D of the memory transistor 1C and the source S of the memory transistor 1D. I have. In the figure, the rightmost memory transistor 1
B, the middle point of connection between the drain of B and the source of a memory transistor (not shown), and the rightmost memory transistor 1D
A bit line BL3 is connected to a connection midpoint between the drain D of the memory cell and the source of a memory transistor (not shown).

However, in the above-mentioned nonvolatile memory device, when information is written by the driving method shown in Table 1, the write selectivity is lost, and the non-selected memory cell sharing the word line with the selected memory cell is lost. Write disturb occurs. That is, as shown in FIG. 10, for example, when the memory cell 2A is selected at the time of writing information, −7 V is applied to the word line WL1 and the bit lines BL1 and BL3 are applied.
0V and 5V to the bit line BL2. Therefore, the unselected memory cell 2B is applied under the same voltage condition as the selected memory cell 2A. Therefore, the electrons accumulated in the floating gate FG of the memory transistor 1B in the memory cell 2B are extracted to the source S side by FN tunneling. As a result, information is erroneously written into the unselected memory cell 2B.

In view of the above, the present invention prevents the occurrence of disturb at the time of writing information and secures the write selectivity.
It is an object of the present invention to provide a nonvolatile memory device capable of reducing a cell area.

[0022]

In order to achieve the above object, a nonvolatile memory device according to the present invention provides a nonvolatile memory device for injecting and extracting electric charges onto and from a semiconductor substrate of a predetermined first conductivity type. A plurality of memory cells composed of memory transistors are arranged in a matrix along a row direction and a column direction, and a predetermined number of memory cells are formed on a surface layer of the semiconductor substrate. The source line and the drain region of the memory transistors adjacent to each other in the row direction are formed along the column direction at intervals, and are the bit lines shared by the memory cells arranged in the column direction. A plurality of impurity diffusion layers having a second conductivity type opposite to the first conductivity type;
A tunnel insulating film formed at a predetermined offset distance from the source region on each of the channel regions generated so as to be sandwiched between the adjacent impurity diffusion layers and capable of passing charges generated in the channel region; A charge accumulation layer formed on the film and accumulating electric charges passing through the tunnel insulating film; and a control layer formed on each of the charge accumulation layers.
And Lumpur gate, on the remaining region of the channel regions,
A channel region, a sidewall gate formed in an insulated state from the charge storage layer and the control gate, and a sidewall direction formed on each of the sidewall gates and the control gate, and formed in the row direction. A word line that is shared by memory cells arranged along the memory cell, and a predetermined control voltage can be applied to a control gate and a side wall gate of a memory transistor adjacent in the row direction . Wardra
When a high voltage with the same polarity as the substrate is applied to
In addition, all bit lines are set to ground potential and all
Control gate of memory transistor in recell
An FN tunnel current is generated between the substrates, and the FN tunnel current is generated.
Erasing means for collectively injecting charges into the charge storage layer by using a charge current
At the time of writing information,
The memory transistor is connected to the connected word line.
Without inverting the substrate surface directly below the sidewall gate
The same pole as the impurity diffusion layer, which can form an offset region
Memory cells to which information is to be written by applying
To select the memory transistor in the memory cell.
Write to the bit line to which the drain region is connected.
Voltage, and other word lines and vias.
The FN tunneling with the
Power of the memory transistor in the selected memory cell.
The charge accumulated in the load accumulation layer is drawn to the drain region side.
Writing means for extracting the information and a means for reading the information when reading the information.
Note the word line to which the memory cell is connected.
Substrate surface just below the re-transistor sidewall gate
A sense voltage that can invert the
To select a memory cell, the memory
The bit line to which the source region of the transistor is connected
To the ground potential and the drain region is connected.
Voltage at which cell current can be generated for each bit line
And the other word lines are connected to the ground potential.
And read means for opening other bit lines.
It is characterized by having .

In the above configuration, since a so-called FACE structure in which a contact with the impurity diffusion layer is not formed on the substrate is provided, there is no need to secure a contact margin, and a one-transistor / one-cell structure is provided. Therefore, the cell area can be significantly reduced .

[0024] In writing information, the charge storage layer of the memory transistors in advance all the memory cells, keep the erased state collectively injecting charges. Each memory transistor is divided into a charge storage layer and a control gate offset with respect to the source region, and a sidewall gate disposed on the offset region, and a predetermined control voltage is applied to both gates. It is supposed to be. Therefore, when writing information, the writing means
A high voltage of the same polarity as the impurity diffusion layer is applied to each control gate and sidewall gate of the memory transistor in the selected memory cell and the memory transistor in the non-selected memory cell sharing the word line with the selected memory cell. Is applied. As a result, the surface of the substrate immediately below each sidewall gate is not inverted,
An offset area is formed.

At this time, in the memory transistor in the selected memory cell, the charge in the charge storage layer is drawn out to the drain region side by FN tunneling. As a result, the selected memory transistor enters a write state in which no charge is stored in the charge storage layer. On the other hand, in a non-selected memory cell that shares a word line with a selected memory cell, although a write voltage is applied, an offset region is formed on the source region side of the non-selected memory transistor, so that charge storage is performed. The FN tunnel mechanism does not work between the layer and the source region. As a result, the charge remains stored in the charge storage layer, and the erased state is maintained. That is, no write disturbance occurs in the non-selected memory cells, and no information is erroneously written.

[0026] At the time of erasing the information, the erasing means, the control gates of all memory transistors is applied a high voltage of the same polarity and the impurity diffusion layers result, control
Lumpur gate - FN tunneling current is generated between the substrates. Along with this, the charges are entirely injected into the charge storage layer. As a result, all the memory transistors enter an erased state in which charges are stored in the charge storage layer. As described above, since information is erased by injecting charges entirely into the charge storage layer by the FN tunnel current,
The deterioration of the tunnel insulating film can be prevented, the number of times of rewriting increases, and the rewriting speed increases.

At the time of reading information, a sense voltage is applied to each control gate and sidewall gate of a selected memory cell and a memory transistor in an unselected memory cell sharing a word line with the selected memory cell. Is applied. Therefore, the surface of the substrate immediately below each sidewall gate is inverted, and an inversion layer is generated. At this time, if the memory transistor in the selected memory cell is in a write state in which no charge is stored in the charge storage layer, the influence of the sense voltage applied to the control gate will affect the charge storage layer. It reaches the substrate surface immediately below. Therefore, the surface of the substrate immediately below the charge storage layer is inverted, and charges are induced on the surface of the substrate. Accordingly, the induced charges are connected to the inversion layer. As a result, conduction is established between the source region and the drain region, and a channel is formed. That is, current flows through the selected memory cell. On the other hand, in the erase state where the charge is stored in the charge storage layer of the non-selected memory transistor, the influence of the sense voltage applied to the control gate affects the charge stored in the charge storage layer. And does not reach the substrate surface immediately below the charge storage layer. As a result, no conduction is made between the source region and the drain region, and no channel is formed. That is, no current flows through the unselected memory cells. in this way,
Since the information can be read using the inversion of the offset area, the reading speed is increased.

[0028]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below in detail with reference to FIGS. 1A and 1B show a configuration of a nonvolatile memory device according to an embodiment of the present invention. FIG. 1A is a plan view showing a state in which a passivation film is removed, and FIG. FIG. 4 is a sectional view taken along line IV-IV of FIG. Referring to FIG.
The configuration of the nonvolatile memory device according to the present embodiment will be described.

The nonvolatile memory device according to the present embodiment has the structure shown in FIG.
As shown in (a), memory transistors 10A, 10B, 10C, 10D, 10
E, 10F, memory cells 20A, 20B, 2
0C, 20D, 20E, and 20F are arranged along the row direction X and the column direction Y. 1B (memory cells 20A, 20B, 2)
Only 0C appears. As shown in (), N-type impurity diffusion layers 31 and 32 serving as source and drain regions of memory transistors adjacent to each other in the row direction X are formed at predetermined intervals. The impurity diffusion layers 31 and 32
N ⁺ layer 31a, and 32a, the N ⁺ layer 31a, surrounding the 32a N ^- layer 31b, consisting of 32b, has a so-called double diffusion structure. 1A, the impurity diffusion layer 31 on the left side extends in the column direction Y as shown in FIG. 1A, and the memory cells 2 arranged in the column direction Y.
The bit line BL1 is shared by 0A and 20D and 20B and 20E. Similarly, the right impurity diffusion layer 32 also extends along the column direction Y, and the memory cells 20B, 20E and 20C, 2C arranged along the column direction Y.
The bit line BL2 is shared by 0F.

As shown in FIG. 1B, a tunnel oxide film 34 is formed on each of the channel regions 33 formed between the impurity diffusion layers 31 and 32 at a predetermined offset distance from the source region. ing. Tunnel oxide film 34
Is for tunneling charges generated in the channel region 33. Therefore, the tunnel oxide film 33 is made of SiO
Consists of _two and has a thickness, as capable of tunneling the charge, for example, is extremely thin set to about 100 Å.

On each tunnel oxide film 34, a floating gate 35 is formed. The floating gate 35 stores charges tunneling through the tunnel oxide film 34 and is made of, for example, polysilicon having a low resistance by doping As, P or the like at a high concentration. Also,
Each floating gate 35 is arranged in an island shape as shown in FIG.

On each floating gate 35, FIG.
As shown in (b), an ONO film 36 is formed.
The ONO film 36 is for keeping electric charges in the floating gate 35 for a long time, and has a structure in which a Si ₃ N ₄ film is sandwiched between SiO ₂ films from above and below. The lowermost SiO ₂ film has a thickness of about 120 °
The thickness of the i ₃ N ₄ film is set to about 200 °, and the thickness of the uppermost SiO ₂ film is set to about 50 °.

On the ONO film 36, a control gate 37 is formed. Each control gate 37
For example, it is made of polysilicon whose resistance is reduced by doping As, P or the like at a high concentration, and is arranged in an island shape as shown in FIG. On the remaining region of each channel region 33, as shown in FIG. 1B, the side wall gate 3 is insulated from the channel region 33, the floating gate 35, the ONO film 36, and the control gate 37.
8 are formed. The side wall gate 38 is made of, for example, polysilicon having a low resistance by doping As, P or the like at a high concentration, and is arranged in an island shape as shown in FIG.

Each memory transistor 10A, 10B, 1
As shown in FIG. 1 (b), the interlayer insulating film 39 is exposed between the control gates 37C and the sidewalls 38 while the upper surfaces of the control gates 37 and the sidewall gates 38 are exposed.
Is filled. Therefore, each floating gate 35 is surrounded by the insulating film and is not connected to the outside. The interlayer insulating film 39 is made of PS doped with P-doped SiO _2.
BPSG with B mixed in G (phosho-silicate-glass)
( boron- phosho-silicate-glass).

Memory transistors 10A, 10B, 10
A word line WL1 is formed on the C control gate 37 and the sidewall gate 38. The word line WL1 extends in the row direction X, and the memory cells 20A, 20B, 2 arranged in the row direction X.
Shared by 0C. Similarly, memory transistor 1
As shown in FIG. 1A, a word line WL2 is formed extending along the row direction X on the control gate 37 and the side wall gate 38 of 0D, 10E, and 10F. Memory cells 20 arranged in
D, 20E, and 20F. Word line W
L1 and WL2 are made of a wiring material such as tungsten polycide. That is, each memory transistor 1
The gates 0A, 10B, 10C, 10D, 10E, and 10F are composed of a floating gate 35 and a control gate 37 arranged offset from the source region, and a sidewall gate 38 arranged on the offset region.
When writing, erasing and reading information, a predetermined control voltage is applied to both gates 37 and 38.

Note that, in the figure, the crosses indicate channel stop ions implanted to suppress surface leakage current in the substrate 30. As described above, since the nonvolatile memory device has a so-called FACE structure in which no contact is made with the impurity diffusion layers 31 and 32 on the substrate 30, it is not necessary to secure a contact margin, and one transistor is required. Since it has a / 1 cell structure, the cell area can be significantly reduced.

FIG. 2 is a schematic sectional view showing a method of manufacturing the nonvolatile memory device in the order of steps, and shows only one memory cell for convenience of explanation. The method for manufacturing the nonvolatile memory device will be described with reference to FIG. First, a tunnel oxide film, a floating gate, an ONO film, and a control gate are formed. That is, as shown in FIG. 2A, the tunnel oxide film 34 is formed by thermally oxidizing the P-type silicon substrate 20 and growing an SiO ₂ film on the entire surface.
Subsequently, LPCVD (low pressure chemical vapor dep
The first polysilicon film 40 is deposited on the tunnel oxide film 34 by the osition method. Further, an ONO film 36 is stacked on the polysilicon film 40. Next, LPCV
Second polysilicon film 4 on ONO film 36 by D method
1 is deposited. Then, on the polysilicon film 41 of the second layer, after forming a resist on the island, this resist as a mask, a portion of the polysilicon film 41, ONO film 36及beauty Po Rishirikon film 40 protruding from the resist Etch. Thereby, as shown in FIG. 2B, the floating gate 35 and the control gate 37 are formed in an island shape. After the formation of the floating gate 35 and the control gate 37, channel stop ions such as B ⁺ are implanted. Note that the resist used as the mask is used up and is removed.

When the gate forming step is completed, a sidewall gate is formed. That is, as shown in FIG. 2C, the silicon substrate 30 is thermally oxidized and SiO
_{2 The} film 42 is grown. Then, by LPCVD method,
After a polysilicon film for forming a sidewall gate is deposited on the entire surface, the SiO ₂ film 5 on the control gate 37 is formed.
The polysilicon film for forming the sidewall gate is etched back until the floating gate 3 is exposed.
5. A pair of sidewalls are formed on both sides of the ONO film 36 and the control gate 37. Thereafter, one sidewall is anisotropically etched. The sidewall remaining at this stage becomes a sidewall gate 38 as shown in FIG.

When the sidewall gate forming step is completed, an impurity diffusion layer is formed. First, as shown in FIG. 2D, P ⁺ is implanted with high energy using the control gate 37, the ONO film 36, and the floating gate 35 as a mask. Subsequently, As ⁺ is implanted with low energy using the control gate 37, the ONO film 36, and the floating gate 35 as a mask. Thereafter, annealing is performed for a predetermined time. Then, impurity diffusion layers 31 and 32 composed of N ⁺ layers 31a and 32a and N ⁻ layers 31b and 32b are formed along the column direction in a self-aligned manner.

When the impurity diffusion layer forming step is completed,
The formation of an interlayer insulating film and metallization are performed. That is, as shown in FIG.
After the BPSG is deposited on the entire surface by the (r deposition) method, the BPSG is etched back until the upper surfaces of the control gate 37 and the sidewall gate 38 are exposed to form an interlayer insulating film 39. After that, PVD (physical
The vapor deposition) method, is deposited on the entire surface of the tungsten polycide, Pas <br/> to te two ring in stripes along the tungsten polycide in the row direction using a mask alignment and RIE. As a result, as shown in FIG.
Word lines WL1 and WL2 are formed along the row direction.

When the interlayer insulating film forming step and the metallization are completed, a passivation film is formed.
That is, as shown in FIG.
An insulating material such as Si ₃ N ₄ is deposited on the entire surface to form a passivation film 43. At this time, the impurity diffusion layer 3
1,32 Toko filtrate far from the (e.g., 32-bit intervals)
Then, the contact is backed by embedding Al or the like, and connected by a bonding wire.

FIG. 3 is an equivalent circuit diagram showing an electrical configuration of the nonvolatile memory device. Referring to FIG. 5, the control gate CG and the side wall gate SG of the memory transistors 10A and 10B arranged along the row direction X include:
The word line WL1 is connected, and similarly, the memory transistors 10C and 10D arranged along the row direction X
Control gate CG and sidewall gate S
The word line WL2 is connected to G.

The memory transistors arranged along the word line WL1 are connected in the form of an array by connecting the sources S and drains D of adjacent memory transistors. Similarly, the memory transistors arranged along the word line WL2 are also connected in an array.
In the figure, the source S of the leftmost memory transistor 10A is shown.
A bit line BL1 is connected to a connection middle point between the memory transistor and the drain of the memory transistor (not shown) and the source S of the leftmost memory transistor 10C and a drain of the memory transistor (not shown).
A bit line BL2 is connected to a connection midpoint between the drain D of the memory transistor 10A and the source S of the memory transistor 10B and a connection midpoint between the drain D of the memory transistor 10C and the source S of the memory transistor 10D. I have. Rightmost memory transistor 1
0B and the middle point of connection between the drain of the memory transistor (not shown) and the rightmost memory transistor 1
A bit line BL3 is connected to a connection midpoint between the drain D of 0D and the source of a memory transistor (not shown).

An X (positive) decoder 51 is connected to one end (left side in the figure) of the word lines WL1 and WL2, and an X (negative) decoder 52 is connected to the other end. The X decoders 51 and 52 apply a predetermined voltage to the word lines WL1 and WL2 when writing, erasing and reading information. A positive voltage boosting circuit 53 is connected to the X (positive) decoder 51, and the X (negative) decoder 5
2, a negative voltage boosting circuit 54 is connected.

A Y decoder 60 is connected to the bit lines BL1, BL2 , BL3 . Y decoder 60
Indicates the bit line B when writing, erasing and reading information.
A predetermined voltage is applied to L1, BL2 and BL3 . A voltage generator 61 is provided at one end of the Y decoder 60.
Is connected, and the other end is connected to a sense amplifier (SA) 62.
Is connected.

X (positive) decoder 51, X (negative) decoder 52, positive voltage booster 53, negative voltage booster 54 and Y
The decoder 60 receives a control signal from the control circuit 70 and is controlled by the control signal. Here, with reference to FIG. 3 and Table 1, each operation of writing, erasing, and reading information in the nonvolatile storage device will be described.

[0047]

[Table 2]

<Write> In FIG. 3, it is assumed that information is written to memory cell 20A. First, at the time of writing information, electrons are collectively injected into the floating gates FG of the memory transistors 10A, 10B, 10C, and 10D in all the memory cells 20A, 20B, 20C, and 20D in advance so that the memory cells are erased. Then, the X (negative) decoder 52 and the negative voltage boosting circuit 54 apply -7 V to the word line WL1 to which the memory cell 20A is connected. Memory cell 2
In order to select 0A, the Y decoder 60 applies 0 V to the bit line BL1 to which the source S of the memory transistor 10A in the memory cell 20A is connected and 5 V to the bit line BL2 to which the drain D is connected.
V is applied. The X (positive) decoder 51 and the Y decoder 60 cause the non-selected memory cells 20B,
0 V is applied to the word line WL2 connected to the memory cell 20D and the bit line BL2 connected to the unselected memory cells 20C and 20D.

Then, the selected memory cell 20A
In this case, the electrons accumulated in the floating gate FG of the memory transistor 10A are
It is pulled out to the drain D side by N tunneling. As a result, memory cell 20A is in a state where information is written.
A gate voltage required for conducting between the source and the drain differs between a state where electrons are accumulated in the floating gate and a state where electrons are not accumulated in the floating gate. That is, the threshold voltage V _TH for conducting between the source and the drain takes a high threshold value V1 (for example, 5 V) in a state where electrons of the floating gate are injected, and a low threshold value in a state where electrons are not injected. Value V2
(For example, 2 V). Thus, the threshold voltage V _TH
Is set to two types, binary data of “0” or “1” can be stored in the memory cell. <Erase (ERASE)> Information is erased collectively. That is, 0 V is applied to all the bit lines BL1, BL2, and BL3 by the Y decoder 60, and 20 V is applied to all the word lines WL1 and WL2 by the X (positive) decoder 51 and the positive voltage boosting circuit 53.
V is applied.

Then, all the memory cells 20A, 2A
0B, 20C and 20D, the memory transistor 10
Control gate CG for A, 10B, 10C, 10D
-An FN tunnel current is generated between the substrates, and electrons are injected into the floating gate FG by the FN tunnel current. As a result, all the memory cells 20A,
20B, 20C, and 20D are in an information erase state. <Reading (READ)> In FIG. 3, it is assumed that information stored in the memory cell 20A is read. The X (positive) decoder 51 applies 3 V to the word line WL1 to which the memory cell 20A is connected. To select the memory cell 20A, the Y decoder 60 applies 0 V to the bit line BL1 connected to the source S of the memory transistor 10A in the memory cell 20A, and applies 0 V to the bit line BL2 connected to the drain D. 1V is applied. The X (positive) decoder 51 is connected to the word line to which the unselected memory cells 20C and 20D are connected.
0 V is applied to WL2 , and the Y decoder 60
The bit line BL3 to which the unselected memory cells 20B and 20D are connected is opened.

Then, in the memory cell 20A, in a write state where electrons are not accumulated in the floating gate FG of the memory transistor 10A, the source S-drain D of the memory transistor 10A conducts, and the channel becomes It is formed. That is, a current flows in the memory cell 20A. On the other hand, when the memory transistor 10A is in an erased state in which electrons are accumulated in the floating gate FG, the source S-drain D of the memory transistor 10A does not conduct, and no channel is formed. That is, no current flows in the memory cell 20A. This state is sensed by the decoders 51 and 60 and the sense amplifier 62, whereby the memory cell 20A
The reading of the information stored in the.

Here, the sense voltage is an intermediate voltage between the two types of V1 and V2 of the threshold voltage _VTH . Therefore, when this sense voltage is applied, conduction / non-conduction between the source and the drain is determined depending on whether electrons are accumulated in the floating gate. As described above, since the FN tunneling is used when rewriting information, low-voltage driving can be performed.

FIG. 4 is a diagram showing the operating principle of the memory transistor at the time of writing, FIG. 5 is a diagram showing the operating principle of the memory transistor at the time of erasing, and FIG. 6 is a diagram showing the operating principle of the memory transistor at the time of reading. . The operation principle of the memory transistor will be described with reference to FIGS. <Write> It is assumed that information is written to the memory cell 20A shown in FIG. At this time, as described above, each memory transistor is divided into a floating gate and a control gate which are arranged offset with respect to the source region, and a sidewall gate which is arranged on the offset region. Since a predetermined control voltage is applied, as shown in FIGS. 4A and 4B,
Memory transistor 1 in selected memory cell 20A
0A, the selected memory cell 20A and the word line WL1.
-7V is applied to each control gate 37 and the side wall gate 38 of the memory transistor 10B in the unselected memory cell 20B sharing the same. Therefore, the surface of the substrate 30 immediately below each sidewall gate 38 is not inverted, and the offset region OS is formed.

At this time, in the memory transistor 10A in the selected memory cell 20A, as shown in FIG.
The electrons in the floating gate 35 are extracted to the drain region side by the FN tunneling. As a result, the memory transistor 10A enters a write state in which no electrons are accumulated in the floating gate 35, as shown in FIG.

On the other hand, in the unselected memory cell 20B sharing the word line WL1 with the selected memory cell 20A,
Although 5 V is applied to the bit line BL2, as shown in FIG.
Since the offset region OS is formed on the source region side of the floating gate 35, the F
N tunnel mechanism does not work. As a result, as shown in FIG. 4B, electrons remain stored in the floating gate 35, and the erased state is maintained. That is, no write disturbance occurs in the unselected memory cell 20B,
No information is accidentally written. <Erasing> As shown in FIG. 5A, a high bias is applied between the control gate 37 of all the memory transistors 10A, 10B, 10C and 10D and the substrate 30,
An FN tunnel current is generated between the control gate 37 and the substrate 30. Accordingly, the floating gate 3
Electrons are totally injected into 5. as a result,
All memory transistors 10A, 10B, 10C, 1
0D is in an erased state in which electrons are accumulated in the floating gate 35, as shown in FIG.

As described above, since information is erased by injecting electrons entirely into the floating gate 35 by the FN tunnel current, deterioration of the tunnel oxide film 34 can be prevented, and the number of times of rewriting increases. At the same time, the rewriting speed increases. <Reading> It is assumed that information stored in the memory cell 20A shown in FIG. 3 is read. At this time, as shown in FIGS. 6A and 6B, each control of the selected memory cell 20A and the memory transistors 10A and 10B in the non-selected memory cell 20B sharing the word line WL1 with the selected memory cell 20A. Gate 37 and sidewall gate 3
8, a sense voltage of 3 V is applied. Therefore, the surface of the substrate 30 immediately below each sidewall gate 38 is inverted, and an inversion layer 60 is generated.

At this time, in the memory transistor 20A in the selected memory cell 20A, as shown in FIG.
If the floating gate 35 is in a write state where electrons are not accumulated, the effect of the sense voltage applied to the control gate 37 reaches the surface of the substrate 30 immediately below the floating gate 37. Therefore, the surface of the substrate 30 immediately below the floating gate 37 is inverted, and electrons are induced on the surface of the substrate 30. Accordingly, the induced electrons and the inversion layer 60 are connected. As a result, conduction is established between the source region and the drain region, and a channel CH is formed. That is, a current flows through the memory transistor 10A.

On the other hand, as shown in FIG. 6B, in an erased state in which electrons are accumulated in the floating gate 35 of the memory transistor 10A, the effect of the sense voltage applied to the control gate affects the floating gate 35. And does not reach the surface of the substrate 30 immediately below the floating gate 35. As a result, no conduction is made between the source region and the drain region, and no channel is formed. That is, no current flows through the memory transistor 10A.

In a non-selected memory cell 20B sharing the word line WL1 with the selected memory cell 20A,
Since the bit line BL3 is open, FIG.
(A) As shown in (b), the memory transistor 1
No cell current flows regardless of the state of 0B. As described above, information can be read using the inversion of the offset area OS, and thus the reading speed is increased.

As described above, according to the nonvolatile memory device of the present embodiment, the cell area can be reduced while preventing the occurrence of disturbance at the time of writing information and ensuring write selectivity. It will be useful for the development of next generation devices. It should be noted that the present invention is not limited to the above-described embodiment, and it goes without saying that many modifications and changes can be made within the scope of the present invention.

For example, in the above-described embodiment, an example is described in which a memory transistor that stores charges in a floating gate is used. However, the same effect can be obtained even if the floating gate is eliminated and the memory transistor is replaced with a MONOS structure or an MNOS structure. Get.

[0062]

As is apparent from the above description, according to the present invention, there is provided an excellent effect that the cell area can be reduced while preventing the occurrence of disturbance at the time of writing information and ensuring write selectivity. is there.

[Brief description of the drawings]

FIGS. 1A and 1B show a configuration of a nonvolatile memory device according to an embodiment of the present invention, in which FIG. 1A is a plan view showing a state in which a passivation film is removed, and FIG. ) IV-
FIG. 4 is a sectional view taken along line IV.

FIG. 2 is a schematic cross-sectional view illustrating a method for manufacturing a nonvolatile memory device in the order of steps.

FIG. 3 is an equivalent circuit diagram illustrating an electrical configuration of a nonvolatile memory device.

FIG. 4 is a diagram illustrating an operation principle of a memory transistor at the time of writing.

FIG. 5 is a diagram illustrating an operation principle of a memory transistor at the time of erasing;

FIG. 6 is a diagram showing the operation principle of a memory transistor at the time of reading.

FIG. 7 shows a configuration of a conventional nonvolatile storage device,
FIG. 3A is a plan view showing a state in which the passivation film is peeled off, and FIG. 3B is a cross-sectional view taken along line II of FIG.

FIG. 8 is an equivalent circuit diagram showing an electrical configuration of a conventional nonvolatile memory device.

9A and 9B show a configuration of a nonvolatile memory device having a FACE structure. FIG. 9A is a plan view showing a state in which a passivation film is removed, and FIG.
FIG. 2 is a sectional view taken along line II.

FIG. 10 is an equivalent circuit diagram showing an electrical configuration of a nonvolatile memory device having a FACE structure.

[Explanation of symbols]

 10A, 10B, 10C, 10D Memory transistor 20A, 20B, 20C, 20D Memory cell 30 Silicon substrate 31, 32 Impurity diffusion layer 33 Channel region 34 Tunnel oxide film 35 Floating gate 36 ONO film 37 Control gate 38 Side wall gate 51X ( Positive) decoder 52 X (negative) decoder 60 Y decoder 62 Sense amplifier WL1, WL2 Word line BL1, BL2, BL3 Bit line

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-5-36986 (JP, A) JP-A-2-114467 (JP, A) JP-A-5-82798 (JP, A) JP-A-6-1994 204493 (JP, A) JP-A-6-196663 (JP, A) JP-A-6-177395 (JP, A) JP-A-6-177358 (JP, A) JP-A-6-151782 (JP, A) JP-A-6-196714 (JP, A) JP-A-5-152579 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 21/8247 H01L 27/115 H01L 29/788 H01L 29/792

Claims (1)

(57) [Claims] A plurality of memory cells, each comprising a memory transistor, for storing information by injecting or extracting electric charges on a semiconductor substrate having a predetermined first conductivity type, are arranged in rows and columns. A source region between memory transistors adjacent to each other in a row direction and formed along a column direction at predetermined intervals on a surface layer of the semiconductor substrate. And a plurality of impurity diffusion layers having a second conductivity type opposite to the first conductivity type, serving as a drain region and a bit line shared by memory cells arranged in the column direction. On each of the channel regions generated so as to be sandwiched between the adjacent impurity diffusion layers, the source regions are formed at a predetermined offset distance and pass through the charge generated in the channel region. A tunnel insulating film that can be formed on each of the tunnel insulating film, a charge storage layer for storing charge that has passed through the tunnel insulating film, a control gate formed on the respective charge storage layer, each channel On the remaining area of the area, the channel area,
And a sidewall gate formed insulated from the charge storage layer and the control gate, and shared by the memory cells formed along the row direction and arranged along the row direction on each of the sidewall gates and the control gate. are, a word line in which a predetermined control voltage is adapted to be applied to the control gate and the side wall gate of the memory transistors adjacent in the row direction, at the time of erasing the information, the a substrate for all the word lines
Apply high voltage of one polarity and all bit lines
To the ground potential, the memory transistors in all memory cells
FN tunneling power between control gate and substrate
Current, and the FN tunnel current causes a charge accumulation layer
Erase means for collectively injecting electric charge into the memory cell and a memory cell for writing information when writing information.
Memory transistor for the word line
Turn the substrate surface directly under the sidewall gate
Of the same polarity as the impurity diffusion layer that can form
Apply high voltage and select memory cell to write information
Therefore, the drain of the memory transistor in the memory cell
Write voltage to the bit line to which the
Pressure and other word lines and bits
Line is set to ground potential and selected by FN tunneling.
Charge accumulation of memory transistor in selected memory cell
For drawing out the charge accumulated in the layer to the drain region side
And the memory cell from which information is to be read at the time of reading the information.
Memory transistor for the word line
A sensor where the substrate surface directly below the sidewall gate can be inverted.
A memory cell for reading information.
Therefore, the source of the memory transistor in the memory cell is
The bit line to which the source region is connected to ground potential
With the bit line to which the drain region is connected.
On the other hand, a read voltage at which a cell current can be generated is applied,
Other word lines are set to ground potential and other bits
A non-volatile storage device, comprising: reading means for opening a line .