JP2003188287A - Non-volatile semiconductor memory device and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a non-volatile semiconductor memory device and the manufacturing method of the same, reduced in the affection of an interference due to a coupling capacity between neighbored memory cells and improved in the operational margin of the memory cell. <P>SOLUTION: The non-volatile semiconductor memory device is provided with a plurality of memory cell transistors 7, having a gate constituted of a floating gate 3 laminated on a gate insulation film 2 formed in an element region 16 on a p-type semiconductor substrate 1 through a gate insulation film 4 and a control gate 5, and an n-type diffusion layer 6 formed on the surface of the p-type semiconductor substrate 1 between the gates so as to become a source or a drain. Further, a source side selective transistor 9 is arranged on the source side of the memory cell transistor 7. A conductive layer 11 constituted of polysilicon added with impurities, for example, is embedded on the memory cell transistor 7 and the source side selective transistor 9 through an insulation film 10. In this case, the source region of the source side selective transistor 9 and the conductive layer 11 are directly connected. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a non-volatile semiconductor memory device, and more particularly to a semiconductor memory device having a non-volatile memory cell transistor having a stacked structure of a floating gate and a control gate, and a manufacturing method thereof. .

[0002]

2. Description of the Related Art Conventionally, as an electrically rewritable non-volatile semiconductor memory device (EEPROM) suitable for large capacity, a NAND flash in which a large number of memory cells connected in series are arranged in a matrix. There is a NAND flash memory having a memory cell array. FIG. 9 shows an equivalent circuit of the NAND flash memory cell array. 10 is a plan view of the memory cell array, and FIG. 11 is a bit line direction of the memory cell array, that is, a sectional view taken along the line AA 'in FIG.

As shown in FIGS. 9 to 11, a memory cell transistor (MT) 101 includes a floating gate 1 on a p-type semiconductor substrate 102 with a gate insulating film 103 interposed therebetween.
04 is formed, and the control gate 106 is stacked on the floating gate 104 with the inter-gate insulating film 105 interposed therebetween. The control gate 106 is formed continuously in the row direction, and the memory cell transistors (M
T) 101 are common to each other and function as a word line (WL).

The n-type diffusion layers 107 serving as the source and drain of the memory cell transistor (MT) 101 are shared by adjacent ones, and the memory cell transistor (M
A plurality of (T) 101 (e.g., 8) are connected in series and NA
Configure an ND cell. The drain side of this NAND cell is connected to the bit line BL formed continuously in the column direction via the select transistor (ST0) 108, and the source side is connected to the common source line (SS) via the select transistor (ST1) 108. It is connected.

In addition, select transistors (ST0, ST
1) The gate of 108 is a memory cell transistor (M
T) 101 is formed in the same process as that of the memory cell transistor (MT) 101 and has the same structure as that of the memory cell transistor (MT) 101. The corresponding second-layer gate is electrically connected at a predetermined location (not shown).

The operation of the NAND flash memory will be described below. Data is written by writing the boosted write voltage (= 20) to the control gate 106 of the selected memory cell transistor (MT) 101, that is, the word line WL.
V), and an intermediate potential (about 10 V) to the control gate 106 of the other non-selected memory cell transistor (MT) 101 and the gate of the drain-side selection transistor (ST0) 108. Done in. Further, depending on the data to be written, 0 V is applied to the bit line (BL) 110 when "0" is written, and an intermediate potential is applied when "1" is written. In this way, the potential of the bit line (BL) 110 is transmitted to the selected memory cell transistor (MT) 101. Therefore, when the data is “0”, a high voltage is applied between the floating gate 104 of the selected memory cell transistor (MT) 101 and the p-type semiconductor substrate 102, and electrons are transferred from the p-type semiconductor substrate 102 to the floating gate 104. Are tunnel-injected, and the threshold voltage of the memory cell transistor (MT) 101 shifts in the positive direction. On the other hand, when the data is "1", the threshold voltage does not change.

Next, data is erased by word line (WL).
A set of select transistors (ST0,
ST1) sandwiched by gate lines SL0 and SL1 of 108,
This is performed in block units, which is a set of memory cell groups (pages) to which word lines (WL) are commonly connected. At this time, all the control gates 106 and select transistors (ST0, ST1) 108 in the block to be erased are set to 0V.
And the boosted potential V is boosted on the p-type semiconductor substrate 102.
ppE (= about 20V) is applied. In addition, VppE is applied to the control gate 106 and the gate of the selection transistor 108 in the non-selected block that is not erased.
As a result, the electrons accumulated in the floating gate in the memory cell of the block in which data is erased are released to the p-type semiconductor substrate, and the threshold value of the transistor shifts in the negative direction.

Next, the data is read out by the bit line (B
L) 110 is precharged and then brought into a floating state, and the selected memory cell transistor (MT) 101
Control gate 106 of 0V, control gate 10 other than
6 and the gate of the selection transistor 108 to the power supply voltage Vc
c (for example, 3V), the source line is set to 0V, and the bit line (BL) 110 detects whether or not a current flows through the selected memory cell transistor (MT) 101. That is, the data written in the selected memory cell transistor (MT) 101 is “0” (the threshold Vth of the memory cell transistor (MT) 101>
0), the transistor is turned off, the bit line maintains the precharge potential, and the data is "1" (threshold Vth <0 of the memory cell transistor (MT) 101).
If so, the transistor turns on and bit line (BL) 1
10 is a potential that is lower than the precharge potential by ΔV. Therefore, by detecting the potential of the bit line (BL) 110, the data stored in the selected memory cell transistor (MT) 101 can be read.

Further, in the conventional NAND type flash memory, for example, GJ Hemink et al., "Fast and Accur.
ate Programming Method for Multi-level NAND EEPROM
s ", 1995 Symposium on VLSI Tech., pp.129-130, there has been proposed a multi-value storage technique for storing three or more values of data in one memory cell.

As an example, a memory cell transistor (MT) for storing four-valued information in one memory cell
FIG. 12 shows the relationship between the threshold voltage of 101 and the four-valued data.

As shown in FIG. 12, the state of "0" data is similar to the state after erasing and has, for example, a negative threshold value. In addition, the state of “1” data is, for example, 0.5 to
The state of 1.0V, “2” data is, for example, 1.75 to 2.
The state of 25V, "3" data has a threshold value of 3.0 to 3.5V.

Therefore, the memory cell transistor (M
T) 101 control gate 106 with read voltage VCG2
The data stored in the memory cell transistor (MT) 101 is “0” or “1” depending on whether the memory cell transistor (MT) 101 is turned on or off by applying R (= about 1.2 V). Either or "2" or "3"
Can be detected. Next, read voltage VCG3R (= about 3.0V) and VCG1R
(= 0 V) can be applied to completely detect the data in the memory cell transistor (MT) 101.

After writing the data,
Verify voltage VCG1V (= about 0.5V), VCG
2V (about 1.75V) and VCG3V (= about 3.0V) are applied to the control gate CG to detect the state of the memory cell, and it is confirmed whether or not writing is sufficiently performed.

[0014]

Conventionally, when the distance between the floating gates 104 of the memory cell transistors (MT) 101 becomes small as the miniaturization of the memory cells progresses, the floating gates 104 of the adjacent memory cell transistors (MT) 101 are reduced.
The threshold voltage of the selected memory cell transistor (MT) 101, to which data is to be written, may be affected by the state of the electric charges.

FIG. 13 is a sectional view taken along line BB 'in FIG. FIG. 13A shows a case where data is not stored in the adjacent second memory cell transistor 112.
3 (b) is an adjacent second memory cell transistor 11
This is the case where data is stored in 2.

A predetermined threshold range is set for the first memory cell transistor 111 selected in a state where data is not stored in the adjacent second memory cell transistor 112 as shown in FIG. After the data is written and the verify operation is performed, the adjacent second data in which the data is not stored is shown in FIG. 13B.
When data is written to the memory cell transistor 112, the interference due to capacitive coupling occurs between the floating gates 104 of the first memory cell transistor 111 and the second memory cell transistor 112, and the written data of the first memory cell transistor 111 is generated. 14 shows the threshold range of
As shown in (a), the voltage shifts to the larger side. This results in the threshold of this data resulting in FIG.
As shown in (b), the distribution width expands to a wide threshold range, the margin between adjacent data and the threshold voltage distribution becomes small, and erroneous writing of data occurs. There was a problem of fear.

Further, with the miniaturization of memory cells, it is necessary to lower the impurity concentration of the n-type diffusion layer 107 serving as the source or the drain in order to suppress the short channel effect of the memory cell transistor (MT) 101. If the impurity concentration is low, the resistance of the n-type diffusion layer 107 increases and the cell current decreases. In addition, since electrons pass through the gate insulating film when data is read from, written in, or erased from the memory cell transistor (MT) 101, there is a defect at the interface between the n-type diffusion layer 107 and the gate insulating film 103. As shown in 15, electrons may be trapped in the side wall insulating film 113 formed on the side wall of the gate insulating film 103 or the gate of the memory cell transistor (MT) 101 due to the influence of the tunnel current. When electrons are trapped near the surface of the n-type diffusion layer 107, the surface of the n-type diffusion layer 107 is depleted and the electric resistance is increased as shown in FIG. 16, and the cell current is decreased as shown in FIG. There was a problem that it would end up.

In consideration of the above circumstances, the present invention reduces the influence of interference due to the coupling capacitance between adjacent memory cells to improve the operation margin of the memory cells, and also ensures a sufficient cell current to be nonvolatile. It is an object to realize a semiconductor memory device and a manufacturing method thereof.

[0019]

To achieve the above object, a nonvolatile semiconductor memory device of the present invention comprises a semiconductor substrate,
A floating gate formed on the semiconductor substrate via a gate insulating film, and a control gate stacked on the floating gate via an inter-gate insulating film, and a source and a drain are formed on the semiconductor substrate. A plurality of memory cell transistors and a source-side selection transistor connected in series to the sources of the memory cell transistors, and having a shield electrode between at least the floating gates of the memory cell transistors. is there.

Further, the nonvolatile semiconductor memory device of the present invention includes a semiconductor substrate, a floating gate formed on the semiconductor substrate via a gate insulating film, and a stack on the floating gate via an inter-gate insulating film. And a control gate
A plurality of memory cell transistors each having a source and a drain formed on the semiconductor substrate, a source-side selection transistor serially connected to the source of the memory cell transistor, and insulation between the memory cell transistors so as to cover the memory cell transistor. Embedded through a membrane,
And a conductive layer directly connected to the source region of the source-side selection transistor.

Further, the nonvolatile semiconductor memory device of the present invention includes a semiconductor substrate, a floating gate formed on the semiconductor substrate via a gate insulating film, and a stack on the floating gate via an inter-gate insulating film. And a control gate
A plurality of memory cell transistors having a source and a drain formed on the semiconductor substrate, and the floating gate formed on the source and the drain between the memory cell transistors with a sidewall insulating film between the memory cells and the memory cell. It is characterized by including a single crystal silicon layer having an equivalent film thickness.

Further, according to the method of manufacturing a nonvolatile semiconductor memory device of the present invention, a memory cell transistor in which a floating gate, an inter-gate insulating film and a control gate are laminated on a first conductivity type semiconductor substrate with an insulating film interposed therebetween. And forming a gate of the select transistor, and using the gate as a mask to diffuse impurities of a second conductivity type opposite to the semiconductor substrate into the semiconductor substrate to form a source and a drain of the memory cell transistor and the select transistor. Forming process,
Forming an insulating film on the gate, the source and the drain; removing the insulating film on the source of the select transistor formed on the source side of the memory cell transistor to expose the semiconductor substrate; And a step of forming a conductive layer on the insulating film and the source of the select transistor.

Further, in the method for manufacturing a nonvolatile semiconductor device of the present invention, a memory cell transistor in which a floating gate, an inter-gate insulating film and a control gate are laminated on a first conductivity type semiconductor substrate via a gate insulating film. And forming a source and a drain of a memory cell transistor by diffusing an impurity of a second conductivity type having a conductivity type opposite to that of the semiconductor substrate into the semiconductor substrate by using the gate as a mask. Forming an insulating film on the gate, source and drain of the memory cell transistor, removing the insulating film formed on the source and drain, and forming a sidewall insulating film on the sidewall of the memory cell transistor, Exposing the semiconductor substrate in a region where the source and drain are formed, and the source and drain. It is characterized in that it has a step of forming a monocrystalline silicon layer by selective epitaxial growth method on.

Further, it is desirable that the single crystal silicon layer has a film thickness equivalent to that of the floating gate.

[0025]

BEST MODE FOR CARRYING OUT THE INVENTION A non-volatile semiconductor device according to a first embodiment of the present invention and a method for manufacturing the same will be described below with reference to the drawings. FIG. 1 is a plan view of a NAND flash memory cell array according to a first embodiment of the present invention, FIG. 2A is a sectional view taken along line XX ′ in FIG.
2B is a sectional view taken along the line YY 'in FIG.

As shown in FIGS. 1 and 2, in the NAND type memory cell array according to the first embodiment of the present invention, element regions separated by an element isolation region 15 on a p-type semiconductor substrate 1 are used. Gate insulating film 2 formed on 16
An n-type gate which is formed on the surface of the p-type semiconductor substrate 1 between the gate and a gate composed of a floating gate 5 and a control gate 6 which are stacked via an inter-gate insulating film 4 and serves as a source or a drain. It has a plurality of memory cell transistors 7 having a diffusion layer 6. The control gate 5 is formed continuously in the row direction, is shared by the memory cell transistors 7 adjacent in the row direction, and is connected to the word line (W
L).

Further, a drain-side selection transistor which is formed at the same time as the memory cell transistor 7 and is arranged on the drain side of a NAND cell in which a plurality of memory cell transistors 7 are connected in series sharing the n-type diffusion layer 6 8 and a source-side selection transistor 9 disposed on the source side, and a set of drain-side selection transistor 8 and source-side selection transistor 9 gate line (SL
0, SL1) are arranged in parallel with the word line (WL) with the word line (WL) interposed therebetween. On the memory cell transistor 7 and the source-side selection transistor 9, a conductive layer 11 made of, for example, impurity-doped polysilicon is flatly buried via an insulating film 10. At this time, the insulating film 10 on the source region 12 of the source-side selection transistor 9 is removed, and the source region 12 and the conductive layer 11 are directly connected. A bit line (BL) 14 is formed on the conductive layer 11 via an interlayer insulating film 13. The bit line (BL) 14 is connected to the element region via a bit line contact 17.

Next, a method of manufacturing the NAND flash memory according to the first embodiment of the present invention will be described with reference to FIG. FIG. 3 is a cross-sectional view showing a manufacturing process of the NAND flash memory according to the first embodiment of the present invention.

First, as shown in FIG.
For example, a silicon oxide film 21 is formed on the p-type semiconductor substrate 1, and then a polysilicon film 22 and an ONO film (silicon oxide film / silicon nitride film / silicon oxide film laminated film) 2 are formed.
3 and the polysilicon film 24 are sequentially laminated.

Next, as shown in FIG.
The silicon oxide film 21, the ONO film 23, and the polysilicon films 22 and 24 are selectively etched to form the gate insulating film 2, the floating gate 3, the inter-gate insulating film 4, and the control gate 5, respectively.
The gate 25 is formed. Then this gate 2
Ions are implanted into the p-type semiconductor substrate 1 by using 5 as a mask to form an n-type diffusion layer 6 serving as a source or a drain, and a memory cell transistor 7 is formed. At this time, gates, sources, and drains of the drain-side selection transistor 8 and the source-side selection transistor 9 are also formed in the same process. At this time, in the drain-side selection transistor 8 and the source-side selection transistor 9, the first-layer gate corresponding to the floating gate 3 of the memory cell transistor 7 and the second-layer gate corresponding to the control gate 5 are not shown. Conductive connection at the point.

Next, as shown in FIG.
An insulating film 10 made of a silicon oxide film, a silicon nitride film, or a laminated film of these two is formed so as to cover the gate and the n-type diffusion layer 6 serving as the source and the drain. After that, only the insulating film 10 on the source region 12 of the source-side selection transistor 9 is removed, and the p-type semiconductor substrate 1 at this portion is removed.
Expose.

Next, as shown in FIG.
Conductive layer 1 made of polysilicon with impurities added to the entire surface
After depositing No. 1, a resist (not shown) is patterned so as to cover the memory cell transistor 7 and the source side select transistor 9. After that, using this resist as a mask, the conductive layer 11 formed on the drain side select transistor 8 is selectively removed. At this time, the source region 12 and the conductive layer 11 of the source-side selection transistor 9
And the conductive layer 11 has a source potential Vss.
It is fixed at the same potential as.

Next, as shown in FIG.
After forming the interlayer insulating film 13 on the conductive layer 11 and planarizing the same, the insulating film 10 and the interlayer insulating film 13 on the predetermined n-type diffusion layer 6 are opened, and the metal film is buried to form the bit line contact 17. To do. After that, the bit line (BL) 14 made of a metal film such as Al is formed. This is the end of the manufacturing process of the NAND flash memory according to the first embodiment of the present invention.

By embedding an electrode layer between the gates 25 of the memory cell transistors 7 and fixing the electrode layer at a predetermined potential, the floating gates 3 of the memory cell transistors 7 are shielded to prevent interference due to capacitive coupling between the floating gates 3. Since this can be prevented, the threshold voltage does not shift when writing data, and erroneous writing can be prevented.

Further, the resistance of the common source line (SS) can be reduced by directly connecting the conductive layer 11 and the source region 12 of the source side selection transistor 9 and setting the conductive layer 11 to the source potential Vss. Further, it is possible to reduce the coupling noise by shielding between the bit line (BL) 14 formed in the upper layer of the non-selected block and the word line (WL) which is the control gate 5 of the memory cell transistor 7. Becomes As a result, the operation margin of the memory cell transistor 7 can be improved.

The present invention is not limited to the above-mentioned first embodiment, and the conductive layer 11 may be formed only between the memory cell transistors 7. A sectional view in this case is shown in FIG.

As shown in FIG. 4, the source line (S
S) 31 is formed on the source line contact 32 formed on the source region 12, and when the conductive layer 11 is embedded only between the memory cell transistors 7, the conductivity is reduced. In order to fix the layer 11 to a predetermined reference potential, for example, the plug 33 formed on the conductive layer 11 by the upper source line (SS) 31 and the source line contact 32 are connected. Thereby, the conductive layer 11
Is fixed to the source potential Vss. The conductive layer 11 may be fixed to the reference potential other than the source potential Vss.

The conductive layer 11 is not limited to the impurity-added polysilicon film, but a metal film of Al, Cu, or the like, or
It is also possible to use a polycide film, a tungsten silicide film, or the like. Also in this case, the shield effect between the floating gates 3 of the memory cell transistor 7 can be obtained as in the case of using the impurity-added polysilicon film.

Next, a nonvolatile semiconductor memory device according to a second embodiment of the present invention and a method for manufacturing the same will be described with reference to FIG.
Will be explained. FIG. 5 is a cross-sectional view of a NAND flash memory cell array according to the second embodiment of the present invention.

As shown in FIG. 5, the second aspect of the present invention is
The NAND type memory cell array according to the embodiment of
A gate formed of a floating gate 3 and a control gate 5 formed on a gate insulating film 2 formed on a p-type semiconductor substrate 1 and laminated via an inter-gate insulating film 4, and a p-type semiconductor between the gates. A plurality of memory cell transistors 7 formed on the surface of the substrate 1 and having an n-type diffusion layer 6 serving as a source or a drain, and the memory cell transistors on the n-type diffusion layer 6 of each memory cell transistor 7. 7
A columnar single crystal silicon layer 42 having the same height as that of the floating gate 3 and separated from the gate of the memory cell transistor 7 through a sidewall 41 is formed. An interlayer insulating film 13 is formed on the memory cell transistor 7 and the columnar single crystal silicon layer 42, and a bit line (BL) 14 is formed via the interlayer insulating film 13.

Next, a method of manufacturing a NAND flash memory according to the second embodiment of the present invention will be described with reference to FIG. FIG. 6 is a cross-sectional view showing the manufacturing process of the NAND flash memory according to the second embodiment of the present invention. The steps up to the step of forming the gate of the memory cell transistor 7 and then forming the memory cell transistor 7 by forming the n-type diffusion layer 6 serving as the source and the drain by using this gate as a mask are the same as those in the first embodiment. The description is omitted.

As shown in FIG. 6A, after forming the n-type diffusion layer 6, an insulating film 43 made of a silicon oxide film is formed on the entire surface.

Next, as shown in FIG. 6 (b),
The insulating film 43 formed on the source and drain of the memory cell transistor 7 is removed, leaving the insulating film 43 formed on the side wall of the gate of the memory cell transistor 7, and the p-type semiconductor substrate 1 in this region is removed. Expose. As a result, the sidewall 41 is formed on the sidewall of the gate of the memory cell transistor 7.

Next, as shown in FIG. 6 (c),
The single crystal silicon layer 4 is formed on the source and drain where the p-type semiconductor substrate 1 is exposed by the selective epitaxial growth method.
2 is selectively formed. At this time, the film thickness of the single crystal silicon layer 42 is made equal to the height of the floating gate 3 of the memory cell transistor 7. Further, since the single crystal silicon layer 42 is directly connected to the n-type diffusion layer 6 serving as the source and the drain, it is fixed at the potential given from the source or the drain.

After that, as shown in FIG. 6D, after the interlayer insulating film 13 is formed and planarized on the entire surface including the memory cell transistor 7 and the single crystal silicon layer 42,
A bit line (BL) 14 made of a metal film such as Al is formed. As described above, the NAND according to the second embodiment of the present invention
The manufacturing process of the flash memory is completed.

Similar to the first embodiment of the present invention, by forming a single crystal silicon layer 42 having a film thickness equivalent to that of the floating gate 3 between the memory cell transistors 7 and fixing the single crystal silicon layer 42 at a predetermined potential, The floating gate 3 of the memory cell transistor 7 can be shielded to prevent interference due to capacitive coupling between the floating gates 3, the threshold voltage does not shift when writing data, and erroneous writing is prevented. be able to.

The single crystal silicon layer 42 may be formed only between the memory cell transistors 7, and the source side selection transistor 9 and the drain side selection transistor 8 may be formed.
Need not be formed on the source or drain of the.
Further, the single crystal silicon layer 42 may be fixed not only at the potential given from the source or the drain but also at another reference potential.

The side wall 41 formed on the side wall of the gate of the memory cell transistor 7 is not limited to the second embodiment of the present invention, and the silicon oxide film 51 is formed as shown in FIG. It may be a laminated film of the silicon nitride film 52 and the silicon nitride film 52. At that time, the silicon nitride film 52 may be formed on the control gate 5.

Next, a NAND flash memory according to the third embodiment of the present invention will be described with reference to FIG. FIG. 8 shows N according to the third embodiment of the present invention.
FIG. 6 is an enlarged cross-sectional view of a memory cell transistor portion of an AND flash memory.

NAN according to the third embodiment of the present invention
The configuration of the D-type flash memory is almost the same as the configuration of the NAND-type flash memory according to the second embodiment shown in FIG. 5, and the features different from those of the second embodiment are shown in FIG. Single crystal silicon layer 42
After the formation, the impurity 61 having the same conductivity type as the source and drain and a higher impurity concentration than the source and drain is diffused in the upper portion of the single crystal silicon layer 42.

At this time, the impurity concentration of the impurity diffused above the single crystal silicon layer 42, eg, As, is about 1 × 10 ¹⁷ to 10 ¹⁸ c in the n-type diffusion layer 6 serving as the source and the drain.
It is about 1 × 10 ¹⁹ to 10 ²⁰ cm ^3, which is larger than about m ³ . Further, as a method of diffusing the impurities 61 into the single crystal silicon layer 42, a method of forming the single crystal silicon layer 42 by the selective epitaxial method and then injecting the impurities 61 into the upper portion of the single crystal silicon layer 42 and diffusing the impurities 61, or a selective epitaxial method. There is a method of simultaneously diffusing the impurities 61 while forming the single crystal silicon layer 42 by the method.

By adding an impurity 61 of the same conductivity type as the source and drain to the upper portion of the single crystal silicon layer 42, the floating of each memory cell transistor 7 is achieved as in the first and second embodiments of the present invention. In addition to shielding the gate 3 to prevent interference due to capacitive coupling between the floating gates 3, electrons are trapped near the surface of the n-type diffusion layer 6 because the impurity concentration of the n-type diffusion layer 6 is low. Even when the surface of the n-type diffusion layer 6 is depleted, the upper portion of the single crystal silicon layer 42 has the same function as that of the n-type diffusion layer 6, and when reading, writing or erasing data,
Electrons can be exchanged with the floating gate 3 through the insulating film 62 formed on the gate side wall. Therefore, the upper portion of the single crystal silicon layer 42 functions as a source and a drain, and the single crystal silicon layer 42 and the floating gate 3
Since the insulating film 62 formed on the gate side wall portion between and functions as a gate insulating film, it becomes possible to operate as a memory cell transistor. By this, n
Even when the vicinity of the surface of the type diffusion layer 6 is depleted, it is possible to apply a potential to the floating gate 3 to induce electrons, reduce the resistance, and secure a sufficient cell current. Further, since the lower portion of the single crystal silicon layer 42 has a low impurity concentration, the influence of the short channel effect can be prevented.

The insulating film 62 on the gate side wall portion according to the third embodiment of the present invention has a breakdown voltage required for the gate side wall portion and a gate insulating film to be a tunnel oxide film of the memory cell transistor. Since it is necessary to fulfill both functions, the film thickness is about 2 to 3 times that of the gate insulating film. For example, when the gate insulating film has a thickness of about 7 to 8 nm, the insulating film 62 on the side wall of the gate is about 20 nm. Further, since the insulating film 62 on the gate side wall portion needs to function as a tunnel oxide film, it is desirable that the insulating film 62 be a silicon oxide film made of the same material as the gate insulating film.

Further, the invention according to the first to third embodiments of the present invention is not limited to the case of storing multivalued information of three or more values in the memory cell, but is applied to the case of binary storage. Is also possible. Also in this case, the threshold voltage distribution can be controlled within a desired range.

[0055]

According to the present invention, since the floating gates of the memory cell transistors are filled with a conductive material and fixed at a predetermined potential, the influence of interference due to the coupling capacitance between the memory cells can be reduced. The threshold voltage distribution width can be controlled within a narrow range.

[Brief description of drawings]

FIG. 1 is a plan view of a NAND flash memory cell array according to a first embodiment of the present invention.

2A is a sectional view taken along line XX ′ in FIG. (B) YY 'sectional view taken on the line in FIG.

FIG. 3 is a cross-sectional view showing a manufacturing process of the NAND flash memory according to the first embodiment of the present invention.

FIG. 4 is a cross-sectional view showing a modified example of the NAND flash memory according to the first embodiment of the present invention.

FIG. 5 is a cross-sectional view of a NAND flash memory cell array according to a second embodiment of the present invention.

FIG. 6 is a sectional view showing a manufacturing process of the NAND flash memory according to the second embodiment of the present invention.

FIG. 7 is an enlarged cross-sectional view showing a modified example of the NAND flash memory according to the second embodiment of the present invention.

FIG. 8 is an enlarged cross-sectional view of a memory cell transistor portion of a NAND flash memory according to a third embodiment of the present invention.

FIG. 9 is an equivalent circuit diagram of a NAND flash memory cell array.

FIG. 10 is a plan view of a conventional NAND flash memory cell array.

11 is a cross-sectional view taken along the line AA ′ in FIG.

FIG. 12 is a diagram showing a relationship between threshold voltage of a memory cell transistor (MT) and four-level data when four-level information is stored in one memory cell.

13 is a cross-sectional view taken along the line BB ′ in FIG.

FIG. 14 is a diagram showing changes in the threshold voltage distribution of the memory cell transistor according to FIG.

FIG. 15 is an enlarged cross-sectional view of a conventional memory cell transistor.

FIG. 16 is a cross-sectional view showing depletion of a conventional memory cell transistor.

FIG. 17 is a diagram showing a relationship between a gate voltage of a memory cell transistor and a cell current.

[Explanation of symbols]

1, 102 ... p-type semiconductor substrate, 2, 103 ... Gate insulating film, 3, 104 ... floating gate, 4, 105 ... Insulating film between gates, 5, 106 ... Control gate, 6, 107 ... N-type diffusion layer, 7, 101 ... Memory cell transistor, 8 ... Drain side selection transistor, 9 ... Source side selection transistor, 10, 43 ... Insulating film, 11 ... Conductive layer, 12 ... Source area, 13, 34, 109 ... Interlayer insulating film, 14, 110 ... Bit line (BL), 15 ... Element isolation region, 16 ... Element area, 17 ... Bit line contact, 21, 51 ... Silicon oxide film, 22, 24 ... Polysilicon film, 23 ... ONO film, 25 ... gate, 31 ... Source line (SS), 32 ... Source line contact, 33 ... plug, 41 ... Sidewall, 42 ... Single crystal silicon layer, 52 ... Silicon nitride film, 61 ... impurities, 108 selection transistor, 111 ... First memory cell transistor, 112 ... a second memory cell transistor, 113 ... Side wall insulating film, 114 ... Depletion layer

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Yuji Takeuchi             8th Shinsugita Town, Isogo Ward, Yokohama City, Kanagawa Prefecture             Ceremony company Toshiba Yokohama office (72) Inventor Akira Goda             8th Shinsugita Town, Isogo Ward, Yokohama City, Kanagawa Prefecture             Ceremony company Toshiba Yokohama office F term (reference) 5F083 EP02 EP23 EP55 EP56 EP76                       ER03 ER22 GA13 GA15 JA04                       JA19 JA32 JA35 JA36 JA37                       PR25 ZA21 ZA30                 5F101 BA29 BA36 BB05 BC01 BD02                       BD34 BD47 BE02 BE05 BE07                       BF05 BF08 BH11

Claims (21)

[Claims] 1. A semiconductor substrate, a floating gate formed on the semiconductor substrate via a gate insulating film, and a control gate stacked on the floating gate via an inter-gate insulating film, A memory cell transistor having a source and a drain formed on a semiconductor substrate; and a source-side selection transistor connected in series to the source of the memory cell transistor, wherein a shield electrode is provided between at least the floating gates of the memory cell transistors. A non-volatile semiconductor memory device comprising: 2. A gate comprising a semiconductor substrate, a floating gate formed on the semiconductor substrate via a gate insulating film, and a control gate stacked on the floating gate via an inter-gate insulating film. A plurality of memory cell transistors each having a source and a drain formed on the semiconductor substrate; a source-side selection transistor connected in series to the source of the memory cell transistor; and interlayer insulation on the memory cell transistor and the source-side selection transistor. A non-volatile semiconductor memory device comprising: a bit line formed through a film; and a shield electrode between the gates of the memory cell transistors and on the gate. 3. A semiconductor substrate, a floating gate formed on the semiconductor substrate via a gate insulating film, and a control gate stacked on the floating gate via an inter-gate insulating film, A plurality of memory cell transistors in which a source and a drain are formed on a semiconductor substrate, a source-side selection transistor connected in series to the source of the memory cell transistor, and an insulating film between the memory cell transistors so as to cover the memory cell transistors. And a conductive layer directly connected to the source region of the source side select transistor. 4. A semiconductor substrate, a floating gate formed on the semiconductor substrate via a gate insulating film, and a control gate stacked on the floating gate via an inter-gate insulating film, A plurality of memory cell transistors in which a source and a drain are formed on a semiconductor substrate, a source-side selection transistor connected in series to the source of the memory cell transistor, and an insulating film between the memory cell transistors so as to cover the memory cell transistors. A conductive layer embedded through the conductive layer, an interlayer insulating film formed on the conductive layer and the source side select transistor, and a plug in which a conductive material is embedded by opening the interlayer insulating film on the conductive layer. And a contact in which a conductive material is embedded by opening an interlayer insulating film on the source region of the source side select transistor, The nonvolatile semiconductor memory device being characterized in that; and a wiring layer electrically connecting the plug contact. 5. The non-volatile semiconductor memory device according to claim 3, wherein the conductive layer has the same potential as the source potential. 6. The nonvolatile semiconductor memory device according to claim 3, wherein the conductive layer has the same potential as a reference potential. 7. The nonvolatile layer according to claim 3, wherein the conductive layer is any one of a polysilicon film, a metal film, a polycide film, and a tungsten silicide film to which impurities are added. Semiconductor memory device. 8. A semiconductor substrate, a floating gate formed on the semiconductor substrate via a gate insulating film, and a control gate stacked on the floating gate via an inter-gate insulating film, A plurality of memory cell transistors having a source and a drain formed on a semiconductor substrate; and a single crystal silicon layer formed on the source and the drain between the memory cell transistors with a sidewall insulating film between the memory cells and the memory cells. A non-volatile semiconductor memory device comprising: 9. The single crystal silicon film has the same potential as a source and a drain.
The nonvolatile semiconductor memory device described. 10. The nonvolatile semiconductor memory device according to claim 8, wherein an impurity having the same conductivity type as that of the source and the drain is diffused in an upper portion of the single crystal silicon film. 11. The non-volatile semiconductor storage device according to claim 8, wherein the single crystal silicon film has a film thickness equivalent to that of the floating gate. 12. The sidewall insulating film is a silicon oxide film,
10. The non-volatile semiconductor memory device according to claim 8, which is a laminated film of a silicon oxide film and a silicon nitride film. 13. The NAND type memory cell according to claim 1, wherein the plurality of memory cell transistors share a source or a drain with those adjacent to each other in the channel length direction to form a NAND type memory cell. 8. The nonvolatile semiconductor memory device according to any one of items 1 to 5. 14. A step of forming a gate of a memory cell transistor and a select transistor, in which a floating gate, an inter-gate insulating film, and a control gate are stacked on an insulating film of a first conductivity type semiconductor substrate, and the gate. Forming a source and a drain of a memory cell transistor and a select transistor by diffusing an impurity of a second conductivity type opposite to the semiconductor substrate into the semiconductor substrate using the mask as a mask; Forming an insulating film, removing the insulating film on the source of the select transistor formed on the source side of the memory cell transistor,
A method of manufacturing a non-volatile semiconductor memory device, comprising: exposing the semiconductor substrate; and forming a conductive layer on the insulating film and the source of the select transistor. 15. A step of forming a gate of a memory cell transistor and a select transistor, in which a floating gate, an inter-gate insulating film and a control gate are stacked on an insulating film of a first conductivity type semiconductor substrate, and the gate. Forming a source and a drain of a memory cell transistor and a select transistor by diffusing an impurity of a second conductivity type opposite to that of the semiconductor substrate into the semiconductor substrate using the mask as a mask, and a gate and a source of the memory cell transistor. And selectively forming an insulating film on the drain, forming a conductive layer on the insulating film, and forming an interlayer insulating film on the conductive layer and on the gate, source and drain of the select transistor. A step of forming a plug by opening the interlayer insulating film on the conductive layer, the memory cell transistor A step of forming the interlayer insulating film forming a contact on the source of the selection transistor formed in the source side of, embedding and the said plug contact with a conductive material,
A method of manufacturing a non-volatile semiconductor memory device, further comprising the step of electrically connecting the plug and the contact. 16. The nonvolatile semiconductor memory according to claim 14, wherein the conductive layer is any one of a polysilicon film, a metal film, a polycide film, and a tungsten silicide film to which impurities are added. Device manufacturing method. 17. A step of forming a gate of a memory cell transistor in which a floating gate, an inter-gate insulating film, and a control gate are stacked on a first conductivity type semiconductor substrate via a gate insulating film, and the gate is masked. Forming a source and a drain of the memory cell transistor by diffusing an impurity of a second conductivity type opposite to that of the semiconductor substrate into the semiconductor substrate, and insulating the gate, the source and the drain of the memory cell transistor. A step of forming a film, removing the insulating film formed on the source and drain, forming a sidewall insulating film on a sidewall of the memory cell transistor, and at the same time, forming a sidewall insulating film on a region where the source and drain are formed. Exposing the semiconductor substrate, and forming a single layer on the source and drain by a selective epitaxial growth method. Method of manufacturing a nonvolatile semiconductor memory device characterized by being a step of forming a silicon layer. 18. The method for manufacturing a nonvolatile semiconductor memory device according to claim 17, wherein the single crystal silicon layer has a film thickness equivalent to that of the floating gate. 19. The method according to claim 17, further comprising: after the step of forming the single crystal silicon layer, adding a second conductivity type impurity to the upper portion of the single crystal silicon layer and diffusing the impurity. Item 19. A method for manufacturing a nonvolatile semiconductor memory device according to item 18. 20. The impurity of the second conductivity type is added to the upper portion of the single crystal silicon layer and diffused in the same step as the step of forming the single crystal silicon layer. Non-volatile semiconductor memory device manufacturing method. 21. The sidewall insulating film is a silicon oxide film,
Alternatively, it is formed of a laminated film of a silicon oxide film and a silicon nitride film.
A method for manufacturing the nonvolatile semiconductor memory device described.