JP2724150B2 - Nonvolatile semiconductor memory device - Google Patents

Description

The present invention relates to a non-volatile semiconductor memory device using a rewritable memory cell having a floating gate and a control gate.

(Prior art) MOSFETs with floating gates in the field of non-volatile memory
An electrically rewritable nonvolatile memory device using a memory cell having a structure is known as an E ² PROM. A memory array of this type of E ² PROM is configured by arranging a memory cell at each intersection of a row line and a column line that cross each other. On the actual pattern, the drains of the two memory cells are made common, and the cell line occupied area is made as small as possible by contacting the column lines. However, even in this case, a contact portion with the column line is required for each common drain of the two memory cells, and this contact portion occupies a large area of the cell.

On the other hand, recently, an E ² PROM has been proposed in which a memory cell is connected in series to form a NAND cell and the number of contacts can be significantly reduced. In this NAND cell, the entire surface is erased by batch injection of electrons into the floating gate (batch erase).
Is performed, writing is performed to discharge electrons from the floating gate only to the selected memory cell. At the time of full erasing, the control gate is set to “H” level and the drain is set to “L” level. In the selective writing, writing is performed in order from the cell on the source side to the cell on the drain side. In this case, the potential of the selected cell is such that the drain is at the “H” level and the control gate is at the “L” level, whereby electrons are emitted from the floating gate to the drain. In an unselected cell that is on the drain side of the selected cell, in order to transfer the potential applied to the drain to the selected cell, the potential of the control gate needs to be approximately equal to the potential applied to the drain. . This is because the voltage applied to the drain is transmitted to the source only up to a voltage obtained by subtracting the threshold voltage of the cell from the voltage applied to the control gate.

However, in the conventionally proposed NAND cell, since the floating gate is disposed across the channel region, the threshold voltage of the cell is uniquely determined by the potential of the floating gate. Therefore, when batch erasing is performed, the threshold voltage of the memory cell moves in the positive direction. Therefore, in a non-selected cell on the drain side of the selected cell at the time of selective writing, the control gate voltage is set higher than the drain voltage. It must be set higher by the voltage. When the threshold voltage of the memory cell is determined by the floating gate potential as described above, the threshold voltage of a certain memory cell increases as a result of the variation of the threshold voltage when batch erasing is performed. , The drain voltage may not be sufficiently transferred with the control gate voltage of the non-selected cell. When data is rewritten, batch erase operation is further repeated in a cell in which electrons are injected into the floating gate, and as a result, the threshold voltage of the cell increases, and the drain voltage at the time of selective writing is increased. Cannot be transferred.

(Problems to be Solved by the Invention) As described above, E ² using the conventionally proposed NAND cell
The PROM has a problem that selective writing is not reliably performed as a result of unselected cells preventing transmission of the drain voltage.

An object of the present invention is to provide a nonvolatile semiconductor memory device which solves such a problem.

According to the present invention, a plurality of electrically rewritable memory cells each having a charge storage layer and a control gate stacked on a semiconductor substrate are connected to form a cell unit. In a nonvolatile semiconductor memory device in which a memory array is formed by arranging the cell units in a matrix, the charge storage layer is provided so as to partially cover a channel region in a channel width direction. And

(Operation) In the present invention, the positive threshold voltage of the memory cell is:
It is determined only by the impurity concentration of the channel region where the charge storage layer is not applied. Therefore, when performing selective writing after batch erasure, the drain voltage is transferred only by raising the control gate voltage of the drain-side unselected cell by the threshold voltage higher than the drain voltage. In addition, in this case, the transferred drain voltage is not affected by the potential of the charge storage layer. Writing becomes possible. At the time of data reading, if the control gate voltage of the selected cell is set lower than the threshold voltage determined by the channel region where the charge storage layer of the cell is not applied, "1", “0” can be determined. In addition, the drain voltage can be transferred regardless of the potential of the charge storage layer even in the unselected cell at the time of data reading, as in the case of selective writing.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a plan view showing a NAND cell of an E ² PROM according to one embodiment, and FIGS. 2 (a) and 2 (b) are sectional views taken along lines AA 'and BB'. FIG. 3 is an equivalent circuit of the NAND cell.

In this embodiment, four memory cells M _{1 to} M ₄ and two select MOS transistors S ₁ and S ₂ are connected in series in such a manner that their source and drain diffusion layers are shared, and one NAND cell is formed. Make up. Such NAND cells are arranged in a matrix to form a memory array. Select NAND cell drain
Is connected to a bit line via a MOS transistor S _1. NAN
The source of the D cell is connected to the ground line via a selection MOS transistor S _2. The control gate CG ₁ ~CG ₄ of each memory cell is connected to a word line WL intersecting the bit lines. In this embodiment, one NAND cell is composed of four memory cells, but one NAND cell can be generally composed of 2 n (n = 1, 2,...) Memory cells. .

The memory cell structure in this embodiment is shown by hatching in FIG. 1 and, as is apparent from the sectional view of FIG.
The floating gate 4 (4 ₁ to 4 ₄₎ at one end thereof the element isolation insulating film 2
In this state, the floating gate 4 partially covers the channel region in the channel width direction. As a result, as shown in FIG. 3, the control transistors T _{1 to} T ₄ are connected in parallel to the memory cells M _{1 to} M _{4 in} an equivalent circuit.

Next, an example of the manufacturing process of the NAND cell of this embodiment will be described with reference to FIGS. FIG. 4 corresponds to the cross section of FIG. 2 (a), and FIG. 5 corresponds to the cross section of FIG. 2 (b). However, in FIG. 5, the left part of FIG.
That is, the drain-side selection MOS transistor S ₁ and the memory cell M ₁
Is shown only. First after forming an isolation insulating film 2 on p-type Si substrate 1, to form a first gate insulating film 3 ₁ made of a thermal oxide film of 300～400A. This first gate insulating film
3 a portion to be the channel region of the memory cell of ₁ is selectively removed by hydrofluoric acid solution or reactive Inn on etching, forming a second gate insulating film 3 _{and second} 50~200Å of a thermally oxidized film on the portion I do. Next, a first-layer polycrystalline silicon film 4 of 500 to 4000 Å for forming a floating gate on the entire surface
Is deposited. After forming the third gate insulating film 3 ₃ 80～200A comprising the first layer polycrystalline silicon film 4 thermal oxide film on, 80～200A depositing a silicon nitride film 5 by CVD (FIG. 4 (a ), FIG. 5 (a)). Then the nitride film 5 by reactive ion etching, the third gate insulating film 3 _3, by selectively etching the first layer polycrystalline silicon film 4 is formed a slit which separates the floating gate between adjacent NAND cells. At the same time, the slit is patterned so as to partially cover the element region so that a part of the channel region is exposed (FIGS. 4 (b) and 5 (b)). The first-layer polycrystalline silicon film 4 still at this stage, is between memory cells M ₁ ~M ₄ are not separated. Thereafter, by thermal oxidation to form a fourth gate insulating film 3 ₄ 300~400Å on the channel region (FIG. 4 (c), FIG. 5 (c)). At this time, the surface of the nitride film 5 on the first-layer polycrystalline silicon film 4 is also oxidized at the same time, and an interlayer insulating film having a three-layer structure of an oxide film-nitride film-oxide film with high withstand voltage is formed. Since the oxidation rate on the nitride film 5 is low, the thickness of the insulating film on the first-layer polycrystalline silicon film 4 is not increased more than necessary. This is meaningful in that the capacitance ratio between the gates is set to an optimum value and the write characteristics are not deteriorated. Next, a second polycrystalline silicon film 6 for forming a control gate
It was 1000~4000Å deposition, which forms the control gate ₆₁ through ₄ and the selection gate 6 _5, 6 ₆ cell is patterned by reactive ion etching. At this time by patterning the first layer polycrystalline silicon film same mask to 4 below separating form the floating gate ₄₁ to ₄ at the same time. Thereafter, ion implantation is performed using these gate electrodes as a mask to form an n-type layer 7 serving as a source / drain diffusion layer. The entire surface is covered with a CVD insulating film 8, and a contact hole is formed in the drain region. Ions are again implanted through the contact holes to form the n ⁺ -type layer 9 (FIGS. 4D and 5D). Finally, wiring such as a bit line is formed by vapor deposition and patterning of Al to complete the process.

The operation of the E ² PROM thus configured will now be described with reference to FIGS. 6 and 7. FIG. 6 shows two NAND cell portions along two adjacent bit lines BL ₁ and BL _2, and FIG. 7 shows the potential relationship of the terminals in each operation mode.
In this embodiment, the operation of injecting electrons into the floating gate to move the threshold voltage in the positive direction is "erasing", and the operation of discharging electrons from the floating gate to move the threshold voltage in the negative direction. Is “write”. The erasing operation uses a batch erasing method in which all NAND cells are simultaneously performed.

The batch erasing operation is performed, as shown in FIG.
_1, SG _2, boosted potential Vpp to the control gate CG ₁ ~CG ₄ (e.g., 20
V), and the bit lines BL ₁ and BL ₂ and the source potential Vss are 0 V
And At this time, in all the memory cells, electrons are injected from the substrate to the floating gate, and the threshold voltage moves in the positive direction.

Next, data writing is performed sequentially from the source side of the NAND cell. In FIG. 7, the selected cell A surrounded by the broken line in FIG.
Shows the voltage conditions when writing is performed. That is,
The BL ₁ Vpp = 20V, the _{BL 2 (1/2) Vpp = 10V} , SG 1 and CG _1, CG ₂
The 20V, the SG ₂ and CG _3, CG ₄ and 0V. The drain of the cell A is in this condition, equivalently parallel connected control transistor threshold voltage and the memory cell selection transistors S ₁
Vpp reduced by the threshold voltages of T ₁ and T ₂ is applied.
For example, assuming that the threshold voltage of S ₁ , T _{1 to} T ₄ is 1 V, the voltage 19 V reduced by about 1 V in the selection transistor S ₁ is transmitted with a small voltage drop in the selection transistors T ₁ , T ₂ , About 19 V is applied to the drain of the selected cell A.
This drain voltage does not depend on the amount of electrons previously injected into the floating gate in the batch erase operation. Normally, when batch erase is performed at Vpp = 20 V, the threshold voltages of the memory cells M ₁ , M ₂ ,... Become 1 V or more, and the control transistors T ₁ , T connected in parallel
_2, to become higher than ... it's, Vpp control transistor T
₁ , T ₂ ,... Are transferred. In this way, in the selected cell A to which about 19 V is applied to the drain, electrons are emitted from the floating gate. When writing starts, the cell A is cut off, and is turned on when electrons are emitted from the floating gate. However, the selection transistor S ₂ the time of writing are cut off, no current flows to the source side. During this writing, the intermediate potential to the unselected bit line BL ₂ (1
/ 2) Vpp = 10V is applied. This is because when the already written to the memory cells along the the non-selected bit lines BL ₂ is being performed, among them, the drain side of the memory cell from the control gate CG _3, i.e. the control gates CG _1, CG ₂ This is to prevent erroneous erasure in the controlled memory cell. Select gates SG _1, SG _2, the control gate CG ₁ ~CG ₄ are continuously disposed in a plurality of NAND cells arranged in the lateral direction, write time CG _1, CG of the cell A as described above _Since Vpp is applied to ₂ , if the unselected bit line BL _{2 is set} to 0, C of the memory cells along this unselected bit line BL ₂
Erroneous erasure occurs in cells controlled by G ₁ and CG ₂ . BL ₂
Is set to an intermediate potential, only a weak electric field is applied to the gate insulating films in these cells, and erroneous erasure does not occur. In cell M ₄ already has been written in the NAND cell of the selected bit line BL _1, to the control gate CG ₄ of the selected cell A and 0V, the drain voltage is not transferred, there is no erroneous erasure.

Data is sequentially written from the cell located on the source side of the NAND cell to the drain side for the bit line selected in this manner. At the time of this selective writing, the gate SG ₂ of the source-side selection transistor S ₂ is cut off in order to prevent a large amount of current from flowing through the memory cell due to punch-through and a drop in the boosted voltage Vpp. is there.

As shown in FIG. 7 for the cell A, the selective read operation of the data is performed by the control gates CG ₁ , CG ₂ , CG other than the selected cell A.
₄ and unselected bit line BL ₁ and selection transistor gate SG
_1, the SG ₂ and 5V, to the selected control gate CG ₃ and select the bit lines BL ₁ and 0V. Thus, the current is turned on and off according to the threshold voltage of the selected cell A, and "1" and "0" are detected. The control transistors T _{1 to} T ₄ connected in parallel to the memory cells have their threshold voltages set to 1V. Thus when the selection read by the control gate CG ₃ and 0V, the control transistor T ₃ which is connected in parallel to the selected cell A is cut off, whether or not a current flows only the floating gate potential of memory cells It is determined. Therefore, despite the presence of the control transistor T ₁ through T _4, allowing data read. Also in this case, as in the case of the selective writing, the drain voltage of the selected cell is not affected by the floating gate potential of the non-selected cell, so that reliable data reading can be performed.

As described above, according to this embodiment, one end of the floating gate of the NAND cell does not touch the element isolation region,
Equivalently, a state is created in which the control transistor is connected in parallel to the memory cell. And this control transistor,
By ensuring that the threshold voltage has a lower positive value than that below the erased floating gate, the drain voltage is reliably transferred through the memory cells constituting the NAND cell without causing a voltage drop. The reliability of selective writing and reading is improved.

8 and 9 are plan views showing a NAND cell according to another embodiment of the present invention. In the above embodiments, a thin second gate insulating film is formed over the entire channel region below the floating gate 4 and is used as a rewrite region, that is, a tunnel region. And a tunnel region 2 partially at the drain side end under the floating gate 4.
2,32. In this case, a mask having openings 23 and 33 indicated by broken lines is used to form a connection between the source and drain diffusion layers under the tunnel region before forming the first-layer polysilicon film for the floating gate. Ion implantation is performed. FIG. 8 shows a case where a mask for forming a thin tunnel oxide film and a mask for ion implantation are shared, and FIG. 9 shows a case where these masks are separately formed. In the case of FIG. 8, it is necessary that the mask opening 23 protrudes from each gate end in the channel length direction when the floating gate 4 and the control gate 6 are formed.
According to these embodiments, effects similar to those of the previous embodiments can be obtained.

FIG. 10 is a plan view of a NAND cell according to still another embodiment.
In the above embodiment, one end of the floating gate is prevented from overlapping the element isolation region.
Are arranged so that both ends do not cover the element isolation region. According to this embodiment, the same effect as that of the previous embodiment can be obtained.

The present invention is not limited to the above embodiment. For example, in the above embodiment, erasing was performed by collectively injecting electrons into the floating gate, but erasing is performed by collectively discharging electrons from the floating gate, and electrons are selectively injected into the floating gate. The present invention is also effective when adopting a method of performing data writing by using a method. In this method, the threshold voltage of the non-selected cell is shifted in the negative direction at the time of selective writing, so that there is no problem in the transfer of the drain voltage from the beginning, but the same effect as in the above embodiment can be obtained at the time of data reading. can get.

In addition, the present invention can be variously modified and implemented without departing from the spirit thereof.

[Effect of the Invention] As described above, according to the present invention, a NAND cell is used.
In the E ² PROM, by allowing the floating gate to partially cover the channel region, it is possible to reliably transfer the drain voltage required at the time of selective writing or reading to the selected cell, and to improve the reliability of writing and reading. Performance can be improved.

[Brief description of the drawings]

FIG. 1 is a plan view showing a NAND cell of an E ² PROM according to one embodiment of the present invention, and FIGS.
A ', BB' sectional view, FIG. 3 is an equivalent circuit diagram of the NAND cell, FIGS. 4 (a) to 4 (d) are sectional views corresponding to FIG. 5 (a) to 5 (d) are cross-sectional views corresponding to FIG.
FIG. 6 is a diagram showing the operation of the adjacent 2 for explaining the operation of the E ² PROM.
FIG. 7 is a diagram showing operating conditions, and FIGS. 8 to 10 are plan views showing NAND cells according to another embodiment of the present invention. 1 ...... silicon substrate, 2 ...... isolation insulating film, 3 ₁ ...... gate insulating film, 4 ...... first layer polycrystalline silicon film (floating gate), 5 ...... silicon nitride film, 6 ...... second layer Polycrystalline silicon film (control gate), 7 ... n-type layer (source / drain diffusion layer), 8 ... CVD oxide film, 9 ... n ⁺ type layer, 10 ...
Bit lines, M ₁ ~M ₄ ...... memory cells, T ₁ ~T ₄ ...... control transistors, S _1, S ₂ ...... selection transistor.

 ──────────────────────────────────────────────────続 き Continuing from the front page (72) Inventor Riichiro Shirata 1 Toshiba-cho, Komukai, Saiwai-ku, Kawasaki-shi, Kanagawa Prefecture (72) Inventor Tetsuro Endo 1 Toshiba-cho, Komukai-Toshiba-cho, Saitama-ku, Kawasaki-shi, Kanagawa Address: Toshiba Research Institute, Inc. (72) Inventor: Fujio Masuoka 1 Toshiba, Komukai Toshiba-cho, Saiwai-ku, Kawasaki City, Kanagawa Prefecture

Claims (4)

(57) [Claims] A plurality of electrically rewritable memory cells each having a charge storage layer and a control gate laminated on a semiconductor substrate to form a cell unit; and the cell units are arranged in a matrix to form a memory array. Wherein the charge storage layer is provided so as to partially cover the channel region in the channel width direction. 2. The non-volatile semiconductor memory device according to claim 1, wherein a gate insulating film in a channel region not covered with the charge storage layer is thicker than a gate insulating film below the charge storage layer. 3. The charge storage layer is provided so as to partially cover a channel region of the memory cell in a channel width direction, and the control gate sandwiches both sides of the channel region covered by the charge storage layer. 2. The nonvolatile semiconductor memory device according to claim 1, wherein the nonvolatile semiconductor memory device is provided. 4. The nonvolatile semiconductor memory device according to claim 1, wherein said cell unit comprises a plurality of memory cells connected in series.