JP2786629B2 - Nonvolatile semiconductor memory device - Google Patents

Description

The present invention relates to a non-volatile semiconductor memory device using a rewritable memory cell having a floating gate and a control gate. (Prior Art) In the field of EPROM, an ultraviolet erasing nonvolatile memory device using a memory cell having a MOSFET structure having a floating gate is widely known. The EPROM memory array is configured by arranging memory cells at respective intersections of row lines and column lines that intersect each other. On the actual pattern, the drains of the two memory cells are made common, and the cell line occupied area is made as small as possible by contacting the column lines. However, even in this case, a contact portion with the column line is required for each common drain of the two memory cells, and this contact portion occupies a large area of the cell. On the other hand, an EPROM has recently been proposed in which a plurality of memory cells are connected to form a cell unit, and the number of contact portions with respect to a column line can be significantly reduced. Here, the memory cells connected in series are called NAND cells. However, in this type of conventionally proposed EPROM, the coupling capacitance between the floating gate and the substrate is set to be larger than that between the floating gate and the control gate. Then, the entire surface is erased by injecting electrons from the substrate into the floating gate by irradiating ultraviolet rays, and data writing is performed by discharging electrons of the floating gate to the control gate side in the selected memory cell. However, EPROMs using such NAND cells have a problem in reliability. Normally, the floating gate and control gate are 2
It is formed as a laminated structure of a layer polycrystalline silicon film, and a thermal oxide film of a polycrystalline silicon film is used as an insulating film therebetween. This oxide film is inferior in film quality to that of single crystal silicon. Therefore, when an electric field is applied between the control gate and the floating gate to exchange charges, the characteristics of the memory cell are degraded. (Problems to be Solved by the Invention) As described above, EPs using NAND cells conventionally proposed
ROM is not reliable enough for electrical stress,
There was a problem. An object of the present invention is to provide a nonvolatile semiconductor memory device which solves such a problem. [Structure of the Invention] (Means for Solving the Problems) In the EPROM according to the present invention, a plurality of memory cells each having a floating gate and a control gate are connected to form a cell unit. Configure the array. In the memory cell, writing and erasing are performed by tunneling electrons between the floating gate and the substrate. Further, the present invention uses a cell having such an operation principle.
In the EPROM, the impurity concentration of the source / drain diffusion layers of the memory cells constituting the cell unit is set lower than that of the source / drain diffusion layers of the peripheral circuit. (Operation) According to the present invention, writing and erasing are performed by tunneling between a floating gate and a substrate, which can provide an oxide film having excellent film quality. Therefore, the EPROM has high reliability. In particular, in the present invention, the source and drain diffusion layers of the memory cells constituting the cell unit are made to have a low concentration, so that the surface breakdown withstand voltage when a reverse bias is applied is increased, and the first gate between the diffusion layer and the floating gate is formed. The withstand voltage of the insulating film is also high. Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a plan view showing a NAND cell of an EPROM of one embodiment, and FIGS. 2 (a) and 2 (b) are sectional views taken along lines AA 'and BB'. FIG. 3 is an equivalent circuit of a NAND cell. In this embodiment, four memory cells M ₁ ~M _4, constitute a NAND cell that source, connected in series in the form of sharing the drain diffusion layer. Such NAND cells are arranged in a matrix to form a memory array. The drain of the NAND cell is connected to the bit line BL via a selection MOS transistor. The control gate CG ₁ ~CG ₄ of each memory cell would be connected to the word line WL intersecting the bit lines BL. The specific cell structure will be described with reference to FIG. 2. In the NAND cell, four memory cells are formed in one region surrounded by the element isolation insulating film 2 of the silicon substrate 1 in this embodiment. Each memory cell is formed on a substrate 1 through a first gate insulating film 3 made of a thermal oxide film of 50 to 200 °, and
The floating gate 4 is formed by the first-layer polycrystalline silicon film of 0 °.
(4 ₁ , 4 ₂ ,...) Are formed, and 1000-4000 are formed thereon through a second gate insulating film 5 made of a thermal oxide film of 150-400 °.
The control gate 6 is formed by the second layer polycrystalline silicon film
(6 _1, 6 _2, ...) are formed. The control gates 6 are arranged continuously in one direction to form word lines WL. Four memory cells are connected in series so that adjacent n-type layers 9 serving as source and drain diffusion layers of each memory cell are shared. The drain at one end of the NAND cell is the gate electrode
6 ₅ connected to the bit line 8 via the configured selection MOS transistor, the source of the other end grounding line (not shown)
It is connected to the. Here, the floating gate 4 and the control gate 6 of each memory cell
Are patterned simultaneously using the same etching mask in the channel length direction to align the edges.
The n-type layer 9 serving as a source / drain diffusion layer is formed by ion-implanting, for example, phosphorus with an acceleration voltage of 40 keV and a dose of 7 × 10 ¹⁴ / cm ^{2 using} the control gate 6 and the floating gate 4 as a mask. I have. These n-type layers 9 have an impurity concentration peak concentration of 10 ²⁰ / cm ³ or less. The process of forming the source and drain diffusion layers of these memory cells is performed separately from the process of forming the source and drain diffusion layers of the peripheral circuit, and has a lower concentration than the source and drain diffusion layers of the peripheral circuit. The overlap between the n-type layer 9 thus formed and the floating gate 4 (d in FIG. 2B) is 0.5 μm or less. On the surface of the n-type layer 9 in the contact hole portion connected to the bit line BL, for example, arsenic is ion-implanted from the contact hole to form an n ⁺ -type layer. Conditions for this ion implantation are, for example, an acceleration voltage of 100 keV and a dose of 5 × 10 ¹⁵ / cm ^2.
And The heat treatment for activating the impurities after the ion implantation is performed at 950 ° C. for about 30 minutes in an N ₂ atmosphere. Coupling capacitance between floating gate 4 and substrate 1 in each memory cell
C ₁ is set smaller than the coupling capacitance C ₂ between the floating gate 4 and the control gate 6. This will be described with reference to specific cell parameters.
The floating gate 4 and the control gate 6 both have a width of 1 μm and a channel width of 1 μm according to the m rule, and the floating gate 4 extends on the field region by 1 μm on both sides. First
The gate insulating film is, for example, a 200 ° thermal oxide film, and the second gate insulating film 5 is a 350 ° thermal oxide film. If the dielectric constant of the thermal oxide film is ε, then C ₁ = ε / 0.02 and C ₂ = 3ε / 0.035. That is, C ₁ <C ₂ . FIG. 4 is a waveform diagram for explaining write and erase operations in the NAND cell of this embodiment. First, collectively erased memory cells M ₁ ~M ₄ constituting the NAND cell. In this embodiment for the selection MOS transistor gate electrode SG ₂ and Q, all the control gates CG ₁ to CS ₄ for the memory cell "H" level in the NAND cell (e.g. boosted potential Vpp
= 20V), and the bit line BL is set to “L” level (for example, OV). Hence, an electric field is applied between the control gate and the substrate of the memory cell M ₁ ~M _4, from the substrate, electrons by tunnel effect are injected into the floating gate. As a result, the threshold value of the memory cells M _{1 to} M ₄ moves in the positive direction, and the memory cells M _{1 to} M ₄ enter the “0” state. Thus, batch erasing of the NAND cells is performed. Next, data is written to the NAND cell. Data writing is performed in order from the memory cell M ₄ distant from the bit line BL. As is clear from the following description, this is because the memory cell on the bit line BL side from the selected memory cell is in the erase mode during the write operation. First of all, writing to the memory cell M ₄ is,
As shown in Figure 4, gate SG and control gate CG ₁ ~CG ₄ (the threshold of the erase state of the memory cell) boosted potential Vpp + Vth or more "H" level of the selection transistor Q (for example, 23
V). The control gate CG ₄ of a selected memory cell M ₄ is at "L" level (e.g., 0V). At this time, the bit line BL
Given a "H" level to the through channel of the select transistor Q and the memory cell M ₁ ~M ₃ is transmitted to the drain diffusion layer of the memory cell M _4, high between memory cell M ₄ the control gate and the substrate An electric field is applied. As a result, electrons in the floating gate are emitted to the substrate by the tunnel effect, and the threshold value moves in the negative direction, for example, the state becomes "1" with a threshold value of -2V. Not applied electric field between the time the memory cell M ₁ in ~M ₃ control gate and the substrate, keeping the erased state. In the case of “0” writing, “L” level is applied to the bit line BL. It becomes a memory cell M ₁ ~M ₃ In the erase mode is from the selected memory cell M ₄ this time to the bit line BL side, they no problem because not yet data writing is performed. Next, as shown in FIG.
It goes to the writing of the memory cell M _3. That is, the selection gate SG is “H”
While maintaining the level, lowering the control gate CG ₃ to "L" level. If this time the bit line BL "H" level is given, the memory cell M ₃ "1" write is performed. Hereinafter, similarly, writing is sequentially performed on the memory cells M ₂ and M ₁ . Read operation, for example, explaining the case of reading data of the memory cell M _3, select MOS transistor Q is turned on, the control gate CG ₁ of the non-selected memory cell, CG ₂ and
CG ₄ is given an “H” level potential to turn on the memory cell in the erased state, and the control gate CG of the selected memory cell is given.
_{3 is set} to “L” level (for example, 0 V). Thus, depending on whether current flows, "0" of the memory cell M _3, it is determined "1". In this embodiment, the source and drain diffusion layers of the memory cells constituting the NAND cell are set to have a lower impurity concentration than usual, so that the junction can be performed even when a high reverse bias is applied to the drain diffusion layer during data writing. No breakdown occurs. Also, the breakdown voltage between the floating gate and the drain diffusion layer is high. Therefore, the margin for data writing is increased, and for example, the thickness of the first gate insulating film can be increased to 200 ° or more. Thus the first
When the thickness of the gate insulating film is increased, the electron retention characteristics of the floating gate are improved, and a situation in which data is destroyed due to electric noise, temperature, or the like is reliably prevented. In addition, the source,
In response to the reduction in the impurity concentration of the drain diffusion layer, p
Increasing the impurity concentration of the mold substrate can prevent the influence of the parasitic field transistor. The present invention is not limited to the above embodiment. For example, a composite structure of a silicon nitride film and a silicon oxide film may be used as the first gate insulating film instead of the thermal oxide film. Thereby, the withstand voltage is improved. Low concentration source,
After forming the drain diffusion layer by ion implantation, by performing a heat treatment in an O ₂ atmosphere, the oxide film around the floating gate can be made thicker, whereby the breakdown voltage can be further increased. The selection transistor has a gate structure of 1
Although it is a layer, it may have a two-layer structure similarly to the memory cell. In this case, the select transistor and the memory cell can be formed in the same step, which is advantageous for miniaturization. It is also effective to form a low-resistance material film on the surface of the diffusion layer in order to compensate for an increase in resistance caused by lowering the impurity concentration of the source and drain diffusion layers. As a result, a decrease in current can be prevented, and a sufficiently high operation speed can be secured. In the embodiment, the case where four memory cells are connected in series to form a NAND cell has been described, but the number of memory cells forming the NAND cell is arbitrary. In addition, the present invention can be variously modified and implemented without departing from the spirit thereof. [Effects of the Invention] As described above, according to the present invention, by using a cell in which writing and erasing can be performed using only tunneling between a substrate and a floating gate, junction breakdown of a diffusion layer particularly at the time of writing is performed. EPROM with improved data retention characteristics can be obtained by preventing gate insulating film breakdown.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a plan view showing a NAND cell of an EPROM according to one embodiment of the present invention, and FIGS. 2 (a) and (b) are AA 'and B- of FIG.
FIG. 3 is an equivalent circuit diagram of the NAND cell, and FIG.
The figure is a signal waveform diagram for explaining the operation of the NAND cell. DESCRIPTION OF SYMBOLS 1 ... Silicon substrate, 2 ... Element isolation insulating film, 3 ... First gate insulating film, 4 ... Floating gate, 5 ... Second gate insulating film, 6
... Control gates, 8 bit lines, 9 source / drain diffusion layers, M (M ₁ , M ₂ ,...) Memory cells, Q selection MOS transistors.

Continuation of front page    (72) Inventor Satoshi Inoue               1 Komukai Toshiba-cho, Saiwai-ku, Kawasaki-shi, Kanagawa               Toshiba Research Institute, Inc. (72) Inventor Riichiro Shirada               1 Komukai Toshiba-cho, Saiwai-ku, Kawasaki-shi, Kanagawa               Toshiba Research Institute, Inc. (72) Inventor Masaki Momomi               1 Komukai Toshiba-cho, Saiwai-ku, Kawasaki-shi, Kanagawa               Toshiba Research Institute, Inc. (72) Inventor Yoshihisa Iwata               1 Komukai Toshiba-cho, Saiwai-ku, Kawasaki-shi, Kanagawa               Toshiba Research Institute, Inc. (72) Inventor Norio Ito               1 Komukai Toshiba-cho, Saiwai-ku, Kawasaki-shi, Kanagawa               Toshiba Research Institute, Inc. (72) Inventor Masahiko Chiba               1 Komukai Toshiba-cho, Saiwai-ku, Kawasaki-shi, Kanagawa               Toshiba Research Institute, Inc. (72) Inventor Fujio Masuzoka               1 Komukai Toshiba-cho, Saiwai-ku, Kawasaki-shi, Kanagawa               Toshiba Research Institute, Inc.                (56) References JP-A-60-137068 (JP, A)                 JP-A-61-166154 (JP, A)                 JP-A-61-13668 (JP, A)

Claims (1)

(57) [Claims] A floating gate and a control gate are stacked on a semiconductor substrate, and a cell unit is formed from an arbitrary number of rewritable memory cells for performing writing and erasing by exchanging charges by a tunnel current between the floating gate and the substrate, A plurality of cell units are connected to bit lines to form a memory cell array, and the source and drain diffusion layers of each of the memory cells constituting the cell unit are connected to metal wiring without increasing the impurity diffusion concentration of the diffusion layers. , Peripheral circuit source,
A non-volatile semiconductor memory device characterized by being set lower than that of a drain diffusion layer. 2. 2. The non-volatile semiconductor memory device according to claim 1, wherein the memory cell constituting the cell unit has a coupling capacitance between the floating gate and the substrate set smaller than that between the floating gate and the control gate. 3. 2. The nonvolatile semiconductor memory device according to claim 1, wherein the floating gate and the control gate of each memory cell constituting the cell unit have edges defined by the same etching mask in the channel direction. 4. In the cell unit, a plurality of the memory cells are connected in series such that the source and drain diffusion layers are shared.
2. The nonvolatile semiconductor memory device according to claim 1, wherein the nonvolatile semiconductor memory device is a NAND cell.