JP2637127B2 - Nonvolatile semiconductor memory device - Google Patents

Description

The present invention relates to a non-volatile semiconductor memory device using a rewritable memory cell having a charge storage layer and a control gate.

(Prior Art) In the field of E ² PROM, an ultraviolet erasing nonvolatile memory device using a MOSFET-structured memory cell having a floating gate as a charge storage layer is widely known. The memory array of the E ² PROM is configured by arranging a memory cell at each intersection of a row line and a column line that cross each other. On the actual pattern, the drains of the two memory cells are made common, and the cell line occupied area is made as small as possible by contacting the column lines. However, even in this case, a contact portion with the column line is required for each common drain of the two memory cells, and this contact portion occupies a large area of the cell.

On the other hand, recently, an E ² PROM has been proposed in which memory cells are connected in series to form a NAND cell block as a cell unit, and the number of contacts can be significantly reduced.

An EPROM using such a NAND type cell has a smaller cell occupation area than a conventional general EPROM because a plurality of NAND memory cells need only be provided with one contact portion with a column line. Yes, but there is a problem in reliability.
In other words, if the charge injection into the floating gate is "erased" and the charge release from the floating gate is "written", the cell that has been erased without writing is a memory cell if this is repeated as shown in FIG. Threshold rises. NA
In the case of ND cells, normally, the gate of unselected cells is read.
By applying the Vcc potential to turn on the memory cell and setting the gate of the selected cell to the ground potential, the "1",
Determine “0”. Therefore, when the threshold voltage of the memory cell becomes equal to or higher than the Vcc potential, there is a problem that a non-selected cell does not turn on and causes a malfunction.

(Problems to be Solved by the Invention) It is an object of the present invention to provide a non-volatile memory device which solves the problem of the malfunction at the time of reading as described above.

[Configuration of the invention]

(Means for Solving the Problem) The present invention is characterized in that, in a nonvolatile semiconductor memory device, data is written to a memory cell before the memory cell is erased collectively.

(Operation) In the memory cell of the present invention, before performing the batch erasure, the "threshold" of the memory cell can be made negative in advance by writing all the memory cells within the erase mode period,
The threshold value after performing the batch erase can be adjusted to 2 to 3 V. Therefore, even if a write mode in which electrons are not emitted from the floating gate follows a certain cell, the threshold value does not change.

(Example) Hereinafter, an example of the present invention will be described. FIG. 2 is a plan view showing a NAND type cell block of one embodiment, and FIGS. 3 (a) and 3 (b) are sectional views taken along lines AA 'and BB', respectively.
Four memory cells M ₁ ~M ₄ and one of the select transistors Q in this embodiment to one of the region surrounded by the element isolation insulating film 2 of P-type silicon substrate 1 is formed. Each memory cell has a first gate insulating film 3 made of a thermal oxide film on a substrate 1 and a floating gate 4 (4 ₁ .
4 ₄₎ is constructed and controlled by the second layer crystal silicon film through the second gate insulating film 5 made of thermally oxidized film gate 6 ₍₆₁ through ₄₎ is formed is formed on this. The control gate 6 of the memory cells are each connected to the word line WL ₁ to WL _4. The n ⁺ -type layer 9 serving as the source and drain of each memory cell is shared by adjacent ones, so that the four memory cells M ₁
~M ₄ are connected in series. A selection transistor Q is connected in series to this to form one NAND cell block. These are arranged in an array on the substrate. The gate electrode 6 ₅ of the selection transistor Q is controlled gate ₆₁ through ₄ simultaneously patterned by the second-layer polycrystalline silicon film. The whole is covered with a CVD insulating film 7, and an Al wiring 8 is provided for the cell block so as to contact an n ⁺ -type layer which is a drain of the selection transistor Q. This Al wiring 8 is a bit line. In FIG. 3 (b), the n ⁺ -type region 9 of the memory cell is provided with an n ^-- type layer outside the n ^{+ -type} layer in order to increase the surface breakdown voltage.

In this configuration, the coupling capacitor C ₁ between the floating gate 4 and the substrate 1 in each memory cell is set smaller than the coupling capacitance C ₂ between the floating gate 4 control gate 6.
This will be described with reference to specific cell parameter examples. As shown in FIG. 1, the pattern size is 1 μm in width for both the floating gate and the control gate according to the 1 μm rule, and the channel width is 1 μm. Floating gate 4
Extend on the field region by 1 μm on both sides.
The first gate insulating film 3 is, for example, a thermal oxide film of 200 °,
The second gate insulating film 5 is a 350 ° thermal oxide film. If the dielectric constant of the thermal oxide film is ε, then C ₁ = ε / 0.02 and C ₂ = 3ε / 0.035. That is, C ₁ <C ₂ .

FIG. 1A is an equivalent circuit diagram of a four-stage NAND cell, and FIG. 1B is a timing waveform diagram in a batch erase mode.

When the batch erase mode is entered, writing (emission of electrons from the floating gate) is performed on all memory cells of the block to be erased, and the "threshold" of the memory cells is set to about -3V. In this embodiment, as shown in FIG. 1 (b), writing is performed sequentially from the cell M4, but this may be performed sequentially from the cell M1. At this time, the drain voltage of the NAND cell is high potential (20 V) and the control gate (W
L) is at ground level. After writing to all memory cells, all control gates (WL) are set to high potential (20V)
The cell is erased (injection of electrons into the floating gate) by setting the drain and source to the ground potential, and the "threshold" of the cell is adjusted to 1 to 3 V. This prevents erroneous operation at the time of reading because there is no excessive erasing.

FIG. 4 shows a state of erasing (a) and writing (b) of the memory cell. Before erasing, a voltage of 18V which is lower than the bit line potential Vp (20V) by a threshold value is applied to the drain of the memory cell, and the control gate is set to 0V, thereby setting the threshold value of the memory cell to about -3V. This operation is performed for all the memory cells to be erased, and then electrons are injected by setting the drain of the memory cell to 0 V and the control gate to 20 V as shown in FIG. As a result, the threshold values of the memory cells after the batch erase are aligned around 2V.

Collective writing of M ₁ ~M _4, after finishing the batch-erase mode or consisting erased, then the write operation is sequentially performed from the memory cell closer to the far cell, i.e. source than the contact with the bit line. The substrate potential was always 0V. Sequentially written from the cell of M ₄ and _{M 3, M 2, M 1} . First write to the memory cell M ₄ is, Vp = cross to the drain of the selection transistor Q gives a high potential to a low level gate SG = high potential, the word line _{4WL 1, WL 2, WL 3} . The high potential is 20V. At this time, Vp is transmitted to the drain region of the memory cell M ₄ through the channel of the select transistor Q, the memory cells _{M 1, M 2, M 3} . Memory cell
Since the word lines WL ₄ connected to the gate of M ₄ is a low-potential = OV, this time, the control gate in the memory M ₄ and large electric field between the substrates is applied. As described above, since the coupling capacitance is C ₂ > C ₁ , electrons of the floating gate 4 are emitted to the diffusion layer 9 and the channel portion via the gate insulating film 3 by a tunnel effect. In the memory cells M ₁ , M ₂ , and M ₃ , such a high voltage is applied to the control gate and the substrate, so that such electron emission does not occur. Thus, the threshold voltage of the memory cell M ₄ is negative,
Data writing is performed. Continue to select Vp, SG and WL
_{1. When} WL ₃ is kept at a low potential while WL ₂ is kept at a high potential, data is written in the memory cell M _{3 according} to the same principle. Hereinafter, data writing of M ₂ and M ₁ is performed in the same manner. After the end of the writing of data to the _{M 1 ~M 4, M 1 ~M} 4 the following data writing
, The batch erase mode described above is executed in the same manner. Read operation, SG is "1", and (= 5V), the word lines WL ₁ to WL ₄ are those selected "O" (= OV), and 5V causes forced ON the other. That only WL ₁ is "O" memory cells M ₁ is selected when only the WL ₄ are "O" memory cell M ₄ is selected when the. For example, if WL ₁ is “O” and memory cell M
_{When 1} is selected, WL ₂ = WL ₃ = WL ₄ = “1”, so that the memory cells M _{2 to} M ₄ are on. Memory cells M ₁ is a threshold positive state off, the negative state is on.
Therefore, whether or not a current flows in the cell block depends on the write state. As a result, "1" or "O" is obtained at the Vp terminal.

The writing mode and the erasing mode may be performed for all NAND cell blocks or for selected blocks.

The present invention can be applied not only to the NAND type cell but also variously to a nonvolatile memory which performs a batch erase mode, and can prevent malfunction.

〔The invention's effect〕

As described above, according to the present invention, it is possible to provide a highly reliable nonvolatile memory that does not cause a malfunction during reading.

[Brief description of the drawings]

FIG. 1 is a diagram for explaining a voltage waveform and an equivalent circuit of a memory cell in a batch erase mode of the present invention, FIG. 2 is a plan view of a NAND type cell, and FIG. 3 is AA 'and BB' thereof. Sectional view of the fourth
FIG. 5 is a diagram for explaining the operation, FIG. 5 is a diagram of another embodiment, and FIG. 6 is a diagram showing characteristics of a change in threshold value of a memory cell with respect to the number of erasures of a memory cell in which writing has not been performed. It is. DESCRIPTION OF SYMBOLS 1 ... Silicon substrate, 2 ... Element isolation insulating film, 3 ... First gate insulating film, 4 ... Floating gate, 5 ... Second gate insulating film, 6 ... Control gate, 7 ... CVD insulating film , 8 ...
Output wiring, 9... N ⁺ type layer.

 ──────────────────────────────────────────────────続 き Continuing from the front page (72) Inventor Satoshi Inoue 1 Komukai Toshiba-cho, Saiwai-ku, Kawasaki-shi, Kanagawa Prefecture Toshiba Research Institute, Inc. (72) Inventor Fujio Masuzoka 1 Stock of Komukai Toshiba-cho, Kochi-ku, Kawasaki-shi, Kanagawa (56) References JP-A-1-113997 (JP, A)

Claims (4)

(57) [Claims] In a nonvolatile semiconductor memory device comprising a plurality of memory cells each having a charge storage layer and a control gate stacked on a semiconductor substrate, electrons are stored in the charge storage layer when a block is erased. A non-volatile semiconductor memory device, wherein electrons are emitted from the charge storage layers of all memory cells in advance in a mode in which electrons are injected into the charge storage layers for all the memory cells to be injected. 2. A non-volatile memory device comprising a plurality of rewritable memory cells each having a charge storage layer and a control gate stacked thereon to form a cell unit, and a plurality of the cell units arranged. In the mode period of injecting electrons into the charge storage layers of the memory cells in the cell unit when erasing a block, it is preferable to discharge electrons from the charge storage layers of all the memory cells of the cell unit in advance. The nonvolatile semiconductor memory device according to claim 1, wherein: 3. The method according to claim 1, wherein the injection and emission of electrons into and from the charge storage layer of the memory cell are performed between the charge storage layer and the substrate by a tunnel current.
Item 7. The nonvolatile semiconductor memory device according to Item 1. 4. The non-volatile memory according to claim 2, wherein a plurality of rewritable memory cells each comprising a stack of said charge storage layer and a control gate are connected in series to form a cell unit. Semiconductor memory device.