JPH11330426A - Nonvolatile semiconductor memory device and method for manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To accurately read out a data from memory cells, without the effects of leakage current in memory cells in a state of excessive erase or excessive write. SOLUTION: A source wire selection transistor, connecting a main source wire and sub-source wires 5a to 5d to be conducted in response to a signal voltage of the corresponding word wires 2a to 2h, is formed. The sub-source wires 5a to 5d are provided corresponding to a combination of the word wires 2a to 2h. A read/write operation is conducted with the use of channel hot electron/Fowler-Nordheim current in applying a voltage to the word wires and bit wires to avoid overvoltage transmission from the main source wires to the subsource wires.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device, and more particularly, to a nonvolatile semiconductor memory device in which a memory cell called a flash memory is composed of one floating gate type field effect transistor.
More specifically, the present invention relates to a structure for stably reading data even when a threshold voltage of a memory cell transistor is low.

[0002]

2. Description of the Related Art As a memory for storing information in a nonvolatile manner, a memory generally called a flash memory is known. In this flash memory, a memory cell is composed of one floating gate type field effect transistor. Data is stored by injecting / extracting electrons into / from the floating gate. In the case of an N-channel memory cell transistor, when electrons are injected into the floating gate, the threshold voltage Vth of the floating gate type field effect transistor (memory cell transistor) increases. On the other hand, by extracting electrons from the floating gate, The threshold voltage Vth of the memory cell transistor decreases. The floating gate is electrically separated from other parts by an insulating film, and electrons are continuously held. The level of the threshold voltage Vth based on the charge amount of the floating gate is made to correspond to the binary information “1” and “0”.

In data reading, an intermediate voltage between a high threshold voltage and a low threshold voltage is applied to a control electrode,
Data is read by detecting whether or not a current flows through the memory cell transistor.

In a nonvolatile semiconductor memory device, memory cells are arranged in rows and columns, word lines are arranged corresponding to rows, and bit lines are arranged corresponding to columns.
In the case where the threshold voltage is reduced, the operation is performed in units of a predetermined number of memory cells. When there is a variation in the write / erase characteristics of the memory cell indicating the degree of injection and extraction of electrons into and from the floating gate, the threshold voltage Vth of a certain memory cell decreases. Leakage current increases. Such a state in which the threshold voltage is low and close to 0 V or negative voltage is caused by NOR
In the flash memory, it is called an "over-erased" state. Here, the NOR flash memory refers to a configuration in which memory cells in one column are all connected to a common bit line. On the other hand, in the DINOR type flash memory, such a state where the threshold voltage is excessively low is called an "overwrite (overprogram)" state. here,
In a DINOR type flash memory, a plurality of sub-bit lines are arranged for one column of memory cells, the memory cells are connected to these sub-bit lines, and the sub-bit lines are connected to a main bit line via a selection transistor. You.

When such over-erased or over-written memory cells are present, a problem arises in that memory cell data cannot be accurately read due to the leakage current. Here, in the following description, when the over-erased state in the NOR flash memory and the “overwrite” in the DINOR flash memory are collectively referred to, they are referred to as “over-low Vth” state. In order to prevent the influence of such an over-low Vth memory cell, a configuration has been proposed in which a memory cell current flows only in a memory cell of a maximum of 2 bits in a selected column.

FIG. 78 schematically shows a structure of an array portion of a conventional NOR type flash memory. FIG. 78 shows memory cells MT arranged in four rows and three columns. Each of the memory cells MT is composed of one floating gate type field effect transistor. Word lines WLa, WLb, WL corresponding to each row of memory cells MT
c and WLd are arranged, and bit lines BLa, BLb and BLc are arranged corresponding to each column of memory cells MT. Sub-source line SSLa is provided for a pair of adjacent word lines, ie, memory cells MT connected to word lines WLa and WLb, and word lines WLc and WLd
Are connected to the memory cell MT connected to the sub-source line SSLb. In each row of the memory cells, there are provided source line select transistors SSTa to SSTd which are turned on in response to signal potentials on word lines WLa to WLd of the corresponding row. These source line select transistors SSTa-S
STd connects the main source line MSL to the sub-source line SSLa or SSLb arranged in the corresponding row when conducting. Further, the main source line MSL is connected to the diodes Da and Db.
Are connected to sub-source lines SSLa and SSLb.

At the time of data reading, about 5 V is applied to a selected word line, and about 1 V is applied to a selected bit line as a read voltage.
Is applied, and 0 V is applied to the main source line MSL.
Now, consider a case where data is read from memory cell MT arranged corresponding to the intersection of word line WLa and bit line BLa. In this case, according to the signal voltage on word line WLa, source line select transistor SSTa is turned on, and main source line MSL is electrically connected to sub source line SSLa. The voltage of the unselected word lines WLb to WLd is 0 V, and the source line select transistors SSTb to SSTd maintain the off state. Therefore, sub source line SSLb is in a floating state, and the current path of the memory cell connected to these word lines WLc and WLd is cut off.

Whether a current flows on the bit line BLa is detected by a sense amplifier (not shown). Word line WL
Even if memory cell MT arranged corresponding to the intersection of b and bit line BLa is in an over-low Vth state, its leakage current is slight, and data of the selected memory cell can be read accurately. In other words, at the time of data reading, only the effect of the memory cell having the overlow Vth of 1 bit at the maximum appears on the selected bit line, and the leak current is sufficiently reduced to read the data accurately. Even if the threshold voltage Vth becomes negative and the leak current is large, only a one-bit defect occurs, and this defect can be corrected by an error detection / correction circuit.

Next, a write operation to the memory cell MT arranged corresponding to the intersection of the word line WLa and the bit line BLa will be described. In this write operation, the threshold voltage of memory cell MT is raised. In this case,
About 12V to the word line WLa, about 6V to the bit line BLa,
0 V is applied to the main source line MSL. The source line selection transistor SSTa is turned on, and the sub source line SS
A ground voltage of 0 V is transmitted on La. Thereby, in the selected memory cell MT, thermoelectrons are generated by avalanche breakdown due to the high electric field near the drain,
These thermoelectrons are injected into the floating gate. Unselected bit lines BLb and BLc and unselected word lines WLb to WLd are held at the ground voltage level, and source line select transistors SSTb to SSTd are turned off.

In the erase operation mode, that is, when the memory cell M
To lower the threshold voltage Vth of T, 0 V is applied to the word lines WLa to WLd, about 12 V is applied to the main source line MSL, and the bit lines BLa to BLc are
All are set to the open state (open state). The high voltage of 12 V on the main source line MSL is connected to the diode Da.
And source lines SSLa and SSLb via Db and Db
Conveyed on. As a result, a high electric field is applied between the floating gate and the source in each of the memory cells MT, and electrons are extracted from the floating gate to the source by the Fowler-Nordheim (FN) tunneling phenomenon. In the erase operation mode, word lines WLa to WLd are all held at the ground voltage level, so that source line select transistors SSTa to SSTd
Maintain the off state. Therefore, diode elements Da and Db are required to apply a high voltage to the source of memory cell MT.

[0011]

In the case of a flash memory as shown in FIG. 78, the sub-source line is configured to be shared only by two adjacent word lines. Only the leak current of the memory cell in the over-erased state of at most 1 bit has an effect, and erroneous reading of data by the memory cell in the over-erased state can be prevented. However, in the case of the configuration shown in FIG. 78, the sub source line SSL (SSLa, SSLa,
For each SSLb), a diode D (Da, D
b) needs to be provided. Therefore, the pitch of the word lines is determined by the sizes of the diodes Da and Db, so that the pitch of the word lines cannot be reduced, which causes a problem that high integration becomes difficult.

Japanese Patent Application Laid-Open No. 6-275083 discloses that the word line pitch is reduced by removing the diode.

FIG. 79 schematically shows a structure of a memory array portion shown in the prior art. Fig. 79
In FIG. 78, portions corresponding to those in FIG. 78 are denoted by the same reference numerals, and detailed description thereof is omitted. As shown in FIG. 79, sub source line SSLa is connected to main source line MSL via source line select transistors SSTa and SSTb, and sub source line SSLb is connected to main source line via source line select transistors SSTc and SSTd. Line MSL
Connected to.

In the arrangement shown in FIG. 79, at the time of data reading, the same voltage is applied as in the memory shown in FIG. On the other hand, in the write mode in which the threshold voltage is increased, a voltage as shown in parentheses is applied. Here, FIG. 79 shows voltage application at the time of writing to the memory cells of word line WLa and bit line BLa.

That is, the word line WLa is set to 12 V, and the unselected word lines WLb to WLd are
It is set to V level. A voltage of 0 V or 6 V is transmitted to selected bit line BLa according to write data, and unselected bit lines BLb and BLc are set to an open state (open state). In the main source line MSL,
A voltage of 6V is applied. Therefore, in this state, 6 V is transmitted to sub source line SSLa via source line select transistor SSTa. Voltages 0V and 6V transmitted on selected bit line BLa are set according to "0" and "1" of the write data. When bit line BLa is set to 0V, in memory cell MT arranged corresponding to the intersection of bit line BLa and word line WLa, bit line B is shifted from sub-source line SSLa to bit line B.
A channel current flows through La, and a high electric field is generated in the impurity region (source region) connected to the sub-source line SSLa. The high electric field generates thermal electrons (channel hot electrons) due to avalanche breakdown, thereby causing floating. Electrons are injected into the gate.

On the other hand, when bit line BLa is set to 6 V, the source and drain voltages of memory cell MT are the same, no channel current flows, and no injection of electrons into the floating gate occurs. Therefore, in this state, the erased state is maintained. However, in this arrangement, since the voltage on word line WLa is as high as 12 V, the memory cell transistors connected to bit lines BLb and BLc conduct, and bit line BLb
And BLc, a voltage of 6 V from sub-source line SSLa is transmitted. Therefore, unselected word lines WLb-WL
6 V is transmitted to the impurity region (drain region) connected to the bit line of the memory cell connected to d, a stress conventionally called “drain disturb” is applied, and the bit line voltage of the unselected memory cell causes Due to the extraction of electrons by the Fowler-Nordheim tunneling current or the injection of holes into the floating gate by the inter-band tunneling current, the amount of charge in the floating gate changes and the threshold voltage changes.

In this case, for example, it is conceivable to simultaneously write data to all memory cells in one row. However, at the time of data writing, the current flowing when injecting thermoelectrons generated by the drain avalanche and injecting electrons from the channel region into the floating gate by channel hot electrons is large (for example, several hundred μA to several mA per cell). ,
It is usually difficult to simultaneously write to all memory cells in one row.

In the erase operation mode, as shown in FIG. 80, all word lines WLa to WLd are set to the ground voltage 0V level. Approximately 1 to selected bit line BLa
A voltage of 0 V is applied, while the unselected bit lines BLb and BLc are set to an open state. In this state, the source line selection transistors SSTa to SSTd
Are all turned off, and sub-source lines SSLa and SSLb are set to an open state. In this state, a large voltage is applied between the floating gate and the drain in the memory cell MT connected to the bit line BLa, and a floating field is generated by the Fowler-Nordheim current due to the high electric field between the floating gate and the drain region. Electrons are extracted from the gate. Therefore, in this case, all memory cells MT connected to bit line BLa are erased. In a configuration in which one word line is selected and a plurality of bits are simultaneously written,
Since the cells that should retain data are also erased, this column-wise erasure cannot be applied.

As shown in FIGS. 79 and 80, in a configuration in which the functions are reversed from those of the source and drain regions of the conventional flash memory only at the time of writing and erasing, the selected memory cell is not written at the time of writing. The drain disturb stress is applied not only to the memory cells connected to the same column but also to the memory cells in the non-selected columns, causing a problem that data cannot be stably held.

The above-described problem of over-erasing occurs as overwriting in a DINOR type flash memory as shown in FIG.

FIG. 81 is a diagram schematically showing a configuration of a main part of a conventional DINOR type flash memory. FIG. 81 representatively shows two sub-bit lines SBLa and SBLb connected to one main bit line MBL. A plurality of sub-bit lines SBL are further connected to the main bit line MBL along the column direction. Memory cells MT are arranged corresponding to the intersections between sub-bit lines SBLa and SBLb and word lines WLa and WLb. This memory cell MT is constituted by a floating gate type field effect transistor. The sub-bit lines SBLa and SBLb are
Each is connected to main bit line MBL via sector select gates SGa and SGb. These sector selection gates SGa and SGb provide sector selection signals φSA and φSA.
It conducts in response to the activation of SB.

In this DINOR type flash memory, no memory cell is connected to main bit line MBL, and memory cell MT is connected only to sub-bit lines SBLa and SBLb. Therefore, the load capacity at the time of reading data from the bit line is small, and high-speed data reading can be performed.

In a write operation, the selected word line
A voltage of about 8 V is applied, a voltage of about 6 V is applied to a selected sub-bit line, and a ground voltage of 0 V is applied to a non-selected word line.
Is applied, and the unselected sub-bit line is kept in a floating state. At this time, a voltage of 0 V or 6 V is applied to the selected sub-bit line according to the write data. In the memory cell connected to the sub-bit line to which the voltage of 6 V is applied, electrons are extracted from the floating gate by the Fowler-Nordheim tunneling current, and the threshold voltage of the memory cell decreases.

In the erase mode, a voltage of about 10 V is applied to the selected word line, and a voltage of about -8 V is applied to the back gate and the sub-source line SSL of the memory cell MT. Electrons are injected into the floating gate by using Fowler-Nordheim tunneling current from the entire channel of the memory cell transistor to increase the threshold voltage Vth of the memory cell.

In such a DINOR type flash memory, although the number of memory cells connected to the sub-bit line is smaller than that of the NOR type flash memory, many memory cells exist in the sub-bit line. Therefore, when there is a memory cell in an overwritten state, there arises a problem that accurate data cannot be read due to a leak current.

An object of the present invention is to provide a nonvolatile semiconductor memory device capable of accurately reading data without increasing the array area, and a method of manufacturing the same.

Another object of the present invention is to provide a nonvolatile semiconductor memory device capable of stably and accurately reading data even when the threshold voltage of a memory cell is low, and a method of manufacturing the same. is there.

[0028]

According to a first aspect of the present invention, there is provided a nonvolatile semiconductor memory device arranged in rows and columns, a plurality of memory cells each including a floating type transistor, and a plurality of memory cells each corresponding to each row. A plurality of word lines to which the control electrode nodes of the memory cells in the corresponding row are connected, and a plurality of bit lines which are arranged corresponding to the columns and are respectively connected to the first conduction nodes of the memory cells in the corresponding column. Provided in each row, selectively conducting in response to a signal voltage on a word line of the corresponding row, and a second one of the memory cells of the corresponding row when conducting.
A plurality of select transistors for transmitting a reference voltage to the conductive node and, in an operation mode of injecting electrons into the floating gate of the memory cell, thermal electrons in a channel region between the first and second conductive nodes of the selected memory cell are used as the selected memory. A word line connected to the selected memory cell so that a Fowler-Nordheim tunneling current flows between the floating gate of the selected memory cell and the channel region in an operation mode in which electrons are injected into the floating gate of the cell and electrons are extracted from the floating gate; Means for setting the bit line voltage is provided.

According to a second aspect of the present invention, there is provided a nonvolatile semiconductor memory device arranged in rows and columns, a plurality of memory cells each including a floating gate type transistor, and a plurality of memory cells arranged corresponding to each row. A plurality of word lines connected to the control electrode nodes of the memory cells in the row, a plurality of bit lines arranged corresponding to the columns, each connected to the first conduction node of the memory cell in the corresponding column, and a plurality of bit lines provided in each row A plurality of select transistors selectively conducting in response to a signal voltage on a word line arranged in a corresponding row, and transmitting a reference voltage to a second conduction node of a memory cell in the corresponding row when conducting; In the operation mode in which electrons are injected into the floating gate of the cell, between the channel region between the first and second conduction nodes of the selected memory cell and the corresponding floating gate And Fowler-Nordheim current flows during the extraction of electrons from the floating gate,
Means are provided for setting the voltage of a word line and a bit line connected to the selected memory cell so that a Fowler-Nordheim tunneling current flows between the floating gate and the first conduction node.

In the nonvolatile semiconductor memory device according to the third aspect, the reference voltage of the first or second aspect is maintained at a constant voltage level regardless of the operation mode.

According to a fourth aspect of the present invention, in the nonvolatile semiconductor memory device according to the first or second aspect, the source line selection transistor comprises:
It is composed of a floating gate type field effect transistor.

In a nonvolatile semiconductor memory device according to a fifth aspect, the source line selection transistor according to the fourth aspect has the same writing and erasing characteristics as a memory cell.

In the nonvolatile semiconductor memory device according to the present invention, in the operation mode in which electrons are injected into the floating gate, all of the select transistors arranged in the same row as the selected memory cell have the memory cells in the corresponding row. Means for setting a reference voltage level such that electrons are injected into the floating gate when electrons are injected into the floating gate.

According to a seventh aspect of the present invention, in the nonvolatile semiconductor memory device according to the fourth aspect, in the operation mode for extracting electrons from the floating gate, the source line selection transistor arranged on the same row as the selected memory cell Means for setting the level of the reference voltage so as to extract electrons from the floating gate.

According to an eighth aspect of the present invention, in the nonvolatile semiconductor memory device according to the first or second aspect, each bit line is
Each of the sub bit lines includes a plurality of sub bit lines connected to the first conduction note of the plurality of memory cells, and a main bit line provided in common to the plurality of sub bit lines.

In the nonvolatile semiconductor memory device according to the present invention, the main bit line is connected to a selected one of the plurality of sub bit lines, and the main bit line voltage is compared with a predetermined voltage. Is provided.

According to a ninth aspect of the present invention, there is provided a nonvolatile semiconductor memory device according to the first or second aspect, further comprising a capacitor having substantially the same capacitance value as the bit line to be measured included in the plurality of bit lines. Means, means for charging the capacity means to a predetermined voltage level, means for connecting the capacity means to the bit line to be determined, and means for comparing the voltage of the bit line to be determined with a reference value.

According to a tenth aspect of the nonvolatile semiconductor memory device, the capacitance means of the ninth aspect is a specific bit line included in a plurality of bit lines.

According to an eleventh aspect of the present invention, in the nonvolatile semiconductor memory device according to the first or second aspect, the two bit lines of the plurality of bit lines are further coupled to capacitance means charged to a predetermined voltage level, respectively. And means for determining whether or not the voltages of the two bit lines are at the same level after the coupling with the capacitance means.

According to a twelfth aspect of the present invention, there is provided a nonvolatile semiconductor memory device according to the first or second aspect, wherein each of the plurality of memory cells is provided in common with a predetermined number of rows. A plurality of reference voltage transmission lines for transmitting a reference voltage from a source line selection transistor provided above to a second conduction node of a corresponding predetermined number of rows of memory cells; and a predetermined word line including a selected word line in a data read mode. Means are provided for setting the voltage of the unselected word line in the set of several rows to a voltage level which is smaller in absolute value than the voltage transmitted on the selected bit line and has a polarity different from that of the voltage on the selected word line.

According to a thirteenth aspect of the present invention, in the nonvolatile semiconductor memory device according to the first or second aspect, the nonvolatile semiconductor memory device is further provided for each of the plurality of word lines and separately from each other. A plurality of reference voltage transmission lines for transmitting a reference voltage from a selection transistor in a row to a second conduction node of a memory cell in a corresponding row.

According to a fourteenth aspect, in the nonvolatile semiconductor memory device according to the first or second aspect, the memory cells in each column are divided into a plurality of groups, and the bit lines correspond to the plurality of groups in each column. A plurality of bit lines are provided and each connected to a corresponding group of memory cells. The plurality of groups are grouped so that memory cells in adjacent rows belong to different groups.

According to a fifteenth aspect of the present invention, in the nonvolatile semiconductor memory device according to the first or second aspect, the source line selection transistor is further arranged corresponding to each of a pair of two adjacent rows. The reference voltage from the corresponding adjacent 2
A plurality of reference voltage transmission lines for transmitting to a row of memory cells are provided. A plurality of bit lines are arranged two in each column, and memory cells in a row sharing a reference voltage transmission line in the same column are connected to different bit lines.

According to a sixteenth aspect of the present invention, there is provided the nonvolatile semiconductor memory device according to the first or second aspect, further arranged corresponding to each row, each corresponding to a reference voltage from a source line selection transistor of a corresponding row. And a wiring layer transmitting to the second conduction node of the memory cells in the row. This wiring layer
It is formed above the substrate on which the memory cell is formed.

According to a seventeenth aspect of the present invention, the wiring layer has a sheet resistance of 20 Ω / □ or less.

According to an eighteenth aspect of the present invention, in the nonvolatile semiconductor memory device according to the fourteenth aspect, the bit line arranged corresponding to each of the plurality of groups in the same column is formed in a different wiring layer. It is formed by wiring.

In the nonvolatile semiconductor memory device according to the nineteenth aspect, the two bit lines according to the fifteenth aspect are formed in mutually different wiring layers.

According to a twentieth aspect of the present invention, in the nonvolatile semiconductor memory device according to the fourteenth aspect, the bit lines arranged corresponding to the plurality of groups are formed in different wiring layers. The bit line portions including conductive wirings adjacent to each other in the row direction include wiring portions formed on different wiring layers.

According to a twenty-first aspect of the present invention, in the nonvolatile semiconductor memory device according to the fourteenth or fifteenth aspect, active regions in which memory cells are formed are aligned in two columns along the bit line extending direction. It is arranged to be shifted.

According to a twenty-second aspect of the present invention, in the nonvolatile semiconductor memory device according to the twenty-first aspect, two memory cells adjacent to each other in the bit line extending direction share a contact hole for making a connection to the bit line, The active region in which the memory cells are formed is arranged so as to be shifted by one cell in the word line extending direction for every two memory cells along the bit line extending direction.

According to a twenty-third aspect of the present invention, there is provided a nonvolatile semiconductor memory device according to the first or second aspect, further comprising: a main reference voltage line for transmitting a reference voltage to the source line selection transistor; Sense means for detecting the current of the main reference voltage line and reading data is provided. A method for manufacturing a nonvolatile semiconductor memory device according to claim 24,
A plurality of non-volatile memory cells arranged in rows and columns and each including a control electrode and a floating gate type field effect transistor; and a plurality of non-volatile memory cells arranged corresponding to each row and connected to the memory cells of the corresponding row. A nonvolatile semiconductor memory device comprising: a word line; and a plurality of source line select transistors arranged in each row, which conduct according to the voltage of the word line in the corresponding row, and transmit a reference voltage to the memory cells in the corresponding row when conducting. It is a manufacturing method. The memory cell includes an insulating film having a lower etching rate than the first etchant between the control gate and the floating gate.

According to a twenty-fourth aspect of the present invention, there is provided a method of performing wet etching using a first etchant in a boundary region between a source line selection transistor forming region and a memory cell forming region to remove an insulating film. After the first step, a second step for forming a word line, and after the second step, a region for forming a source line selection transistor is masked, and a region etched in the first step is formed. A third step of etching and removing the insulating film from the region including.

According to a twenty-fifth aspect of the present invention, there is provided a method of manufacturing a nonvolatile semiconductor memory device, comprising a plurality of nonvolatile memory cells arranged in rows and columns, each of which is composed of a floating gate type field effect transistor, and arranged corresponding to each row. A plurality of word lines each connected to a memory cell of a corresponding row;
A plurality of selection transistors arranged corresponding to each row, each conducting in response to a signal voltage of a word line of the corresponding row, and transmitting a reference voltage when conducting, and provided corresponding to each word line, respectively And a plurality of reference voltage transmission lines transmitting a reference voltage from a corresponding source line selection transistor to a memory cell connected to a corresponding word line. Each of the memory cells has a first conduction node and a second conduction node connected to a corresponding reference voltage transmission line. According to this manufacturing method, a first conductive node of a memory cell adjacent in a column direction is masked, and a dopant of a first conductivity type is implanted in a second conductive node formation region to form a second conductive node and a reference voltage transmission line. A second step of selectively implanting a second conductivity type dopant into the second conduction node forming region to offset the first dopant to form an isolation region after the first step. And

According to a twenty-sixth aspect of the present invention, there is provided a method of manufacturing a nonvolatile semiconductor memory device, wherein a plurality of nonvolatile memory cells arranged in rows and columns and each including a floating gate type field effect transistor are arranged corresponding to each row. And a plurality of word lines to which the memory cells of the corresponding row are connected, respectively, and are arranged corresponding to each row, each of which conducts in response to the signal voltage of the word line of the corresponding row, and sets a reference voltage at the time of conduction. A plurality of source line selecting transistors for transmitting, and a plurality of reference voltage transmitting circuits provided corresponding to each of the word lines, each transmitting a reference voltage from the corresponding source line selecting transistor to a memory cell connected to the corresponding word line. And a method of manufacturing a nonvolatile semiconductor memory device including a line. The memory cell has a first conduction node and a second reference node connected to a corresponding reference voltage transmission line.
And a conduction node.

According to a twenty-sixth aspect of the present invention, a method for manufacturing a nonvolatile semiconductor memory device is provided for selectively forming a second conductive node by masking an isolation region between second conductive nodes of memory cells adjacent in a column direction. Performing high-concentration ion implantation to form an impurity region serving as a second conduction node and a reference voltage transmission line of the memory cell.

According to a twenty-seventh aspect of the present invention, in the method of manufacturing a nonvolatile semiconductor memory device, a plurality of nonvolatile memory cells arranged in rows and columns and each including a floating gate type field effect transistor are arranged corresponding to each row. A plurality of word lines each connected to a memory cell in a corresponding row;
A plurality of source line selection transistors arranged in each row, each conducting in response to a signal voltage of a word line in the corresponding row, and transmitting a reference voltage at the time of conduction, and provided corresponding to each word line, each provided A method for manufacturing a nonvolatile semiconductor memory device including a plurality of reference voltage transmission lines transmitting a reference voltage from a corresponding source line selection transistor to a memory cell connected to a corresponding word line. The memory cell has a first conduction node and a second conduction node connected to a corresponding reference voltage transmission line.

According to a twenty-seventh aspect of the present invention, in the method of manufacturing a nonvolatile semiconductor memory device, an isolation insulating film is formed over a second conductive node forming region of a memory cell adjacent in a column direction and a region therebetween, and is patterned into a predetermined shape. Exposing the second conductive node formation region, and performing ion implantation using the isolation insulating film as a mask.
Forming a conduction node and a region serving as a reference voltage transmission line connected to the conduction node. The isolation insulating film is a thermal oxide film.

In the method for manufacturing a nonvolatile semiconductor memory device according to claim 28, the step of selectively forming the thermal oxide film according to claim 27 includes the steps of: Forming a first thermal oxide film over the entire area between the second conductive node region and the reference voltage isolation region by removing the first thermal oxide film by etching except for the second conductive node region and the reference voltage isolation region; Exposing the transmission line forming region.

In the operation mode in which electrons are extracted from the floating gate, electrons are extracted between the floating gate and the channel region of the selected memory cell by a Fowler-Nordheim current, and when the electrons are injected into the floating gate, the first and second electrons are extracted. Since the configuration is such that thermal electrons in the channel region between the conduction nodes are injected into the floating gate, a high voltage is not applied to the unselected bit line, and the drain disturb stress of the memory cell on the unselected bit line is reduced. Can be prevented from being applied unnecessarily.

In addition, electrons are injected into the floating gate by a Fowler-Nordheim current between the channel region and the floating gate, and in a mode of extracting electrons from the floating gate, the Fowler is connected between the floating gate and the second conduction node.・ Since the Nordheim tunnel current flows, unnecessary high voltage is not applied to the memory cell via the unselected bit line, drain disturb stress can be reduced, and data can be stably transferred. Retention can be performed.

Further, the reference voltage transmission line merely transmits the reference voltage by the source line selection transistor, and there is no need to provide an element for applying a high voltage such as a diode. And the word line pitch can be reduced.

[0062]

[First Embodiment] FIG. 1 schematically shows a structure of an array portion of a nonvolatile semiconductor memory device according to a first embodiment of the present invention. In FIG. 1, memory cells MT each formed of an N-channel floating gate type field effect transistor are arranged in rows and columns.
In FIG. 1, memory cells MT arranged in 8 rows and 6 columns
Is shown. The configuration shown in FIG. 1 is provided repeatedly along the row and column directions.

Bit line 1a corresponding to each column of memory cells
To 1f. Each of bit lines 1a to 1f is commonly connected to a drain node as a first conduction node of memory cell MT in a corresponding column. Word lines 2a to 2h are provided corresponding to each row of memory cells MT. Each of the word lines 2a to 2h is connected to a control electrode of a memory cell MT in a corresponding row.

Sub-source lines 5a to 5d as reference voltage transmission lines are provided commonly to two adjacent word lines in the column direction. Each of these sub-source lines 5a to 5d is commonly connected to a second conduction node (source) of a memory cell in a corresponding row. Sub source line 5a is provided commonly to word lines 2a and 2b, and sub source line 5b is
Word line 2c and 2d are provided in common, sub source line 5c is provided in common to word lines 2e and 2f, and sub source line 5d is provided in common to word lines 2g and 2h.

In each row of memory cells MT, furthermore, the source lines are rendered conductive in response to the signal voltages on word lines 2a to 2h of the corresponding row, and connect main source line 3 to corresponding sub source lines 5a to 5d, respectively. Select transistors 4a to 4h are provided. The ground voltage (0 V) is always transmitted to the main source line 3 regardless of the operation mode. Next, write, erase and read operations of the nonvolatile semiconductor memory device shown in FIG. 1 will be described.

(I) Write operation mode The nonvolatile semiconductor memory device shown in FIG.
The drain of the memory cell MT is connected to a to 1f, which is a NOR flash memory. In this case, the write operation mode is an operation mode in which the threshold voltage Vth of memory cell MT is increased, and electrons are injected into the floating gate of memory cell MT. Now, consider a case where writing is performed on a memory cell MT arranged corresponding to the intersection of bit line 1a and word line 2a. In this case, as shown in FIG.
Is applied to the selected bit line 1a.
Is applied with a voltage of 5V. Unselected word lines 2b to 2h
And unselected bit lines 1b to 1f are held at the ground voltage level. In this state, the source line selection transistor 4a connected to the word line 2a is turned on,
The ground voltage (0 V) on main source line 3 is transmitted to corresponding sub source line 5a.

In this state, as shown in FIG. 2A, a channel is formed in the selected memory cell and a channel current flows, and electrons accelerated by the channel current become thermoelectrons and injected into the floating gate. Is done. That is, at the time of the writing operation to the selected memory cell, writing using channel hot electrons is performed. In the unselected memory cell, as shown in FIG. 2B, the corresponding source line selection transistor is off, the sub-source line is open, no channel current flows, and the drain high electric field is not applied. Also, the voltage of the drain node is 0 V and is not generated, and electrons are not injected into the floating gate.

In the unselected memory cell connected to the selected word line 2a, as shown in FIG. 2C, the source and the drain are at the ground voltage (0V), and the control electrode node receives a high voltage of 10V. Only, no channel current flows, and no electrons are injected into the floating gate. In a memory cell connected to an unselected bit line, even if the voltage on the corresponding word line is 10 V or 0 V, the bit line is kept at the voltage level of 0 V, so that the drain disturb stress is applied. ,
Only the memory cells connected to the selected bit line 1a can reduce the number of times the drain disturb stress is applied as compared with the nonvolatile semiconductor memory device having the configuration shown in FIG. 80, and greatly reduce the drain disturb stress. Can be eased.

(Ii) Erase Operation Mode FIG. 3 is a diagram showing a voltage application mode in the erase operation mode. In the erase mode, electrons are extracted from the floating gate of the selected memory cell. For the selected memory cell, as shown in FIG. 3A, the control electrode node is set to a negative voltage level of −17 V, and the corresponding bit line is set to 0 V. The ground voltage (0 V) is transmitted to unselected word lines, and 0 V is also transmitted to unselected bit lines. In this state,
For example, consider the case where memory cell MT arranged corresponding to the intersection of bit line 1a and word line 2a shown in FIG. 1 is selected and erased. In this state, as shown in FIG. 3B, the corresponding source line selection transistor receives a voltage of −17 V at the gate, and this voltage is lower than the voltage (0 V) on main source line 3. The voltage is a voltage, and the off state is maintained, and the sub source line 5a is in an open state. As shown in FIG. 3 (C), the memory cells connected to the remaining unselected word lines also receive a voltage of 0 V on their control electrode nodes and a voltage of 0 V on their bit lines. As shown in FIG. 3D, the source line selection transistor corresponding to the unselected word line is in the off state, and the corresponding sub-source line remains open. In this state, a large electric field is applied between the channel region on the substrate surface and the floating gate, and as shown in FIG. 3E, the Fowler-Nordheim tunneling current flows between the entire channel region and the floating gate. Flows, and the electrons accumulated in the floating gate are extracted to the substrate region. In other unselected memory cells, the control electrode node is at 0 V, and no electrons are extracted. Therefore, erasing is performed on the memory cells connected to the selected word line all at once. All the bit lines are at a voltage level of 0 V, a negative voltage level of -17 V is transmitted to the control electrode of the memory cell of the selected row, and the corresponding sub-source line is open. is there.

(Iii) Data Read Mode FIGS. 4A to 4D are diagrams showing voltages applied to memory cells during data read. As shown in FIG. 4A, a voltage of 3.3 V is applied to a word line connected to the selected memory cell, and a voltage of 1 V is applied to a bit line connected to the selected memory cell. In the selected memory cell, the impurity region (normal node) connected to the bit line is a drain node, and the conduction node connected to the sub-source line is the source. Therefore, the selected memory cell shown in FIG. 4A is turned on or off according to the threshold voltage. The voltage 3.3V on the selected word line is a voltage level between the threshold voltage Vth in the write state and the threshold voltage Vth in the erase state. The selected source line selection transistor receives the voltage of 3.3 V on the selected word line, conducts, and transmits the voltage on main source line 3 to the corresponding sub source line (see FIG. 4B).

On the other hand, in a non-selected cell, FIG.
As shown in FIG. 7, the voltage on the word line and the voltage on the bit line are both 0V. In this case, the corresponding source line selection transistor also receives the word line voltage of 0 V at its gate and is in the off state, as shown in FIG. Therefore, in the unselected cell, the sub-source line is in the open state, and the current path is cut off (this sub-source line portion is simply charged / discharged).

Therefore, when it is determined whether or not the selected cell causes a current to flow through the bit line, a leak current is caused to flow through the bit line similarly to the case where the selected memory cell is connected to the same sub-source line. Memory cell, and each column is a memory cell of at most 1 bit, so that the leak current can be greatly reduced. Therefore, the unselected memory cells arranged in the same column as the selected column and sharing the sub-source line are in the over-erased state, and even if a leak current flows, the leak current of one memory cell is small and almost ignored. And accurate and stable reading of memory cell data can be performed.

A source line selection transistor is provided for each word line, and a voltage of 0 V of the main source line is transmitted to the corresponding sub-source line only when the corresponding word line is selected. Only a high voltage (5 V) for writing is applied to the drains of the memory cells on the same column. Even if the memory cells connected to the remaining unselected bit lines are turned on according to the voltage (10 V) on the selected word line, the voltage on the unselected bit line is 0 V, which is the same as the voltage on the sub-source line. The selected bit line can be prevented from being at a high voltage level, the drain disturb stress can be greatly reduced, and the write operation can be performed stably without destruction of data.

In the read mode, the leak current of the memory cell of a maximum of one bit in the selected column only affects the current of the selected memory cell, and the non-selected one-bit memory cell is in the over-low Vth state (excessive). Even in the erased state, data can be read accurately.

FIG. 5 is a diagram schematically showing an entire configuration of the nonvolatile semiconductor memory device according to the first embodiment of the present invention. In FIG. 5, the nonvolatile semiconductor memory device
Memory cell MT includes memory cell array 10 arranged in a matrix. In FIG. 5, in memory cell array 10, one word line 2, one bit line 1, and corresponding sub-source line 5, a source line select transistor 4 coupled to word line 2, and a ground voltage. A main source line 3 transmitting as a reference voltage is representatively shown.

This nonvolatile semiconductor memory device further comprises:
Row decoder 11 for decoding an address signal (not shown) to drive a word line arranged corresponding to an addressed row of memory cell array 10 to a selected state.
And a column decoder 12 that decodes an address signal (not shown) to generate a column selection signal for selecting an addressed column of the memory cell array 10. The memory cell array 10 is addressed according to a column selection signal from the column decoder 12. A column selection circuit 13 for selecting the selected column. FIG. 5 representatively shows a column selection gate YG connected to bit line 1 in column selection circuit 13.

This nonvolatile semiconductor memory device further comprises:
At the time of data reading, it is detected whether or not a current flows through the bit line selected by the column selection circuit 13 to read data, and at the time of data writing operation, a voltage (corresponding to write data) at the time of data writing operation. 0 V or 5 V), a word line voltage generation circuit 16 that generates a voltage according to the operation mode and supplies it to the row decoder 11, and determines the voltage level of the column selection signal according to the operation mode. Column voltage generating circuit 17 for generating a voltage to apply to column decoder 12 and ground circuit 1 for transmitting a ground voltage to main source line 3
8 inclusive. Word line voltage generation circuit 16 generates a high voltage Vp of, for example, about 10 V in the write mode,
In the erase operation mode, for example, a negative voltage V of about -17 V
n in the read operation mode, for example, 3.3 V
Is generated and applied to the row decoder 11. Column voltage generating circuit 17 generates a voltage higher than the write data in the write mode, and applies the generated voltage to column decoder 12. In the erase and read operation modes, bit line BL of memory cell array 10 is connected to ground voltage or read voltage 1V.
Of the column decoder 1
2 is set to the voltage Vcc level.
Here, in the write mode, the voltage level of the column selection signal from column decoder 12 is raised because of the presence of column selection circuit 13.
In order to prevent the threshold voltage loss of the column selection gate YG included in the above. The ground circuit 18 always supplies the ground voltage to the main source line 3.

By generating a voltage corresponding to the operation mode from word line voltage generation circuit 16 and column voltage generation circuit 17, a voltage required for writing or erasing is transmitted to the selected memory cell.

FIG. 6 shows one of the row decoders 11 shown in FIG.
FIG. 3 is a diagram showing a configuration of a portion for one word line. The row decoder 11 includes a NAND circuit 11a for decoding an address signal (not shown), and an EXOR circuit 11 for receiving an output signal of the NAND circuit 11a and an erase mode instruction signal Er.
b and an inverter circuit 11c having a level conversion function of receiving an output signal of the EXOR circuit 11b. EXOR
Circuit 11b operates using power supply voltage Vcc and ground voltage GND as both operation power supply voltages. Inverter circuit 11c
, One power supply node is supplied with power supply voltage Vcc or high voltage Vp, and the other power supply node is supplied with ground voltage GND or negative voltage Vn. This inverter circuit 11
c has a level conversion function, and converts the voltage level of the output signal of the EXOR circuit 11b according to the operation mode.

When erase mode instructing signal Er is inactive L
When the level is at the level, the EXOR circuit 11b operates as a buffer, and the decode signal from the NAND circuit 11a is transmitted to the inverter circuit 11c. NAND circuit 11
a is at the L level in the selected state, so that the selected word line WL in the write and read modes is
, The voltage Vcc or Vp is transmitted. In the erase mode, the erase mode instructing signal Er attains the H level, the EXOR circuit 11b operates as an inverter, and the negative voltage Vn is transmitted from the inverter circuit 11c to the selected word line WL. Thereby, a voltage corresponding to each operation mode can be transmitted to the selected word line.

As described above, according to the first embodiment of the present invention, in the NOR type flash memory, the source line selection transistor is provided in each row, and the main source line and the sub source line are selectively connected. Electrons are injected into the floating gate using channel hot electrons (CHE) during writing, and electrons are extracted from the floating gate over the entire channel region using Fowler-Nordheim tunneling current during the erasing mode. Therefore, the drain disturb stress can be significantly reduced without applying a high voltage to the memory cells connected to the unselected bit lines. Also, the voltage level of the main source line is always constant,
The configuration of the source line voltage generator can be simplified.

In normal data reading, the leakage current of the memory cell of at most 1 bit in each column only affects the selected memory cell data, and the leakage current value is small, so that the data can be read accurately. Can be performed.

In the above description, a NOR type flash memory is used, but writing is performed using channel hot electrons (CHE), and erasing operation is performed using Fowler-Nordheim current over the entire channel. Then, the same effect can be obtained.

In the erase operation mode, the selected word line is set to the ground voltage (0 V) and the selected bit line is set to 8 V, so that the Fowler-Nordheim using the drain end of the memory cell transistor is set. Erasing can be performed by a tunneling current. In this case, if the voltage of the selected word line is at the level of the ground voltage (0 V), the corresponding source line selection transistor is off, and the sub-source line is open. In this case, the voltage level applied to the selected bit line can be reduced by setting the selected word line WL to a negative voltage.
When the selected word line is set to the ground voltage level, the entire chip is erased collectively (to set all the bit lines to about 8V). This is to prevent a high voltage from being unnecessarily applied to the memory cells connected to the non-selected bit lines, thereby preventing the drain disturb stress from increasing. To make the erase unit smaller than the whole chip,
Like the DINOR type, it is necessary to provide a transistor for dividing the bit line. The number of erase units is determined by the number of bit line divisions.

[Second Embodiment] FIG. 7 shows a structure of a main portion of a nonvolatile semiconductor memory device according to a second embodiment of the present invention. FIG. 7 shows a configuration of an array portion of memory cells MT arranged in 8 rows and 8 columns. This FIG.
In the configuration shown in (1), the bit line is divided into a main bit line 21 arranged corresponding to the memory cell column and a sub-bit line 22 connected to the memory cell MT. In FIG.
Main bit lines 21a, 21b, 21c and 21d provided for memory cells arranged in two columns are shown. For the main bit line 21a, the sub bit line 22aa
To 22ad, and for the main bit line 21b,
Sub bit lines 22ba to 22bd are provided. The main bit line 21c is provided with sub bit lines 22ca to 22cd, and the main bit line 21d is connected to the sub bit line 22d.
a to 22dd are provided. These sub bit lines 22a
a to 22ad are section selection signals φa to φ
The section selection transistor 23 which becomes conductive in response to d.
It is connected to the main bit line 21a via aa to 23ad. The sub-bit lines 22ba to 22bd are connected to the main bit line 21b via section selection transistors 23ba to 23bd which become conductive in response to the section selection signals φa to φd.
Connected to. The sub-bit lines 22ca to 22cd are connected to the main bit line 21c via section selection transistors 23ca to 23cd which become conductive in response to section selection signals φa to φd, respectively. Sub bit line 22d
a to 22dd are section selection signals φa to φa, respectively.
Section selection transistor 2 that conducts in response to φd
It is connected to the main bit line 21d through 3da to 23dd.

In FIG. 7, one main bit line is provided for two columns of memory cells, and a sub bit line is connected to the corresponding main bit line via section selection transistors 23 (23aa to 23dd). And increase the main bit line pitch.

Word lines 2a to 2h are provided corresponding to each row of memory cells MT, and sub source lines 5a to 5d are provided corresponding to each pair of adjacent word lines. Source line select transistors 4a to 4h are provided for word lines 2a to 2h, respectively. These source line select transistors 4a to 4h connect the main source line 3 to the corresponding sub source line 5 (5a to 5d) when conducting.

The arrangement of the memory cells shown in FIG.
This is called a NOR type arrangement. Next, the operation will be described.

(I) Write operation mode: In the DINOR type flash memory, in the write operation mode, electrons are extracted from the floating gate, and the threshold voltage Vth is lowered. In the write operation mode, as shown in FIG. 8A, a negative voltage of -8 V is applied to the word line connected to the selected memory cell, and a positive voltage of 6 V is applied to sub-bit line 22. . The source line select transistor connected to the selected word line
As shown in FIG. 8B, the negative voltage -8 on the selected word line
V, it is turned off, and the ground voltage of the main source line is
It is not transmitted to the corresponding sub source line 5.

On the other hand, in a memory cell connected to an unselected word line, as shown in FIG. 8C, its gate receives ground voltage 0V, and its sub-bit line has 0V.
Is transmitted or set to the open state (the section selection transistor is turned off). As shown in FIG. 8D, the source line selection transistor connected to the unselected word line has a gate having a voltage of 0 V on the unselected word line.
In response to V, the sub-source line 5 is turned off, and the corresponding sub-source line 5 is opened.

In the voltage arrangement shown in FIG.
In the selected memory cell, a large voltage is applied between the control electrode node and the drain node, a Fowler-Nordheim current (FN tunnel current) flows between the floating gate and the drain, and electrons e are extracted from the floating gate. , The threshold voltage Vth of the selected memory cell decreases. In an unselected memory cell, such a current does not flow and its state does not change.

In a non-selected memory cell connected to the selected word line, a negative voltage of -8 V is applied to its control electrode node, and the off state is maintained even in the over-low Vth state. The selected memory cell also receives a negative voltage at its control electrode node,
Since the sources are non-conductive, the voltage on the corresponding sub-bit line 22 is not transmitted to the corresponding sub-source line 5.
Therefore, no high voltage is transmitted to the unselected bit line via the unselected memory cell connected to the selected word line. The drain disturb stress of the unselected memory cell is only applied to the memory cell connected to the same sub-bit line as the selected memory cell,
Since such a drain disturb stress is not applied to other unselected memory cells, the drain disturb stress of the memory cell at the time of writing is greatly reduced.

(Ii) In erase operation mode: DINOR
In the type flash memory, in the erase operation mode, electrons are injected into the floating gate, and the threshold voltage Vth is increased.

As shown in FIG. 9A, a high voltage of 18 V is applied to the selected word line on the selected word line. In this state, as shown in FIG. 9B, the source line selection transistor connected to the selected word line is turned on, and the ground voltage 0 V on main source line 3 is transmitted to corresponding sub source line 5. Is done. A ground voltage is applied to the substrate region of the memory cell. On the other hand, a ground voltage of 0 V is applied to the non-selected word lines.
As shown in FIG. 7, the memory cells connected to the unselected word line maintain the off state, the source line selection transistor connected to the unselected word line also maintains the off state, and the corresponding sub-source line 5 is open.

In the selected memory cell, as shown in FIG. 9A, a channel is formed over the entire channel region by the high voltage 18V applied to the control electrode node (word line 2), and the channel and the floating gate are formed. Between Fowler-Nordheim current (channel F
N tunnel current) flows, electrons e are injected into the floating gate, and its threshold voltage Vth rises.

In FIGS. 9A and 9C, sub bit line 22 may be set to an open state instead of ground voltage 0V. This is because, in the selected memory cell, a channel is formed in the channel region by the high voltage on the selected word line, and it is not particularly necessary to keep this sub-bit line (drain node) at the ground voltage level.

In the erase operation mode, non-selected memory cells connected to the selected word line receive a high voltage of 18 V at their control electrode nodes, and are turned on. However, the corresponding sub-source line is at the voltage level of the ground voltage 0V, and no high voltage is transmitted to the corresponding unselected sub-bit line.

(Iii) Read operation mode: In the read operation mode, a voltage of about 3.3 V is applied to the selected word line as shown in FIG. In this state, main bit line 21 and sub-bit line 22 are connected via corresponding section select transistors, and a read voltage of about 1 V is transmitted to the selected sub-bit line. The source line selection transistor connected to the selected word line is shown in FIG.
As shown at 0 (B), the gate receives a voltage of about 3.3 V and is turned on, transmitting the voltage on the main source line 22 to the corresponding sub source line 5. In this state, whether a current flows through main bit line 21 and sub-bit line 22 is detected by a sense amplifier (not shown), and data is read.

On the other hand, for an unselected memory cell, FIG.
As shown at 0 (C), the ground voltage V is transmitted to the unselected word lines, and 0 V is transmitted to the unselected sub-bit lines 22 (memory cells belonging to the selected section). On the other hand, as shown in FIG. 10D, the source line select transistor connected to the non-selected word line receives the ground voltage 0 V at its gate and is off, and the corresponding sub-source line 5 is open. Maintain state. Therefore, the unselected cell has no path through which a leak current flows even in the overwrite state, and the data in the memory cell is accurately read.

In an unselected section (a sub-bit line in which the corresponding section selection transistor is off), the main bit line and the sub-bit line are separated by the corresponding section selection transistor, and the drain node is It becomes open.

In the configuration of the DINOR type flash memory shown in FIG. 7, a source line selection transistor is provided for each word line, and the ground voltage is applied only to the sub-source line provided corresponding to the selected word line. Communicate,
By using the FN tunnel current in the write operation and using the FN tunnel current in the entire channel in the erase operation mode, there is no state where a high voltage is always applied to the sub-source line, and the high voltage applied to the non-selected memory cells An increase in drain disturb stress due to voltage application can be prevented, and writing, erasing, and data reading of a memory cell can be reliably performed.

Main source line 3 is held at the ground voltage level in any of the write, erase, and read operation modes, and there is no need to switch the voltage level of the main source line. The occupied area can be reduced.

FIG. 11 is a diagram schematically showing an entire configuration of a nonvolatile semiconductor memory device according to the second embodiment of the present invention. In FIG. 11, the nonvolatile semiconductor memory device includes a memory cell array 30 having a plurality of memory cells MT arranged in a matrix. This memory cell array 3
0 is divided into a plurality of sections by the section selection transistor 23. 11, one word line 2, one sub-bit line 22, one main bit line 21 arranged corresponding to sub-bit line 22, source line select transistor 4 and main source Line 3 is representatively shown.

The nonvolatile semiconductor memory device further decodes an address signal (not shown) and decodes an address signal (not shown) and a row / section decoder 31 for selecting a section and a row.
A column decoder 32 for generating a signal for selecting a column of
A column selection circuit 33 for selecting a selected column (main bit line) of the memory cell array 30 according to a column selection signal from a column decoder 32, and at the time of data reading, determining whether or not a current flows through the selected column to read data. Perform sense amplifier 34
And a write circuit 35 for generating write data at the time of writing and transmitting the data to the selected column. Column selection circuit 33 includes a column selection gate YG that is turned on in response to a column selection signal from column decoder 32. A main bit line arranged corresponding to the selected column is connected to sense amplifier 34 and write circuit 35 via column select gate YG.

The nonvolatile semiconductor memory device further generates a voltage of a different voltage level according to the operation mode and supplies it to row / section decoder 31, and a voltage according to the operation mode. Column data generating circuit 37 to be applied to column decoder 32 and a ground circuit 38 for transmitting a ground voltage to main source line 3.

In the write operation mode, selection voltage generating circuit 36 generates a negative voltage to apply to the row decoder included in row / section decoder 31, and generates a high voltage to be included in row / section decoder 31. Give to section decoder. By applying a high voltage to this section decoder during a write operation, a voltage of, for example, 6 V is transmitted onto the selected sub-bit line. In the erase operation mode, select voltage generating circuit 36 transmits a high voltage of about 18 V to a row decoder included in row / section decoder 31. In the read operation mode, selection voltage generation circuit 36 transmits a voltage of a normal power supply voltage level to row / section decoder 31.

In write operation mode, column voltage generation circuit 37 transmits a voltage of 6 V corresponding to write data.
It transmits higher voltages. Thereby, the write circuit 3
The voltage corresponding to the write data generated by 5 is transmitted to the memory cell via the selected main bit line and the selected sub bit line. However, for each main bit line,
When a circuit for latching write data is provided, it is not necessary to provide column voltage generating circuit 37 in particular. Only a power supply voltage or a ground voltage level is transmitted from write circuit 35 to the main bit line and latched by the latch circuit. A high voltage for writing is generated according to the latch data.

The high voltage generation circuit and the negative voltage generation circuit included in selection voltage generation circuit 36 are realized by a usual circuit using, for example, a charge pump circuit.

As can be seen from FIG. 11, the ground voltage is merely transmitted from ground circuit 38 to main source line 3, and it is not necessary to change the voltage of main source line 3 in the operation mode. Therefore, the area occupied by the main source line voltage generation section can be reduced.

In the above description, DINOR
However, during write operation, Fowler-Nordheim tunneling current between the floating gate and the drain region is used, and during erase operation, Fowler-Nordheim tunneling current over the entire channel is used. The same effect can be obtained if the configuration is used.
That is, the same effect can be obtained in a normal NOR type flash memory by a similar voltage application mode.

As described above, according to the second embodiment of the present invention, the sub-source line is grounded corresponding to the set of word lines,
In the configuration of selectively connecting to the main source line that transmits the ground voltage, in the operation of extracting electrons from the floating gate, the Fowler-Nordheim tunneling current between the floating gate and the drain region is used to connect to the floating gate. At the time of electron injection, since the Fowler-Nordheim tunneling current from the entire surface of the channel is used, writing / erasing of the memory cell is always performed without changing the voltage level of the main source line. It can be performed without increasing disturbance stress. Also, at the time of reading, in each column, the leak current of the memory cell of at most 1 bit only affects the read current,
Accurate data reading can be performed, and data can be accurately read even when a low threshold voltage memory cell exists.

[Third Embodiment] FIG. 12 shows a structure of a main portion of a nonvolatile semiconductor memory device according to a third embodiment of the present invention. The nonvolatile semiconductor memory device shown in FIG. 12 differs from the nonvolatile semiconductor memory device shown in FIG. 7 in the following points.

That is, the source line selection transistor 44 provided corresponding to each of the word lines 2a to 2h and connecting the sub source lines 5a to 5d to the main source line 43.
a to 44h are constituted by floating gate type field effect transistors. The source line selection transistors 44a to 44h constituted by these floating gate type field effect transistors are coupled to the memory cell MT by a coupling ratio (capacitance between the floating gate and the substrate and capacitance formed between the floating gate and the word line). Ratio) should be the same. By making the capacitance ratio the same in the memory cell MT and the source line selection transistors 44a to 44h, the writing and erasing characteristics are the same. Therefore, source line select transistor 44 constituted by these floating gate type field effect transistors
a to 44h need not have the same size as the memory cell MT.

The source line select transistors 44a to 44a-4
4h, by using a floating gate type field effect transistor, it is only necessary to form the same floating gate type field effect transistor as the memory cell MT, and a single-layer insulated gate type field effect transistor having a normal one-layer control electrode No separation region is required for forming the semiconductor device, and the array area can be reduced. Since a floating gate type field effect transistor similar to the memory cell MT is used as the source line selection transistor, the voltage transmitted to the main source line 3 also differs depending on the operation mode, and the source line selection transistor also has The write / erase state is set according to the write / erase state of the memory cell in the row. Next, the operation will be described.

(I) Erasing operation mode: At the time of writing data to a memory cell, first, after erasing, data writing to a memory cell storing data different from the erased state is performed. In the erase operation mode, FIG.
As shown in FIG. 3A, a voltage of 18 V is applied to the selected word line. The sub-bit line 22 has a ground voltage of 0 V
Is transmitted via main bit line 21 and section select transistor 23 shown in FIG. In this state, the source line select transistor 44 connected to the selected word line also receives a high voltage of about 18 V at its gate as shown in FIG. The upper ground voltage is transmitted onto corresponding sub-source line 5. Therefore, in the selected memory cell, FIG.
As shown in (A), a channel is formed in a channel region on the substrate surface, and electrons are injected into the floating gate by Fowler-Nordheim tunneling current from the entire surface of the channel.

On the other hand, in the case of unselected word lines, FIG.
As shown in (C), a ground voltage of 0 V is transmitted. In this state, as shown in FIG. 13D, the source line selection transistor connected to the non-selected word line is also off (however, threshold voltage Vth needs to be set to a positive voltage level). The main source line 43 and the sub source line 5 are separated. Therefore, as shown in FIG. 13 (C), the source of the unselected cell is open, and no electrons are injected into the floating gate.

In FIG. 13C, although the ground voltage 0 V is applied to the drain of the non-selected cell,
This indicates a memory cell connected to the same sub-bit line as the selected cell. When an unselected cell is connected to a different sub-bit line than the selected memory cell, the drain node (sub-bit line 22) of this unselected cell is in an open state.

Therefore, in this erase operation mode, when the source line select transistor is connected to the selected word line, the source line select transistor is set to the erase state (the state where the threshold voltage Vth is high). In this erasing, erasing is performed in units of word lines (in units of memory cell rows where sub-source lines are commonly provided).

(Ii) Write operation mode: In the write operation mode, an erase operation is performed to erase a memory cell to which data is to be written, and then to a memory cell to which data different from the erased state is written. , A write operation is performed.

In the write operation mode, a negative voltage of -8 V is applied to the selected word line as shown in FIG. When there is a memory cell to be set to a write state different from the erase state in a write unit, a write voltage of 6 V is applied to the selected memory cell via the main bit line and the section select transistor to the sub-bit line 22.
Is transmitted. When writing is performed on at least one-bit memory cell in this writing unit, main source line 43 is set to a voltage level of 6 V similarly to the writing voltage. In this case, therefore, as shown in FIG. 14B, the source line select transistor connected to the selected word line receives a voltage of -8 V at its gate and a write voltage of 6 V at its drain. Therefore, when data is written to the selected cell, the corresponding source line select transistor is also written at the same time by the Fowler-Nordheim tunneling current. Therefore, when the threshold voltage Vth of the source line select transistor is set to a low state, at least one bit of the memory cell is written on the corresponding word line (or write unit).

On the other hand, in a memory cell connected to an unselected word line, as shown in FIG. 14C, a ground voltage of 0 V is transmitted on the word line, and a corresponding sub bit line 2
2 is supplied with a ground voltage of 0 V or is opened (by a section selection transistor). Therefore, in this state, a voltage of 6 V is transmitted to the unselected source line selection transistor via main source line 43 as shown in FIG. Receiving the ground voltage 0V,
The sub-source line 5 is turned off and the corresponding sub-source line 5 is opened. Therefore, a voltage of 6 V is simply applied between the control electrode node and the source of the unselected source line selection transistor, and the Fowler transistor
No Nordheim current flows and its threshold voltage does not change.

In the write operation mode, the source line select transistor has one conduction node (drain)
Receives write voltage 6V via main source line 43. In order to generate a Fowler-Nordheim tunneling current, it is only required that the floating gate and the drain region overlap, and in particular, it is not required that hot electrons be generated at the drain edge or the source edge. The erase operation is performed by the Fowler-Nordheim current on the entire surface of the channel.
Therefore, this source line select transistor has a symmetrical source / drain structure, and generates a Fowler-Nordheim tunneling current between main source line 43 and its floating gate during writing in the source line select transistor. be able to.

(Iii) Read operation mode: In the read operation mode, a voltage of 3.3 V is applied to the selected word line, and a read voltage of 1 V is transmitted to the selected sub-bit line. In this case, there are two states according to the state of the source line selection transistor 44 connected to the selected word line. That is, as shown in FIG. 15A, when the source line selection transistor 44 is in an erased state and has a high threshold voltage (high Vth state), the source line selection transistor 44 The off state is maintained even when a voltage of 3.3 V is applied thereto. Therefore, in this state, the selected memory cell MT is in the erased state in which the threshold voltage is also high, and no current flows, so that the data is accurately read. The state where the source line selection transistor 44 is in the erased state indicates that all the memory cells connected to the selected word line are in the erased state and are in the high Vth state. Further, by determining whether or not a current flows through the main source line 43, it is possible to determine whether or not the source line selection transistor connected to the selected word line is in the erased state, and the data of one page can be determined. 1
It can be read with a single access. However, this reading method is based on the premise that the threshold voltages Vth of all the source line select transistors are at a positive voltage level and the league current is sufficiently small.

When source line select transistor 44 connected to the selected word line is in a write state and has a low threshold voltage (low Vth state), 3.3 on the selected word line
The source line selection transistor is turned on according to the voltage V (see FIG. 15B). Therefore, in this state, the memory cell of at least one bit on the selected row is in a write state, and the same as in normal data read,
When a read voltage of 1 V is applied to sub-bit line 22, it is possible to read data by determining whether or not a current flows from the sub-bit line through the section selection transistor and the main bit line.

In an unselected memory cell, FIG.
As shown in (C), a ground voltage of 0 is applied to unselected word lines.
V is transmitted, and unselected memory cell MT and unselected source line selection transistor 44 maintain the off state. In this case, sub bit line 22 is set to one of write voltage 1 V, ground voltage 0 V, and open state according to the position of the non-selected memory cell.

Here, it is described that when the source line selection transistor 44 is in the erased state, it is determined whether or not a current flows through the main source line 43. When the source line select transistor 44 is in a write state, a current flows from the main source line 43 to the sub source line when selected. The sub-source line extends over one row, has a relatively large capacitance, and can sufficiently absorb current even when it is in an open state. By this current detection, it is possible to accurately identify whether the selection transistor is in the erased state or the written state.

FIG. 16 is a diagram schematically showing an overall configuration of a nonvolatile semiconductor memory device according to the third embodiment of the present invention. In the nonvolatile semiconductor memory device shown in FIG. 16, unlike the configuration shown in FIG. 11, a floating gate type field effect transistor having the same write / erase characteristics as a memory cell is used as source line select transistor 44. . Therefore, in order to set the voltage of main source line 3, a source line voltage setting circuit 48 for setting the voltage of source line 3 in the write mode according to the write data from write circuit 35 is newly provided. Another configuration is shown in FIG.
Is the same as that shown in FIG.

By applying write data from write circuit 35 to source line voltage setting circuit 48, main source line 3 is set to a predetermined voltage of 0 V or write voltage 6 in the write operation mode.
V can be set.

FIG. 17 is a diagram schematically showing an example of the configuration of source line voltage setting circuit 48 shown in FIG. FIG.
, Source line voltage setting circuit 48 includes a data latch 48a for latching write data corresponding to a low threshold voltage from write circuit 35 shown in FIG.
a multiplexer 48b for selecting one of the latch data of data latch 48a and the ground voltage in accordance with r and transmitting it to main source line 3. Data latch 48a receives voltage Vcc / Vp at one power supply node. Voltage V
cc / Vp is set to write high voltage Vp (6 V) in the write operation mode, and is set to power supply voltage Vcc level in other operation modes. Multiplexer 48
When the write instruction signal Pr is in the active state and the write operation mode is designated, b is written to the selected row transmitting the data on the main source line 3 by selecting the latch data of the data latch 48a. When a memory cell is present, the latch data corresponds to a low threshold voltage state. In other operation modes, multiplexer 48b selects the ground voltage and transmits it to main source line 3.

Thus, at the time of data writing on the selected word line, the data signal voltage on main source line 3 can be set according to the write data.

FIG. 18 is a diagram showing a list of correspondences between memory cells and threshold voltages of corresponding source line selection transistors. Memory cell MT has a low threshold voltage (low Vth) state in a write state and a high threshold voltage (high Vth) state in an erase state. The corresponding source line select transistor is similarly written when the memory cell MT is in the low Vth state, and is in the low Vth state. Therefore, in this case, when a memory cell is selected, the current flowing through the main / sub bit line accurately represents the data of the memory cell. On the other hand, when the memory cell MT is in the high Vth state,
The corresponding source select transistor is in a low Vth state or a high Vth state. However, in either case, no current flows through the main and sub bit lines, so that memory cell data can be read by detecting the current of the main and sub bit lines.

In addition to this, when the selected memory cell is in the high Vth state, the source line selection transistor
By identifying whether or not the memory cell is in the th state, it is possible to determine whether or not all the memory cells in the word line, that is, one row, are in the high Vth state. Therefore, when memory cells of a certain page (one row) are sequentially accessed,
By additionally determining whether or not the source line select transistor is in the high Vth state, it is possible to determine whether or not all the memory cells of the page to be accessed are in the high Vth state, realizing high-speed access. Is done.

FIG. 19 shows another structure of source line voltage setting circuit 48 shown in FIG. The configuration shown in FIG. 19 includes, in addition to the configuration shown in FIG. 17, a high Vth determination signal φhv from sense amplifier 34 (see FIG. 16).
And a current sense circuit 48c for detecting whether or not a current flows through main source line 43. When current does not flow through main source line 43, current sense circuit 48c activates output signal φpah to indicate that all memory cells in the corresponding selected row are in the high Vth state.

In the above description, the current sense circuit 48c included in the source line voltage setting circuit 48 is activated according to the data detected by the sense amplifier 34. However, conversely, in the data read mode, the current sense circuit 48c is first activated to detect whether or not a current flows through the main source line 43 after selecting the word line, and thereafter, the sense amplifier 34c shown in FIG. The operation may be configured to be performed.

[Modification] FIG. 20 shows a structure of a modification of the third embodiment of the present invention. FIG. 20 shows the configuration of the NOR flash memory shown in FIG. In FIG. 20, the same writing / writing as memory cell MT is performed.
Floating gate type field effect transistors having erasing characteristics are used as source line select transistors 54a to 54f. These source line selection transistors 5
4a to 54f are arranged corresponding to word lines 2a to 2f, respectively. Memory cells MT are arranged in three columns, and bit lines 1a, 1b and 1c are arranged in each column. The main source lines 53 may be provided for each of the predetermined number of columns, and it is not necessary to provide one source line 53 for one row of memory cells.

In the configuration of the NOR flash memory shown in FIG. 20, source line select transistor 54a
To 54f have the same write / erase characteristics as the memory cells MT, and, like the DINOR type flash memory shown in FIG. 12, select these source lines according to the storage data of the memory cells in the corresponding row. The threshold voltage of the transistor can be set. Next, the operation will be described.

(I) Erasing operation mode: In the NOR flash memory, as shown in FIG. 21A, at the time of erasing, a negative voltage of -17 V is transmitted to the selected word line. In this state, as shown in FIG.
Source line selection transistor 5 connected to the selected word line
Reference numeral 4 receives a negative voltage of -17 V at its gate, is turned off, and the corresponding sub-source line 5 is opened. In the selected memory cell, a Fowler-Nordheim tunneling current flows between the floating gate and a conduction node (drain) connected to the bit line 1, and electrons are extracted from the floating gate. At this time, similarly, in the source line selection transistor connected to the selected word line, the ground voltage 0 V is transmitted to the main source line 53, and electrons are emitted from the floating gate by the Fowler-Nordheim tunneling current. It is pulled out.

On the other hand, in a memory cell connected to an unselected word line, a voltage of 0 V is transmitted as shown in FIG.
Also, as shown in FIG. 21D, the corresponding sub-source line 5 is turned off (threshold voltage V
th is higher than 0 V). Therefore, no current flows in the memory cells connected to the unselected word lines. Therefore, data in the memory cell is erased in units of the selected word line.

(Ii) Write operation mode: In the write operation mode, as shown in FIG. 22A, a voltage of 10 V is applied to the selected word line 2, and a write operation is performed on a memory cell to be written. In accordance with the write data, a voltage of 5 V is transmitted onto corresponding bit line 1 (when the write data is the same data as the erased state, the bit line is held at the ground voltage level). . In this state, FIG.
, The source line selection transistor 54 is also turned on by the high voltage 10 V on its control electrode node, and transmits the ground voltage 0 V onto the corresponding sub-source line 5.
Thereby, as shown in FIG. 22A, in the selected memory cell, a channel current flows, channel hot electrons are injected into the floating gate, and writing is performed.

On the other hand, for an unselected word line, FIG.
As shown in (C), the ground voltage is transmitted, and the corresponding bit line 1 is also maintained at the ground voltage level. FIG.
As shown in (D), the source line selection transistor 54 connected to the unselected word line is also in the off state, and the corresponding sub source line 5 is disconnected from the main source line 53. Therefore, as shown in FIG. 22C, no channel current flows in the unselected memory cell, and the threshold voltage does not change.

(Iii) Writing of source line selection transistor: When all the memory cells connected to the selected word line are set to the writing state, the corresponding source line selection transistor 54 also has the configuration shown in FIG. Is set to the write state as shown in FIG. In this state, 1
A voltage of 0V is transmitted, and a voltage of 5V is transmitted to main source line 53. The sub source line 5 is set to the ground voltage (0 V) (this configuration will be described below). on the other hand,
In the source line select transistor connected to the unselected word line, as shown in FIG. 23B, the voltage on word line 2 is 0 V, the off state is maintained, and the corresponding sub source line 5 is open. State. Therefore, when all the memory cells connected to the selected word line are set to the written state, the corresponding source line selection transistor 54 also
Similarly, the entire channel FN (Fowler Nordheim)
The writing state is set by the tunneling current. Source line select transistor 54 connected to an unselected word line
Are kept in the erased state.

FIG. 24 shows an example of a structure for setting the source line select transistor to a write state. In the configuration shown in FIG. 24, a floating gate field effect transistor 55 is provided for sub-source line 5, which discharges sub-source line 5 to the ground voltage level in response to the voltage level on main source line 53. This floating gate type field effect transistor 55 is kept in an erased state. As shown in FIG. 24, when all the memory cells MT connected to word line 2 are set to the write state, a voltage of 5 V is applied to each of bit lines 1a to 1m. In this state, a voltage of 5 V is transmitted to main source line 53 as well. Thereby, floating gate type field effect transistor 55 is turned on, and sub-source line 5 is discharged to the ground voltage level. Therefore, memory cell MT and source line select transistor 54 can all be set to the written state.

In the structure shown in FIG. 24, a floating gate type field effect transistor 55 is provided for sub bit line 5. Therefore, all floating gate type field effect transistors 55 connected to main source line 53 are turned on. Therefore, the sub source line 5 provided for the non-selected word line
Are also discharged to the ground voltage level. However, the unselected word lines are at the ground voltage level as shown in FIG. 22, and the unselected memory cells maintain the off state and no channel current flows, so that there is no adverse effect.

In the structure shown in FIG. 24, by providing a floating gate type field effect transistor 55 for discharge, a normal single-layer gate type n channel
There is no need to provide a special area exclusively as compared with the configuration using the S transistor. However, floating gate type field effect transistor 55 may be replaced with a normal n channel MOS transistor.

(Iv) Read operation mode: In the read operation mode, ground voltage 0 V is transmitted on main source line 53. A voltage of, for example, about 3.3 V is transmitted on the selected word line. As shown in FIG. 25A, the source line selection transistor 54 connected to the selected word line
When in the erased state and in the low threshold voltage state, this source line select transistor 54 is turned on. Therefore, the data stored in memory cell MT can be read by detecting the presence / absence of a current in bit line 1.

On the other hand, as shown in FIG. 25B, the source line selection transistor 54 connected to the selected word line
When in a write state and at a high threshold voltage (high Vth) state, source line select transistor 54 maintains an off state. Therefore, no current flows through bit line 1. However, the source line selection transistor 54
Are set to the write state, all memory cells MT connected to the selected word line 2 are set to the write state. Therefore, by detecting that no current flows through bit line 1, it is possible to accurately determine that selected memory cell MT is in the written state. in this case,
Further, by determining whether or not the current flows also through the main source line 53, it is possible to determine whether or not all the memory cells of the selected word line are in the written state.

In the case of a non-selected word line, FIG.
As shown in FIG. 5, since the voltage of 0 V is transmitted, both the memory cell MT and the source line selection transistor 54 are turned off, and the sub source line 5 is not connected except when the paired word line is the selected word line. , Is set to the open state. Therefore, these unselected memory cells MT do not supply any current to bit line 1, and do not adversely affect the read operation.

In the structure shown in FIG. 24, FIG.
And using the structure shown in FIG. 19, when all the memory cells connected to the selected word line are in the write state, the corresponding source line select transistor is set to the write state, and in the read operation mode, , This main source line 5
By detecting whether or not a current flows through the memory cell 3, it is possible to determine that all the memory cells in one row are in the written state.

FIG. 26 schematically shows a whole structure of a nonvolatile semiconductor memory device according to a modification of the third embodiment of the present invention. The nonvolatile semiconductor memory device shown in FIG. 26 differs from the configuration of the nonvolatile semiconductor memory device shown in FIG. 16 in the following points. That is, since the memory cell array 30 is a NOR flash memory, the memory cell MT is connected to the bit line 1 and the source line selection transistor 54 and the source line selection transistor are programmed with respect to the sub-source line 5. Floating gate type field effect transistor 55 is provided.

Row decoder 57 is connected to selection voltage generation circuit 5
6 transmits the voltage generated according to the operation mode to the selected word line. In the write operation mode, when all the memory cells connected to the selected word line indicate the write state, source line voltage setting circuit 58 sets the voltage transmitted on main source line 53 to the write voltage level. Set. The other configuration is the same as the configuration shown in FIG. 16, and corresponding portions are denoted by the same reference numerals and detailed description thereof will not be repeated.

FIG. 27 is a diagram schematically showing an example of the configuration of source line voltage setting circuit 58 shown in FIG. FIG.
, Source line voltage setting circuit 58 includes a data latch 58a for storing all the write data indicating that the memory cell is set to a write state, and a data latch 58a in accordance with write operation mode instruction signal Pr. 58a to select one of the latch data and the ground voltage to
3 includes a multiplexer 58b that communicates on.

Data latch 58a includes inverter circuits 58aa and 58ab forming a latch circuit, and an n-channel MOS transistor 58ac for setting an output node of inverter 58ab and an input node of inverter 58aa to the ground voltage level in accordance with initialization signal φre.
And write data from write circuit 35 shown in FIG.
Signal φlv indicating that data is set to an erased state
, And sets an output node of inverter 58aa and an input node of inverter 58ab to the ground voltage level.

In the structure of data latch 58a shown in FIG. 27, in the data write mode, initialization signal φre is activated, and the input node of inverter 58aa is set to the ground voltage level. Therefore, at the time of initial setting, the output signal of inverter 58aa is at H level. This H-level signal is supplied to the inverter 58ab.
Is fed back to the input section of the inverter 58aa and latched. When the write circuit 35 receives data for setting the memory cell to the erased state among the write data, it activates signal φlv to make MOS transistor 58ad conductive, and sets the output node of inverter 58aa to the ground voltage. Set to level. Therefore, when all the memory cells connected to the selected word line are set to the write state, signal φlv maintains the inactive state, and data latch 58a sets the initially set H level data. Latch. Thereby, in the mode in which the data of the memory cell is actually written, the write voltage (5 V) is applied to the main source line 53 via the multiplexer 58b.
, And both memory cell MT and source line select transistor 54 are set to the written state.

In the above description, memory cell MT and source line select transistor 54 are simultaneously set to the write state. However, the memory cell M
After the write operation of T is completed, the setting of the write state of source line select transistor 54 may be performed.

As described above, according to the third embodiment of the present invention, a floating gate type field effect transistor having the same write / erase characteristics as a memory cell is used as a source line select transistor. An isolation region for forming a normal MOS transistor is not required as a line selection transistor, and the area occupied by the array can be reduced.

When all the memory cells on the selected word line are in the high threshold voltage state, the corresponding floating gate type field effect transistor for source line selection is also set to the high threshold voltage state. By reading the storage information of the source line selection transistor via the main source line, it can be easily determined whether or not all the memory cells connected to the selected word line are in the high threshold voltage state. , All data of the selected word line can be read by one access without accessing all the memory cells of the selected word line.

[Fourth Embodiment] FIG. 28 schematically shows a structure of a memory array portion. In FIG. 28,
Word lines WLa and WL sharing sub-source line SSL
b. The memory cell MTa and the source line select transistor SSTa are connected to the word line WLa, and the memory cell MTb and the source line select transistor SSTb are connected to the word line WLb. Memory cell MTa
And MTb are arranged in the same column and connected to bit line BL. Here, the bit line may be any of the bit line of the NOR type flash memory and the sub-bit line of the DINOR type flash memory, and thus the symbol “BL” is used. As shown in FIG. 28, the source line select transistor may be formed of an n-channel MOS transistor, or may be formed of a floating gate type field effect transistor having the same write / erase characteristics as a memory cell. Therefore, the code “SST” is used. Therefore, in the following description, the bit line BL comprehensively indicates a bit line of a NOR type flash memory and a bit line (main / sub bit line) of a DINOR type flash memory, and the source line select transistor SST includes an n-channel M
An OS transistor and a floating gate type field effect transistor are comprehensively shown.

In the structure shown in FIG.
Consider a case where Tb is in an over-low Vth state.
When memory cell MTa is in the low threshold voltage state, erroneous reading of data does not occur even if a current flows through bit line BL through memory cell MTb in the overlow Vth state. However, when memory cell MTa is in the high Vth state, memory cell M in this overlow Vth state
Due to Tb, a current flows through the bit line BL, which may cause erroneous data reading (when the threshold voltage becomes negative). Therefore, when reading data, 1
There is a possibility that a bit defect will occur (when reading multiple bit data). Normally, to detect such an over-low Vth state memory cell, the word line WL (WL
a, WLb) is set to a voltage level of a voltage (0 to 0.5 V) lower than that in normal reading, and it is detected whether or not a current flows through the bit line BL. However, in this state, source line select transistors SSTa and STa
STb is also in a state in which it is not completely turned on (operation of the subthreshold region) or in an off state, and almost no current flows in a current path from bit line BL to main source line MSL. Therefore, the overlow Vt
In order to detect the memory cell in the h state, a method similar to the conventional method cannot be used. Hereinafter, a method of detecting the memory cell in the over-low Vth state will be described.

FIG. 29 schematically shows a structure of a main part of a nonvolatile semiconductor memory device according to the fourth embodiment of the present invention. FIG. 29 shows a configuration of a DINOR type flash memory. In FIG. 29, main bit lines MBL1-MBL1
MBLn is coupled to internal data bus 61 via column select gates (Y gates) YG1 to YGn which are turned on in response to column select signals Y1 to Yn, respectively. These main bit lines MBL1 to MBLn have a section selection signal φs
Section select transistor SG1 which becomes conductive in response to
To SGn are connected to sub-bit lines SBL1 to SBLn. Word line WL and these sub-bit lines SBL1 to SBL1
Memory cells MT are arranged corresponding to the intersections of SBLn. These memory cells MT are commonly connected to a sub source line SS
L, and the sub source line SSL is connected to the main source line MSL via the source line selection transistor SST. The source line selection transistor SST is connected to the word line W
Conducts in response to the signal voltage on L.

Internal data bus 61 has a test voltage generating circuit 62 for generating test voltage Vr of a predetermined voltage level in the test operation mode, and a test voltage generation circuit 62 in the test operation mode.
A determination circuit 63 for comparing test voltage Vr from test voltage generation circuit 62 with a voltage on internal data bus 61 is included. Test voltage Vr from test voltage generation circuit 62
May be the read voltage transmitted to the selected bit line at the time of reading, or may be a voltage slightly lower than this read voltage, for example, a ground voltage of about +0.5 V. Next, an over-low Vth memory cell detecting operation of the nonvolatile semiconductor memory device shown in FIG. 29 will be described.

First, in the test mode operation, test voltage generation circuit 62 is activated to generate test voltage Vr of a predetermined voltage level. In this test operation mode, column select signals Y1 to Yn are all driven to the selected state at the same time, and test voltage Vr is transmitted to main bit lines MBL1 to MBLn. In this state, section selection signal φs is inactive. When a predetermined time has elapsed and the main bit lines MBL1 to MBLn are charged to the test voltage Vr level, all the column selection signals Y1 to Yn are set to a non-selected state, and the main bit lines MBL1 to MBLn are set to a floating state. Then, for a predetermined period, the section selection signal φ
s, and the section selection transistors SG1 to SG
Gn is turned on. Thereby, the main bit line M
The charges charged in BL1 to MBLn are transmitted to corresponding sub-bit lines SBL1 to SBLn. The word line WL is
All are in a non-selected state, and the voltage level is the ground voltage (0
V) Hold at the level. In this state, when there is a memory cell in the over-low Vth state (over-write state) in the memory cell, the electric charge transmitted to the sub-bit line via the memory cell in the over-low Vth state is transferred to the sub-source line. It flows to SSL. The sub source line SSL is connected to the word line W
L, and the source line selection transistor SST is also in the off state, so that the sub source line SS
The voltage level of L rises. As a result, the voltage level of the main bit line provided for the sub-bit line connected to the memory cell in the over-low Vth state decreases. The connection between the sub bit line and the main bit line is established for a predetermined time (for example, 1
00ns), and then the column selection signals Y1 to Y
n are sequentially driven to a selected state, and the main bit lines MBL1 to MBL
Ln are sequentially connected to the internal data lines 61. Judgment circuit 63
Compares the voltage transmitted from the main bit line on the internal data 61 with a test voltage Vr, and generates a signal P / F indicating whether or not a memory cell in an over-low Vth state exists according to the comparison result. Occur.

FIG. 30 is a diagram showing a capacitance distribution of a main bit line, a sub-bit line, and a sub-source line. In FIG. 30, the main bit line MBL has a parasitic capacitance Ca, the sub-bit line SBL has a parasitic capacitance Cb, and the sub-source line SSL has a parasitic capacitance Cc. The word line voltage is 0 V in a non-selected state, and when the memory cell MT is normal, the current path from the sub bit line SBL to the sub source line SSL is cut off. Therefore, in this case, voltage V1 on main bit line MBL is expressed by the following equation.

V1 = Vr · Ca / (Ca + Cb) -Vr Here, the capacitance value of the parasitic capacitance Cb of the sub-bit line SBL is
This is approximated as being negligible compared to the capacitance value of the parasitic capacitance Ca of the main bit line MBL.

On the other hand, when the memory cell MT
In the th state, the sub bit line SBL is connected to the sub source line SS
Current flows to L. Therefore, in this case, the main bit line M
The voltage V2 on BL is represented by the following equation.

V2 = Vr · Ca / (Ca + Cb + Cc) to Vr / 2 Here, it is approximated that the capacitance values of the parasitic capacitances Ca and Cc of the main bit line MBL and the sub-source line SSL are equal to each other. Therefore, by detecting these voltages V1 and V2, it is possible to identify whether or not a memory cell in the over-low Vth state exists in the selected row.

In the arrangement shown in FIG. 29, test voltage generation circuit 62 and determination circuit 63 are connected to main bit lines MBL1 to MBLn via internal data line 61. Instead, main bit lines MBL1-MBLn
A test voltage generation circuit and a judgment circuit are provided for each, and the test voltage generation circuit and the judgment circuit are
Alternatively, a configuration for connecting to each corresponding main bit line may be used. The voltage levels of main bit lines MBL1 to MBLn can be accurately determined without being affected by the parasitic capacitance of the internal data lines.

As the determination circuit 63, an ordinary comparison circuit may be used. The test voltage generation circuit 62
For example, a circuit for generating a voltage applied to the selected bit line at the time of reading may be used, or a constant voltage generating circuit using a diode or the like may be used.

[Modification] FIG. 31 shows a structure of a modification of the fourth embodiment of the present invention. In FIG. 31, capacitive elements C1 to Cm are provided corresponding to bit lines 1-1 to 1-m, respectively. Bit lines 1-1 to 1-m
Are connected to internal data lines 65 through column selection gates YG1 to YGm which are turned on in response to column selection signals Y1 to Yn, respectively.
Connected to. At the other end, these bit lines 1-1 to 1-m are connected to capacitance elements C1 to Cm via switching elements SW1 to SWm which are turned on in response to test mode instruction signal TE. These capacitive elements C
1 to Cm receive test voltage Vr from test voltage generation circuit 62 via switching element SWa. Switching element SWa is supplied with complementary test mode instruction signal ZT.
Conducts in response to E. The internal data line 65 is provided with a determination circuit 63 for comparing the test voltage Vr from the test voltage generation circuit 62 with the voltage of the selected bit line.

In the arrangement shown in FIG. 31, in the test operation mode, first, switching element SWa is turned on, while switching elements SW1 to SWm are turned off. In this state, the capacitative elements C1 to C
m is charged. When the charging operation of these capacitive elements C1 to Cm is completed, the switching elements SW1 to SW
Wm is turned on, switching element SWa is turned off, and the charged charges of capacitance elements C1 to Cm are transmitted to corresponding bit lines 1-1 to 1m. Memory cells are connected to the bit lines 1-1 to 1m, respectively. When there is a memory cell in the over-low Vth state (over-erased state), the electric charge transmitted to the bit line via the memory cell in the over-erased state is transmitted to the corresponding sub-source line. Therefore, similar to the arrangement shown in FIGS.
The voltage of the bit line connected to the memory cell in the over-low Vth state falls below the level of test voltage Vr.
After a lapse of a predetermined time, the column selection signals Y1 to Ym are sequentially driven to a selected state, and the determination circuit 63 supplies the bit lines 1-1 to
m are sequentially connected to perform a determination operation.

In the configuration of the NOR type flash memory as shown in FIG. 31, a capacitance element is provided corresponding to each bit line, and a source line selection transistor is provided by utilizing the charge of the capacitance element. Also in the configuration, it is possible to easily identify whether or not a memory cell in an over-erased state exists. Here, also in the arrangement shown in FIG. 31, the word lines are all kept in a non-selected state in the test operation mode.

As described above, according to the fourth embodiment of the present invention, the charge of the capacitance means (capacitance element or main bit line) charged to a predetermined voltage level is transmitted to the bit line or the sub bit line, Since it is configured to determine whether the voltage level of the bit line or the main bit line decreases,
Even when the source line selection transistor is used, it is possible to accurately determine whether or not there is a memory cell in the over-low Vth state.

[Fifth Embodiment] FIG. 32 shows a structure of a main part of a nonvolatile semiconductor memory device according to a fifth embodiment of the present invention. FIG. 32 schematically shows a configuration of an array portion and a peripheral portion of a NOR circuit flash memory.
In FIG. 32, bit lines 1-1 to 1-m are connected to column select gates YG1 to YG1 to be conductive in response to column select signals Y1 to Ym.
Connected to internal data line 71 via YGm. The internal data line 71 has a test voltage Vr in the test operation mode.
And a determination circuit 74 for comparing the voltage on internal data line 71 with voltage Vr / 2 provided from voltage dividing circuit 73. Test voltage generation circuit 72 is set to an output high impedance state when inactive. The voltage dividing circuit 73 converts the test voltage Vr generated from the test voltage generating circuit 72 into
The pressure is divided at a division ratio of 2.

In FIG. 32, bit lines 1-1 to 1--1
A word line WL intersecting with m and a sub-source line SSL arranged corresponding thereto are representatively shown. This sub source line SSL is connected to the main source line MSL via a source line selection transistor SST which becomes conductive in response to a signal voltage on the word line WL. Next, the operation of the nonvolatile semiconductor memory device shown in FIG. 32 will be described with reference to a signal waveform diagram shown in FIG. Here, FIG. 33 shows a signal waveform at the time of an operation of determining whether or not a memory cell in an over-low Vth state exists on bit lines 1-1 and 1-2. First, at time t0, test voltage generation circuit 72 is activated to generate test voltage Vr of a predetermined voltage level and transmit it to internal data line 71.

Next, at time t1, the column selection signal Y1
To the selected state to turn on the column selection gate YG1, to transmit the test voltage Vr onto the bit line 1-1,
The bit line 1-1 is charged to the level of the test voltage Vr.

After a predetermined period (time required for charging bit line 1-1) has elapsed, at time t2, test voltage generating circuit 72 is inactivated and set to the output high impedance state. In this state, column select signal Y1 still maintains the active state.

Then, at time t3, column select signal Y
2 is activated, the column select gate YG2 is turned on, and the bit lines 1-1 and 1-2 are electrically connected. In this state, the charge charged on the bit line 1-1 is transmitted to the bit line 1-2. These bit lines 1-1 and 1
When a period necessary for transferring the electric charge between −2 and −2 elapses, at time t4, the column selection signal Y1 is driven to the non-selection state, and the column selection gate YG1 is turned off.

With column select gate YG2 turned on, decision circuit 74 is activated, and the voltage level on internal data line 71 is compared with voltage Vr / 2 from voltage divider circuit 73. At time t5, The signal P / F indicating the result of this determination is determined from the determination circuit 74. When the determination operation is completed, at time t6, the column selection signal Y2 is driven to the non-selection state, and the over-low Vt for the bit line 1-2 is set.
The operation of detecting the presence or absence of the memory cell in the h state (over-erased state) is completed.

When performing the determination operation on bit line Y1, the activation sequence of column select signals Y1 and Y2 is reversed. That is, the column selection signal Y2 is first activated for a predetermined period, and then the column selection signal Y1 is activated for a predetermined period. Next, the determination operation of the determination circuit 74 will be described.

(I) When both bit lines 1-1 and 1-2 are normal: In this case, bit lines 1-1 and 1--2
When 2 is connected, the electric charge charged in the bit line 1-1 is merely transmitted to the bit line 1-2. Therefore, as shown in FIG. 34, charge is divided by bit line capacitance CB. Therefore, bit lines 1-1 and 1-2 have a voltage level of Vr / 2. The determination circuit 74 determines that the charging voltage of the bit line 1-2 is Vr / 2
It is determined that there is no over-low Vth memory cell on the bit line 1-2.

(Ii) When one bit line is defective:
When a memory cell in an over-low Vth state is connected to the bit line 1-1, as shown in FIG. 35A, the bit line 1-1 has a bit line capacitance CB and a sub-source line capacitance CS. Are connected in parallel. This is because the word lines are all in the non-selected state and the source line select transistors are all in the off state. When the bit line 1-2 is normal and the memory cell in the over-low Vth state is not connected, only the capacitance CB of the bit line 1-2 affects the bit line voltage. Therefore, in this case, the charging voltage V1 of the bit lines 1-1 and 1-2 is given by the following equation.

V1 = Vr · (CB + CS) / (2 · CB + CS) The voltage V1 is a voltage level higher than the voltage Vr / 2 from the voltage dividing circuit.

On the other hand, when a memory cell in an over-low Vth state is connected to bit line 1-2, FIG.
As shown in (B), the capacitance CB of 1-1 of this bit line is obtained.
Is accumulated in the parasitic capacitance CB + of the bit line 1-2.
Distributed to CS. Therefore, in this state,
The charging voltage V2 is given by the following equation.

V2 = Vr · CB / (2 · CB + CS) This voltage level corresponds to the voltage V output from the voltage dividing circuit 73.
The voltage level is lower than r / 2. The determination circuit 74
If the charging voltage of bit line 1-2 is different from charging voltage Vr / 2, it is determined that one of bit lines 1-1 and 1-2 has a memory cell in an over-low Vth state, and that The bit line in which the memory cell in the over-low Vth state exists is identified according to which of the voltages V1 and V2 the charging voltage is. In this case, another identification method is possible, which will be described later.

(Iii) Bit lines 1-1 and 1-2
Are both defective: when the memory cell connected to the same sub-source line is in the over-low Vth state when charging the bit line 1-1, this common sub-source line is used when charging the bit line 1-1. Is charged. Therefore,
In this state, the state is the same as that in FIG.
On the other hand, when memory cells in the over-low Vth state exist in different rows and the sub-source line charged in the bit line 1-1 is different from the sub-source line charged in the bit line 1-2, FIG. As shown, bit line 1
-1 and 1-2 are the bit line capacitances C
B and the sub-source line capacitance CS, and the charging voltage is at the voltage level of the intermediate voltage Vr / 2. Even in such a state, since the capacitance CS of the sub-source line is sufficiently large, the abnormality can be determined by setting the charging time of the bit line to the time required for charging the normal bit line.
That is, the charging period (time t2 and time t1) shown in FIG.
Is set to a period required only for charging the bit line, the charging voltage of the bit line and the sub-source line becomes the voltage level of the voltage Vr ′ lower than the test voltage Vr. Therefore, the charging voltage level after connection of bit lines 1-2 and 1-1 becomes the voltage level of Vr '/ 2, which is lower than the voltage level of intermediate voltage Vr / 2, and the voltage level can be accurately determined. Can do it.

In the configuration shown in FIG. 35A, when charging bit line 1-1, if bit line capacitance CB and sub-source line capacitance CS are substantially the same, bit line 1
-1 is about Vr / 2, and the charging voltage Vr 'when the bit lines 1-1 and 1-2 are connected is Vr'.
1 becomes lower than the intermediate voltage Vr / 2 as shown in parentheses in FIG. Therefore, also in this case, it can be determined that one of bit lines 1-1 and 1-2 is defective. That is, by performing a test using each of the bit lines 1-1 and 1-2 as a charge supply source, it is possible to identify which is the defective bit line.

In this case, determination circuit 74 only needs to determine the level of intermediate voltage Vr / 2 from voltage dividing circuit 73 and the bit line charging voltage, and the circuit configuration is simplified.

FIG. 37 is a diagram schematically showing a configuration of a column selection signal generating portion according to the fifth embodiment of the present invention.
Referring to FIG. 37, a column selection signal generation unit is activated in response to test mode instruction signal TEM, and generates an address generation circuit 75 for generating a column address in a predetermined sequence, and in response to activation of test mode instruction signal TEM. An address control circuit 76 receiving an address given from address generation circuit 75 as a charging bit line specific address and generating an address signal designating a corresponding column and an adjacent column at a predetermined timing; A column decoder 77 that statically performs a decoding operation in accordance with an address signal from circuit 76 to generate column selection signal Y is included.

Address generation circuit 75 and address control circuit 76 are activated in response to activation of test mode instruction signal TEM, and apply a column address signal to column decoder 77 at a predetermined timing. Column decoder 77
Simply decodes the column address given from the address control circuit 76 statically to generate a column selection signal Y. The address generation circuit 75 and the address control circuit 76 may be used in the write / erase operation mode. In the operation mode for performing normal data reading, column decoder 77 is supplied with a column address signal from a column address input buffer (not shown).

[First Modification] FIG. 38 schematically shows a structure of a first modification of the fifth embodiment of the present invention. In the configuration shown in FIG. 38, bit lines 1-1 to 1-m
Are connected to the upper bit lines 1-1u to 1-mu and the lower bit lines 1-1l to 1-ml by the isolation gates IG1u to IGm.
u and IG11 to IGml. These isolation gates IG1u to IGmu and corresponding isolation gate I
The test voltage Vr from the test voltage generation circuit 72a is transmitted to the connection node of G11 to IGml via the switching element 72b. Test voltage Vr generated by test voltage generation circuit 72 a is applied to determination circuit 73 via voltage dividing circuit 72.

In the configuration shown in FIG. 38, switching element 72b is rendered conductive in response to activation of test instruction signal TE, and transmits test voltage Vr from test voltage generating circuit 72a to a connection node of each isolation gate. . When the voltage of the connection node between isolation gates IG1u to IGmu and GI11 to IGml is stabilized, control signal φA is then activated under the control of a control circuit (not shown),
Isolation gates IG1u to IGmu are turned on, and upper bit lines 1-1u to 1-mu are charged to the level of test voltage Vr. When this charging is performed for a predetermined period, test instructing signal TE is inactivated, and bit line 1-
1u to 1-mu are set in a floating state. In this state, control signals φA and φB are both turned on, and upper bit lines 1-1u to 1-mu are electrically connected to corresponding lower bit lines 1-1l to 1-ml,
Charge is transmitted. Control signals φA and φB for a predetermined period
Are maintained in an active state, then both control signals φA and φB are driven to an inactive state.

Next, the column selection signals Y1 to Ym are sequentially driven to the selected state, and the determination circuit 73 determines the charging voltage levels of the upper bit lines 1-1u to 1-mu. This judgment circuit 7
The determination operation of No. 3 is the same as the determination operation of the determination circuit 73 described above. When there is a memory cell in the over-low Vth state in the upper bit line or the lower bit line, the charging voltage of the bit line is at a voltage level lower than the intermediate voltage Vr / 2. This makes it possible to determine whether or not there is a memory cell in the over-low Vth state on a bit line basis.

In the structure of the first modification as well, by setting the charging time by the test voltage Vr from the test voltage generating circuit 72a to an appropriate value, the sub source line is connected via the memory cell in the over-low Vth state. Can be prevented from being charged to the test voltage Vr level. Except in the test mode, control signals φA and φB are both in an active state, and isolation gates IG1u to
IGmu and IG1L to IGml are all kept on.

In the structure shown in FIG. 38, it cannot be determined which of the upper bit line and the lower bit line has the memory cell in the over-low Vth state. However, in units of bit lines, the over-low Vt
It can be determined whether there is a memory cell in the h state.

[Modification 2] FIG. 39 schematically shows a structure of a modification 2 of the embodiment 5 of the invention. FIG.
In the configuration shown in FIG. 9, sectors 80 and 81 are arranged to share local data bus 82. Sector 80 includes a memory cell array 80a having memory cells arranged in a matrix, and a Y gate circuit 80b for selecting a column of memory cell array 80a according to a column selection signal from a column decoder (not shown). The sector 81 includes a memory cell array 8 having memory cells arranged in a matrix.
1a, and a Y gate circuit 81b for connecting a selected column of the memory cell array 81a to the local data bus 82 according to a column selection signal from a column decoder (not shown). Local data bus 82 is provided with a write / sense amplifier circuit 84 for writing / reading data and a test circuit 83. This test circuit 83 includes the test voltage generating circuit, the voltage dividing circuit, and the determination circuit described above (see FIGS. 32 and 38).

The write / sense amplifier circuit 84 is connected to a global data bus 86 via a sector select gate 85. This sector selection gate 85 receives a sector selection signal φsec at its gate.

In the structure shown in FIG. 39, the Y gates included in Y gate circuits 80b and 81b are selectively connected to local data bus 82, and the bit line on one sector is tested by test circuit 83 from test circuit 83. The charging of the voltage level and the connection of the bit lines of both sectors are performed, and the level of the charging voltage of the bit line of the other sector is determined. The voltage level determination operation by test circuit 83 is the same as that shown in FIG. Instead of using the charging voltage of the adjacent column or the same bit line in the same memory cell array, the charging voltage of the bit line of the memory cell array included in the adjacent sector is used. Also in this case, since each bit line has the same capacitance value, if the bit line is a normal bit line, the charging voltage is at the voltage level of the intermediate voltage Vr / 2, and the same determination operation can be performed.

As described above, according to the fifth embodiment of the present invention, it is determined whether or not a corresponding bit line is charged to a predetermined voltage level using a charging voltage of a bit line, and the determination result is obtained. , The over-low Vth state (over-erased state)
Because it is determined whether there is a memory cell of,
With a simple circuit configuration, it is possible to easily determine the presence or absence of a memory cell in the over-low Vth state.

[Sixth Embodiment] FIG. 40 shows a structure of a main portion of a nonvolatile semiconductor memory device according to a sixth embodiment of the present invention. 40, test signal lines 92a and 92b are provided separately from internal data line 71. Bit lines 1-1 to 1-m are connected to test column selection signals TY1 to T
Test column selection gates TG1-T that conduct in response to Yk
Connected to test signal lines 92a and 92b via Gm. Test column selection signals TY1 to TYk are commonly generated for two columns of bit lines, and two columns of bit lines are simultaneously selected and connected to test signal lines 92a and 92b, respectively.

Test signal lines 92a and 92b are rendered conductive when test mode instruction signal TE is activated, and transfer gate 79 for transmitting a test voltage from test voltage generating circuit 90 to test signal lines 92a and 92b. And a comparison circuit 91 for comparing signal voltages on test signal lines 92a and 92b. Other configurations are
The configuration is the same as that shown in FIG. 32, and corresponding portions are denoted by the same reference numerals.

In the structure shown in FIG. 40, column select signals Y1 to Ym used in the normal operation mode are not used. Signal lines 92a and 9 provided exclusively for testing
The bit line is charged and the level of the charging voltage is determined via 2b. Next, the operation of the nonvolatile semiconductor memory device shown in FIG. 40 will be described with reference to a signal waveform diagram shown in FIG.

At time t0, test voltage generation circuit 90
Is activated and released from the output high impedance state to generate the test voltage Vr. At the right time,
When test mode instruction signal TE is activated, the transfer gate is turned on, and test voltage Vr of the same voltage level is transmitted to test signal lines 92a and 92b.

At time t1, test column select signal TY1
Is driven to the selected state, test column select gates TG1 and TG2 are turned on, and bit lines 1-1 and 1-2 are connected to test signal lines 92a and 92b, respectively. Thus, the bit lines 1-1 and 1-2 are charged to the test voltage Vr level, respectively.

After a predetermined time has elapsed, at time t2, test voltage generation circuit 90 is inactivated to be in an output high impedance state, and transfer gate 79 is also deactivated in response to inactivation of test mode instruction signal TE. The conduction state is established, and the charging operation for bit lines TY1 and TY2 is completed.

In this state, at time t3, test column select signal TY2 is driven to the selected state, and bit line 1
-1 and 1-2 are electrically connected to bit lines 1-3 and 1-4, respectively, between which charge moves.

Then, at time t4, test column select signal TY1 is driven to a non-selected state, and test column select gate T
G1 and TG2 are turned off. On the other hand, test column select signal TY2 is in an active state, and test column select gate T
G3 and TG4 are on. Bit lines 1-3 and 1-4 are connected to test signal lines 92a and 9a, respectively.
2b, and the voltage levels of test signal lines 92a and 92b are connected to bit lines 1-3 and 1-
4 A voltage level corresponding to each charging voltage level is reached.

Then, test signal lines 92a and 9a
When the voltage level of 2b is stabilized, comparison circuit 91 is activated at time t4, and signal lines 92a and 92b are activated.
Are compared, and the output signal P / F is driven based on the comparison result.

When bit lines 1-1 to 1-4 are all in a normal state and no memory cell is in an over-low Vth state, bit lines 1-3 and 1-4 are connected to intermediate voltage Vr / 2. Precharged to voltage level. When the voltage levels of the bit lines 1-3 and 1-4 are the same, the comparison circuit 91 determines that the bit lines are normal.

On the other hand, when bit lines 1-1 and 1-2 are normal and one of bit lines 1-3 and 1-4 is abnormal (a state where a memory cell in an over-low Vth state is connected). Causes a difference in the voltage levels of the bit lines 1-3 and 1-4. By detecting this difference with the comparison circuit 91, it is determined which of the bit lines 1-3 and 1-4 is connected to the memory cell in the over-low Vth state.

In the arrangement shown in FIG. 40, when both bit lines forming a pair are defective and a memory cell in an over-low Vth state is connected, a signal indicating the same voltage level is output from comparison circuit 91. Is output.

As shown in FIG. 40, a test voltage generating circuit and a comparing circuit are provided separately from the data bus to compare the level of the charging voltage of the bit line forming a pair. Can be detected.

The test column selection signals TY1 to TY
The generation mode of k can be easily realized by simply setting the least significant column address bit to the degenerated state in the configuration shown in FIG. In the case of reading a multi-bit data by simultaneously selecting a plurality of memory cells from one row of memory cells, an internal data bus line may be used as a test signal line.

[Modification] FIG. 42 schematically shows a structure of a modification of the sixth embodiment of the present invention. FIG. 42 shows a configuration of a main part of two sections 95 and 96. The section 95 includes a memory cell array 95a having a plurality of memory cells arranged in a matrix, a Y gate circuit 95b for selecting an addressed column of the memory cell array 95a, and a memory cell array 95 in a test operation mode. 95a includes a test gate circuit 95c for simultaneously selecting two columns and connecting to the test signal bus 97. Test gate circuit 95c is equivalent to test column selection gates TG1 to TGm shown in FIG.

The section 96 includes a memory cell array 96a having a plurality of memory cells arranged in a matrix, and a Y gate circuit 96 for selecting an addressed column.
b, and a test gate circuit 96c for simultaneously selecting two columns and connecting to the test signal bus 97 in the test operation mode. The test data bus 97 is provided with a test voltage generation circuit 93 for generating a voltage of a predetermined voltage level in the test operation mode, and a comparison circuit 94 for comparing the signal voltage on the test signal bus 97. Test signal bus 97
Has a 2-bit signal line, and has a test gate circuit 95c.
And 96c are electrically connected to the two columns of bit lines selected respectively.

In the structure shown in FIG. 42, one of the two columns of bit lines of memory cell arrays 95a and 96a is charged with a test voltage from test voltage generating circuit 93. After this charging, the memory cell array 95a
And interconnection between the two columns of bit lines 96a. Subsequently, the signal voltages of the two columns of bit lines in the other memory cell array are transmitted to the test signal bus 97 and compared by the comparison circuit 94.

As shown in FIG. 42, the same effect can be obtained even when the structure is such that both memory cell arrays 95a and 96a are charged.

As described above, according to the sixth embodiment of the present invention, the charging and the detection of the charging voltage level are performed in units of two bit lines, so that the test time can be shortened. Thus, an accurate determination operation can be performed.

[Embodiment 7] FIG. 43 schematically shows a structure of a main part of a nonvolatile semiconductor memory device according to an embodiment 7 of the invention. FIG. 43 shows a configuration of a portion related to four word lines WLa to WLd. Word lines WLa and WLb share sub-source line SSLa,
Word lines WLc and WLd share source line SSLb. Word lines WLa-WLd and sub source line SS
A memory cell MT and a source line select transistor SST are provided corresponding to La to SSLb. Source line select transistor SST drives the corresponding word line to the selected state, and transmits the ground voltage from main source line MSL to the corresponding sub source line.

Word line selection circuits 100a to 100d are provided for decoding word lines WLa to WLd into given address signals and driving corresponding word lines to a selected state. Word line selection circuits 100a-10
0d each include a NAND type decode circuit ND for decoding a given address signal, and a word line drive circuit WD for inverting an output signal of the NAND type decode circuit ND and driving a corresponding word line to a selected state. Including. N
AND circuit decode circuit ND and word line drive circuit WD operate using power supply voltage Vcc (3.3 V) and ground voltage as both operation power supply voltages.

On the other side of word lines WLa to WLd, negative voltage driving circuits 102a to 102d for driving a word line paired with a selected word line to a negative voltage level are provided. Each of word line negative voltage drive circuits 102a to 102d has a NAND decode circuit NG for decoding a given address signal, and a NAND decode circuit NG
And an n-channel MOS transistor NWT transmitting a negative voltage Vn to a corresponding word line in accordance with an output signal of inverter circuit LG with a level conversion function.

NAND type decode circuit NG operates using power supply voltage Vcc and ground voltage as both operation power supply voltages. The inverter circuit LG with the level conversion function operates using the ground voltage (0 V) and the negative voltage Vn as both operation power supply voltages,
The amplitude of the output signal of the NAND decode circuit NG is set to 0V
And a negative voltage Vn.

In word line selecting circuits 100a-100d and word line negative voltage driving circuits 102a-102d,
The least significant bit of the applied row address signal is replaced on a paired word line. That is, the word line WLa is selected by the word line selection circuit 100a,
When the selected word line WLa is driven to the power supply voltage Vcc level, the word line negative voltage driving circuit 102b is selected and transmits the negative voltage Vn to the word line WLb. The unselected word lines WLc and WLd are connected to the word line selection circuit 100
the output signals of c and 100d are at ground voltage level,
Word line negative voltage driving circuits 102c and 102d
Are kept at the ground voltage level because they are in an output high impedance state.

More specifically, for example, the output signal of NAND type decode circuit ND of word line select circuit 100a is at L level.
Level, indicating the selected state, the output signal of the corresponding word line drive circuit WD goes high. At this time, in the word line selection circuit 100b, the NAND
The output signal of type decode circuit ND is at H level, and the output signal of corresponding word line drive circuit WD is at L level. On the other hand, in the word line negative voltage drive circuit 102a, since the least significant bit of the address signal applied to the NAND decode circuit NG is different, NAN
The output signal of the D-type decode circuit NG goes high,
In the non-selected state, the output signal of the corresponding inverter circuit LG with a level conversion function becomes the L level of the negative voltage Vn level, and the MOS transistor NWT is turned off. On the other hand, in word line negative voltage drive circuit 102b, the output signal of NAND decode circuit NG attains the L level, and the output signal of corresponding inverter circuit LG with the level conversion function attains the H level of the ground voltage level.
The OS transistor NWT is turned on, and the word line W
Lb is transmitted with negative voltage Vn.

Therefore, in the structure shown in FIG. 43, for example, when word line WLa is selected, word line WLb is driven to the level of negative voltage Vn. Even when memory cell MT connected to word line WLb is in the overlow Vth state, its threshold voltage Vth is higher than the voltage level of negative voltage Vn transmitted on word line WLb, and the leakage current is lower. It is surely suppressed. Therefore, only the current from memory cell MT connected to word line WLa flows through bit line BL, and accurate data reading can be performed.

Normally, in the nonvolatile memory cell, the threshold voltage Vth of the memory cell in the overlow Vth state
Has the highest probability of being near the ground voltage (0 V) and has a very low probability of becoming a deeper negative voltage, and therefore has a voltage -VWL (about the opposite of the sign of the voltage VWL transmitted on the selected word line WLa). If the voltage level is -3.3 V), the leak current of the memory cell in the over-low Vth state can be surely suppressed.

In memory cell characteristics, normally, the threshold voltage of a memory cell in a low threshold voltage state is distributed between ground voltage (0 V) and voltage VWL transmitted on a selected word line. The memory cell is manufactured. To lower the threshold voltage Vth, Fowler-Nordheim tunneling current is used regardless of the NOR flash memory and the DINOR flash memory. The Fowler-Nordheim tunneling current decreases exponentially when the threshold voltage Vth decreases by 1V. When the threshold voltage Vth decreases and enters the over-low Vth state, the Fowler-Nordheim tunneling current becomes extremely small, and the decrease in the threshold voltage Vth is suppressed.

As shown in FIG. 44, the memory cell in the low threshold voltage state exists in a very narrow range around the threshold voltage Vt0, and is a memory cell having a negative threshold voltage. The number is extremely small. Therefore, if negative voltage -VWL is transmitted to a word line paired with this selected word line (sharing a sub-source line), the allowable distribution range of the threshold voltage of the memory cell will be in the range of VWL to -VWL. Thus, the distribution becomes much wider than the actual distribution of the threshold voltage of the memory cell, and the probability that the threshold voltage Vth of the memory cell becomes equal to or lower than the negative voltage −VWL can be regarded as almost zero. Therefore, the leak current of the memory cell in the over-low Vth state can be surely suppressed.

In the structure shown in FIG. 43, when a negative voltage is transmitted to a word line, a corresponding word line selection circuit transmits a voltage at the ground voltage level. In this case, in word line drive circuit WD, a p-channel MOS transistor receiving a signal of the word line forming a pair at its gate is inserted between the ground node and the word line, and a word line paired with the selected word line is provided. If the configuration in which the provided word line drive circuit is set to the output high impedance state is used, the current consumption at the time of transmitting the negative voltage is surely suppressed,
Further, the unselected word lines can be reliably driven to the negative voltage VN level.

As described above, according to the seventh embodiment of the present invention, since the negative voltage is transmitted to the unselected word line paired with the selected word line, the sub-source line is surely shared. The memory cell in the over-low Vth state can be set to the off state, and the memory cell data can be accurately read.

[Eighth Embodiment] FIG. 45 shows a structure of a main portion of a nonvolatile semiconductor memory device according to an eighth embodiment of the present invention. FIG. 45 shows memory cells MT arranged in four rows and four columns. In the configuration shown in FIG. 45, corresponding to each of word lines WLa to WLd,
Sub source lines SSLDa to SSLDd are provided. These sub source lines SSLDa to SSLDd are connected to a main source line MSL via corresponding source line select transistors SSTa to SSTd, respectively.

In the case of the arrangement shown in FIG. 45, only the sub-source lines provided corresponding to the selected row are connected to main source line MSL. Sub-source lines provided corresponding to non-selected word lines are separated from main source lines MSL. Therefore, when a word line is selected, the current flows from the bit line to the main source line only through the memory cell connected to the selected word line and the corresponding sub-source line, and to the other non-selected word lines. The source (node connected to the sub-source line) of the memory cell to be opened is in an open state, and its current path is cut off. Therefore, when reading the memory cell data, the data of the selected memory cell can be accurately read without being affected by other memory cells in the overlow Vth state.

Next, a method of providing a sub-source line corresponding to each word line will be described.

Manufacturing Method 1: With reference to FIGS. 46A to 46C, a first method of manufacturing a sub-source line will be described below.

First, as shown in FIG. 46A, a nitride film 112 is formed except for the sub-source line separation region 111 of the semiconductor substrate 110. Using this nitride film 112 as a mask, a thermal oxidation process is performed to form a thermal oxide film (LOCOS film) 113 as shown in FIG.

Next, as shown in FIG. 46C, the gate insulating film 114 and the conductive layer 1 serving as a floating gate are formed.
15 and an interlayer isolation insulating film 116 are sequentially formed. The interlayer insulating film 116 separates a word line (control electrode) formed in an upper layer from a floating gate.

A conductive layer 117 serving as a word line (control electrode) is formed on the interlayer insulating film 116, and an interlayer insulating film 118 is further formed thereon, followed by patterning. Through these series of steps, the gate structure of the memory cell is formed. Next, ion implantation is performed using the gate structure as a mask to form a drain region, a source region, and a sub-source line. Thermal oxide film 113 is formed, and the sub-source lines formed in region 119 are separated from each other. Thereby, a sub source line can be provided corresponding to each word line.

Manufacturing Method 2: FIG. 47 shows main steps of a second sub-source line manufacturing method according to the eighth embodiment of the present invention. As shown in FIG. 47, the gate structure 120 is formed on the surface of the semiconductor substrate 110. This gate structure 12
0 denotes a gate insulating film, a conductive layer serving as a floating gate on the gate insulating film, and a word line formed on the floating gate via an interlayer insulating film as shown in FIG. Conductive layer, and an interlayer insulating film formed on the word line conductive layer. After these gate structures 120 are formed, a mask 121 made of, for example, a resist film is formed in the drain region of the memory cell in order to perform ion implantation into the source region. At this time, the separation region 1 between the sub-source lines on the surface of the semiconductor substrate 110 is also formed.
A mask 122 made of, for example, a resist film is formed on 11. Using these masks 121 and 122 as masks, ion implantation is performed to form memory cell source regions and sub-source lines. No ion implantation is performed on the surface of the semiconductor substrate 110 immediately below the mask 122. Therefore, sub-source line isolation region 111 has the same impurity concentration as the channel region immediately below gate structure 120 of the memory cell. On the sub-source line separation region 111,
Since no gate electrode or the like is formed, the isolation region 11
1 is always in a high resistance state. In particular, the source / sub-source line region 119 has almost no potential difference (in both the open state and the case where the ground voltage is transmitted). Therefore, the sub-source line separation region 111 can sufficiently function as a region for electrically separating the source / sub-source line region 119.

Manufacturing method 3: FIGS. 48 (A) and (B)
FIG. 26 is a diagram showing each step of a third manufacturing method according to the eighth embodiment of the present invention. First, as shown in FIG. 48A, the gate structure 12 of the memory cell is formed on the surface of the semiconductor substrate 110.
After forming 0, for ion implantation into the source region,
A source implantation mask 121 made of, for example, a resist film is formed to cover the drain region of the memory cell. Then
Using mask 121 and gate structure 120 as a mask, an N-type impurity region such as phosphorus or arsenic is implanted. Thereby, the gate structure 1 of the semiconductor substrate 110
An impurity region is formed on region 123 between 20, and a source region and a sub-source line of the memory cell are formed.

Next, as shown in FIG. 48B, a new mask 124 made of, for example, a resist film is formed.
The source region and the sub-source line region of the memory cell in the region 123 are covered. In this state, the semiconductor substrate 1
Only the surfaces of the ten isolation regions 111 are exposed. Using this mask 124 as a mask, a P-type impurity such as boron, which is of a conductivity type opposite to that of the impurity (N-type) implanted over the entire region 123, is ion-implanted. This separation area 111
48A, the N-type impurity implanted in FIG. 48A is offset into the isolation region 111, and the isolation region 111 is equivalently a high-impurity region having a low impurity concentration. Becomes As a result, the separation region 111
Function as an isolation region between the source / sub-source line region 119.

Manufacturing method 4: FIGS. 49 (A) to 50
(B) is a diagram showing a step of a fourth manufacturing method of sub-source line isolation according to the eighth embodiment of the present invention. FIG.
As shown in FIG. 9A, a gate electrode structure 120 is formed in a predetermined shape on the surface of the semiconductor substrate 110. Next, an oxidation-resistant film 125 such as a nitride film, which is resistant to thermal oxidation, is formed so as to cover the memory cell drain region 126 and a part of the gate structure 120 except for the source / sub-source line region 123. The oxidation-resistant film 125 is formed so as to cover the transistor formation region in the peripheral circuit portion.

The oxidation resistant film 125 and the gate structure 12
Using 0 as a mask, a P-type dopant such as boron is implanted into region 123 for source isolation.

Next, as shown in FIG. 49B, a thermal oxidation process is performed using the oxidation-resistant film 125 as a mask to form a thermal oxide film 128 in the region 123. This thermal oxide film 12
8 functions as a mask for ion implantation performed in a subsequent source region and sub-source line forming step.
The thickness may be smaller than 100 nm.

Next, as shown in FIG. 50A, a mask 129 made of, for example, a resist film is formed except for the source / sub-source line region 119. A mask 129 is also formed in a portion to be an isolation region between sub-source lines. At this time, in the peripheral circuit portion (not shown), the resist film is not formed because the nitride film provided for preventing thermal oxidation is removed. Mask 12 made of this resist film
Using thermal mask 9 as a mask, thermal oxide film 128 is etched. In the peripheral circuit portion, since the nitride film 125 is etched away, it is necessary to adjust the selectivity of the etchant with respect to the thermal oxide film 128 and the nitride film 125 (adjustment of the etchant etching rate).

In FIG. 50A, nitride film 1
A mask 129 is formed so as to cover 25. However, this nitride film 125 is merely left as a mask for ion implantation into the source, and the nitride film 125 may be exposed and removed by etching. At the time of ion implantation into the source in a later process,
What is necessary is just to newly form a resist film.

After this etching, when mask 129 is removed, thermal oxide film 128a is left in source / sub-source line isolation region 111, as shown in FIG.
Further, a part of the thermal oxide film 128a is left under the gate structure 120. In this state, the gate structure 12
In the case of No. 0, the upper interlayer insulating film is partially etched away. However, since the interlayer insulating film is formed in a later step, there is no problem even if the conductive layer serving as a word line is exposed at this stage.

Next, ion implantation of the source region is performed using a mask as shown in FIG. 48A to form source / sub-source lines. At the time of this ion implantation, the thermal oxide film 128a formed in the isolation region 111 functions as a mask to prevent ion implantation into the source / sub-source line region 111. Thereby, separation between the sub-source lines can be performed (because a non-doped high-resistance region is left).

In the state shown in FIG. 50B, a part of thermal oxide film 128a is left under gate structure 120. However, also in this case, the source region is surely formed below the gate structure 120 by the impurity diffusion step by the heat treatment after the ion implantation into the region 119.

Any of manufacturing methods 1 to 5 shown in FIGS. 46 to 50 may be used, and a sub source line can be arranged corresponding to each word line.

Sub-source line structure: FIG. 51A schematically shows a sub-source line structure. A gate structure 120 is formed as shown in FIG.
51 (FIG. 51A), a sidewall oxide film for alleviating the drain electric field is formed on the gate structure 120, and then an interlayer insulating film is formed so as to cover the surfaces of the gate structure 120 and the substrate 110. 129 are formed.

In the interlayer insulating film 129, contact holes are provided at predetermined intervals along the direction in which the sub-source lines extend, and electrical contact is made to the source / sub-source line region 119 with the conductive material 131 through the contact holes. Take. This conductive material 131 is connected to a low-resistance conductive layer 130 made of, for example, aluminum or doped polysilicon formed thereon.

FIG. 51B schematically shows a planar layout of the sub-source line. In FIG. 51 (B),
Sub-source line 119a formed of a diffusion layer (impurity region)
And a low-resistance conductive layer 130 formed in parallel with the upper layer
Are electrically connected via contact holes 132 formed at predetermined intervals. This diffusion layer (impurity region) 119
By connecting a to the low-resistance conductive layer 130 at predetermined intervals, a so-called “pile-out structure” of the sub-source line is realized, and the resistance of the sub-source line is reduced. FIG. 52 schematically shows an arrangement of one row of the memory cell array. FIG.
2, a source line select transistor SST is arranged for each of a predetermined number (k) of memory cells MT. Main source line MSL is arranged corresponding to these source line select transistors SST, and is coupled to sub source line SSL arranged corresponding to word line WL. As in a NOR flash memory, channel hot electrons (CH
When writing is performed using E), a large current of, for example, about 100 μA per memory cell is applied to the sub source line SSL.
Flows to The sub-source line SSL has a low resistance, and the source line selection transistor S
By providing the ST, the current flowing through the sub-source line SSL can be dispersed and supplied via the relatively small source line selection transistor SST. Absent. Further, since the sub-source line SSL has a low resistance, even if a large current flows through the sub-source line SSL,
An increase in the source voltage of the memory cell can be prevented, and a write operation using channel hot electrons can be stably performed.

When the area of the memory cell array is limited, the number (k) of memory cells MT provided corresponding to source line select transistor SST is increased, and the channel of source line select transistor SST is increased. Increase the width a little. Also in this case, since the resistance value of the sub source line SSL is small,
For example, even if a current such as a Fowler-Nordheim current flows, voltage distribution (increase) due to the resistance value and the current does not occur, and writing / erasing can be performed accurately.

Now, as shown in FIG. 53, the resistance between the source line selection transistors of the sub source line is R. Source line select transistors SST0 to SST6 are connected in parallel, and these source line select transistors SST0 to SST6 are connected in parallel.
T6 is connected to a main source line MSL (not shown). Now, consider removing source line select transistor SST3. When this source line select transistor SST3 is removed, at least the source line select transistors SST1, SST2, SST4 and SST5 on both sides thereof are removed.
Needs to supply the supply current of the source line selection transistor SST3 instead. Since the resistance element R is driven to the ground voltage level by the source line selection transistors on both sides thereof, current flows on both sides equivalently in each of the resistance elements R. Therefore, when the source line selection transistor SST3 is removed, the fluctuation of the current driving force is caused by the source line selection transistors SST1 and SST on both sides.
2, affecting SST4 and SST5, and
Further, source line select transistors SST0 and SST
6 is also affected. In this case, the source line select transistors SST0 and SST6 are equivalent to a configuration for supplying a current from one side to the source line select transistor SST3. Therefore, when the source line select transistor SST3 is removed, the influence of the source line select transistors SST0 and SST6 is reduced to 、, and the other source line select transistors SST1, SST2, SST
4 and SST5 are affected,
One source line select transistor. In other words, it affects the current in the region where five resistive elements R are connected in series (source line select transistor SS
The effect of the source line selection transistor further outside T0 and SST6 is approximately negligible). Therefore, when using a sub-source line piled with this low-resistance metal conductive layer without using the diffusion layer as a sub-source line, in order to obtain an effect, the sheet resistance of the conductive layer must be equal to the sheet resistance of the diffusion layer. At least about 1/5 or less is required. Normally, when the diffusion layer is formed of an N-type impurity region, the sheet resistance is about 100 Ω / □, and therefore, the resistance of the sub-source line piled with the low-resistance conductive layer 130 is 20 Ω / □ or less. The effect can be obtained in the case.

As described above, according to the eighth embodiment of the present invention, sub-source lines are provided corresponding to respective word lines, so that the memory cells are surely affected by the over-low Vth state. It is possible to read the memory cell data accurately without the need.

[Ninth Embodiment] FIG. 54 shows a structure of a main portion of a nonvolatile semiconductor memory device according to a ninth embodiment of the present invention. In FIG. 54, a word line WL is arranged corresponding to each row of memory cells, while two bit lines BLi are arranged corresponding to each column of memory cells.
0, BLi1 (i = 0 to 3) are arranged. The sub-source lines SSLj (j = 0) correspond to each pair of adjacent word lines.
To 2) are arranged. These word lines WL0 to WL5
Source line select transistors SST0 corresponding to each
To SST5, and a selective connection between main source line MSL and sub-source lines SSL0 to SSL2 is performed.

In the arrangement shown in FIG. 50, memory cells sharing a sub-source line are connected to different bit lines BLi0 and BLi1 arranged corresponding to the respective memory cell columns. That is, the memory cell MT connected to the word line WL0 is connected to the bit line BLi0, and the memory cell MT connected to the word line WL1 is connected to the bit line BLi1. The memory cell MT connected to the word line WL2 is connected to the bit line BLi1,
Memory cell MT connected to word line WL3 is connected to bit line BLi0. Memory cell MT connected to word line WL4 is connected to bit line BLi0, and memory cell MT connected to word line WL5 is connected to bit line BL
i1. That is, in the memory cell column direction, the connection between the memory cell and the bit line is periodically switched with a 4-bit memory cell as a cycle. In other words, the memory cells MT are connected to the same bit line for each 2-bit memory cell in the column direction.

In the arrangement shown in FIG. 50, when a word line is selected, only one memory cell is connected to sub-source line SSL to main source line MSL in one bit line. For example, when word line WL0 is selected, bit lines BL00, BL10, BL2
0 and BL30 are connected to sub-source line SSL0 and main source line MSL via memory cell MT. Memory cell MT connected to word line WL1 is connected to bit lines BL01, BL11, BL21, and BL31. Therefore, the selected bit lines BL00, BL1
In 0, BL20, and BL30, current only flows through the selected memory cell of up to 1 bit.
Even if there is a memory cell in the over-low Vth state in the same column, the memory cell data can be read accurately without being affected by the memory cell.

In the arrangement shown in FIG. 54, a configuration for selecting a bit line can be realized by selecting a group of bit lines using the lower two bits of a row address signal for selecting a word line. That is, the least significant two bits of the row address signal for specifying the word line are, for example, (0,
0) and (1, 1) and the word line WL0 or W1
When designating L3, select bit line BLi0,
On the other hand, when the least significant bits of the word line specifying address signal are (0, 1) and (1, 0), the bit line BL
Select i1. Thereafter, the bit line of the corresponding column is selected according to the column address signal. Thereby, each memory cell column is grouped according to the word line group,
Even in a configuration in which bit lines are arranged corresponding to each group, accurate data reading can be performed.

In the structure shown in FIG. 54, even when bit line BL is a sub-bit line, the sub-selection signal applied to the section select transistor is simply combined with the word line group specifying signal to form the sub-line. Data can be read even if a plurality of bit lines are arranged corresponding to the respective memory cell columns.

Bit Line Layout 1: FIG. 55 shows a first layout of bit lines. In the bit line division (structure in which a bit line to be arranged corresponding to one column is divided into two columns) shown in FIG. 55, conductive layers 135a to 135h serving as word lines are arranged in the row direction, and in the column direction. Extending, conductive layers 137a to 137h to be bit lines are arranged at a ratio of two conductive layers to one column of the memory cells. An active region 138 for forming a memory cell is formed extending in the column direction. In each column, conductive layers 137a to 137h serving as bit lines are electrically connected to active regions 138 via contact holes 136 alternately in the column direction. In this arrangement, one contact hole 1
36 are shared by 2-bit memory cells arranged extending in the column direction. The sub-source lines are arranged every two word lines along the word line extending direction. Adjacent memory cells that do not share contact hole 136 share a sub-source line and are coupled to different bit line conductive layers. These conductive layers 137a to 137h are the same wiring layer.

In the case of the arrangement shown in FIG. 55, two conductive layers serving as bit lines are arranged corresponding to the respective memory cell columns, and the conductive layers serving as two bit lines are alternately provided in the contact holes in each column. 136 is electrically connected. This makes it possible to easily connect memory cells sharing a sub-source line to different bit lines for one column of memory cells.

Bit Line Layout 2: FIG. 56 schematically shows a second layout of the divided bit line structure according to the eighth embodiment of the present invention. In FIG. 56, conductive layers 135a to 135h to be word lines are arranged in the row direction, conductive layers 141a to 141f to be first bit lines are arranged corresponding to the memory cell columns, and the first conductive layer 14
Conductive layers 142a to 142f to be second bit lines are arranged above layers 1a to 141f corresponding to the memory cells.

The conductive layers 141a to 141f are electrically connected to the lower active region via the contact hole 140, and the conductive layers 142a to 142f are connected to the lower active region via the contact hole 139. It is electrically connected to the area. The memory cells on both sides of the region (SSL region) in which the sub source line is provided are connected to different bit line conductive layers. With the two-layer structure of the bit lines, two bit lines can be arranged for each memory cell column without increasing the occupied area in a planar layout. Upper conductive layers 142a to 142f
Is in contact with the lower active region in the region of the contact hole 139, so that it is only required that this region not be in contact with the lower conductive layers 141a to 141f. Therefore, two bit lines can be arranged for each memory cell column with sufficient margin. In the case of this two-layer structure, the first conductive layers 141a to 141f are formed in order to form bit lines.
And a step of forming the upper conductive layers 142a to 142f are required. However, for example, when a wiring formed in the same wiring layer as the upper or lower conductive layer is formed in another peripheral circuit portion or the like, the use of such a step allows the number of manufacturing steps to be increased without increasing the number of manufacturing steps. A bit line having a layer structure can be realized.

Layout of Divided Bit Line Structure 3: FIG.
FIG. 14 is a drawing schematically showing a third layout of a divided bit line structure. In the layout shown in FIG. 57, the memory cell array has a plurality of sub-arrays 145a to 145c.
Is divided along the column direction. Subarray 145a-
Each of 145c has a word line and a sub-source line arranged extending in the row direction, but is not shown in FIG. 57 for simplification of the drawing. In the case of a nonvolatile semiconductor memory device such as a NOR type flash memory, many memory cells are connected to one bit line. When this bit line has a two-layer structure as shown in FIG. 56, the electrical characteristics of the bit line may be different. Therefore, the bit line wiring is switched for each memory sub-array. That is, the conductive layers 141 and 142 arranged in the memory sub-array 145a are replaced in the sub-array 140b so that the conductive layer 141 is
The upper word line 1 is connected to the upper conductive layer 142.
Reference numeral 42 connects to the lower conductive layer 141 in the sub-array 145b.

Next, in the sub-array 145c, the lower conductive layer 141 is connected to the upper conductive layer 142.
Upper conductive layer 142 is connected to lower conductive layer 141 in subarray 145c. Therefore, in each bit line (divided bit line), lower conductive layers and upper conductive layers are alternately arranged in sub-array units, and the electrical characteristics (such as wiring resistance and wiring capacitance) of the bit lines in each column are substantially the same. Thus, it is possible to prevent characteristic degradation due to signal propagation delay and the like.

In the structure shown in FIG. 57, the memory array is divided into three memory arrays 145a to 145c.
However, the number of divisions may be four or more. If the memory array is divided into an even number of sub-arrays, the number of upper conductive layers and the number of lower conductive layers can be the same in each divided bit line, and the electrical characteristics can be made the same in each divided bit line. it can.

Note that these sub-arrays 145a to 145c
May be any sub-array sharing a bit line.

Layout of Divided Bit Line 4: FIG.
FIG. 14 is a drawing schematically showing a fourth layout of the divided bit line structure. In FIG. 58, conductive layers 135a to 135f which become word lines and extend in the row direction are arranged. Active regions 150 for forming memory cells are arranged along the column direction. However, active region 150 is arranged to be shifted by one column in the word line direction for every two bit cells in the column direction. An isolation region 15 is provided between these active regions.
3 are arranged. An insulating film is formed in the isolation region 153, and the isolation insulating film may be, for example, a thermal oxide film (an insulating film having a small thickness).

As shown in FIG. 58, by arranging active regions 150 by one column in the row direction for each 2-bit memory cell in the column direction, bit lines can be easily formed using the same wiring layer. (Since the drain contacts are arranged so as to be shifted by one column for every two word lines). Active region 15 for forming this memory cell
By alternately arranging 0s, memory cell columns can be arranged according to the minimum pitch of the wiring. Further, a bit line having a sufficiently large wiring width can be realized.

In the case of the alternate arrangement shown in FIG. 58, distance U between word line / floating gate and the end of isolation region 53 and distance Z between word line / floating gate and the end of the active region are ensured. There is a need. When the distance Z becomes 0, the source region of the memory cell transistor does not exist, and the channel current cannot flow. On the other hand, the distance U between the end of the isolation insulating film and the word line is 0.
In this case, coupling occurs between the source region and the word line / floating gate of the memory cell adjacent in the column direction, and a sufficient electric field cannot be formed between the floating gate and the drain region.
This is because the coupling ratio determined by the ratio between the capacitance between the word line and the floating gate and the capacitance between the drain and the floating gate is degraded, and the desired write / erase characteristics cannot be realized. That's why. Further, when the distance U becomes negative, the channel length becomes short, a short channel effect occurs, and the transistor characteristics deviate from desired values.

In the structure shown in FIG. 58, adjacent active regions in the row direction are continuously connected. Even if the active regions 150 are connected in the sub source line forming region (SSL region), there is no problem as long as the above-described distances U and Z are sufficiently ensured.

FIG. 59 shows an arrangement of the sub-source lines with respect to the arrangement shown in FIG. In FIG. 59, diffusion region 155 serving as a sub-source line is formed of conductive layer 1 serving as a word line.
35b and 135c, 135d and 135e, 13
It is formed by using a self-aligned source (SAS) method, which is formed in a self-aligned manner, using 5f as a mask.
In the arrangement shown in FIG. 59, an isolation insulating film is formed below conductive layers 135a, 135b, 135c, 135d, 135e, and 135f serving as word lines.
Therefore, even if diffusion region 155 serving as the sub-source line is formed in a self-aligned manner, distance U shown in FIG. 58 is sufficiently ensured.

Therefore, as shown in FIG.
Even in the case where the memory cells are shifted by one column and row for each bit memory cell, a diffusion region serving as a source region and a sub-source line can be easily formed.

FIG. 60 is a diagram showing a first example of the bit line arrangement in the arrangement shown in FIG. In FIG. 60, conductive layer 1 serving as a bit line corresponds to each column of the active region.
59a to 159h are arranged. These conductive layers 159
a to 159h are formed in the same wiring layer, and are electrically connected to these active regions via contact holes 157 in regions overlapping with the active regions (not shown in FIG. 60). With this arrangement, the active region serving as a memory cell can be arranged in accordance with the minimum wiring pitch of conductive layers 159a to 159h, and an increase in cell array area can be suppressed.

Conductive layers 135a to 135 serving as word lines
After forming diffusion regions 155 to be source and sub-source lines in a self-aligned manner using these word lines as masks, conductive layers 159a to 159h to be bit lines are formed.
And a contact hole 137 are formed to connect memory cells sharing the sub-source line to different bit lines.

FIG. 61 shows a second example of the bit line arrangement in the arrangement of FIG. In the arrangement shown in FIG. 61, conductive layers 135a to 135f serving as word lines are formed, and then diffusion regions 155 serving as source / sub-source lines are formed.
Are formed, first, conductive layers 162a to 162d to be first bit lines are formed in every other row of the memory cell. Next, the conductive layers 162a to 162a to be these bit lines
A conductive layer 164 to be a second bit line is formed above 162d.
a to 164d are arranged corresponding to the remaining columns of the active region. The conductive layers 162a to 162d are
Via a corresponding active region (not shown in FIG. 61)
The conductive layers 164a to 164d are electrically connected to the corresponding active regions through the contact holes 161 in regions overlapping the active regions.

As shown in FIG. 61, as a divided bit line structure, conductive layers 16 formed on mutually different wiring layers are formed.
By using 2a to 162d and 164a to 164d, the influence of the wiring pitch can be minimized, and the memory cells can be arranged at a small pitch along the row direction.
An increase in the cell array area can be suppressed. In the arrangement shown in FIG.
The wiring pitch is determined by the area required for the region where the wirings 161 and 161 are formed.

In the arrangement shown in FIG. 61, FIG.
As shown in (1), by replacing the conductive layer in the bit line extending direction, the electrical characteristics of the divided bit lines can be made the same. In this case, when contact holes are arranged in a row direction in a portion connecting different conductive layers in one bit line (divided bit line), the contact holes for interconnecting the conductive layers are formed. Depending on the occupied area, the wiring pitch may be widened. However, in this case, by increasing the area of each contact hole in the column direction, it is possible to suppress an increase in the wiring pitch.

As described above, according to the ninth embodiment of the present invention, since the memory cells sharing the sub-source line are connected to different bit lines, the memory cells in the over-low Vth state are in the same column. , The memory cell data can be accurately read without being affected by the memory cell in the over-low Vth state.

[Tenth Embodiment] FIG. 62 schematically shows a whole structure of a nonvolatile semiconductor memory device according to a tenth embodiment of the invention. In FIG. 62, the memory cell array is divided into four sub-array regions # 0 to # 3 along the row direction. These subarray regions # 0
Word lines WL1 to WLn are arranged commonly to # 3.
On the other hand, the sub-source lines are provided for each sub-array region. That is, in sub-array region # 0, sub-source lines SSL01 to SSL01 correspond to word lines WL1 to WLn.
SL0m is arranged, and in sub-array region # 1, sub-source line SSL11 corresponding to word lines WL1 to WLn is provided.
To SSL1m. Similarly, subarray area # 2
And # 3, the sub source lines SSL21 to SSL2m and SSL3 correspond to the word lines WL1 to WLn.
1 to SSL3m are arranged. Sub-source line SSL (SS
L01 to SSL3m) are arranged extending in the row direction only in the corresponding sub-array region, and the sub-source lines between different sub-array regions are separated.

These sub source lines SSL01 to SSL3
m corresponding to each of the source line selection transistors SST
Is arranged. These source line selection transistors SS
T is coupled to main source lines MSL0 to MSL3 provided corresponding to sub array regions # 0 to # 3, respectively. Sense amplifier SA for reading data corresponding to main source lines MSL0 to MSL3
0 to SA3 are arranged. These sense amplifiers SA0
To SA3 respectively correspond to output data bits Q0 to Q3. The sub source lines SSL01 to SSL3m may be provided corresponding to the word lines WL1 to WLn, respectively, or may be configured to be shared by adjacent word lines.

At the time of data reading, only the selected bit line is connected to the ground voltage level, and the remaining unselected bit lines are set to the open state. Only the source line select transistor SST connected to the selected word line is connected to the corresponding main source line. Main source line MSL (MSL0 to MSL)
3) determines whether a current flows through the sense amplifier SA (SA0).
To SA3), when the current flows, it is determined that the selected memory cell is a memory cell in a low threshold voltage state. The sub source line SSL is connected to the word line WL (WL
1 to WLn), data can be read accurately without being affected by unselected memory cells. Even when the sub source line is shared by two adjacent word lines, 1
It is only affected by the leak current of the bit memory cell, and similarly, data can be read accurately.

Since a voltage is merely applied to each bit line (not shown in FIG. 62) at the time of writing and reading, a voltage is applied to this bit line at the time of writing and reading. The circuit portion does not need a large current supply capability, and the transistor size of the circuit portion for applying a voltage to the bit line at the time of writing and reading can be reduced, and accordingly the circuit occupation area can be reduced. it can. In each of the sense amplifiers SA0 to SA3,
When reading data, it is necessary to detect whether a current flows or not, and a relatively large current driving force is required.

FIG. 63 shows a structure of the sub-array region of the nonvolatile semiconductor memory device shown in FIG. 62 in more detail. FIG. 63 shows a configuration of a portion of two sub-array regions #i and #j.

In FIG. 63, sub-array regions #i and #j are further divided into memory blocks for each predetermined number of memory cells along the row direction. In FIG.
The sub-array area #i is a memory block B # i0, B #
, and the sub-array area #j is divided into memory blocks B # j0, B # j1,. Each memory block B # (B # i0 or the like) has, for example, an 8-bit memory along the row direction.

In the arrangement shown in FIG. 63, sub-source lines SL are arranged corresponding to sets of adjacent word lines WL. Sub-source line SL # i included in sub-array region #i
Are arranged extending only in the region within sub-array region #i along the row direction. Similarly, in sub array region #j, sub source line SL # j extends along the row direction only in sub array region #j.

Memory block B {i0, B {i1, B}
Main source lines MLi0, MLi1, MLj0, MLj1 are arranged corresponding to j0 and B♯j1, respectively. These main source lines MLi0, MLi1, MLj
0, MLj1 and sub-source lines SL # i, and source line select transistors SST are arranged corresponding to intersections of SL # j.

Main source lines MLi0, MLi1, MLj
0 and MLj1, at the time of data reading, sense amplifiers SAi0, SAi for detecting whether a current flows in the corresponding main source line and generating a signal indicating the detection result.
1, SAj0 and SAj1,... Sense amplifier SA provided corresponding to sub-array region #i
are commonly connected to readout circuit RAi, and sense amplifiers SAj0 and SAj1 provided for sub-array region #j are commonly connected to readout circuit RAj. Read circuits RAi and RAj collectively correspond to corresponding sense amplifiers SA (SAi0,..., SAj1).
Determines that a memory cell in a low threshold voltage state has been selected when a signal indicating that a current has flowed to a corresponding main source line is selected, and outputs data indicating a low threshold voltage state (eg, logic "1") is output.

Memory block B # (B {i0,..., B})
The bit line group BLG provided corresponding to j1 is generically coupled to a write circuit and a read voltage generating circuit for supplying a ground voltage at the time of read via a column select gate (not shown).

In the arrangement shown in FIG. 63, subarray regions {i and #j are further divided into a plurality of memory blocks B along the row direction for every predetermined number of bits.
When the selected memory cell is in the low threshold voltage state, a current flows through sub source lines SL # (SL # i and SL # j) from main source lines ML (MLi1,..., MLj1), and A current flows to the bit line via the selected memory cell. This is detected by the sense amplifier SA. Normally, a relatively large current flows through the main source line closest to the selected memory cell, and the presence or absence of the current flow is detected by a corresponding sense amplifier.

By dividing each sub-array region #i, #j into a plurality of memory blocks, the distance between the selected memory cell and the main source line is shortened, and sub-source line S
The resistance of L # also decreases accordingly, and the read current can be accurately generated on the main source line without being affected by the wiring resistance.

FIG. 64 shows a whole structure of a nonvolatile semiconductor memory device according to the tenth embodiment of the present invention. In FIG. 64, memory cell array 170 is divided into a plurality of sub-array regions # 0 to #s. These subarray regions # 0 to #s are each divided into a plurality of memory blocks B # 0 to B # k. Memory block B♯0
Main source lines MSL are arranged for each of B # k, and sense amplifiers SA are provided corresponding to these main source lines MSL. A sense amplifier group included in each of sub-array regions # 0- # s is coupled to corresponding read circuits RA0-RAs. Each of read circuits RA0 to RAs may be configured by a logic circuit, or may be configured such that outputs of corresponding sense amplifier groups are wired and transmitted.

For memory cell array 170, a row decoder 172 for selecting a word line corresponding to an addressed row and a row decoder 172 for selecting an addressed column from each of memory sub-array regions # 0- # s. Column decoder 174 for generating a column selection signal, and Y gate circuit 1 for selecting one column from each of sub-array regions # 0- # s according to the column selection signal from column decoder 174
76. A column (bit line or main bit line) selected by Y gate circuit 176 has a read voltage generating circuit 178 for generating a ground voltage at the time of data reading and a write circuit 179 for transmitting external write data at the time of data writing.
Via a bus 177. This writing circuit 179
May simply be provided with a configuration for transmitting write data from the outside onto the selected column and latching the write data in each of the selected columns. Write circuit 179 has a configuration for generating a write voltage. It may be set to an appropriate form according to the configuration of the nonvolatile semiconductor memory device.

FIG. 65 schematically shows a structure at the time of data reading of one row portion of one memory block. In FIG. 65, bit lines BL0 to BLu are coupled to signal line 177a via column selection gates YG0 to YGu which receive column selection signals Y0 to Yu from column decoder 174 shown in FIG. Bit lines BL0
At the intersection of BLu and word line WL, a memory cell MT is arranged, and a sub-source line SSL is arranged commonly to these memory cells MT. The sub source line SSL is coupled to the main source line MSL via the source line select transistor SST.

In data reading, one of Y gates YG0 to YGu is turned on by a column selection signal from column decoder 174 (see FIG. 64). FIG. 65 shows a state where Y gate YG0 is turned on. In this state, the ground voltage from read voltage generation circuit 178 shown in FIG. 64 is transmitted to bit line BL0 provided corresponding to the selected column. Remaining bit line BL1
In ~ BLu, the YG gate is in an off state, and is in a floating state. For example, about 3.
A voltage of 3 V is transmitted, and the source line selection transistor SS
T is turned on, the main source line MSL and the sub source line S
SL is combined. When the selected memory cell MT is in the low threshold voltage state, a current flows from the main source line MSL to the bit line BL0 via the source line select transistor SST, the sub-source line SSL and the memory cell MT. This current flow is detected by the sense amplifier SA. When selected memory cell MT is in the high threshold voltage state, memory cell MT is off, and no current flows through main source line MSL. Since bit lines BL1 to BLu are all in a floating state and the current path is cut off, data can be accurately read from the selected memory cell.

In the structure shown in FIGS. 62 and 63, the sub source line is divided corresponding to each output data bit. However, the sub-source line may be divided in the sub-array region corresponding to one bit. That is, in FIG. 63, sense amplifiers SAi0, SAi1, SAj0, and SAj
One output may be coupled to a common read circuit, and 1-bit data may be read from the common read circuit.

In the above configuration, the configuration of the array portion of the NOR type flash memory is shown as an example. However, the present invention can be similarly applied to the configuration of the DINOR type flash memory.

[Modification] FIG. 66 schematically shows a structure of a modification of the nonvolatile semiconductor memory device according to the tenth embodiment of the present invention. The nonvolatile semiconductor memory device shown in FIG. 66 differs from the nonvolatile semiconductor memory device shown in FIG. 63 in the following points. That is, one sense amplifier SAi and SAj is provided for each of sub-array regions #i and #j. Each of these sense amplifiers SAi and SAj is commonly connected to a main source line of a corresponding sub-array region. That is, the main source line MLi of the sub-array region #i is
0, MLi1,... Are commonly connected. Sense amplifier S
Aj, the main source line ML of sub-array region #j
j0, MLj1,... are commonly connected. One sense amplifier SA (SAi, SAi,
Even when SAj) is provided, when the selected memory cell is in the low threshold voltage state, a current flows through the main source line, so that sufficient detection can be performed. In the case of the configuration shown in FIG. 66, it is only necessary to provide one sense amplifier for each sub-array region, and it is not necessary to provide a sense amplifier for each memory block, and the circuit occupation area can be reduced. .

As described above, the tenth embodiment of the present invention is described.
According to the configuration, data is read according to whether or not a current flows through the main source line.
It is only necessary to transmit a voltage, and it is possible to reduce a current driving force of a circuit portion that applies a read voltage to a bit line at the time of reading, and accordingly, to reduce a transistor size, and thus a circuit size. Can be.

[Embodiment 11] FIGS. 67 (A)-(C)
FIG. 2 is a diagram schematically showing a configuration of a conventional sub-source line connection portion. In FIG. 67A, main source line MSL and sub-source line SSL are directly connected at intersection CP. In the arrangement shown in FIG. 67A, a voltage is transmitted from main source line MSL to sub source line SSL in the memory cell array, and voltage is not selectively transmitted to the sub source line.

FIG. 67B schematically shows a planar layout of intersection CP shown in FIG. 67A. FIG.
In FIG. 7B, at the intersection CP, the active region 200 is formed in the same manner as the memory cell. This is because a memory cell is also arranged near the intersection CP, and its pattern layout is repeated so that its regularity is not lost. The conductive layers 203a and 203a serving as word lines cross the active region 200.
3b is formed. A low-resistance conductive layer 202 made of a low-resistance metal such as polysilicon or aluminum is provided in the same direction as the extending direction of active region 200. This low-resistance conductive layer 202 is connected via a contact hole 206 in a region between conductive layers 203a and 203b to be word lines. In this region, since the contact holes 206 are formed, the distance between the conductive layers 203a and 203b to be word lines is widened.
Active region 200a connected by contact hole 206
Is connected to the diffusion layer 205 extending in the row direction between the conductive layers 203a and 203b. This diffusion layer 205
It functions as the sub source line SSL.

FIG. 67 (C) shows line 6 in FIG. 67 (B).
It is a figure which shows roughly the cross-section along 7A-67A. In FIG. 67C, impurity regions 212a, 200a, and 212b are formed on the surface of semiconductor substrate region 210 with a space therebetween. The active region 200 is a region formed by these impurity regions 212a, 200a, and 212b, and its periphery is surrounded by an isolation insulating film.

On the channel region between impurity regions 212a and 200a, on the same layer as the floating gate,
A conductive layer 211b is formed via a gate insulating film (not shown). A conductive layer 203a to be a word line is further formed on conductive layer 211b with an interlayer insulating film (not shown) interposed.

Over a channel region between impurity regions 200a and 212b, via a gate insulating film (not shown),
A conductive layer 211b is formed in the same layer as the floating gate electrode. On this conductive layer 211b, a conductive layer 203b to be a word line is formed via an interlayer insulating film (not shown). Impurity region 200a is connected to conductive layer 202 via contact hole 206.

As shown in FIG. 67C, at the intersection CP between the main source line MSL and the sub source line SSL,
A structure similar to that of the memory cell is formed. This is simply to maintain the regularity of the pattern repetition. Conventionally, the memory cells formed at the intersections CP are not actively used at all. In the present invention, the cell structure at the intersection CP is positively used.

FIG. 68A shows Embodiment 1 of the present invention.
FIG. 3 is a drawing schematically showing a planar layout of a source line selection transistor according to No. 1. In FIG. 68A, conductive layers 213a and 213b serving as word lines are formed linearly so as to intersect with active region 200. Diffusion layer 205 serving as a sub-source line is formed between conductive layers 213a and 213b. In parallel with the direction in which active region 200 extends, low-resistance conductive layer 202 serving as a main source line
Is provided, and the low-resistance conductive layer 202 is formed of a conductive layer 213.
a and contact hole 2 formed outside of 213b
Electrically connected to active region 200 via 16a and 216b.

The layout shown in FIG. 68A is different from the layout shown in FIG. 67B in that the position of the contact hole is provided not between the conductive layers serving as word lines but outside the conductive layer. The conductive layers 213a and 213
Since there is no need to provide a contact hole between the conductive layers 213b and 213b, the conductive layers 213a and 213b serving as word lines can be formed to extend linearly.

FIG. 68 (B) shows line 6 in FIG. 68 (A).
It is a figure which shows the sectional structure of 8A-68A schematically. FIG.
8B, parts corresponding to those in FIG. 67C are denoted by the same reference numerals, and description thereof will be omitted. Fig. 68
In (B), the low-resistance conductive layer 202 is connected to the impurity regions 212a and 212b via the contact holes 216a and 216b. The impurity region 200a is not connected to the low-resistance conductive layer 202, and is simply shown in FIG.
Is connected only to the diffusion layer 205 shown in FIG.

As shown in FIG. 68B, a floating gate having the same structure as that of a memory cell can be easily formed only by changing the position of a contact hole in a structure in which a main source line and a sub source line are directly connected. A field-effect transistor can be used as a source line selection transistor. In this case, the position of the contact hole is simply changed, and no extra manufacturing process is required.

Configuration 2 of Source Line Select Transistor: A single layer gate type field effect transistor having a single gate electrode layer is used as a source line select transistor instead of a stacked gate type field effect transistor such as a floating gate type field effect transistor. When a transistor is used, the structures of the memory cell and the source line selection transistor are different, and accordingly, the electrical characteristics are different. Therefore, it is necessary to provide an isolation region between the memory cell and the source line selection transistor. This is because steps such as impurity ion implantation need to be performed in another step, and the transistor size is different. Hereinafter, a single-layer gate type MO
A manufacturing method when an S transistor is used as a source line selection transistor will be described.

In FIG. 69A, an active region 230a for forming a memory cell transistor is formed extending in the column direction in a memory cell region, and an active region 230b for forming a source line select transistor is formed.
Are formed extending in the column direction. An isolation region is formed between the memory cell region and the source line selection transistor formation region (SST region) by a relatively wide thermal oxide film 232b. Even between memory cell transistors,
Similarly, a thermal oxide film 232a for element isolation is formed. After the formation of the active regions, in the memory cell region, a conductive layer 230a serving as a floating gate is formed so as to cover each active region. This conductive layer 230a
Is then patterned along the bit line extending direction (column direction).

FIG. 69 (B) is a diagram schematically showing a cross-sectional structure along line 69A-69A shown in FIG. 69 (A). As shown in FIG. 69B, thermal oxide films 232a and 232b are formed on the surface of semiconductor substrate region 235 at intervals. A conductive layer 233 serving as a floating gate is formed on semiconductor substrate region 235 so as to be in contact with these thermal oxide films. Since no floating gate is required in the source line selection transistor formation region, the substrate region (active region) is kept exposed (masked for manufacturing a floating gate).

Next, as shown in FIG. 70A, after an interlayer insulating film such as an ONO film having a multilayer structure of an oxide film / nitride film / oxide film is formed on the entire surface, a resist is formed so as to cover the memory cell region. A film 236 is formed. FIG. 70A does not show an interlayer insulating film formed of an ONO film or the like. The resist film 236 is formed so as to completely cover the conductive layer 230a serving as a floating gate electrode formed on the thermal oxide film 232b formed in the isolation region.

FIG. 70B schematically shows a cross sectional structure taken along line 70A-70A of the planar layout shown in FIG. 70A. As shown in FIG. 70B, a resist film 236 is formed to cover the memory cell region and part of the isolation region. This resist film 236
In the lower portion, the isolation region, and the source line selection transistor formation region, an interlayer insulating film composed of, for example, an ONO film is formed.

Using resist film 236 as a mask, an etching process is performed to remove an interlayer insulating film between a conductive layer serving as a floating gate electrode and a word line formed thereover.

The interlayer insulating film (hereinafter referred to as ONO film) composed of the ONO film is necessary at the portion where the floating gate electrode is formed, but is used for other peripheral circuit portions and section selection in the DINOR type flash memory. It is unnecessary in the transistor section. Therefore, similarly to the etching removal step in the SST region, etching is performed on these peripheral circuit portions and section selection transistor regions. Since the ONO film has a multilayer structure of an oxide film and a nitride film,
The ONO film removal step includes, for example, an oxide film etching step and a nitride film etching step using hydrofluoric acid (HF). Therefore, as shown in FIG. 71, when the ONO film 237 is removed by etching, the surface of the thermal oxide film 232b formed in the isolation region is also partially removed by etching. In this step, the lowermost layer (oxide film) of the ONO film 237 to be removed is also in contact with the peripheral circuit portion and the region to be the channel region of the source line select transistor. Therefore, the ONO film 237
The removal of the lowermost oxide film must not damage the surface of the semiconductor substrate 235, and therefore, an oxide film wet etching method using an etching solution such as hydrofluoric acid is used.

As shown in FIG. 72, the ONO film has a multilayer structure of an oxide film 237a, a nitride film 237b and an oxide film 237c. When the oxide film is etched using an etchant, the nitride film 237b formed on the oxide film 237a, which is the lowermost layer of the ONO film 237, is not removed by etching when the isolation oxide film 232b is removed by etching. The etching rate is extremely low with respect to an etching solution (for example, hydrofluoric acid) used for etching an oxide film. Therefore, as shown in FIG. 72, a lateral hole 239 is formed at the end of isolation oxide film 230b. After the ONO film 237 is removed by etching, as shown in FIG. 73, after forming a gate insulating film in the SST region, the conductive layer 240 serving as a word line is formed.
Is formed and patterned, and then an interlayer insulating film 241 is formed on the conductive layer 240 to be the word line.

When the conductive layer 240 serving as the word line is formed, as shown in FIG. 74A, the conductive layer 240 is deposited on the lateral holes 239 of the thermal oxide film 232b formed in the isolation region. Is done. Here, in FIG.
The symbol β indicates the amount of the conductive layer deposited in the horizontal hole 239. The conductive layer 240 deposited in the lateral hole 239 cannot be removed by simply performing anisotropic etching on the conductive layer 240 because the ONO film 237 serves as a mask. As shown in B), the conductive layer 240 remains in the horizontal hole 239. The conductive layer 240 remaining in the horizontal hole 239 extends in the column direction, and causes a short circuit between word lines. Therefore, the conductive layer 24 remaining in the horizontal hole 239
0 must be removed. Therefore, as shown in FIG. 75, a process of etching an ONO film and an electrode layer serving as a floating gate using a conductive layer patterned as a word line as a mask is used.

As shown in FIG. 73, a conductive layer 240 serving as a word line and an interlayer insulating film 241 thereover are formed.
After patterning, etching of conductive layer 233 serving as a floating gate and ONO film 237 are performed using patterned interlayer insulating film 241 as a mask.

As shown in FIG. 75, in the step of patterning the floating gate and the underlying ONO film, first, a mask 245 is formed so as to cover this select transistor formation region. The end of mask 245 is closer to the end of active region 230b in the source line selection transistor formation region than the end of resist film 236 formed in FIGS. It is formed so as to cover active region 230b. In this state, patterning of the floating gate and ONO
Etching for patterning the film is performed.
At this time, in the source line selection transistor formation region, in the configuration shown in FIG. 71, the ONO film 237 is removed by etching and the substrate surface is exposed, and then a gate insulating film is formed.

The gate insulating film in the source line selection transistor forming region is patterned by using the conductive layer 240 serving as a word line and the electrode layer 233 serving as a floating gate using the interlayer insulating film 241 thereabove as a mask and the ONO film thereabove. 237 may be performed before or after the etching removal step.

By removing the conductive layer 240 (or the upper insulating film 241) serving as the word line by etching in a self-aligned manner, an electrode serving as a floating gate is formed in the memory cell region as shown in FIG. A layer 233 is formed below the conductive layer 240 to be a word line. At this time, the upper ONO film is similarly removed in a self-aligned manner through an oxide film / nitride film / oxide film etching process. At this time, in the separation region, the horizontal hole 2
The region where 39 is formed is etched away in the region between the word lines. Therefore, in this state,
The cross-sectional structure along the line 76A-76A in FIG. 76 is the same as the structure shown in FIG. Here, in FIG. 73, a source line selection transistor formation region (SST region)
Shows a state in which the gate insulating film of the single-layer gate field effect transistor has already been formed.

On the other hand, lines 76B-76B in FIG.
77 has a configuration shown in FIG. 77. Figure 77
As shown in FIG. 5, in the region where the conductive layer serving as the word line is not formed, the ON of the surface of the semiconductor substrate region 235 is
The gate insulating film made of the O film (including the gate insulating film of the source line selection transistor) is all removed by etching. In the step of removing the ONO film by etching and the step of etching the conductive layer 233 to be the floating gate, the region 2 where the lateral hole of the isolation oxide film 232b was formed
39 is exposed in the portion between the word lines,
Similarly, etching is performed in this etching step, and FIG.
As shown in FIG. 7, the region 25 where the horizontal hole 239 was formed is formed.
0 is not covered with the resist 245 and is similarly etched and removed, and as shown in FIG.
Is removed by etching.
The ONO film includes a nitride film, and includes a film having a low etching rate with respect to an etchant such as hydrofluoric acid (HF). In order to form a source line selection transistor and a single-layer gate field effect transistor in the peripheral circuit region, O
After the NO film is removed by etching, this region is turned ON again.
The O film is etched using an etchant such as hydrofluoric acid, and the conductive layer 233 serving as a floating gate is formed.
By performing the etching removal step, the portion of the lateral hole 239 between the conductive layers 240 to be word lines can be removed, and short-circuiting between adjacent word lines due to the conductive layer 240 formed in the lateral hole 239 can be prevented. Is done. However, in this case, as shown in FIG. 77, the isolation oxide film 232b is partially removed by etching (the region where the lateral hole 239 is formed) and the corresponding portion 250 is thinned. In the process, care must be taken so that this recess 250 of the isolation oxide film 232b does not reach the semiconductor substrate region 235.

Here, the two processes of etching the ONO film and the floating gate electrode layer are used. In the lateral hole 239, a nitride film and an oxide film of the ONO film are formed as an upper layer. A conductive layer 240 serving as a word line is deposited thereunder. These oxide / nitride film structures and conductive layer 240
Is to be removed by etching. In the region of the horizontal hole 239 below the conductive layer 240 serving as a word line, the conductive layer 240 remains in the horizontal hole 239.
The conductive layers serving as adjacent word lines are separated from each other,
Has no adverse effect.

Here, the reason why the depression 250 is formed in FIG. 77 is as follows. When the ONO film is removed by etching, a step of sequentially removing the oxide film, the nitride film and the oxide film by etching is performed. At this time, at the time of etching the lowermost oxide film, conductive layer 240 is partially removed by etching (the oxide film and the conductive layer have different etching rates), and the remaining conductive layer 240 remains at the time of etching the conductive layer to be the floating gate again. Since the conductive layer 240 is removed by etching, a depression 250 is formed in the lateral hole forming region. Further, a resist film (mask) 24
In the portion not covered by 5, the surface of the isolation insulating film 232b is etched similarly in the ONO film etching step and the oxide film etching.

In the isolation insulating film 232a, an ONO film is formed on the entire surface thereof to prevent the thickness thereof from being reduced. Further, during the step of etching the conductive layer 240, the etching of the isolation oxide film 232a is performed. The etching rate is lower than that of an etchant for etching the conductive layer 240, and the film thickness is not reduced. As described above, Embodiment 11 of the present invention
According to this, a stacked / single-layer gate type field effect transistor can be manufactured as a source line selection transistor without adding a complicated manufacturing process.

[0326]

As described above, according to the present invention, a source line select transistor is provided corresponding to a word line, and a sub-source line corresponding to a main source line is provided for a memory cell connected to the selected word line. And write / write
In erasing, the word line and bit line voltages are set so that a high writing voltage is not applied to the sub-source line, so that the drain disturb stress on the memory cell during data writing is reduced, and Writing / erasing can be performed without loss of reliability. In the selected column, a maximum of 1-bit overlow Vt is selected.
The memory cell in the h state only affects the selected memory cell, and accurate data reading can be performed.

That is, according to the invention of claim 1,
The sub-source line corresponding to the selected word line is connected to the main source line, and in the operation mode of injecting electrons into the floating gate, channel hot electrons are generated to inject electrons into the floating gate, and to release electrons from the floating gate. At the time of extraction, a Fowler-Nordheim current flows between the floating gate and the channel region, so that a high voltage can be prevented from being applied to the sub-source line. Voltage can be prevented from being applied, and the reliability of the memory cell can be prevented from being impaired.

According to the invention of claim 2, in the operation mode in which electrons are injected into the floating gate, a Fowler-Nordheim current flows between the channel region of the selected memory cell and the corresponding floating gate to cause the floating gate to flow. In the operation mode in which electrons are injected into the floating gate and electrons are extracted from the floating gate, a Fowler-Nordheim current is caused to flow between the floating gate and the bit line of the selected memory cell. On the other hand, it is possible to prevent an excessive voltage from being transmitted, to reduce the drain disturb stress of the non-selected memory cells,
It is possible to prevent the reliability of the memory cell from being lowered and the data from being destroyed.

According to the third aspect of the present invention, since a voltage of a constant voltage level is always applied to the main source line regardless of the operation mode, there is no need to switch the main source line voltage. It is possible to reduce the circuit configuration scale for applying a voltage to the line, and to reduce the circuit occupation area.

According to the invention of claim 4, since the source line selection transistor is constituted by a floating gate type field effect transistor, an extra isolation region for separating the memory cell from the source line selection transistor is added. There is no need to provide them, and the cell array occupation area can be reduced.

According to the fifth aspect of the invention, since the source line selection transistor and the floating gate type field effect transistor having the same writing and erasing characteristics as the memory cell are formed, the same manufacturing process as that of the memory cell is performed. , A source line select transistor can be formed,
An increase in the number of manufacturing steps can be prevented.

According to the invention of claim 6, when all the memory cells in one row are set to the high threshold voltage state at the time of injecting electrons into the floating gate into the selected memory cell, the corresponding source is set. Since the line select transistor is also set to the high threshold voltage state, reading the stored data of the source line select transistor determines whether all the memory cells in the corresponding row are in the high threshold voltage state. Whether or not it can be easily identified.

According to the seventh aspect of the present invention, when electrons are extracted from the floating gate, the source line select transistors on the same row as the selected memory cell also extract electrons from the floating gate. ,
When memory cells in both the written state and the erased state coexist in the corresponding row, data can be read correctly, and electrons are injected into the floating gate of this source line select transistor to increase the threshold voltage. In the value voltage state, it can be easily identified that all the corresponding memory cells are in the high threshold voltage state.

According to the eighth aspect of the present invention, in the main / sub bit line configuration, after charging the main bit line to a predetermined voltage level, one sub bit line of the plurality of sub bit lines corresponding to the main bit line is charged. Since the configuration is such that the main bit line voltage is compared with a predetermined voltage by connecting to the bit line,
It is possible to identify whether or not a memory cell in the over-low Vth state exists on the sub-bit line.

According to the ninth aspect of the present invention, after charging the capacitor to a predetermined voltage level, the capacitor is connected to the bit line to be determined, and the voltage of the bit line to be determined is compared with a reference value. With such a configuration, it is possible to easily identify whether or not the memory cell in the over-low Vth state exists on the bit line to be determined.

According to the tenth aspect of the present invention, since a specific bit line of a plurality of bit lines is used as the capacitance means, it is possible to easily overwrite the bit line without adding an extra circuit configuration. It can be determined whether or not the memory cell in the low Vth state is connected.

According to the eleventh aspect of the present invention, two of the plurality of bit lines are charged to a predetermined voltage level, respectively, and then connected to each other, so that the voltage levels of these voltage bit lines are reduced. Since it is determined whether they are the same or not, it is possible to easily determine whether or not the memory cells in the over-low Vth state are connected to these bit lines.

According to the twelfth aspect, when one of the word lines sharing the sub-source line is selected, the other non-selected word line is supplied with the voltage transmitted to the selected word line and the absolute value. Since a voltage having a small value and a different sign is transmitted, even if a memory cell in the overlow Vth state is connected to this unselected word line, the memory cell in the overlow Vth state is reliably turned off. Data can be accurately read from the selected memory cell.

According to the thirteenth aspect of the present invention, since the sub source lines are provided corresponding to the respective word lines, only the memory cells connected to the selected word line in each column are provided. Connected to the main source line via the sub-source line, the data in the memory cell can be accurately read without being affected by the memory cell in the over-low Vth state.

According to the fourteenth aspect of the present invention, a plurality of bit lines are provided in each column, and memory cells connected to a word line sharing a sub-source line are connected to different bit lines. Therefore, even when memory cells in the over-low Vth state are connected to a common sub-source line, data can be accurately read from a selected memory cell without being affected by the same.

According to the fifteenth aspect of the present invention, two adjacent word lines are provided with a common sub-source line, two bit lines are provided in each column, and the memory is connected to a common sub-source line. Since the cell is configured to be connected to a different bit line, the memory cell in the over-low Vth state is connected to a different bit line from the selected memory cell, and is not affected by the memory cell in the over-low Vth state. Thus, data of the selected memory cell can be accurately read.

According to the sixteenth aspect of the present invention, since the upper wiring layer is used as the sub-source line, the resistance of the sub-source line can be reduced, and a large current can flow. Writing / erasing can be performed stably.
Further, even when the number of source line select transistors is reduced, a source voltage of a predetermined voltage level can be accurately transmitted to each memory cell.

According to the seventeenth aspect of the present invention, since the sheet resistance of this wiring layer is set to 20 Ω / □ or less, the number of source line select transistors can be reduced and the number of source line select transistors can be reduced accurately by lowering the resistance of the sub source line. It is possible to realize a source line selection transistor that drives a large current by increasing the channel width of the line selection transistor.

According to the eighteenth aspect of the present invention, since the plurality of bit lines arranged corresponding to each column of the memory cells are constituted by bit lines of different wiring layers, the area occupied by the cell array is not increased. A plurality of bit lines can be easily arranged corresponding to each memory cell column.

According to the nineteenth aspect of the invention, since the two bit lines arranged in each column are formed of different wiring layers, each of the two bit lines can be easily occupied by the cell array. They can be arranged without increasing the area.

According to the twentieth aspect of the present invention, each bit line divided into a plurality of groups includes wirings formed on different wiring layers, and the bit lines in each column have the same electrical characteristics. And performance degradation such as a reduction in access time can be prevented.

According to the twenty-first aspect of the present invention, the active regions in which the memory cells are formed are displaced so as to be aligned in two columns along the bit line extending direction. In accordance with the above, memory cells can be arranged in two columns, and a configuration can be realized in which each sub-source line is connected to a different bit line from a memory cell sharing the sub-source line without increasing the array occupation area. .

According to the twenty-second aspect of the present invention, in a configuration in which memory cells share a bit line contact, the active region is extended in the word line extending direction for every two memory cells along the bit line extending direction. Since the memory cells are arranged so as to be shifted by one cell, in a configuration in which a common sub-source line is provided for two word lines, a memory cell sharing a sub-source line is connected to different bit lines. Can be realized without increasing the cell array area.

According to the twenty-third aspect of the present invention, data is read from a selected memory cell by detecting the presence or absence of a voltage on a main source line. Is required only to apply a voltage, a large current driving force is not required, and a transistor size of a circuit portion for applying a voltage to a bit line at the time of writing / reading is required. Can be reduced, and the area occupied by the circuit can be reduced accordingly.

According to the twenty-fourth aspect, in the isolation region between the source line selection transistor formation region and the memory cell formation region, wet etching is performed using the first etchant to form an insulating film on the floating gate. Is etched again, and then the region including the boundary region is etched again. Therefore, even when the conductive layer (word line) remains under the insulating film above the floating gate, the adjacent word line can be removed. The remaining film between them can be removed, and a word line short circuit can be prevented.

According to the twenty-fifth aspect, in the active region of the memory cell adjacent in the column direction, after forming the source region, a dopant of the opposite conductivity type to that of the dopant implanted for forming the source region is implanted. Because
A source region between adjacent memory cells can be easily separated, and a sub-source line can be arranged corresponding to each word line.

According to the twenty-sixth aspect of the present invention, since a mask is formed in an isolation region and ion implantation for forming a source region of a memory cell is performed, a complicated process can be easily performed. A sub-source line can be arranged corresponding to each word line.

According to the twenty-seventh aspect, since a thermal oxide film is selectively formed in an isolation region and then ion implantation is performed using the thermal oxide film as a mask, each word line can be formed without complicated steps. A sub source line can be arranged corresponding to each.

According to the twenty-eighth aspect of the present invention, after forming a thermal oxide film over the entire active region of the memory cell adjacent in the column direction, the thermal oxide film is selectively etched and removed to form a region to be an isolation region. Since a thermal oxide film is formed, a separation region having a required size can be easily formed without complicated steps.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of an array unit of a nonvolatile semiconductor memory device according to a first embodiment of the present invention.

FIGS. 2A to 2C are diagrams showing voltage application modes during a write operation of the nonvolatile semiconductor memory device shown in FIG. 1;

FIGS. 3A to 3E are diagrams illustrating a voltage application mode during an erasing operation of the nonvolatile semiconductor memory device illustrated in FIG. 1;

FIGS. 4A to 4D are diagrams showing voltage application modes during data reading of the nonvolatile semiconductor memory device shown in FIG. 1;

FIG. 5 schematically shows an entire configuration of a nonvolatile semiconductor memory device according to the first embodiment of the present invention.

FIG. 6 is a diagram illustrating an example of a configuration of a row decoder illustrated in FIG. 5;

FIG. 7 is a diagram showing a configuration of an array unit of a nonvolatile semiconductor memory device according to a second embodiment of the present invention.

FIGS. 8A to 8D are diagrams showing voltage application modes during a write operation of the nonvolatile semiconductor memory device shown in FIG. 7;

FIGS. 9A to 9D are diagrams illustrating voltage application modes during an erasing operation of the nonvolatile semiconductor memory device illustrated in FIG. 7;

FIGS. 10A to 10D are diagrams illustrating voltage application modes during data reading of the nonvolatile semiconductor memory device illustrated in FIG. 7;

11 is a diagram schematically showing an overall configuration of a nonvolatile semiconductor memory device shown in FIG. 7;

FIG. 12 is a diagram showing a configuration of an array portion of a nonvolatile semiconductor memory device according to a third embodiment of the present invention.

13A to 13D are diagrams illustrating voltage application modes during an erasing operation of the nonvolatile semiconductor memory device illustrated in FIG. 12;

FIGS. 14A to 14D are diagrams illustrating voltage application modes during a write operation of the nonvolatile semiconductor memory device illustrated in FIG. 12;

FIGS. 15A to 15C are diagrams showing voltage application modes during data reading of the nonvolatile semiconductor memory device shown in FIG. 12;

16 is a diagram schematically showing an entire configuration of a nonvolatile semiconductor memory device shown in FIG. 12;

17 is a diagram schematically showing a configuration of a source line voltage setting circuit shown in FIG. 16;

18 is a view showing a list of a relationship between a threshold voltage of a corresponding one row of memory cells and a threshold voltage of a source line selection transistor in the nonvolatile semiconductor memory device shown in FIG. 12;

19 is a diagram schematically showing a configuration of a main part of the source line voltage setting circuit shown in FIG. 16;

FIG. 20 is a diagram showing a configuration of a modification of the third embodiment of the present invention.

FIGS. 21A to 21D are diagrams showing voltage application modes during an erasing operation of the nonvolatile semiconductor memory device shown in FIG. 20;

FIGS. 22A to 22D are diagrams showing voltage application modes in the write mode of the nonvolatile semiconductor memory device shown in FIG. 20;

FIGS. 23A and 23B are diagrams showing voltage application modes during data reading of the nonvolatile semiconductor memory device shown in FIG. 20;

24 is a diagram showing a configuration of a source line selection transistor section of the nonvolatile semiconductor memory device shown in FIG.

FIGS. 25A to 25C are diagrams showing voltage application modes during data reading of the nonvolatile semiconductor memory device shown in FIG. 20;

26 is a diagram schematically showing an entire configuration of the nonvolatile semiconductor memory device shown in FIG. 20;

FIG. 27 is a diagram illustrating an example of a configuration of a source line voltage setting circuit illustrated in FIG. 26;

FIG. 28 schematically shows a structure of an array portion of the nonvolatile semiconductor memory device according to the fourth embodiment of the present invention.

FIG. 29 schematically shows a structure of a main part of a nonvolatile semiconductor memory device according to a fourth embodiment of the present invention.

FIG. 30 illustrates an operation of the nonvolatile semiconductor memory device according to the fourth embodiment of the present invention.

FIG. 31 schematically shows a structure of a modification of the fourth embodiment of the present invention.

FIG. 32 schematically shows a structure of a main part of a nonvolatile semiconductor memory device according to a fifth embodiment of the present invention.

FIG. 33 is a signal waveform diagram representing an operation of the nonvolatile semiconductor memory device shown in FIG. 32.

FIG. 34 is a view illustrating an operation of the nonvolatile semiconductor memory device shown in FIG. 32;

FIGS. 35A and 35B are diagrams for explaining the operation of the nonvolatile semiconductor memory device shown in FIG. 32;

FIG. 36 is a view illustrating an operation of the nonvolatile semiconductor memory device shown in FIG. 32;

FIG. 37 is a drawing illustrating roughly configuration of a column address generation unit of the nonvolatile semiconductor memory device illustrated in FIG. 32;

FIG. 38 is a drawing illustrating roughly configuration of a modification of Embodiment 5 of the present invention;

FIG. 39 schematically shows a structure of still another modification of the nonvolatile semiconductor memory device according to the fifth embodiment of the present invention.

FIG. 40 schematically shows a structure of a main part of a nonvolatile semiconductor memory device according to a sixth embodiment of the present invention.

FIG. 41 is a signal waveform diagram representing an operation of the nonvolatile semiconductor memory device shown in FIG. 40.

FIG. 42 is a drawing illustrating roughly configuration of a modification of Embodiment 6 of the present invention;

FIG. 43 schematically shows a structure of a main part of a nonvolatile semiconductor memory device according to a seventh embodiment of the present invention.

FIG. 44 schematically shows a distribution of threshold voltages of memory cells.

FIG. 45 schematically shows a structure of a main part of a nonvolatile semiconductor memory device according to an eighth embodiment of the present invention.

46 (A)-(C) are views showing the steps of manufacturing the sub-source line shown in FIG. 45.

FIG. 47 is a drawing schematically showing a step in accordance with the second method of manufacturing the sub source line shown in FIG. 45.

48 (A) and (B) are views showing steps of a third method of manufacturing the sub-source line shown in FIG. 45.

FIGS. 49A and 49B are diagrams showing steps of a fourth method of manufacturing the sub source line shown in FIG. 45.

FIGS. 50A and 50B are diagrams showing steps of a fifth method of manufacturing the sub source line shown in FIG. 45;

FIGS. 51A and 51B are diagrams schematically showing a configuration of a sub source line shown in FIG. 45;

FIG. 52 is a view illustrating an effect of the sub source line structure shown in FIG. 51;

FIG. 53 is a view illustrating an advantage of the sub source line shown in FIG. 51;

FIG. 54 shows a structure of a main portion of a nonvolatile semiconductor memory device according to a ninth embodiment of the present invention.

FIG. 55 shows a first layout of the bit lines shown in FIG. 54.

FIG. 56 shows a second layout of the bit lines shown in FIG. 54.

FIG. 57 is a diagram showing a third arrangement of bit lines in the nonvolatile semiconductor memory device shown in FIG. 54.

FIG. 58 schematically shows a memory cell array of the nonvolatile semiconductor memory device shown in FIG. 54.

FIG. 59 shows a sub-source line forming region in the memory cell arrangement shown in FIG. 58;

FIG. 60 schematically shows an arrangement of bit lines with respect to the memory cell arrangement in FIG. 58.

FIG. 61 shows a second bit line arrangement with respect to the memory cell arrangement shown in FIGS. 58 and 59.

FIG. 62 schematically shows a structure of a main part of a nonvolatile semiconductor memory device according to the tenth embodiment of the present invention.

63 is a diagram showing the configuration of a main part of the nonvolatile semiconductor memory device shown in FIG. 62 in more detail;

FIG. 64 is a diagram showing the overall configuration of the nonvolatile semiconductor memory device shown in FIG. 62 in more detail;

65 is a diagram schematically showing a configuration of a main part at the time of data reading of the nonvolatile semiconductor memory device shown in FIG. 64;

FIG. 66 is a diagram showing a configuration of a modification of the tenth embodiment of the present invention.

67 (A)-(C) are diagrams schematically showing a configuration of a portion directly connecting a main source line and a sub source line.

FIGS. 68A and 68B schematically show a structure of a source line select transistor according to an eleventh embodiment of the present invention.

FIGS. 69A and 69B are views showing steps of a method for manufacturing a nonvolatile semiconductor memory device according to Embodiment 11 of the present invention.

FIGS. 70A and 70B are views showing steps of a method for manufacturing a nonvolatile semiconductor memory device according to Embodiment 11 of the present invention.

FIG. 71 is a cross sectional view showing a method for manufacturing a nonvolatile semiconductor memory device according to Embodiment 11 of the present invention.

FIG. 72 is an enlarged view showing a configuration of a boundary portion of the isolation insulating film shown in FIG. 71.

FIG. 73 shows a step of a method for manufacturing a nonvolatile semiconductor memory device according to Embodiment 11 of the present invention.

74 (A) and (B) are diagrams showing a further enlarged configuration of a boundary portion of an isolation insulating film in the step of FIG. 73.

FIG. 75 shows a step of a method for manufacturing a nonvolatile semiconductor memory device according to Embodiment 11 of the present invention.

FIG. 76 shows a step of a method for manufacturing a nonvolatile semiconductor memory device according to Embodiment 11 of the present invention.

FIG. 77 is a drawing illustrating roughly a cross section along a line 76B-76B in FIG. 76;

FIG. 78 is a diagram showing a configuration of a main part of a conventional nonvolatile semiconductor memory device.

FIG. 79 is a view showing another configuration of a conventional nonvolatile semiconductor memory device.

80 is a diagram illustrating a voltage application mode during writing of the nonvolatile semiconductor memory device illustrated in FIG. 79;

FIG. 81 is a view schematically showing a configuration of a main part of a conventional nonvolatile semiconductor memory device.

[Explanation of symbols]

1, 1a-1f bit line, 2a-2h word line, 3
Main source lines, 4a to 4e Source line selection transistors, 5a to 5d Sub source lines, 21a to 21d main bit lines, 22aa to 22ad, 22ba to 22bd, 22c
a to 22cd, 22da to 22dd sub bit line, 23
aa to 23ad, 23ba to 23bd, 23ca to 23
cd, 23da to 23dd section selection transistor, 44a to 44h source line selection transistor, 43
Main source line, 53 Main source line, 54a to 54f Source line selection transistor, BL bit line, WLa, W
Lb word line, MSL main source line, SSL sub source line, SST source line selection transistor, SBL1
SBLn sub-bit line, MBL1 to MBLn main bit line, C1 to Cm capacitive element, IG1u to IGmu, IG
11 to IGml isolation gate transistor, 80a, 8
1a memory cell array, 80b, 81b Y gate circuit, 83 test circuit, TG1 to TGm test column selection gate, 90 test voltage generation circuit, 91 comparison circuit, 9
5a, 96a Memory cell array, 95c, 96c Test gate circuit, 100a to 100d Row decode circuit, 102a to 102d Word line negative voltage drive circuit, S
SLDa to SSLDd divided sub-source lines, 111 isolation regions, 113 thermal oxide films, 119 source / sub-source line regions, 120 gate electrode structures, 121 and 122 masks, 123 active regions between memory cells, 128 thermal oxide films, 129 masks, 130 conductive layer, WL0-WL5
Word line, SST0 to SST5 Source line selection transistor, SSL0 to SSL2 Sub source line, BL00 to BL00
BL31 bit line, 137a to 137h conductive layer to be a bit line, 135a to 135h conductive layer to be a word line, 141a to 141f conductive layer to be a first bit line, 142a to 142f conductive layer to be a second bit line, 152 floating gate electrode layer, 150 active regions, 153 isolation regions, 159a to 159h conductive layers to be bit lines, 162a to 162d, 164a to 1
64d conductive layer serving as bit line, SA0-SA3 sense amplifier, SSL01-SSL3m sub-source line, MS
L0 to MSL3 main source line, $ 0 to $ 3 subarray area, B $ i0, B $ i1, B $ j0, B $ j1 memory block, SAi0, SAi1, SAj0, SAj1
Sense amplifier, B # 0-B @ k memory block, SA
i, SAj sense amplifier, 200 active area, 202
Signal line, 216a, 216b Contact hole, 233
Floating gate electrode conductive layer, 232a isolation insulating film, 232b isolation oxide film, 230a, 230b active region, 236 resist film, 237 ONO film, 23
9 lateral holes, 240 conductive layers serving as word lines, 241 interlayer insulating film, 245 resist film.

──────────────────────────────────────────────────続 き Continued on front page (51) Int.Cl. ⁶ Identification code FI H01L 29/792

Claims (28)

[Claims] 1. A plurality of memory cells each comprising a floating transistor arranged in rows and columns, each having first and second conduction nodes and a control electrode node. A plurality of word lines connected to control electrode nodes of memory cells in a corresponding row, a plurality of bit lines arranged corresponding to the columns, each connected to a first conduction node of a memory cell in a corresponding column, A plurality of transistors provided in the row for selectively conducting in response to a signal voltage on a word line arranged in the corresponding row, and transmitting a reference voltage to a second conduction node of a memory cell in the corresponding row when conducting; Generated in the channel region between the first and second conduction nodes of the selected memory cell in the operation mode of injecting electrons into the select transistor and the floating gate of the memory cell In the operation mode in which electrons are injected into the floating gate of the selected memory cell and electrons are extracted from the floating gate, the selected memory cell is set so that a Fowler-Nordheim current flows between the floating gate and the channel region of the selected memory cell. A non-volatile semiconductor storage device, comprising: means for setting the voltage of the word line and the bit line to be connected. 2. A plurality of memory cells arranged in rows and columns, each including a floating gate transistor having first and second conduction nodes and a control electrode node, and arranged corresponding to each row. A plurality of word lines each connected to a control electrode node of a memory cell of a corresponding row; a plurality of bit lines arranged corresponding to the column and connected to a first conduction node of a memory cell of a corresponding column. Provided in each of the rows, selectively conducting in response to a signal voltage on a word line arranged in the corresponding row, and transmitting a reference voltage to a second conduction node of a memory cell in the corresponding row when conducting. In the operation mode of injecting electrons into the floating gates of the plurality of select transistors and the memory cell, the memory cell corresponds to the channel region between the first and second conductive nodes of the selected memory cell A Fowler-Nordheim current flows between the floating gate and the first conduction node between the floating gate and the first conduction node in an operation for extracting electrons from the floating gate.
A nonvolatile semiconductor memory device comprising: means for selectively setting voltages of a word line and a bit line connected to a selected memory cell so that a Nordheim tunneling current flows. 3. The reference voltage according to claim 1, wherein the reference voltage is a voltage maintained at a constant voltage level regardless of an operation mode.
Or the nonvolatile semiconductor memory device according to 2. 4. The nonvolatile semiconductor memory device according to claim 1, wherein each of said select transistors is constituted by a floating gate type field effect transistor. 5. The nonvolatile semiconductor memory device according to claim 4, wherein each of said select transistors has the same write and erase characteristics as said memory cell. 6. In an operation mode in which electrons are injected into the floating gate, in a select transistor arranged in the same row as the selected memory cell, all the memory cells in the same row have electrons injected into the floating gate. 5. The nonvolatile semiconductor memory device according to claim 4, further comprising means for setting the level of said reference voltage so that electrons are injected into said floating gate. 7. In the operation mode for extracting electrons from the floating gate, the level of the reference voltage is set such that electrons are extracted from the floating gate of a select transistor arranged on the same row as the selected memory cell. 5. The nonvolatile semiconductor memory device according to claim 4, further comprising: means. 8. Each of the bit lines includes a plurality of sub-bit lines each connected to a first conduction note of a plurality of memory cells,
Means for charging the main bit line to a predetermined voltage level, and means for charging the main bit line to a predetermined voltage level, wherein the main bit line is charged to a predetermined voltage level of the main bit line. 3. The nonvolatile semiconductor memory device according to claim 1, further comprising: means for connecting a selected one of the plurality of sub-bit lines to a selected one of the sub-bit lines, and comparing a voltage on the main bit line with the predetermined voltage. 9. A capacitance means having substantially the same capacitance value as a bit line to be measured included in the plurality of bit lines, a means for charging the capacitance means to a predetermined voltage level, 3. The nonvolatile semiconductor memory device according to claim 1, further comprising: means for connecting to a determination bit line and comparing a voltage of said bit line to be determined with a reference value. 10. The nonvolatile semiconductor memory device according to claim 9, wherein said capacitance means is a specific bit line included in said plurality of bit lines. 11. A means for coupling selected two bit lines of the plurality of bit lines to a capacitance means charged to a predetermined voltage level respectively, and after coupling the two bit lines to the capacitance means. , Said 2
3. The nonvolatile semiconductor memory device according to claim 1, further comprising: means for determining whether or not the voltages of the bit lines are at the same level. 12. Each of the memory cells of a predetermined number of rows is provided in common, and a reference voltage from a selection transistor provided in the corresponding predetermined number of rows is used as a second voltage of the memory cells of the corresponding predetermined number of rows. A plurality of reference voltage transmission lines for transmitting to the conduction node; and in a data read mode, a voltage of an unselected word line of the predetermined number of rows in a predetermined number of rows including a selected word line in absolute value. 3. The nonvolatile semiconductor memory device according to claim 1, further comprising: means for setting a voltage level lower than a voltage transmitted to a selected bit line and having a polarity different from that of a voltage on said selected word line. 13. A plurality of word lines provided corresponding to each of the plurality of word lines and separately from each other, each transmitting a reference voltage from a selection transistor in a corresponding row to a second conduction node of a memory cell in the corresponding row. 3. The nonvolatile semiconductor memory device according to claim 1, further comprising: a reference voltage transmission line. 14. The memory cells of each column are divided into a plurality of groups, and the plurality of bit lines are arranged corresponding to a plurality of groups in each column, and the memory cells of the corresponding groups are respectively connected. A plurality of bit lines,
3. The nonvolatile semiconductor memory device according to claim 1, wherein said plurality of groups are grouped such that memory cells in adjacent rows belong to different groups. 15. A plurality of reference voltages arranged corresponding to each of two adjacent sets of rows, each transmitting a reference voltage from a selection transistor of the corresponding set of rows to corresponding two adjacent rows of memory cells. 3. The semiconductor device according to claim 1, further comprising a transmission line, wherein the plurality of bit lines are arranged two in each column, and memory cells in a row sharing the same column reference voltage transmission line are connected to different bit lines. 14. The nonvolatile semiconductor memory device according to claim 1. 16. The memory cells are formed corresponding to the rows, each for transmitting a reference voltage from a select transistor in the corresponding row to a second conduction node of a memory cell in the corresponding row. 3. The nonvolatile semiconductor memory device according to claim 1, further comprising a conductive wiring layer formed above the substrate. 17. The wiring layer has a sheet resistance of 20Ω /.
□ The nonvolatile semiconductor memory device according to claim 16, wherein 18. The nonvolatile semiconductor memory device according to claim 14, wherein the bit lines arranged corresponding to each of said plurality of groups in the same column include conductive wires formed in different wiring layers. 19. The semiconductor device according to claim 15, wherein the two bit lines in the same column include wirings formed in different wiring layers.
14. The nonvolatile semiconductor memory device according to claim 1. 20. Each of bit lines arranged corresponding to each of the plurality of groups includes a conductive wiring formed on a different wiring layer, and bit line portions adjacent in the row direction are formed on different wiring layers. 15. The nonvolatile semiconductor memory device according to claim 14, comprising a formed wiring. 21. An active region in which a memory cell is formed,
16. The non-volatile semiconductor memory device according to claim 14, wherein the non-volatile semiconductor memory device is arranged so as to be shifted in two rows along the bit line extending direction. 22. Two adjacent pixels in the bit line extending direction
One memory cell shares a contact hole for making an electrical connection to a bit line, and an active region in which a memory cell is formed has a word line extending for every two memory cells along the bit line extending direction. 22. The non-volatile semiconductor storage device according to claim 21, wherein the non-volatile semiconductor storage device is arranged so as to be shifted by one cell in the direction. 23. A semiconductor device further comprising: a main reference voltage line for transmitting the reference voltage to each of the selection transistors; and a sense unit for reading data by detecting a current flowing through the main reference voltage line in a data read operation mode. The nonvolatile semiconductor memory device according to claim 1, further comprising: 24. A floating gate arranged in rows and columns, each having a control electrode and a floating gate, and an insulating film having a low etching rate with respect to a first etchant formed between the control electrode and the floating gate. A plurality of non-volatile memory cells comprising field-effect transistors, a plurality of word lines arranged corresponding to each row, and a plurality of word lines respectively connected to the memory cells of the corresponding row, each arranged in each of the rows, A selection transistor that conducts according to the voltage of the word line in the corresponding row and transmits a reference voltage to the memory cells in the corresponding row when conducting, the method comprising the steps of: In the boundary region between the region for forming the memory cell and the region for forming the memory cell, the wet etching is performed using the first etchant. A second step of forming the word line after the first step, and a step of forming the select transistor after the second step. A third step of masking the region and etching the region including the region etched in the first step to remove at least the insulating film by etching. Method. 25. A plurality of nonvolatile memory cells arranged in rows and columns, each of which is composed of a floating gate type field effect transistor, and arranged in correspondence with each row, and connected to each of the memory cells in the corresponding row. A plurality of word lines, a plurality of selection transistors arranged in each row, each conducting in response to a signal voltage of a word line in a corresponding row, and transmitting a reference voltage at the time of conduction; And a plurality of reference voltage transmission lines each transmitting a reference voltage from a corresponding transistor to a memory cell connected to the corresponding word line. Each of the plurality of memory cells is
A first conduction node, a second conduction node connected to a corresponding reference voltage transmission line, and a first conductivity type dopant implanted into a second conduction node formation region of a memory cell adjacent in the column direction And a first step of forming the second conduction node and the reference voltage transmission line; and, after the first step, selectively adding a second conductivity type dopant to a region between the second conduction nodes. Implanting and canceling the implanted first conductivity type dopant to form a second conduction node isolation region. 26. A plurality of nonvolatile memory cells arranged in rows and columns, each of which is composed of a floating gate type field effect transistor, and a plurality of words arranged in each row and connected to memory cells of a corresponding row, respectively. And a plurality of selection transistors arranged in each row, each conducting in response to a signal voltage of a word line in the corresponding row, and transmitting a reference voltage at the time of conduction, and provided for each word line, A plurality of reference voltage transmission lines each transmitting a reference voltage from a corresponding select transistor to a memory cell connected to the corresponding word line, wherein each of the memory cells is , A first conduction node and a second conduction node connected to a corresponding reference voltage transmission line, and are arranged between the second conduction node forming regions of memory cells adjacent in the column direction. Mask the isolation region comprises forming a second conduction node and the reference voltage transmission line by performing high-concentration ion implantation method of manufacturing a nonvolatile semiconductor memory device. 27. A plurality of nonvolatile memory cells arranged in rows and columns, each including a floating gate type field effect transistor, and a plurality of nonvolatile memory cells arranged corresponding to each row, each of which is connected to a memory cell in a corresponding row. Word line and
A plurality of selection transistors arranged in each row, each conducting in response to a signal voltage of a word line in the corresponding row and transmitting a reference voltage when conducting, and a plurality of selection transistors arranged in each row, each corresponding to a corresponding selection transistor And a plurality of reference voltage transmission lines for transmitting a reference voltage from memory cell to a corresponding row of memory cells, wherein each of the memory cells has a first conduction node and a corresponding reference voltage. A second conductive node connected to a transmission line, and a step of selectively forming a thermal oxide film in an isolation region between the second conductive node formation regions of the memory cells adjacent in the extending direction of the column; Forming the second conduction node and a corresponding reference voltage transmission line by performing ion implantation using the thermal oxide film as a mask. 28. The step of selectively forming a thermal oxide film, comprising: forming a first thermal oxide film over an entire region between second conductive node formation regions of memory cells adjacent in a column direction; 28. The method for manufacturing a nonvolatile semiconductor memory device according to claim 27, further comprising: exposing the second conductive node and the reference voltage transmission line forming region by etching and removing the first thermal oxide film except for the isolation region. .