JP3692664B2 - Nonvolatile semiconductor memory device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an electrically rewritable nonvolatile memory, for example, a nonvolatile semiconductor memory device such as a flash EEPROM.
[0002]
[Prior art]
Currently, many methods have been proposed for nonvolatile memories such as flash EEPROMs. Among them, bit lines and source lines in a memory cell array are hierarchized, and drains and source diffusion layers of memory cells are separated into element isolation regions. In some cases, the cell area per bit is reduced by embedding under the structure, and the structure is suitable for high integration. FIG. 6 is a cross-sectional view showing the configuration of such a memory cell.
[0003]
In FIG. 6, 1 is a p-well or p-substrate, 2 is, for example, silicon oxide (SiO 2₂) 3 is a floating gate, 4 is an interlayer insulating film, 5 is a control gate (control gate), 6 is a source diffusion layer, 7 is a drain diffusion layer, 8 is a channel region, 9 is a sidewall, Reference numeral 10 denotes element isolation (LOCOS). Arrows a and b indicate the direction of electron transition during erasing and writing, respectively.
[0004]
In the memory cell shown in FIG. 6, the state in which electrons are injected into the floating gate 3 of the memory cell and the threshold voltage is high is the erased state, and the state in which electrons are emitted from the floating gate 3 and the threshold voltage is low is the written state. To do.
In the erase operation, a positive voltage is applied to the control gate 5 to set the drain diffusion layer 7, the source diffusion layer 6, and the substrate 1 to 0 V, thereby injecting electrons from the channel region 8 of the memory cell to the floating gate 3.
In the write operation, a positive voltage is applied to the drain diffusion layer 7 of the selected memory cell, a negative voltage is applied to the control gate, and a voltage of 0 V is applied to the substrate to bring the source diffusion layer 6 into a floating state. Electrons are extracted into the drain diffusion layer 7.
[0005]
FIG. 7 shows an example of a memory cell array configured by using a plurality of memory cells shown in FIG. 6 and arranging them in a matrix.
The memory cell array shown in FIG. 7 is an AND type memory cell array composed of m × n memory cells connected in parallel to m word lines, n main bit lines, sub bit lines, and sub source lines. .
[0006]
In the memory cell array shown in FIG. 7, the bit line and the source line are hierarchized into a main wiring and a sub wiring, and a selection transistor is arranged between the main wiring and the sub wiring, respectively, between the sub source line and the sub bit line. The memory cell transistors are arranged in parallel and have a so-called contactless NOR type memory cell array structure.
[0007]
In the memory array of FIG. 7, WL1, WL2,..., WLm are word lines, SD1, SS1 are select gate lines, BL1, BL2,..., BLn are main bit lines, S-DBL is a sub bit line, and SBL is a common source. Line, S-SBL is sub-source line, M₁₁, M₁₂, ..., M_1n, M_{twenty one}, M_{twenty two}, ..., M_2n, M_m1, M_m2, ..., M_mnIs a memory cell transistor, ST1₁ , ST1₂ , ..., ST1_n, ST2₁, ST2₂, ..., ST2_nIndicates selection transistors.
[0008]
FIG. 8 is a diagram showing bias conditions at the time of erasing, writing, and reading of the AND type flash memory as shown in FIG.
In the memory cell array shown in FIG. 7, each memory cell is connected to a sub-bit line S-DBL and a sub-source line S-SBL, and the sub-bit line S-DBL and the sub-source line S-SBL are selected in units of a plurality of bits. The transistors are connected to the main bit lines BL1, BL2,..., BLn and the common source line SBL through transistors.
[0009]
Erasing is performed in units of word lines, and is performed in units of word lines by setting the selected word line to a positive voltage (for example, 12V) and the non-selected word lines to 0V. For writing, a negative voltage (for example, −7 V) is applied to the selected word line, and data writing is performed (“0” state)._CCFor example, a voltage of 3.3 V and a voltage of 0 V are applied to the bit lines where writing is not performed (“1” state) and the selected word lines are collectively performed. A read operation is also performed in batches in units of word lines by selecting word lines. For example, the power supply voltage V is applied to the selected word line._CCFor example, a voltage of 3.3 V and a voltage of 0 V are applied to the non-selected word lines, and data is determined by the conduction and non-conduction of the memory cells.
As shown in FIG. 8, in the erase, write, and read operations described above, the common source line SBL and the substrate are both held at the ground potential (0 V).
[0010]
Since the AND type memory cell array shown in FIG. 7 has a structure in which bit lines and source lines are hierarchized, no voltage is applied when other blocks are selected, and erroneous writing and erroneous erasure (disturb). It has a structure that is difficult to occur. Further, the sub-bit line S-DBL and the sub-source line S-SBL are formed under the element isolation region 10 as shown in FIG. 6, and one bit contact is required for a plurality of memory cells. Since it has a contactless cell structure, the area occupied by one bit is small, and there is an advantage that the structure is suitable for high integration.
[0011]
[Problems to be solved by the invention]
By the way, in the conventional nonvolatile semiconductor memory device described above, since writing is performed by extracting electrons to the diffusion layer, there are some problems. One is that the drain diffusion layer and the gate electrode need to overlap in order to secure the extraction region. There is no problem when the gate length is long, but when the gate length is about 0.35 μm or less, the overlap length becomes equal to the gate length, so that the transistor cannot be formed and miniaturization is reduced. become unable. Second, current consumption increases because interband current flows from the drain to the substrate in the electron extraction region of the drain diffusion layer during writing. This current consumption is particularly problematic when the voltage applied to the drain diffusion layer at the time of writing is generated internally by the booster circuit in view of the current supply capability. Third, the interband current causes hot holes to be generated in the overlap portion between the drain diffusion layer and the gate, and the holes are trapped in the oxide film, thereby causing deterioration of the oxide film.
[0012]
The above three problems become more severe as the memory device is highly integrated and the power supply voltage is lowered. Therefore, as a future memory system, a new cell system that can solve these problems has been proposed. It was requested.
As a memory device that solves these problems, a new operation method based on erase, write, and read bias conditions shown in FIG. 9 has been proposed. In this new method, a memory cell array is constituted by the memory cells shown in FIG. The configuration of the memory cell array is the same as that of the AND type flash memory cell array shown in FIG. 7, and the above problem is solved by devising the operation method.
[0013]
As one example of operation, the write operation is performed by applying a positive voltage, for example, 22V, to the control gate 5 and injecting electrons from the channel to the floating gate 3, and erasing is performed by applying a negative voltage to the control gate 5. For example, a positive voltage is applied to the substrate 1 by applying a voltage of −18 V, and electrons are extracted from the floating gate 3 to the substrate 1.
[0014]
In FIG. 10, an arrow c indicates an electron transition direction at the time of erasing, and an arrow d indicates an electron transition direction at the time of writing. As shown in the figure, erasing and writing are performed by the transition of electrons between the floating gate 3 and the channel region 8, so that the diffusion layer and the gate do not need to be overlapped, and the memory cell can be miniaturized.
In this method, the level relationship of the threshold voltage of the memory cell by writing and erasing is reversed from the bias state shown in FIG. That is, in this method, the threshold voltage of the memory cell is set to a low level, for example, the power supply voltage V_CCThe threshold voltage of the memory cell is set to a high level by writing, for example, the power supply voltage V_CCSet above level.
[0015]
In this example, the erase operation is performed in units of word lines or memory blocks. When batch erasing is performed in units of memory blocks, as shown in FIG. 9, a negative voltage, for example, a voltage of −18 V is applied to all the word lines WL1, WL2,. This is done by applying a voltage of 0V. In this case, electrons are extracted from the floating gate 3 to the channel region 8.
In the write operation, a positive voltage, for example, 22V is applied to the selected word line, a positive voltage, for example, 11V, is applied to the non-selected word line, and 0V is applied to the main bit line to which the write memory cell is connected. For example, a voltage of 11 V is applied to the main bit line to which the voltage and non-write memory cells are connected, similarly to the non-selected word line. In this case, electrons are injected from the channel into the floating gate 3 in the write memory cell.
[0016]
As described above, in the erasing operation, electrons are extracted into the channel region, so that there is essentially no need to overlap the diffusion layer and the gate, and no interband current is generated. One problem is solved, and a memory cell system suitable for miniaturization and low voltage can be obtained.
However, this method has a problem in that erroneous writing and erroneous erasure of unselected memory cells are likely to occur, and it is difficult to perform a design that satisfies the guarantee of reliability.
[0017]
The present invention has been made in view of such circumstances, and an object of the present invention is to provide a nonvolatile semiconductor memory device capable of improving reliability by preventing erroneous erasure and erroneous writing of memory cells. .
[0018]
[Means for Solving the Problems]
  In order to achieve the above object, according to the present invention, both the bit line and the source line are hierarchized into a main wiring and a sub wiring, and a selection transistor is arranged between the main wiring and the sub wiring, respectively. Are connected in accordance with the operation, and memory cells having a control gate connected to the charge storage layer and the word line are connected in parallel between the sub-source line and the sub-bit line, and a plurality of the bit lines are provided. The semiconductor non-volatile memory device, in which data is written for each word line, applies a positive first voltage to the selected word line during writing, and is intermediate between the first voltage and the ground potential to the unselected word line. Is applied to the bit line for write data, the power supply voltage is applied to the bit line for non-write data, and the selection transistor connected to the bit line is selected. A memory cell in which a power supply voltage is applied to a gate line and data is written in a memory cell in which data is written by injecting charges from the entire surface of the channel into the charge storage layer by Fowler-Nordheim tunneling. The potential of the memory cell is raised to a potential determined by the potential division of the series capacitance between the control gate and the substrate of these memory cells, and data is erased from the charge storage layer to the entire channel surface by Fowler-Nordheim tunneling. At the time of erasing, a positive third voltage is applied to the substrate, and a fourth voltage is applied to all the word lines of the selected memory block.As negative voltage or ground potential voltageIs applied to hold the selection transistor connecting the main wiring and the sub wiring in a non-conductive state.
[0021]
According to the present invention, writing is performed for each word line by injecting charges from the entire surface of the channel into the charge storage layer by Fowler-Nordheim (hereinafter referred to as FN) tunneling. A first voltage, for example, a positive high voltage, is applied to the non-selected word line, and a second voltage that does not cause the memory cell to conduct, for example, 0 V or a voltage close thereto is applied. Further, at the time of writing, the potential of the diffusion layer of the memory cell to which writing is not performed is increased by capacitive coupling between the control gate and the substrate of these memory cells.
[0022]
Erasing is performed by extracting charges from the charge storage layer to the entire surface of the channel by FN tunneling. At the time of erasing, a third voltage, for example, a positive high voltage is applied to the substrate, and a fourth voltage is applied to the word line. For example, a negative voltage or a voltage of 0 V is applied, and the selection transistor that connects the main wiring and the sub wiring is held in a non-conductive state.
[0023]
Accordingly, erroneous writing to unselected memory cells can be prevented during writing, and erroneous erasing can be prevented when erasing is performed for each selected word line, thereby improving the reliability of the memory device.
[0024]
DETAILED DESCRIPTION OF THE INVENTION
First embodiment
FIG. 1 is a circuit diagram showing a first embodiment of a nonvolatile semiconductor memory device according to the present invention.
1, WL1, WL2,..., WLm are word lines, SD1, SS1 are select gate lines, BL1, BL2,..., BLn are main bit lines, S-DBL is a sub bit line, SBL is a common source line, S -SBL is sub-source line, M₁₁, M₁₂, ..., M_1n, M_{twenty one}, M_{twenty two}, ..., M_2n, M_m1, M_m2, ..., M_mnIs a memory cell transistor, ST1₁ , ST1₂ , ..., ST1_n, ST2₁, ST2₂, ..., ST2_nIndicates selection transistors.
[0025]
The configuration of the memory cell array shown in FIG. 1 is the same as that of the AND flash memory array shown in FIG. That is, both the bit line and the source line are hierarchized into a main wiring and a sub wiring, a selection transistor is arranged between the main wiring and the sub wiring, respectively, and memory cell transistors are arranged in parallel between the sub source line and the sub bit line. It has a so-called contactless NOR type memory array structure.
However, as shown in FIG. 2, the bias condition for each wiring at the time of erasing, writing, and reading is different from the bias condition of the conventional AND type memory array shown in FIGS.
In the following, the bias conditions and operations for each wiring at the time of erasing, writing, and reading of the flash memory according to the present invention will be described in order with reference to the drawings.
[0026]
The structure of each memory cell transistor that constitutes the memory cell array shown in FIG. 1 is the same as that of the memory cell transistor shown in FIG. The bias conditions for the wiring are set differently.
[0027]
The erase operation of the memory cell array shown in FIG. 1 can be performed on selected memory blocks at once or for each selected word line.
Specifically, when performing batch erase of a memory block, as shown in FIG. 2, a positive voltage, for example, a voltage of 15 V is applied to the substrate of the selected memory block, and the word line and bit line of the memory block are applied. The voltage of 0 V is applied to each wiring of the common source line. When erasing is performed for each word line, a positive voltage, for example, a voltage of 15 V is applied to the substrate, a voltage of, for example, 0 V is applied to the selected word line, and the unselected word line is approximately the same as the substrate voltage. A positive voltage of, for example, 12V is applied.
[0028]
Under such a bias condition, in each memory cell on the selected memory block or selected word line, electrons are extracted from the floating gate to the substrate by FN tunneling, and the threshold voltage of the memory cell is low, for example, the power supply Voltage V_CCHeld at the following levels:
At the time of erasing, the drain and source diffusion layers of each memory cell transistor are set in a floating state by setting the selection gate lines SD1 and SS1 to 0V.
[0029]
Writing is performed in the bias state shown in FIG. Here, in the memory cell array shown in FIG. 1, the memory cell M on the word line WL2_{twenty one}, M_{twenty two}, ..., M_2nIs written. As a result of writing, the memory cell M_{twenty two}The threshold voltage of the power supply voltage V_CCThe memory cell M is set to the above level._{twenty two}Is set to a so-called write state. Further, other memory cells M connected to the same word line WL2_{twenty one}, M_{twenty three}, ..., M_2nIn the unwritten state, that is, the threshold voltage is the power supply voltage V_CCHold in the following state.
In the following, the memory cell M to be written is written._{twenty two}Are connected to the main bit line BL2, and the other bit lines BL1, BL3,..., BLn are referred to as non-write data bit lines.
[0030]
FIG. 1 shows the bias state of each wiring during such writing. As shown in the figure, a positive voltage, for example, a voltage of 12V is applied to the word line WL2 for writing, and a voltage of 0V is applied to the other word lines WL1, WL3,. And a voltage of 10V are applied to the bit lines BL1, BL3,. Further, a memory block is selected by applying a voltage of 12V to the selection gate line SD1 as in the case of the selection word line WL2. Further, by applying a voltage of 0 V to the selection gate line SS1, the source diffusion layer of each memory cell in the selected memory block is set in a floating state.
[0031]
In such a bias state, first, a high voltage of 12V is applied to the selected word line WL2, a voltage of 0V is applied to the bit line BL2 for write data, and a voltage of 0V is applied to the selection gate line SS1. Write memory cell M_{twenty two}In FIG. 5, since the control gate is held at 12V, the drain diffusion layer is held at 0V, and the source diffusion layer is set in a floating state, electrons are injected from the channel region into the floating gate by FN tunneling.
[0032]
On the other hand, the non-selected cell M on the bit line BL2 for write data₁₂, M₃₂, ..., M_m2In this case, since a voltage of 0 V is applied to the control gate, a channel is not formed, the potential difference between the floating gate and the substrate is maintained at 0 V, and no erroneous writing occurs essentially.
[0033]
In addition, as an applied voltage to the unselected word lines WL1, WL3,..., WLm, 0V or a low voltage that does not cause the unselected memory cells to become conductive is applied, and the bit lines BL1, BL3,. Since almost the same voltage as BLn, for example, 10V, is applied to BLn, the non-write memory cell M on the selected word line WL2 is applied._{twenty one}, M_{twenty three}, ..., M_2nCan be almost completely prevented.
[0034]
Here, in the non-selected word lines WL1, WL3,..., WLm, the memory cell M on the bit line of the non-write data.₁₁, M₁₃, ..., M_1n, M₃₁, M₃₃, ..., M_3n, M_m1, M_m3, ..., M_mnIn, a high voltage of, for example, 10 V is applied only to the drain diffusion layer. In this embodiment, the tunnel current to the diffusion layer is reduced by setting the overlap between the drain diffusion layer and the gate electrode small. Can be prevented.
[0035]
Reading is the same as in the prior art, and the power supply voltage V is applied to the selected word line WL._CCFor example, a voltage of 3.3 V is applied, a voltage of 2 V, for example, is applied to the selected bit line, and a power supply voltage V, for example, is applied to the selection gate lines SD1, SS1._CCIs applied, and a voltage of 0 V is applied to all other wirings.
As a result, the memory cell at the intersection of the selected word line and the selected bit line is selected, and the power supply voltage V is applied to its control gate._CCTherefore, the stored data is discriminated based on the conduction / non-conduction state of the selected memory cell.
[0036]
In the above description, as the voltage to be applied to the bit line of non-write data, a voltage substantially equal to the voltage to be applied to the selected word line is applied. Diffusive layer breakdown voltage setting tends to be strict. In such a case, the voltage applied to the non-write data bit line can be freely reduced within a range in which erroneous writing can be prevented.
[0037]
As described above, according to the present embodiment, in the AND memory cell array, erasing is performed in a block at a time, a positive high voltage (18 V) is applied to the substrate of the selected memory block, and the substrate is removed from the floating gate by FN tunneling. Electrons are extracted and written to each word line, the positive voltage (12V) is applied to the selected word line, the voltage is 0V to the non-selected word line, the voltage is 0V to the write data bit line, and the non-write data is to the bit line. Since a positive voltage (10 V) is applied, electrons are injected from the channel region to the floating gate by FN tunneling in the write memory cell, and in the non-write memory cell on the selected word line and the memory cell on the non-selected word line, Incorrect writing can be prevented.
[0038]
Second embodiment
FIG. 3 is a circuit diagram showing a second embodiment of the nonvolatile semiconductor memory device according to the present invention.
The circuit diagram shown in FIG. 3 is the same as the circuit diagram of the first embodiment shown in FIG. 1. Here, the same constituent elements or the same wirings as those in FIG. To do. Further, since the circuit configuration is the same as that of FIG. 1, detailed description thereof is omitted here. The structure of the memory cell in this embodiment is the same as the structure of the memory cell transistor shown in FIG.
[0039]
In this embodiment, except for the write operation, the erase and read operations are the same as in the first embodiment. Here, with reference to FIGS. 3 and 4, focusing on the write operation different from the first embodiment. While explaining.
[0040]
FIG. 4 is a diagram showing a bias state at the time of erasing, writing and reading in the present embodiment. As shown in the figure, in this embodiment, the erase and read operations are performed in the same bias state as in the first embodiment shown in FIG.
[0041]
The write operation in this embodiment is performed for each word line. FIG. 3 shows a bias state of each wiring at the time of writing.
Here, the memory cell M on the word line WL2 with the word line WL2 as the selected word line._{twenty one}, M_{twenty two}, ..., M_2nOn the other hand, an operation of performing writing will be described.
As shown in the figure, at the time of writing, a positive voltage, for example, a voltage of 12V is applied to the selected word line WL2, and half of the bias voltage applied to the selected word line to the unselected word lines WL1, WL3,. A voltage, for example a voltage of 6V, is applied.
[0042]
Here, for example, by writing, the memory cell M on the selected word line WL2_{twenty one}, M_{twenty two}, ..., M_2nMemory cell M_{twenty two}Write state, that is, the threshold voltage is the power supply voltage V_CCOther memory cells M are set to the above high level._{twenty one}, M_{twenty three}, ..., M_2nIs in an unwritten state, that is, the threshold voltage is the power supply voltage V_CCSet to keep the following low level.
[0043]
Accordingly, of the bit lines BL1, BL2,..., BLn, the bit line BL2 becomes a write data bit line, and the bit lines BL1, BL3,.
As shown in FIG. 3, a voltage of 0 V is applied to the write data bit line BL2, and the power supply voltage V1 is applied to the non-write data bit lines BL1, BL3,._CCFor example, a voltage of 3.3 V is applied.
[0044]
Further, the power supply voltage V is applied to the selection gate line SD1._CCIs applied, and a voltage of 0 V is applied to the selection gate SS1. Thereby, the selection transistor ST2₁, ST2₂, ..., ST2_nAre set in a non-conductive state, and the source diffusion layer of each memory cell is in a floating gate state.
[0045]
As described above, in this embodiment, a high voltage of about 12 V is applied to the selected word line WL2 as in the first embodiment, but the selected word line WL1, WL3,. A voltage approximately in the middle of the voltage applied to the line, for example, about 6V is applied.
[0046]
On the other hand, the potential of the write data bit line BL2 is 0V, but the non-write data bit lines BL1, BL3,..., BLn are different from the write of the first embodiment shown in FIG. Power supply voltage V_CCIs applied.
[0047]
When such a bias voltage is applied to the memory cell array, a voltage of 0 V is applied as it is to the sub-bit line and sub-source line of the write data bit line BL2, but the non-write data bit lines BL1, BL3, .., BLn, the sub-bit lines and sub-source lines are raised to potentials determined by potential division of the series capacitance between the control gate and the substrate, as shown by the equivalent circuit of the memory cell in FIG.
[0048]
As shown in FIG. 5, in the memory cell, the parasitic capacitance C between the control gate and the floating gate, between the floating gate and the channel, and between the channel and the substrate, respectively._int, C_tunAnd C_chaExists. The capacitance values of these parasitic capacitances are determined by the size of the memory cell.
[0049]
That is, the potentials of the sub-bit line and the sub-source line are determined by various parameters such as the size of the memory cell and are not uniquely determined. However, as shown in FIG. When the potential of the selected word line is 6V, the potential of the sub bit line and the sub source line is about 5V.
[0050]
As described above, the potentials of the source and drain diffusion layers of the memory cells connected to the bit lines BL1, BL3,..., BLn for non-write data are divided by the potential division of the serial parasitic capacitance between the control gate and the substrate in the memory cells. Lifting to a potential approximately in the middle of the voltage applied to the control gate is called self-boost.
[0051]
Due to the above-described self-boost, the memory cell M for non-write data on the same word line WL2_{twenty one}, M_{twenty three}, ..., M_2nThe potential difference between the floating gate and the substrate becomes about 7 V, and erroneous writing is prevented.
On the other hand, the non-selected cell M on the bit line of the write data₁₂, M₃₂, ..., M_m2Since the drain diffusion layer is maintained at 0V and the potential difference between the floating gate and the substrate is 6V, erroneous writing is prevented.
[0052]
Note that erasing and reading in the present embodiment are the same as those in the first embodiment, and a description thereof will be omitted.
In the second embodiment, erroneous writing of unselected memory cells is likely to occur compared to the first embodiment. However, the advantage is that a high voltage is not required for the potential of the bit line, and the power supply voltage V_CCThis is possible by setting the level. When application of a high voltage is required as in the first embodiment, a large charge / discharge current is required to collectively write memory cells (about 512 bits) on the same word line. It takes time to write. However, in this embodiment, the power supply voltage V_CCIf charging and discharging are possible, both current consumption and writing time can be saved.
[0053]
In the above writing method, about 6 V is applied as the voltage applied to the non-selected word line so that the diffusion layer potential of the sub-bit line and the sub-source line is increased efficiently. If it is possible to set the potential sufficiently high only with a high voltage, the potential of the non-selected word line can be set to 0 V as in the first embodiment.
[0054]
As described above, according to the present embodiment, in the AND memory cell array, erasing is performed in a block at a time, a positive high voltage (18 V) is applied to the substrate of the selected memory block, and the substrate is removed from the floating gate by FN tunneling. Electrons are extracted and writing is performed for each word line. A positive voltage (12 V) is applied to the selected word line, an intermediate voltage (6 V) is applied to the non-selected word line, a voltage of 0 V is applied to the bit line of the write data, and the non-write data Power supply voltage V_CC(3.3 V) is applied, and the potential of the source and drain diffusion layers of the memory cell on the bit line of the non-write data is set to about 5 V by self-boost, so that the write memory cell floats from the channel region by FN tunneling. Electrons are injected into the gate, and erroneous writing can be prevented in the unwritten memory cell on the selected word line and the memory cell on the unselected word line.
[0055]
【The invention's effect】
As described above, according to the nonvolatile semiconductor memory device of the present invention, there is an advantage that it is possible to realize a memory device that can prevent erroneous writing and erroneous erasure of unselected memory cells and can improve reliability.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing a first embodiment of a nonvolatile semiconductor memory device according to the present invention.
FIG. 2 is a diagram illustrating a bias state at the time of erasing, writing, and reading in the first embodiment.
FIG. 3 is a circuit diagram showing a second embodiment of a nonvolatile semiconductor memory device according to the present invention.
FIG. 4 is a diagram illustrating a bias state at the time of erasing, writing, and reading in the second embodiment.
FIG. 5 is an equivalent circuit of a memory cell.
FIG. 6 is a cross-sectional view showing an example of a conventional nonvolatile memory cell.
FIG. 7 is a circuit diagram showing a configuration example of a general AND type memory cell array.
FIG. 8 is a diagram illustrating an example of a bias state at the time of erasing, writing, and reading in a conventional nonvolatile memory.
FIG. 9 is a diagram showing another example of a bias state at the time of erasing, writing and reading in a conventional nonvolatile memory.
FIG. 10 is a cross-sectional view showing an example of a conventional nonvolatile memory cell.
[Explanation of symbols]
WL1, WL2,..., WLm, word line, SD1, SS1, selection gate line, BL1, BL2,..., BLn, main bit line, S-DBL, sub bit line, SBL, common source line, S-SBL, sub. Source line, M₁₁, M₁₂, ..., M_1n, M_{twenty one}, M_{twenty two}, ..., M_2n, M_m1, M_m2, ..., M_mn... Memory cell transistor, ST1₁ , ST1₂ , ..., ST1_n, ST2₁, ST2₂, ..., ST2_n... select transistor, 1 ... p well or ... p substrate, 2 ... gate insulating film, 3 ... floating gate, 4 ... interlayer insulating film, 5 ... control gate, 6 ... source diffusion layer, 7 ... drain diffusion layer, 8 ... channel Region, 9 ... sidewall, 10 ... element isolation, V_CC... power supply voltage, GND ... ground potential.

Claims (2)

Both bit lines and source lines are hierarchized into main wiring and sub wiring, and select transistors are arranged between the main wiring and sub wiring, respectively, and the main wiring and sub wiring are selectively connected according to the operation. In addition, a memory cell having a charge storage layer and a control gate connected to a word line are connected in parallel between the sub-source line and the sub-bit line, a plurality of the bit lines are provided, and data writing is performed for each word line A non-volatile storage device,
At the time of writing, a positive first voltage is applied to the selected word line, a second voltage that is an intermediate voltage between the first voltage and the ground potential is applied to the non-selected word line, and the write data bit line is grounded. In a memory cell to which writing is applied, a potential voltage is applied, a power supply voltage is applied to the bit line of non-write data, a power supply voltage is applied to the selection gate line of the selection transistor connected to the bit line, and Fowler Nordheim By tunneling, data is written by injecting charges from the entire surface of the channel into the charge storage layer, and the potential of the diffusion layer of the memory cells to which data is not written is set to the potential of the series capacitance between the control gate and the substrate of these memory cells. Let the potential be determined by the division,
Data is erased by extracting charges from the charge storage layer to the entire channel surface by Fowler-Nordheim tunneling,
At the time of erasing, a positive third voltage is applied to the substrate, a negative voltage as the fourth voltage or a ground potential voltage is applied to all word lines of the selected memory block, and the main wiring and the sub wiring are connected. A non-volatile semiconductor memory device that holds a selection transistor in a non-conductive state The erasing is performed for each selected word line by applying the fourth voltage to a selected word line and applying a positive voltage equivalent to a voltage applied to the substrate to an unselected word line during the erasing. 1. The nonvolatile semiconductor memory device according to 1.

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