JP2815077B2 - Method of using semiconductor nonvolatile memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of using a semiconductor nonvolatile memory device, and more particularly, to an improvement in operation reliability thereof.

[0002]

^2. Description of the Related Art At present, a flash type E ² PROM (hereinafter referred to as a flash memory) is known as a rewritable nonvolatile memory. FIG. 5 shows the flash memory 1
1 shows a flash memory cell 50 which is a cell. In the flash memory cell 50, an n ⁺ -type drain 3 and an n ^{+ -type} source 4 are provided in a p-type silicon well 2 provided in a substrate. Silicon oxide film 10 on p-type silicon well 2
8 are provided. Further, a floating gate 112 made of a conductor, a silicon oxide film 113, and a control gate electrode 114 are sequentially provided on the silicon oxide film 108. Further, the silicon oxide film 108 sandwiched between the substrate 116 and the floating gate 112 is formed in a thin film (about 10 nm in thickness).

[0005] Writing and erasing of information in the flash memory cell 50 will be described. When writing information “1”, a high voltage of about 12 V is applied to the control gate electrode 114, a voltage of about 7 V is applied to the drain 3, and a ground potential is applied to the source 4. Hot electrons generated near the drain 3 jump over the potential barrier of the silicon oxide film 108 and flow into the control gate and the floating gate 112.

The threshold value of the control gate voltage necessary for forming a channel in the channel formation region 116 is increased by the electrons thus introduced. That is,
Threshold value V of flash memory cell 50 in current state
th1 is Vthh shown in FIG. 6A. This state is a state where the information “1” is written in the flash memory cell 50 (hereinafter, referred to as a write state).

On the other hand, the information “
To store (erase) 0 ″, the electrons that have flowed into the floating gate 112 may be returned to the source 4. Between the floating gate 112 and the source 4,
A voltage of about 12 V in a direction opposite to the direction at the time of writing information is applied. As a result, an electric field is generated in a direction opposite to that in writing,
Electrons are returned to the source 4 by FN (Fowler-Nordheim) tunneling. As a result of the electron being pulled back in this manner, the threshold value of the control gate voltage required for forming a channel in the channel formation region 116 decreases. That is, the current threshold value Vth1 of the flash memory cell 50 becomes VthL shown in FIG. This state
This is a state where information “0” is stored in the flash memory cell 50 (hereinafter referred to as a non-write state).

As shown in FIG. 1A, the threshold value Vth1 of the flash memory cell 50 is the threshold voltage Vthh in the write state and the threshold voltage VthL in the non-write state.

Next, the operation of reading information from the flash memory cell 50 will be described. First, a sense voltage Vs is applied to the control gate electrode 114. The sense voltage Vs is a voltage intermediate between the threshold voltage Vthh in the write state and the threshold voltage VthL in the non-write state, as shown in FIG.

When the flash memory cell 50 is in the write state, the sense voltage Vs is lower than the threshold voltage Vthh of the flash memory cell 50 as shown in FIG. No channel is formed. Therefore, even when the potential of the drain 3 is higher than the potential of the source 4, no current flows between the drain 3 and the source 4.

On the other hand, the flash memory cell 50
Is in a non-writing state, the sense voltage Vsh is set higher than the threshold voltage Vthh of the flash memory cell 50 as shown in FIG.
Is higher, a channel is formed in the channel formation region 116. Therefore, by making the potential of the drain 3 higher than the potential of the source 4, a current flows between the drain 3 and the source 4.

As described above, in the flash memory cell 50, at the time of reading, the control gate electrode 1
By applying a sense voltage Vs, which is a voltage between the threshold voltages of the write state and the non-write state to 14, it is detected whether or not a channel is formed in the channel formation region 116. It is determined whether the state is a write state or a non-write state.

When erasing information stored in the flash memory cell 50, as described above,
Floating gate 112 by FN tunneling
From the source 4 by drawing electrons back to the source 4. Therefore, if the erasing time is not accurately controlled, the threshold voltage Vth1 of the flash memory cell 50 may become VthLL of 0 V or less as shown in FIG. In such a state, the flash memory cell 50 operates as a depression type transistor. When such excessive erasing occurs, a problem of erroneous reading occurs when the flash memory cells 50 are arranged in a matrix, as described below.

FIG. 7A shows an equivalent circuit of a flash memory 60 in which flash memory cells 50 are arranged in a matrix.
Shown in Reading from the flash memory 60 is performed as follows. When the flash memory cell C11 is selected, the sense voltage 5 is applied to the word line WL1n.
V, 0 V is applied to the source line SL, and the cell C to be read is
2 V is applied to the bit line BLn connected to 11 and a sense amplifier is connected to the bit line BLn.

When the flash memory cell C11 is in the write state, no channel is formed in the channel forming region 116 as described above, and no current flows between the drain 3 and the source 4. On the other hand, in the non-write state, a channel is formed in the channel formation region 116, a current flows between the drain 3 and the source 4, and this may be read by a sense amplifier connected to the bit line BLn.

Here, when the flash memory cell C13 has been over-erased, the flash memory cell C13 is in a state as shown in FIG. In this case the threshold voltage
Vth1 is VthLL of 0 V or less. Therefore,
Even though 0 V is applied to the control gate electrode 5, a channel is formed in the channel formation region 116, a current flows between the source 4 and the drain 3, and erroneous information is read.

Further, even if the erasing time is accurately controlled, excessive erasing may occur for the following reasons.

FIG. 8A shows a matrix circuit 15 in which a plurality of flash memory cells 50 are combined. When the flash memory cells 50 are combined in a matrix as shown in FIG. 2A, word lines WL1n and WL2n connecting the respective control gate electrodes 114 in the row direction and the column direction.
..., Bit lines BLn and B connecting drain 3
Ln + 1..., Source lines SL connecting all the sources 4 are provided. Thus, since all the sources 4 are connected, when erasing, the cells to which the sources 4 are connected are collectively erased.

Here, due to the variation in the coupling ratio caused by the film thickness and dimension of each flash memory cell 50 or the misalignment, and the variation in the silicon oxide film 108 serving as a tunnel oxide film, the F−
The amount of N current changes. Therefore, the threshold voltage Vth1 at the time of erasing will vary. That is, when the threshold voltage of a certain cell becomes the threshold voltage VthL shown in FIG. 6A, the current threshold voltage Vth1 of another cell indicates a value higher than the threshold voltage VthL. Become.

As described above, since the erasing speed is different for each cell, in order to erase all cells,
It is necessary to perform the erasing operation until the threshold voltage value of the cell having a low erasing speed becomes equal to the threshold voltage VthL.
As a result, the threshold voltage of a cell having a fast erase speed may be lower than the threshold voltage VthL (excessive erase).

In order to prevent such erroneous reading due to occurrence of over-erased cells, the following method has been proposed. A first method is to provide an erase control circuit in a semiconductor device. In this method, first, writing is performed on all bits in order to equalize the threshold voltage before erasing. Next,
A relatively short erase pulse in a range where excessive erasure does not occur even in the cell with the fastest erasure is applied, and verification is performed at the start address. This operation is repeated until the start address is verified OK. As described above, erasing is performed for each cell little by little while monitoring the threshold voltage. The second method is to prevent variations in erase speed by suppressing variations in tunnel current in cells. Variations in the erasing speed in the erasing operation are caused by unevenness between the floating gate 112 and the substrate. The unevenness is increased as the concentration of phosphorus in the floating gate 112 increases. Therefore, by reducing the concentration of phosphorus in the floating gate 112, the variation in tunnel current in the cell is suppressed.

The third method is a method in which the threshold voltage of the cell is converged to a certain value by injecting hot carriers into the cell after normal erasing. More specifically, once erased, a certain voltage is applied to the control gate electrode 5 and the drain 3 for a certain period of time. As a result, if over-erased, electrons will be
2 and if the erase is insufficient, holes flow into the floating gate 112. This allows the threshold voltage Vth1 of each cell to converge to a certain value.

[0021]

However, the above-described method for preventing over-erasing and erroneous reading has the following problems.

In the first method, the peripheral circuit becomes complicated,
The area occupied by the semiconductor device also increases, and the cost increases.

The second method has no effect on the variation of the coupling ratio caused by the deviation of the film thickness and the dimensional alignment of each cell.

In the third method, since hot holes need to be injected, the silicon oxide film 108 which is a tunnel oxide film is used.
Degradation occurs. Further, after erasing, a current flows through the cell for a certain period of time to generate hot electrons, so that power consumption increases.

An object of the present invention is to solve the above-mentioned problems and to provide a method of using a semiconductor non-volatile memory device capable of preventing reading of erroneous information even if there is an over-erased cell. .

[0026]

According to a first aspect of the present invention, there is provided a method of using a semiconductor nonvolatile memory device, wherein a control electrode line to which a memory cell which is not desired to be read is connected is provided with a memory cell which has been overerased. The method is characterized in that a read inhibit voltage that does not exceed a threshold voltage is applied.

In the method of using the semiconductor nonvolatile memory device according to the second aspect, the read inhibit voltage is a voltage having an absolute value larger than the threshold voltage of the overerased memory cell and is reverse to that at the time of writing. And a voltage having a polarity of

According to a third aspect of the present invention, in the method of using the semiconductor non-volatile memory device, the read inhibit voltage is a voltage at which no tunnel current is generated.

[0029]

In the method of using a semiconductor nonvolatile memory device according to the first aspect, a read inhibit voltage is applied to a control electrode line to which a memory cell not desired to be read is connected. Therefore, even if a memory cell that is not desired to be read is over-erased, current can be prevented from leaking from the memory cell.

In the method of using the semiconductor nonvolatile memory device according to the second aspect, the control electrode line to which the memory cell that is not desired to be read is connected is higher than the threshold voltage of the overerased memory cell. A voltage having an absolute value and having a polarity opposite to that at the time of writing is applied. Therefore, even if a memory cell that is not desired to be read is excessively erased and the threshold voltage is a voltage having a polarity opposite to that at the time of writing, current can be prevented from leaking from the memory cell.

In the method of using the semiconductor nonvolatile memory device according to the third aspect, a voltage that does not generate a tunnel current is further applied to the control electrode line to which a memory cell that is not desired to be read is connected. Therefore,
Even if a memory cell that is not desired to be read is in a written state, erroneous erasure can be prevented.

[0032]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to FIG. 1, a read operation of a flash memory 41 according to an embodiment of the present invention will be described. FIG. 1 is an equivalent circuit of a flash memory 41 in which a plurality of flash memory cells 50 are combined in a matrix circuit.

The structure of the flash memory cell 50 is the same as that of the prior art, and a description thereof will be omitted. In this embodiment, the source 4, the drain 3, the silicon oxide film 108,
Floating gate 112, silicon oxide film 113,
The control gate electrode 114 forms a first region, a second region, a first insulating film, a floating electrode, a second insulating film, and a control electrode, respectively. In addition, word lines WL1 to WL
4, bit lines BL1 and BL2, source line SL
Constitute a control electrode line, a second region line, and a first region line, respectively.

The word lines WL1 to WL4 connect the control gate electrodes 114 for the respective flash memory cells 50 arranged on the same row. Bit line B
L1 and BL2 connect the drain 3 for each flash memory cell 50 arranged in the same column. The source line SL connects the sources 4 for all the flash memory cells 50 arranged in the matrix.

Next, the read operation of the flash memory 41 will be described. When the cell C12 is a cell desired to be read (selected cell), the word line WL2
5 V as a sense voltage and 2 V to the bit line BL1 and a sense amplifier are connected. Further, the read inhibit voltage is applied to the word lines WL1, WL3, WL4.
2V is applied and the bit line BL2 is opened.

In this embodiment, the read inhibit voltage is a voltage having an absolute value larger than the threshold voltage of the overerased memory cell and a voltage having a polarity opposite to that of the write operation, ie, -2 V However, any voltage may be used as long as it does not exceed the threshold voltage of the over-erased memory cell. Here, the voltage that does not exceed the threshold voltage of the over-erased memory cell refers to the β1 part shown in FIG. 6A. The case shown in FIG. 4A is a case where the threshold voltage VthLL when over-erased is a negative voltage, but the threshold voltage VthL when over-erased.
When L is a positive voltage, the read prohibition voltage is a portion β2 as shown in FIG.

The method of reading the selected cell C12 is the same as the conventional one. That is, when the cell C12 is in the write state, no channel is formed in the channel formation region 116, and no current flows between the drain 3 and the source 4. On the other hand, in the non-writing state, the channel formation region 116
And a current flows between the drain 3 and the source 4, and this can be read by a sense amplifier connected to the bit line BL1. On the other hand, when looking at the cell (unselected cell) C11 not desiring to read, since −2 V is applied to the word line WL1 as a read prohibition voltage, as shown in FIG.
14 is applied with a read inhibit voltage of -2V. Here, if the cell C11 is excessively erased, the threshold voltage Vth1 becomes VthLL of 0 V or less (see FIG. 6A). However, since -2 V is applied to the control gate electrode 114, the channel formation region 116 of the cell C11 is
And no current flows between the source 4 and the drain 3.

The other unselected cells C13, C14, C21,
The same applies to C23 and C24. The unselected cell C22 is not erroneously read because the bit line BL2 is open.

As described above, by applying the read inhibit voltage as a voltage having a polarity opposite to the voltage at the time of writing to the bit line to which the unselected cell is connected, it is assumed that there is an overerased cell. Also, it is possible to prevent erroneous information from being read.

Further, by employing such a reading method, erroneous information can be obtained even when the threshold voltage when the selected cell stores information "0" (at the time of erasing) is lowered as a whole. It will not be read. Therefore, the difference (memory window) between the threshold voltage at the time of writing and the time of erasing can be increased, and a larger current can flow. That is, the speed of the read operation can be improved.

The memory window will be specifically described. FIG. 3A shows a distribution state of threshold values of a general flash memory. In this case, memory window α
Is about 3V. However, by adopting the reading method in the present embodiment, the threshold voltage at the time of erasing can be reduced as a whole as shown in FIG. That is, in this case, the memory window α is about 4V.

As described above, by increasing the memory window α, even if the same voltage is applied to the source line, the difference from the sense voltage applied to the control gate electrode 114 can be increased, and a larger current can flow. it can. Thereby, the read operation speed is improved. Furthermore, since the tolerance of the sense voltage is increased, it is possible to reliably read even if the sense voltage slightly changes.

In particular, the variation of the threshold voltage at the time of erasing is about 3 V in the chip, and the variation is even greater in the semiconductor memory device as a whole.

[Other Embodiments] By employing a voltage that does not generate a tunnel current as a read voltage, a more reliable read can be performed.
The voltage at which no tunnel current occurs will be described below.

The voltage at which the tunnel current is generated means that an electric field is generated between the silicon oxide film 108 and the substrate 2 in a direction opposite to that during writing, and the cell in the written state is FN.
The voltage at which electrons are pulled back to the source 4 by tunneling. That is, the voltage at which no tunnel current occurs is
A voltage at which such FN tunneling does not occur.

FIG. 4A is a principle diagram showing the structure of the flash memory 50, and FIG. 4B is an equivalent circuit diagram thereof. A capacitance is generated between the control gate electrode 114, the floating gate 112, the drain 3, the source 4, and the substrate 2. The equivalent circuit in this state is shown in FIG. In this case, the capacitance between control gate electrode 114 and floating gate 112 is capacitance C1, the capacitance between floating gate 112 and source 4 is capacitance C2, and the capacitance between floating gate 112 and P well 2 is capacitance C1.
3, if the capacitance between the floating gate 112 and the drain 3 is a capacitance C4, the potential of the floating gate 112 is Vfg, the potential of the drain 3 is V1, and the potential of the control gate electrode 114 is V2, V1, V2, Vf
g, and the capacitances C1, C2, C3, C4 have the following relationship.

(V1−Vfg) · C4 = Vfg · (C2 + C3) + (Vfg−V2) · C1 (1) From equation (1), Vfg is given by the following equation.

Vfg = (V 2 · C 1 + V 1 · C 4) / (C 1 + C 2 + C 3 + C 4) (2) On the other hand, if the thickness of the silicon oxide film 108 is Tox, the electric field E applied to the silicon oxide film 108 Is represented by the following equation.

E = Vfg / Tox (3) From the equations (2) and (3), the electric field E is given by: E = (V2 · C1 + V1 · C4) / {(C1 + C2 + C3 + C4) · Tox} (4)

From equation (4), V2 = [{(C1 + C2 + C3 + C4) .Tox.E} -V1.C4] / C1 (5)

In general, when the electric field strength exceeds 5 MV / cm, FN tunneling occurs. Therefore, the voltage V2 may be determined so that the electric field E does not become such an electric field.

For example, the capacitances C1 and C1 + C2 + C3 + C
4 is 6:10 and the thickness of the silicon oxide film 108 is 1
0 nm, the electric field E at which the electric field intensity becomes 5 MV / cm or more
Is about 8.3 V, and the read inhibit voltage is -8.3.
What is necessary is just to set it as a negative voltage smaller than 3V.

As described above, by adopting a voltage that does not generate a tunnel current as the read inhibition voltage,
Erroneous erasure can be prevented.

As described above, the variation in the coupling ratio caused by the deviation of the film thickness and the dimensional alignment constituting each flash memory cell 50 and the variation in the quality of the silicon oxide film 108 as the tunnel oxide film cause Even if excessive erasure occurs when the cells 50 are arranged in a matrix, erroneous reading can be prevented by the reading method in each of the above embodiments.

[0055]

According to the method of using the semiconductor nonvolatile memory device according to the first aspect, the read inhibition voltage is applied to the control electrode line to which the memory cell which is not desired to be read is connected. Therefore, even if a memory cell that is not desired to be read is over-erased, current can be prevented from leaking from the memory cell. For this reason,
Even if there is an over-erased cell, reading of erroneous information can be prevented.

In the method of using the semiconductor nonvolatile memory device according to the second aspect, the control electrode line to which the memory cell that is not desired to be read is connected is higher than the threshold voltage of the overerased memory cell. A voltage having an absolute value and having a polarity opposite to that at the time of writing is applied. Therefore, even if a memory cell that is not desired to be read is excessively erased and the threshold voltage is a voltage having a polarity opposite to that at the time of writing, current can be prevented from leaking from the memory cell. For this reason, even if there is an over-erased cell, reading of erroneous information can be prevented.

In the method for using the semiconductor nonvolatile memory device according to the third aspect, a voltage that does not generate a tunnel current is further applied to the control electrode line to which the memory cell that is not desired to be read is connected. Therefore,
Even if a memory cell that is not desired to be read is in a written state, erroneous erasure can be prevented. Therefore, a more reliable information reading method can be provided.

[Brief description of the drawings]

FIG. 1 is a diagram showing an equivalent circuit of a flash memory 41.

FIG. 2 shows a flash memory cell 50 that has been over-erased.

FIG. 3 is a diagram showing a distribution of a threshold voltage of the flash memory cell 50;

FIG. 4 is a diagram showing the relationship between the capacitance of the flash memory cell 50 and the applied voltage.

FIG. 5 is a diagram showing a structure of a flash memory cell 50;

FIG. 6 shows a threshold voltage Vthh of the flash memory cell 50 at the time of writing, a threshold voltage VthL of the non-writing state, and a sense voltage.
FIG. 7 is a diagram showing Vs and a threshold voltage VthLL at the time of excessive erasing.

FIG. 7 is a diagram showing an equivalent circuit diagram in which the flash memory cells 50 are combined in a matrix and a flash memory cell 50 that has been over-erased.

FIG. 8 is a diagram in which flash memory cells 50 are combined in a matrix. A is a diagram at the start of erasing, and B is a diagram showing a relationship with other cells when the erasing speed of only the cell C14 is reduced.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 3 ... Drain 4 ... Source 5 ... Control gate electrode 108 ... Silicon oxide film 112 ... Floating gate WL ... Word line BL ... Bit line SL ... Source line

Claims (3)

(57) [Claims] 1. A method of using a semiconductor memory device comprising A) to D), comprising: A) a nonvolatile memory comprising a1) to a6) and arranged in a matrix, a1) a first region, a2 A) a second region provided so as to form a region where an electric path can be formed with the first region; a3) a first insulating film provided above the region where the electric circuit can be formed; a4) a first insulating film provided above the insulating film A5) a second insulating film provided above the floating electrode; a6) a control electrode provided above the second insulating film; and B) a control electrode provided for each row. C) a control electrode line for connecting control electrodes of the nonvolatile memories arranged in the same row; C) a second area provided for each column and connecting the second areas of the nonvolatile memories arranged in the same column Line, D) a first area line connecting the first areas of all the non-volatile memories, Riseru applies a sense voltage to the control electrode lines are connected, the voltage applied to the first region line, the difference between the voltage applied to the second region line is selected memory are connected is provided,
In a method of using a semiconductor nonvolatile memory device for reading information stored in a memory cell desired to be read depending on whether a current flows between the first region and the second region, a memory cell not desired to be read is connected. A method of applying a read inhibit voltage that does not exceed a threshold voltage of an overerased memory cell to a control electrode line. 2. The method according to claim 1, wherein the read inhibit voltage is a voltage having an absolute value larger than a threshold voltage of the over-erased memory cell and is opposite to a voltage at the time of writing. A method of using the semiconductor nonvolatile storage device, wherein 3. The method according to claim 2, wherein the read inhibit voltage is a voltage at which no tunnel current is generated.