JPH05234382A - Nonvolatile memory device - Google Patents

Abstract

PURPOSE:To achieve an erasure operation which does not cause any excess erasure in a one-cell one-stacked gate memory MOS Tr type E<2>PROM and to shorten the erasure time of the title memory device by a method wherein a source for each memory MOS Tr is connected to a bit line and a drain is connected to a common line. CONSTITUTION:A write operation is performed in the following manner: a negative voltage (e.g. -9V) is applied to a word line ML; a common line COM (i.e., a drain line D) is made open; a voltage of, e.g. +5V is applied to a bit line BL; and electrons are tunneled and injected into a source from a floating gate for a memory cell. A readout operation is performed in the following manner: the line COM is set to 0 V; the line BL (i.e., a source S) is set to, e.g. 1V; a voltage of +5 is applied to the ward line WL; and a channel current is detected. An erasure operation can be performed by two methods. In one method, the line COM is set to, e.g. 5V, the line BL (i.e., the source) is set to 0V, 10V is applied to the line ML, a corresponding channel current is made to flow and hot electrons are injected, by a tunneling effect, into the floating gate from the drain D.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a non-volatile memory device, and more particularly to an electrically rewritable device composed of one stack gate type memory MOS transistor in which one cell is laminated with a floating gate and a control gate via an insulating film. Possible non-volatile storage.

[0002]

2. Description of the Related Art As a non-volatile memory device, an electrically rewritable non-volatile memory device comprising one stack gate type memory MOS transistor in which one cell is laminated with a floating gate and a control gate via an insulating film. (JP-A-1-158777).

Conventionally, such a non-volatile memory device has been used as shown in FIG. That is, the source S of each memory MOS transistor is connected to a common line (common), the drain D is connected to a bit line (BL), and the control gate is connected to a word line WL. Then, writing is performed by setting the source S to 0 V, the drain D to 5 V, and applying a positive high voltage, for example, +10 to 12 V to the control gate to inject channel hot electrons from the drain D to the floating gate.

For reading, + 5V is applied to the control gate.
Is applied (the word line WL is set to 5V), the source (common line) is set to 0V, and the drain (bit line BL).
Is applied by applying a positive voltage, for example, +1 V to the memory MOS transistor to detect whether or not a current flows through the memory MOS transistor. For erasing, a positive voltage, for example, + 5V is applied to the source S, and a high negative voltage, for example, −9 is applied to the control gate.
This is performed by applying V to extract electrons in the floating gate to the source S.

[0005]

By the way, in the conventional nonvolatile memory device, as shown in FIG. 3B, the written bit (cell) has a high Vth and the unwritten bit has a Vth.
Is low. Then, erasing is performed on the written bit, that is, Vt.
This is performed by injecting the electrons in the floating gate of the bit having a high h into the source S by the FN tunnel. However, when erasing, the injection amount becomes excessive and V
th may be lower than OV. If this happens, it means that the cells that must be normally off when reading are normally on. This inevitably causes erroneous reading. Such excessive injection of electrons is called overerasure.

Such overerase is caused by the subtle variations in the characteristics of the stack gate type MOS transistors forming each cell, and it is extremely difficult to eliminate the variations in the characteristics. Therefore, in the conventional erasing, it was indispensable to erase every bit while confirming (Verify). That is, it was impossible to erase all at once.

Further, it is necessary to write data in all bits once as a premise of the erasing. This is because some non-volatile memory devices have been programmed and some have not been programmed before they are erased.
This is because, as shown in (B), the Vths of the cells are different, and when erase processing is performed on such cells, all the cells that are not written are overerased.

That is, conventionally, when erasing data, all bits are once written in order to equalize the Vth levels of the cells before erasing, and after the writing, it is confirmed whether the erasing level is proper ( It was necessary to erase gradually while verifying. As described above, conventionally, a special algorithm is required for rewriting, and therefore the time required for rewriting is extremely long.

The present invention has been made to solve the above problems, and it is a one-cell one-stalli gate memory M.
An electrically rewritable non-volatile memory device of an OS transistor type is designed to enable erasing without fear of overerasing and to shorten the time required for erasing.

[0010]

According to the nonvolatile memory device of the present invention, the source of each memory MOS transistor is connected to the bit line and the drain is connected to the common line. Channel hot electronics injection or electron injection by FN tunnel with high voltage applied to the control gate is performed, and writing is performed by applying a negative voltage to the control gate and applying a positive voltage to the source to extract electrons from the floating gate to the source. It is characterized in that it is performed by doing so.

[0011]

According to the nonvolatile memory device of the present invention, writing is performed by extracting electrons from the floating gate to the source, and erasing is performed by injecting electrons from the drain or channel to the floating gate. The overerase as in the case of erasing by drawing electrons from the source to the source cannot occur. That is, since erasing is performed by the same operation as conventional writing, there is no room for overerasure.

It should be noted that, as in the case of the conventional nonvolatile memory device, the possibility of excessive extraction of electrons from the floating gate at the time of programming, which is caused by performing the programming by the same operation as the conventional erasing, is confirmed by the programming level. It can be eliminated by performing an operation of writing little by little while (Verify).

[0013]

The nonvolatile memory device of the present invention will be described in detail below with reference to the illustrated embodiments. 1A and 1B show one embodiment of the nonvolatile memory device of the present invention.
Is a cross-sectional view showing the structure of a memory MOS transistor,
FIG. 6B is an explanatory diagram of a usage mode of the memory MOS transistor. In the drawings, 1 is a p ^- type semiconductor substrate, 2 is n
It is an n ⁺ type source formed around the ⁺⁺ type source 2.

Reference numeral 3 denotes an n ⁺⁺ type drain, 3a denotes an n ⁺ type lightly-doped drain formed inside the drain 3, 4 denotes a p-type region provided at the periphery of the lightly doped drain 3a. is there. As described above, in the memory MOS transistor of the present nonvolatile memory device, the source 2 and the drain 3 have an asymmetrical shape. This is because the drain 3 makes it easier to generate channel hot electrons, and the source 2 makes the breakdown voltage with the substrate 1 higher. Of course, in the present invention, it is not essential to make the source and drain asymmetrical, but it can be said that this is more preferable for both writing and erasing. 5 is the first between the source and drain (channel)
The floating gate is formed via the gate insulating film 6, and the control gate 8 is formed on the floating gate 5 via the second gate insulating film 7.

Next, how to use the nonvolatile memory device will be described with reference to FIG. Each cell is the same as the conventional one in that the control gate is connected to the word line WL, but the source S is connected to the bit line BL and the drain D is connected to the common line (common line) COM. Different from the conventional one.

For writing, a negative voltage, for example, -9V is applied to the word line WL, the common line CMO (that is, the drain D) is opened, and the bit line BL is, for example, +.
Electrons are tunnel-injected from the floating gate of the memory cell to the source by applying a voltage of 5V. This is the same operation as the conventional erase.

For reading, the common line COM (that is, the drain D) is set to 0V, and the bit line BL (that is, the source S).
Is set to, for example, 1 V, a voltage of +5 V is applied to the word line WL, and the channel current is detected. Current flows in the written cells, and no current flows in the unwritten cells. This is the opposite of the case of the conventional nonvolatile memory device.

Erasing can be done in two ways. One method is to set the common line COM (that is, the drain D) to, for example, 5V, and set the bit line BL (that is, the source).
Is set to 0 V, 10 V is applied to the word line WL, and a corresponding channel current is caused to flow, whereby hot electrons are injected from the drain D to the floating gate by a tunnel effect.

According to such a method, since a large number of cells can be erased by one pulse, erasing can be performed at high speed, and since the erasing is performed by the conventional writing operation, the problem of overerase cannot occur, which will be described in detail later. However, according to this channel hot electron injection, a current of several hundred μA must be applied to each bit, so that the number of cells that can be erased at one time is limited. Specifically, only a few bytes can be erased at one time. However, since the time required for erasing once is as short as 10 μsec, the time required for erasing is short even if the number of erasing operations necessary for erasing the entire nonvolatile memory device increases.

When the source S side, that is, the bit line BL is opened, the channel current does not flow in the cell, so that the erase operation is not performed (however, the disturb due to the charge and discharge of the bit line BL needs to be careful. is there). Therefore,
It may be possible to prevent the erase operation by opening the bit line BL for the case where all the bits are read and erased before the erase.
According to this, it is expected that the stress at the time of writing can be reduced and the endurance can be enhanced by preventing the cells from increasing the Vth.

As a way of dividing the common line COM, FIG.
As shown in (A), (B), and (C), three types of division are possible. (A) shows that the common line COM is common to all the bits, (B) shows that the common line COM is divided into blocks, and (C) shows that the common line COM is provided for each word line WL. .. The cell indicated by the broken line in FIG. 2 is the selected cell.

The method of providing the common line COM for each word line WL shown in FIG. 2C is generally adopted in the full-function type float type E ² PROM.
When this method is adopted, erase / write for each word line WL
Writing can be easily realized, and the disturb due to bit line charging / discharging which is a problem when the bit line is opened does not occur.

Another method of erasing is to inject electrons from the substrate into the floating gate through an FN tunnel. Specifically, as shown in parentheses in FIG. 1B, the word line WL is set to 10 to 15V,
The source S and the drain D are set to 0V, the channel (substrate) is set to, for example, -3V (or 0V), and electrons are injected from the substrate side to the floating gate by an FN tunnel.

According to this method, since injection can be performed by tunneling without flowing a high voltage current, it is possible to erase all word lines at once, that is, all bits at once, and 1mse regardless of the number
The nonvolatile memory device can be erased in an extremely short time of c to 100 msec. The reason why the negative potential is applied to the substrate is to reduce the voltage required for the word line.

3 (A) and 3 (B) show V of the cell associated with erasing.
In order to explain the change of th, (A) shows the case of the present invention and (B) shows the conventional case. According to the invention, FIG.
As shown in (A), the Vth of an unwritten cell is high, and the Vth of a written cell is low. Then, the erase operation increases the Vth of the cell, and the written cell has the same Vth as the unwritten cell before the erase operation.
Becomes higher. The Vth of an unwritten cell becomes higher.

Therefore, erasing can completely erase data by considering the characteristics of each cell so that insufficient erasing does not occur, and erasing becomes excessive and causes erroneous reading. Theoretically, this cannot happen.
Therefore, it is not necessary to erase while confirming (Verify). Also, Vt of unwritten cells
Although h changes depending on the erase operation, since it changes in the direction of becoming higher, only the degree of erase becomes higher and there is no problem.

Therefore, it is not necessary to detect a cell that is not read and written once before erasing as in the conventional case, write to that cell to make Vth of all cells uniform, and then perform erasing. However, also in the present invention, if all bits have been read and erased before erasing, the bit line BL is opened so that the erasing operation is not performed, so that the Vth of the cell is unnecessarily increased.
It is also possible to reduce the stress at the time of writing by not increasing the endurance to achieve the effect of increasing the endurance.

Incidentally, in the conventional case, as described above, as shown in FIG. 3B, the threshold value of the written cell (bit) is high and the threshold value of the unwritten bit is high. Is low. When the written cell (bit) is erased, its V
Vth is 0 due to variations in cell characteristics.
Some cells become lower than V, which is overerase. Also, the cells (bits) not written are originally V
Since th is low and Vth is lower due to erasing, the total number of unwritten cells is overerased.

Therefore, conventionally, all bit data is read before erasing, which cell is not written with a signal is read, and the unwritten bit is written to set all bits to the same Vth. After that, it was necessary to erase the data while verifying because there was a variation in the characteristics. However, according to the invention,
It is not necessary at all, and one pulse can collectively be used, for example, 1
Since it can be erased word by word, the time required for erasing can be significantly shortened.

As described above, the write operation is performed from the same floating gate to FN as in the conventional erase operation.
This is done by extracting electrons through a tunnel. Therefore, if pulling out excessively, a reduction corresponding to overerase will occur. However, writing is conventionally performed by a method of writing little by little and monitoring the write level, and in the present invention, excessive drawing of electrons can be avoided by writing in such a manner.

Therefore, there is no possibility that the pull-out becomes excessive and the reduction corresponding to the overerase occurs. That is, the time required for writing is about the same as the conventional one. Therefore, overall, according to the present invention, there is an effect that the erasing time can be remarkably shortened, and there is no demerit.

FIG. 4 illustrates one case of the write operation while confirming (Verify).
When selecting one word line, for example, WL1, the word line WL1 is set to −10V, for example. The other word lines WL are set to 5V. Also, the common line COM is opened. Then, the bit line BL to be written is set to 5
V and the bit lines not written are set to 0V. Word line WL
When writing to the bit of, but not to the bit of, the bit lines BL2 and BL3 are set to 5V and the bit line BL1 is set to 0V. Such writing is performed in order, for example, one bit in the same word.

Then, for example, when one word line is completed, it is confirmed (Verify) whether or not the data can be read and written. Then, if the bit is written but the bit is not written, the bit line BL2 is set to 0V instead of 5V when writing again.
The bit line BL3 is set to 5V and writing is performed for that bit. In this way, since it is possible to write one bit at a time while confirming (Verify), it is possible to write so as not to excessively pull out.

It is to be noted that a full-function type E ² which writes every 1 word
Although it is possible to realize a PROM, since the writing speed is 10 to 100 msec / Biak, the page mode in which the bits of one word are simultaneously written is effective. For example, assuming that one word line has 1 Kbyte of bits, the time required for writing is 10 to 100 μsec per byte, and a writing speed almost the same as the conventional one can be secured.

[0035]

According to the nonvolatile memory device of the present invention, each memory M
The source of the OS transistor is connected to the bit line and the drain is connected to the common line. Further, erasing is performed by injecting channel hot electronics from the drain side or by FN tunneling by applying a high voltage to the control gate. It is characterized in that writing is performed by electron injection, and writing is performed by applying a negative voltage to the control gate and applying a positive voltage to the source to extract electrons from the floating gate to the source. Therefore, according to the nonvolatile memory device of the present invention, writing is performed by extracting electrons from the floating gate to the source, and erasing is performed by injecting electrons from the drain or channel to the floating gate. Overerasure cannot occur as in the case of erasing by drawing electrons to the source. Since Vth of a cell having a low Vth being written is increased by erasing, many bits can be completely erased collectively in consideration of variations in cell characteristics, and verification is not necessary. ..

Moreover, the unwritten cells are Vth
Is originally high, and it only gets higher due to erasure. Therefore, unlike the conventional case, it is not necessary to perform an operation that is necessary before erasing, in which all bits are read out before erasing, cells which are not written are detected, and those cells are written to make Vth uniform for all bits. .. Excessive extraction of electrons by writing can be easily avoided by performing an operation of writing little by little (for example, one bit at a time) while performing confirmation (Verify), which is also performed in the conventional nonvolatile memory device. ..

[Brief description of drawings]

1A and 1B show one embodiment of a nonvolatile memory device of the present invention, FIG. 1A is a sectional view of a memory MOS transistor (cell), and FIG. is there.

2A to 2C are circuit diagrams showing different examples of how to divide a common line (common line) of a nonvolatile memory device.

3 (A) and 3 (B) are V of a cell associated with writing and erasing.
FIG. 3A is a diagram showing a change in th, FIG.
(B) shows a conventional case.

FIG. 4 is an explanatory diagram of one case of a write operation in the nonvolatile memory device of the present invention.

FIG. 5 is an illustration of a conventional use of a non-volatile storage device.

[Explanation of symbols]

 1 substrate 2 source 3 drain 5 floating gate 6, 7 gate insulating film 8 control gate

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location H01L 29/792 H01L 29/78 371

Claims (2)

[Claims] 1. An electrically rewritable non-volatile memory device comprising one stack gate type memory MOS transistor in which one cell has a floating gate and a control gate laminated with an insulating film interposed therebetween. A non-volatile memory device characterized in that the source of a transistor is connected to a bit line and the drain is connected to a common line. 2. Erase is performed by injecting channel hot electrons from the drain side to the floating gate or by injecting electrons by FN tunnel from the substrate side to the floating gate while applying a high voltage to the control gate. 2. The non-volatile memory device according to claim 1, wherein a negative voltage is applied to the gate and a positive voltage is applied to the source to extract electrons from the floating gate to the source.