KR100629193B1 - Nonvolatile semiconductor storage device - Google Patents

Abstract

A nonvolatile semiconductor memory device includes a memory cell transistor capable of storing two bits of a first bit and a second bit at both ends of a charge trapping layer, a comparator for reading data of the first bit to determine a data state, and a data state of zero. And a voltage conversion circuit for changing the voltage condition of the write operation for the second bit in accordance with whether or not.

Description

Nonvolatile semiconductor memory device and recording method thereof {NONVOLATILE SEMICONDUCTOR STORAGE DEVICE}

BACKGROUND OF THE INVENTION Field of the Invention The present invention generally relates to a nonvolatile semiconductor memory device and a recording method thereof, and more particularly, to a nonvolatile semiconductor memory device and a recording method thereof for storing charge in a nitride film.

Some nonvolatile semiconductor memory devices use a nitride film as a charge trapping layer in a virtual ground array structure, and physically store two bits of information in one memory cell transistor. In such a nonvolatile semiconductor memory device, both ends of a single nitride film existing between bit lines are treated as two independent memory cells, and data of a total of 2 bits can be stored depending on whether or not hot electrons are injected into each of them. This is made possible by the property that the charge does not move in the nitride film as the charge trapping layer in this case.

In general, in the conventional nonvolatile semiconductor memory device, in the write operation for injecting hot electrons, the write voltage applied to the drain terminal is common to all bits. In the write verify operation and the data read operation, the voltage applied to the drain terminal is the same voltage.                 

However, in the method of storing two bits of information in a single charge trapping layer as described above, the threshold of one cell is affected by the threshold of the other cell. In other words, the threshold value of the other cell changes depending on whether the one cell is in the recorded or erased state. Therefore, if a fixed write voltage is used as in the prior art, the threshold value after writing varies depending on the state of the other cell. For example, the threshold value after recording of the other cell becomes higher in the state in which the cell is being recorded than in the state in which one cell is erased.

As a result, the threshold value fluctuates between memory cells in the sector after the end of the write operation. In this manner, if the threshold value is changed, the tunnel current between bands at the time of erasing changes, and the threshold value fluctuation is further increased after erasing, leading to a delay in erasing time and deterioration of the rewriting characteristic.

In view of the above, it is an object of the present invention to provide a nonvolatile semiconductor memory device which reduces variations in threshold values after recording.

A nonvolatile semiconductor memory device according to the present invention includes a memory cell transistor capable of storing two bits of a first bit and a second bit at both ends of a charge trapping layer, a comparator for reading data of the first bit to determine a data state; And a voltage conversion circuit for changing the voltage condition of the write operation for the second bit depending on whether the data state is zero or one.

In the above invention, when writing to a memory cell of one end of the charge trapping layer of a memory cell transistor, the voltage condition (write voltage, verification) of the write operation according to the data of the memory cell of the other end of the charge trapping layer of the memory cell transistor Voltage, reference cell threshold voltage, etc.). This can prevent variations in the threshold value after data recording.

Specifically, since the threshold value after the writing of the cell A tends to be relatively low when the cell B is in the erased state (data " 1 "), the injection charge amount is increased by using a relatively high write voltage and verify voltage. The threshold value after recording is made into a desired value. When the cell B is in the write state (data "0"), since the threshold value after the writing of the cell A tends to be relatively high, the threshold value after the writing is reduced by using a relatively low write voltage and the verify voltage. To the desired value.

According to another aspect of the present invention, a nonvolatile semiconductor memory device provides a memory cell transistor capable of storing two bits at both ends of a charge trapping layer, and simultaneously supplies write verification to a memory cell transistor during a read operation. And a voltage conversion circuit for supplying a second drain voltage higher than the first drain voltage in operation.

In the above invention, by making the drain voltage at the write verify time higher than the drain voltage at the read operation, the influence from the other memory cell of the charge trapping layer is reduced, so that the threshold value after the write is not changed.

1 is a block diagram showing the configuration of a nonvolatile semiconductor memory device according to the present invention.

2 illustrates a portion of a cell array.

3 is a cross-sectional view of a portion of a cell array.

4 is a flowchart showing a data recording operation according to the first embodiment of the present invention.

5 is a diagram illustrating a threshold dependency between a drain voltage and a memory cell.

6A and 6B are diagrams showing the difference in voltage setting between the read operation and the write verify operation.

1 is a block diagram showing the configuration of a nonvolatile semiconductor memory device according to the present invention. The nonvolatile semiconductor memory device 10 of FIG. 1 includes a control circuit 11, an input / output buffer 12, an address latch 13, an X decoder 14, a Y decoder 15, a cell array 16, and a data latch. (Comparator) 17, voltage conversion circuit 18, erase circuit 19, chip enable / output enable circuit 20, and reference cell 21.

The control circuit 11 receives a control signal from the outside and operates as a state machine based on the control signal to control the operation of each part of the nonvolatile semiconductor memory device 10.

The input / output buffer 12 receives data externally and supplies the data to the data latch 17. The address latch 13 receives and latches an address signal supplied from the outside and supplies this address signal to the X decoder 14 and the Y decoder 15. The X decoder 14 decodes the address supplied from the address latch 13, and activates the word line provided in the cell array 16 in accordance with the decoding result. The Y decoder 15 decodes the address supplied from the address latch 13, selectively reads data of the bit line of the cell array 16 based on the decode address signal, and supplies it to the data latch 17.

The cell array 16 includes an array of memory cell transistors, a word line and a bit line, and stores two bits of information in each memory cell transistor. At the time of data reading, data from the memory cell designated in the active word line is read in the bit line. At the time of programming or erasing, the word line and the bit line are set to appropriate potentials according to the respective operations to perform charge injection or charge extraction operations for the memory cells.

The data latch (comparator) 17 determines whether the data is 0 or 1 by comparing the level of data supplied from the cell array 16 through the Y decoder 15 with the reference level indicated by the reference cell 21. . The determination result is supplied to the input / output buffer 12 as read data. The verify operation according to the program operation and the erase operation is also performed by comparing the level of data supplied from the cell array 16 through the Y decoder 15 with the reference level indicated by the reference cell 21.

The voltage converting circuit 18 generates and supplies a potential applied to the word line and the bit line in the write operation (in the program operation), and a potential applied to the word line and the bit line in the read operation, and supplies it to the X decoder 14. do. The erase circuit 19 generates a potential applied to the word line and the bit line during the erase operation to perform the sector-by-sector erase operation on the cell array 16.

The chip enable / output enable circuit 20 receives the chip enable signal / CE and the output enable signal / OE as a control signal from outside the device, and operates the input / output buffer 12 and the cell array 16. Control nonoperation.

In the first embodiment of the present invention, when writing to a memory cell of one end of the charge trapping layer of a memory cell transistor, data of the memory cell of the other end of the charge trapping layer of the memory cell transistor is first given to the data latch 17. Is read in to change the voltage generated by the voltage conversion circuit 18 in relation to the write operation in accordance with the read data contents.

2 shows a portion of cell array 16.

As shown in FIG. 2, a plurality of word lines WL1 to WL3 and a plurality of bit lines B1 to B6 are disposed in the cell array 16. Further, a plurality of memory cell transistors 22 are vertically and horizontally arranged so that two adjacent bit lines serve as a drain and a source, and a word line serves as a gate.

3 is a cross-sectional view of a portion of the cell array 16.

3 includes a buried diffusion layer 110, a word line 111, a charge trapping layer 112, and a bit line oxide 113. The charge trapping layer 112 has an ONO (Oxide Nitride Oxide) structure including a nitride film 114 and an oxide film 115, which are charge storage films. As a result, a memory cell transistor capable of storing hot electrons in the charge trapping layer 112 is formed. The word line 111 corresponds to the gate of the memory cell transistor, and the buried diffusion layer 110 corresponds to the source and drain of the memory cell transistor.

In order to facilitate understanding of the present invention, a conventional data recording and data reading operation will first be described.

One of the two buried diffusion layers 110 corresponding to a certain memory cell transistor is applied with a high voltage (for example, 5 V) as a drain and connected to a reference potential (for example, a power supply ground VSS) as a source. Further, when a high voltage (for example, 9 V) is applied to the word line 111 corresponding to the memory cell transistor, hot electrons are generated in the vicinity of the buried diffusion layer 110 on the drain side (the side to which the high voltage is applied). (e) is injected into the charge trapping film 114. At this time, the position where charge e is accumulated in the charge trapping film 114 is closer to the buried diffusion layer 110 to which a high voltage is applied as a drain.

Next, the above-mentioned drain side is connected to the reference potential as the source side, and the above-described source side is applied at this time as a drain side to store the charge e in the position opposite to the charge trapping film 114. Can be. In this way, by injecting the charges (e) at both ends of the charge trapping layer 112, it becomes possible to store two bits for one memory cell transistor. This is based on the property that charge does not move in the nitride film 114 which is the charge trapping material of the charge trapping film 114.

When reading the information of the injected electric charges (electrons), the buried diffusion layer 110 on the drain side is set as the reference potential at the time of writing, and the read voltage (for example, 1.5 V) is applied to the buried diffusion layer 110 on the source side at the time of writing. Is applied. In addition, a read gate voltage (for example, 5 V) is applied to the word line 111. In this way, the read operation is executed.

When erasing the injected charges (electrons), a high voltage (for example, 5 V) is applied to the buried diffusion layer 110 on the drain side at the time of writing, and the buried diffusion layer 110 on the source side is floating at the time of writing. Shall be. In this state, by applying a negative high voltage (for example, -5 V) to the word line 111, holes generated by the band-to-band tunnel current flowing from the diffusion layer 110 to which the high voltage is applied are transferred to the charge storage film 114. It can inject and neutralize the trapped electron. As a result, the erase operation is executed.

As described above, in the conventional data writing, a high voltage (for example, 5 V) is applied as one of the bit lines as a drain, and the other is connected to a reference potential (for example, a power supply ground (VSS)) as a source. A high voltage (for example, 9 V) is further applied to the word line corresponding to. However, as described above, the threshold value of the memory cell existing at one end of the charge trapping layer is affected by the state of data of the memory cell present at the other end. Therefore, in the case where the write voltage is alternatively applied in this way, the threshold value after data writing occurs.

In the first embodiment of the present invention, when writing to a memory cell of one end of the charge trapping layer of a memory cell transistor, the write voltage and the verification voltage are changed in accordance with the data of the memory cell of the other end of the charge trapping layer of the memory cell transistor. And the reference cell threshold voltages are varied. This can prevent variations in the threshold value after data recording.                 

4 is a flowchart showing a data recording operation according to the first embodiment of the present invention. This flowchart is for explaining the case where one memory cell of the charge trapping layer of a certain memory cell transistor is referred to as cell A, the other memory cell is referred to as cell B, and the cell A is written.

First, in step S1, the verify operation for the cell B is performed. Referring to FIG. 1, the data of the cell B is read from the cell array 16 through the Y decoder 15 to the data latch 17 to compare the data level with the reference level of the reference cell 21. Confirm. If data is "1", the processing proceeds to step S2. If the data is "0", the processing proceeds to step S3.

The program level 1 is set in step S2. In step S3, program level 2 is set. Referring to FIG. 1, if the data of cell B is "1" based on the data check result supplied from the data latch 17 to the voltage conversion circuit 18, the voltage conversion circuit 18 is for writing the cell A. FIG. And set the voltage generated for verification to program level 1. If the data of the cell B is "0", the voltage conversion circuit 18 sets the voltage generated for the writing and verification of the cell A to the program level 2.

The verify operation of cell A is executed in accordance with the program level set in step S4. If the verification operation passes, the process ends. In the case of failure, the flow advances to step S5 to execute the write operation for the cell A in accordance with the set program level. After that, the process returns to step S4 to execute the verify operation again.

Here, the program levels set in steps S2 and S3 determine the respective levels of the drain voltage and the gate voltage during the write operation and the verify operation, and the threshold voltages of the verification reference cell.

Program level 1

Cell write voltage: Vg = 9.0 V, Vd = 5.0 V

Cell write verify voltage: Vg = 5.0 V, Vd = 1.0 V

Cell write verification reference cell threshold voltage: Vth = 4.5 V

Program level 2

Cell write voltage: Vg = 8.5 V, Vd = 4.5 V

Cell write verify voltage: Vg = 4.5 V, Vd = 1.0 V

Cell write verification reference cell threshold voltage: Vth = 4.0 V

Where Vg is the gate voltage and Vd is the drain voltage

Thus, by controlling the voltages of the write and verify operations for the cell A in accordance with the data contents of the cell B, the variation of the threshold value after the data writing does not occur. Specifically, since the threshold value after the writing of the cell A tends to be relatively low when the cell B is in the erased state (data " 1 "), by using a relatively high write voltage and verify voltage as in program level 1 The injection charge amount is increased to make the threshold value after writing the desired value. In addition, when the cell B is in the write state (data "0"), since the threshold value after the write of the cell A tends to be relatively high, the amount of injected charges is reduced by using a relatively low write voltage and verify voltage as in program level 2. The threshold value after recording is made a desired value.                 

A second embodiment of the present invention will be described below.

In the second embodiment of the present invention, by making the drain voltage at the write verify time higher than the drain voltage at the read time, the influence from the other memory cell of the charge trapping layer is reduced, and the threshold value after the write is not changed.

In general, it is possible to reduce the influence from the other memory cell of the charge trapping layer by increasing the drain voltage. It is not preferable to increase the drain voltage at the time of data reading because charge gain due to reading and interruption occurs. However, the time for which the verify voltage is applied to the memory cell transistor in the write verify operation is particularly shorter than the time for which the read voltage is applied in the read operation. Therefore, no problem arises even if a certain high verify voltage is used in the write verify operation.

5 is a diagram illustrating a threshold dependency between a drain voltage and a memory cell.

In FIG. 5, the drain voltage is shown on the horizontal axis, the threshold value of the cell A is shown on one side of the vertical axis, and the threshold shift amount of the cell B due to the stress of reading to the cell A is shown on the other side of the vertical axis. The cutting line C1 indicates how much the threshold value of the cell A rises under the influence of the charge of the cell B when the drain voltage is applied in reading or verifying the cell A. FIG. As shown by cut line C1, when the drain voltage is high, the influence of the cell B on the threshold value of the cell A hardly exists. However, the lower the drain voltage, the greater the effect of cell B on the threshold of cell A. In general, the drain voltage used for data reading is 1.5 V, and as shown in FIG. 5, at a drain voltage of 1.5 V, the threshold of the cell A increases considerably under the influence of the charge of the cell B.                 

In Fig. 5, the cut line C2 shows how much the threshold value of the cell B shifts when the drain voltage is applied in the read operation of the cell A. As shown by the cut line C2, when the drain voltage is low, there is almost no interruption of read to the cell B due to the read stress of the cell A. However, the higher the drain voltage, the greater the influence of read disturb on the cell B. Generally, the drain voltage used for data reading is 1.5V, and it is set to the voltage which does not produce a data error by reading interruption.

As described above, the time for which the verify voltage is applied to the memory cell transistor in the write verify operation is particularly shorter than the time for which the read voltage is applied in the read operation. Therefore, even if a certain high verify voltage is used in the write verify operation, the disturbance to the cell B due to the read stress of the cell A does not become a problem.

In the present invention, the drain voltage during the write verify operation for the cell A is, for example, about 2.5 V which is not affected by the cell B. In addition, this drain voltage is such a voltage that the write verification operation does not cause an incorrect writing to the cell B. As can be seen from Fig. 5, the drain voltage in the write verify operation is set to a voltage higher than the drain voltage in the read operation.

Referring to Fig. 1, the voltage conversion circuit 18 generates a potential applied to the word line and the bit line in the write operation, and a potential applied to the word line and the bit line in the read operation. For example, in the first embodiment, a configuration in which the potential 1.5 V applied to the bit line of the drain terminal during the read operation is applied to the drain terminal even during the write verification. In this second embodiment, the voltage conversion circuit 18 further generates, for example, 2.5 V as the drain terminal potential for the write verification, and supplies it to the X decoder 14.

6A and 6B are diagrams showing the difference in voltage setting between the read operation and the write verify operation.

FIG. 6A shows voltages applied to gates, drains, and source ends of the memory cell transistors 22 in the read operation. Vg = 5 V is applied to the gate, and Vd = 1.5 V and Vs = 0 V are supplied to the drain and the source, respectively. Also shown here is a read operation for cell A, in which charge e is injected into cell B. As shown in FIG.

FIG. 6B shows voltages applied to the gate, the drain, and the source terminal of the memory cell transistor 22 in the write verify operation. Vg = 5V is applied to the gate, and Vd = 2.5V and Vs = 0V are supplied to the drain and the source, respectively.

As described above, in the second embodiment of the present invention, the drain voltage during the write verification is made higher than the drain voltage during the read so that an incorrect writing does not occur, so that the influence from the other memory cell of the charge trapping layer is reduced, and the write is performed. Ensure that the later threshold does not change.

In addition, although the said 1st Example and the 2nd Example can be implemented independently, you may comprise so that both may be implemented simultaneously.

As mentioned above, although this invention was demonstrated based on the Example, this invention is not limited to the said Example, A various deformation | transformation is possible within the range described in the claim.

Claims (8)

A memory cell transistor capable of storing two bits of the first bit and the second bit at both ends of the charge trapping layer; A comparator for reading data of the first bit to determine a data state; And a voltage conversion circuit for changing a voltage condition of a write operation for the second bit in accordance with whether the data state is 0 or 1. The nonvolatile semiconductor memory device according to claim 1, wherein the voltage conversion circuit changes the write voltage for the second bit depending on whether the data state is 0 or 1. The nonvolatile semiconductor memory device according to claim 1, wherein the voltage conversion circuit changes the write verify voltage for the second bit depending on whether the data state is zero or one. The nonvolatile semiconductor memory device according to claim 1, further comprising a reference cell in which a threshold voltage at the time of write verification is changed depending on whether the data state is 0 or 1. FIG. A memory cell transistor capable of storing two bits at both ends of the charge trapping layer; And a voltage conversion circuit for supplying a first drain voltage to the memory cell transistor during a read operation and a second drain voltage higher than the first drain voltage during a write verify operation. store. 6. The method of claim 5, wherein the second drain voltage is a voltage that is high enough not to be affected by the other bit when writing and verifying one bit of the two bits, and so as not to incorrectly write to the other bit. A nonvolatile semiconductor memory device, characterized by low voltage. Reading data of the first bit from a memory cell transistor capable of storing two bits of the first bit and the second bit at both ends of the charge trapping layer to determine a data state, Determine a voltage condition of a write operation for the second bit according to whether the data state is 0 or 1, And each step of executing a write operation on the second bit under the determined voltage condition. When writing data to a memory cell transistor capable of storing two bits at both ends of the charge trapping layer, during write verification, data is applied to the memory cell transistor by applying a second drain voltage higher than a first drain voltage applied during a read operation. And a step of reading the nonvolatile semiconductor memory device.

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