JP2006351112A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To raise efficiency of write back processing to a nonvolatile memory transistor in an over-erasure state. <P>SOLUTION: A semiconductor device has a plurality of pages, to each of which a plurality of nonvolatile memory transistors are assigned per wordline. In the nonvolatile memory transistor, threshold voltage is made low by erasure processing to discharge an electron from an electrical charge storage area and the threshold voltage is made high by program processing to inject the electron into the electrical charge storage area. Responding to an initialization command, a control circuit (16) performs program processing in the unit of wordline after making upper skirt of threshold voltage distribution lower than the object level by erasure processing in the unit of wordline, and before performing program processing in the unit of page for making lower skirt of the threshold voltage distribution higher than the object level. The lower skirt of the threshold voltage distribution of the nonvolatile memory transistor is raised as a whole by program processing in the unit of wordline. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device including a nonvolatile memory transistor that stores information by changing an electrical threshold voltage, and relates to a technique that is effective when applied to, for example, a flash memory.

  The threshold voltage of the nonvolatile memory transistor constituting the flash memory or the like is determined according to the amount of charge accumulated in the charge accumulation region. For example, information can be stored by an initialization process (erasing) for emitting electrons (electrons) from the charge storage region and a program process (writing) for injecting electrons into the charge storage region. When rewriting stored information, for example, an erase high voltage is applied to the word line, and electrons are extracted toward the substrate by an FN (Fowler-Nordheim) tunnel, thereby erasing the threshold voltage of the nonvolatile memory transistor in units of word lines. Can be initialized to the state. Thereafter, a write high voltage is applied to the word line for the nonvolatile memory transistor to be written, a write current is passed through the channel, and hot electrons generated thereby are injected into the charge storage region. The electron injection operation is repeated until the threshold voltage is confirmed to be a predetermined level by verify.

  Incidentally, non-volatile memory transistors have manufacturing variations such as oxide film thickness and minute defects. Due to this manufacturing variation, a difference occurs in the electron emission characteristics and the injection characteristics with respect to the charge accumulation region. Therefore, even if the initialization process (erase process) is similarly performed on a plurality of memory cells, the threshold voltage of each memory cell is not constant and a threshold voltage distribution is formed. Therefore, if a high voltage pulse for erasing is applied to the memory cell transistors in units of word lines, when a memory cell with a low erasing speed reaches a target threshold voltage, the memory cell with a high erasing speed is over-erased. It will be in the state of. In the over-erased state, even if reading is not selected, it becomes conductive and cannot be used for normal memory operation. Therefore, after erasure, a program process (write-back process) is performed to increase the lower skirt level of the threshold voltage distribution. The target of the write-back process is a nonvolatile memory transistor having a threshold voltage lower than the target lower skirt level. On the contrary, the threshold voltage distribution is narrowed by performing verification while gradually applying high voltage pulses so that the threshold voltage does not become too high in the write-back process.

  Patent Document 1 describes a write-back process for an over-erased memory cell. According to this, it is described that writing back and verifying are performed in several times according to the degree of over-erasing.

Japanese Patent Laid-Open No. 2001-184876

  The present inventor examined the efficiency of the write-back process for the over-erased nonvolatile memory transistor. For example, the case where the erasing unit is a word line unit of a plurality of pages with respect to a page which is a writing unit was examined. According to this, an erasing voltage can be applied in units of word lines, but a high voltage application for writing back is performed in units of pages from the beginning. As a result, the number of write-back processes increases and the processing time becomes longer. If the write-back is performed by the same method as the normal write, the control form becomes the same, and it can contribute to suppressing an increase in the logic scale of the control circuit. However, the present inventor has revealed that the time required for the write-back process may be long.

  An object of the present invention is to provide a semiconductor device capable of improving the efficiency of write-back processing for a nonvolatile memory transistor.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The following is a brief description of an outline of typical inventions disclosed in the present application.

  [1] The semiconductor device has a plurality of pages corresponding to one word line, each of which is assigned a plurality of nonvolatile memory transistors (21). The non-volatile memory transistor has a charge storage region (36), and a threshold voltage of the non-volatile memory transistor is lowered by an erasing process for releasing electrons from the charge storage region, and a program process for injecting electrons into the charge storage region As a result, the threshold voltage of the nonvolatile memory transistor is increased. A control circuit (16) for controlling the erasure process and the program process in response to a command. In response to the initialization command, the control circuit lowers the upper skirt of the threshold voltage distribution below its target level by erasing processing in units of word lines, and then raises the lower skirt of the threshold voltage distribution higher than the target level. Before performing page unit program processing (T5) for this purpose, word line unit program processing (T4) is performed.

  According to the above-described means, in the write-back after the erase process in units of word lines, the program process in units of word lines is first performed, so that the lower skirt of the threshold voltage distribution of the nonvolatile memory transistor is raised as a whole. Since writing back is performed in units of pages from this stage, the overall writing back processing time is shortened. In short, the number of high voltage application processes for write back can be reduced.

  As one specific form of the present invention, the erasing process in units of word lines is a process of extracting electrons from the charge storage region through the gate insulating film to the semiconductor substrate by an FN tunnel. The program processing in units of word lines is processing for injecting electrons from the semiconductor substrate through the gate insulating film to the charge storage region by an FN tunnel. The page-by-page program process is a process for injecting hot electrons into the charge storage region. By adopting the program processing by the FN tunnel as the pre-write back processing, it is possible to easily perform the write back in units of word lines. This is because it is not necessary to form a current path as in hot electron injection. Instead, the electron injection efficiency is lower than that of hot electron injection. The purpose of the write-back is to increase the threshold voltage of the memory transistor having a fast erase speed, in other words, to raise the lower tail of the erase distribution that is too low to the target level. It is necessary to completely eliminate the possibility of overwriting. In this respect, pre-writing back by the FN tunnel is preferable. This is especially true when verifying is not performed for the program processing in units of word lines.

  As another specific form of the present invention, the control circuit applies a negative high voltage pulse to the word line (WL) with the semiconductor substrate (30) as a ground potential in the erasing process in units of word lines, In the unit program processing, the semiconductor substrate is set to the ground potential, and a positive high voltage pulse is applied to the word line. At this time, the level of the positive high voltage pulse is lower in absolute value than the negative high voltage pulse. This is to completely eliminate the possibility that the threshold voltage is excessively written back at the pre-write-back stage.

  As another specific form of the present invention, a plurality of nonvolatile memory transistors sharing the word line are connected in series via the control transistors (20, 22). The control transistor has a gate electrode (33, 34) capable of forming an inversion layer (23) extending in a direction crossing the series direction. Four gate control lines (AG0 to AG3) in which every four gate electrodes are commonly connected in the word line direction. The control circuit controls the level of the four gate control lines, and conducts the non-volatile memory transistor to the inversion layer of the control transistor adjacent to each other at a ratio of one in four to store the stored information in units of pages. Reading can be performed, and current flows from one to the other through the inversion layers of the control transistors on both sides of the adjacent non-volatile memory transistors at a ratio of two to four, and the hot electrons near one non-volatile memory transistor. In the erase process in units of word lines and the program process in units of word lines, an inversion layer is not formed in the control transistor. This memory array configuration is not suitable for program processing by hot electron injection in units of word lines. This is because it is impossible to secure a current path for performing hot electron injection in parallel to the nonvolatile memory transistors of the four pages. It is inevitable that program processing using an FN tunnel is adopted as pre-write-back for each page.

  As another specific mode of the present invention, the semiconductor device includes an insulating film (31) formed on the main surface of the semiconductor substrate, first to third electrodes, and a charge storage region (36). A plurality of first electrodes (33) and second electrodes (34) are formed on the insulating film alternately in a first direction at a predetermined interval. The third electrode (35) is formed on the insulating film at a predetermined interval in a second direction intersecting with the first direction, and is insulated from the first electrode and the second electrode. The charge accumulation region is disposed between the first electrode and the second electrode, and can selectively accumulate charges immediately below the third electrode. At this time, the word line is a third electrode. The nonvolatile memory transistor has a charge storage region and a third electrode. The control transistor has a first electrode or a second electrode.

  [2] A semiconductor device according to another aspect has a plurality of nonvolatile memory transistors, and the nonvolatile memory transistors have a charge storage region. The threshold voltage of the nonvolatile memory transistor is lowered by an erasing process for releasing electrons from the charge storage region, and the threshold voltage of the nonvolatile memory transistor is increased by a program process for injecting electrons into the charge storage region. A control circuit for controlling the erasure process and the program process in response to a command; In response to the initialization command, the control circuit lowers the upper skirt of the threshold voltage distribution below the target level by the erasing process, and then hots the lower skirt of the threshold voltage distribution above the target level. Before the program process (T5) by electron injection, the program process (T4) by the FN tunnel is performed.

  By adopting the program processing by the FN tunnel as the pre-write-back processing, the pre-write-back processing for each word line can be easily performed. This is because it is not necessary to form a current path as in hot electron injection. Instead, the electron injection efficiency is lower than that of hot electron injection. The purpose of the write-back is to increase the threshold voltage of the memory transistor having a high erase speed, in other words, to raise the lower tail of the erase distribution that is too low to the target level. It is necessary to completely eliminate the possibility of overwriting. In this respect, pre-writing back by the FN tunnel is preferable. This is especially true when verifying is not performed for the program processing in units of word lines.

  As one specific form of the present invention, the erasing process is a process of extracting electrons from the charge storage region to the semiconductor substrate by an FN tunnel. The program process by the FN tunnel is a process of injecting electrons from the semiconductor substrate to the charge storage region by the FN tunnel.

  As another specific mode of the present invention, a semiconductor device includes an insulating film formed on a main surface of a semiconductor substrate, first to third electrodes, and a charge storage region. A plurality of first electrodes and second electrodes are alternately formed on the insulating film at predetermined intervals. The third electrode is formed on the insulating film at a predetermined interval in a second direction intersecting with the first direction, and is insulated from the first electrode and the second electrode. The charge accumulation region is disposed between the first electrode and the second electrode, and can selectively accumulate charges immediately below the third electrode. The nonvolatile memory transistor has a charge storage region and a third electrode. The inversion layer immediately below the first electrode and the inversion layer immediately below the second electrode are used as data lines.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  That is, the write-back process for the nonvolatile memory transistor can be made efficient.

<Overall configuration of flash memory>
FIG. 1 shows a flash memory as an example of a semiconductor device. The flash memory 1 is formed on a single semiconductor substrate such as single crystal silicon.

  The flash memory 1 is not particularly limited, but has four memory banks BNK0 to BNK3. Each of the memory banks BNK0 to BNK3 has the same configuration and can be operated in parallel. In the figure, the configuration of the memory bank BNK0 is typically illustrated in detail. The memory banks BNK0 to BNK3 include a memory array (ARY) 3, an X decoder (XDEC) 4, a data register (DRG) 5, a data control circuit (DCNT) 6, and a Y address control circuit (YACNT) 7.

  The memory array 3 has a large number of nonvolatile memory transistors capable of electrically rewriting stored information. Although the memory transistor is not particularly limited, the memory transistor has a stacked gate structure in which a memory gate is overlapped with a charge storage region via an insulating film. Although not particularly limited, each memory transistor stores 2 bits of data. In short, information is stored in four values. The four values are, for example, four values “11”, “10”, “00”, and “01”. The stored information “11” is obtained by an erasing process that is initialization for the memory transistor. The erasing process is not particularly limited, but the circuit ground potential is applied to the source, drain and well of the memory transistor, and a negative high voltage is applied to the memory gate to move the electrons in the charge storage region. Thus, the threshold voltage is lowered. The stored information “10”, “00”, “01” is obtained by program processing (write processing). The write process is not particularly limited, but a current is passed from the drain to the source of the memory transistor, hot electrons are generated on the substrate surface at the source end, and this is injected into the charge storage region by an electric field due to the high voltage of the memory gate. The threshold voltage is increased. The target threshold voltage is different depending on the stored information “10”, “00”, “01”. In the read process, the bit line is precharged in advance, and the memory information is selected by changing the current flowing in the bit line or the voltage level appearing on the bit line by selecting the memory transistor with the predetermined read determination level as the word line selection level. It is supposed to be a process that enables The word line selection level differs depending on the storage information “11”, “10”, “00”, “01”. The memory array 3 has a read / write circuit (not shown) connected to the bit line. The read / write circuit latches the storage information read to the bit line in the read process, and controls the bit line potential according to the write data in the write process.

  In the memory array 3, the memory gate of the memory transistor is connected to the word line. One word line is connected to memory gates of memory transistors for four pages (page 0, page 1, page 2, page 3). One page corresponds to 1k × 8 memory transistors (2 kbytes of storage capacity). Although details will be described later, the erasing process is performed in units of four pages, the writing process is performed in units of one page, and the reading process is performed in units of one page.

  The flash memory array 3 and the data register 5 input / output data. For example, the data register 5 is constituted by an SRAM and functions as a buffer for write data to be written to the flash memory array 3 and a buffer for read data read from the flash memory array 3.

  The data control circuit 6 controls input / output of data to / from the data register 5. The Y address control circuit 7 performs address control for the data register 5.

  The external input / output terminals I / O 1 to I / O 16 are also used as address input terminals, data input terminals, data output terminals, and command input terminals, and are connected to the multiplexer (MPX) 10. The page address input to the external input / output terminals I / O 1 to I / O 16 is input from the multiplexer 10 to the page address buffer (PABUF) 11, and the Y address (column address) is input from the multiplexer 10 to the Y address counter (YACUNT) 12. Preset. Write data input to the external input / output terminals I / O 1 to I / O 16 is supplied from the multiplexer 4 to the data input buffer (DIBUF) 13. Write data supplied to the data input buffer 13 is input to the data control circuit 6 via an input data control circuit (IDCNT) 14. Read data output from the data control circuit 6 is supplied to the multiplexer 10 via the data output buffer (DOBUF) 15 and output from the external input / output terminals I / O1 to I / O16.

  A part of the command code and the address signal supplied to the external input / output terminals I / O1 to I / O16 are supplied from the multiplexer 10 to the internal control circuit (OPCNT) 16.

  The page address supplied to the page address buffer 11 is decoded by the X decoder 4 and a word line is selected from the memory array 5 according to the decoding result. The Y address counter 12 preset with the Y address supplied to the page address buffer 11 performs address counting with the preset value as a starting point, and supplies the Y address counted to the Y address control circuit 7. The counted Y address is used as an address signal when write data from the input data control circuit (IDCNT) 14 is written to the data register 5 and when read data to be supplied to the output buffer 15 is selected from the data register 5. The The Y address supplied to the page address buffer 11 is equal to the head address of the counted Y address. This head Y address is referred to as an access head Y address.

  The control signal buffer (CSBUF) 18 includes a chip enable signal / CE, a command latch enable signal CLE, an address latch enable signal ALE, a write enable signal / WE, a read enable signal / RE, and a write protect signal as external access control signals. / WP, power on read enable signal PRE, and reset signal / RES are supplied. The symbol “/” attached to the head of a signal means that the signal is low enable.

  The chip enable signal / CE is a signal for selecting the operation of the flash memory 1, and the flash memory (device) 1 is activated (operable) at a low level, and the flash memory 1 is set to standby (operation stopped) at a high level. The The read enable signal / RE controls the data output timing from the external input / output terminals I / O1 to I / O16, and data is read in synchronization with the clock change of the signal. The write enable signal / WE instructs the flash memory 1 to fetch the command, address, and data at the rising edge. The command latch enable signal CLE is a signal for designating data supplied from the outside to the external input / output terminals I / O1 to I / O16 as a command, and the data of the output terminals I / O1 to I / O16 is CLE = "H". At (high level), it is taken in synchronization with the rising edge of / WE and recognized as a command. The address latch enable signal ALE is a signal for instructing that the data supplied from the outside to the external input / output terminals I / O1 to I / O16 is an address, and the data of the output terminals I / O1 to I / O16 is ALE = When it is “H” (high level), it is fetched in synchronization with the rising edge of / WE and is recognized as an address. When the write protect signal / WP is at a low level, the flash memory 1 is inhibited from being erased and written.

  The internal control circuit 16 performs interface control according to the access control signal and the like, and controls internal operations such as erase processing, write processing, and read processing according to the input command. The internal control circuit 16 outputs a ready / busy signal R / B. The ready / busy signal R / B is set to a low level during the operation of the flash memory 1, thereby notifying the outside of the busy state. Vcc is a power supply voltage, and Vss is a ground voltage. The high voltage required for the writing process and the erasing process is not particularly limited, but is generated by an internal booster circuit (not shown) based on the power supply voltage Vcc.

<< Memory array using inversion layer for bit line >>
FIG. 2 illustrates the transistor arrangement of the memory array 3. The memory array 3 includes a plurality of rows of circuits in which the first control transistor 20, the memory transistor 21, the second control transistor 22, and the memory transistor 21 are sequentially and repeatedly connected in series. The selection terminal (memory gate) of the memory transistor 21 is connected to the word line WL for each row. The first control transistor 20 is switch-controlled by control signals AG0 and AG2 sequentially for each column. The second control transistor 22 is switch-controlled by the control signals AG1 and AG3 sequentially for each column. In short, the switch states of the first control transistor 20 and the second control transistor 22 are controlled by the control signals AG0 to AG3 every four columns. In short, the channel regions of the control transistors 20 and 22 extend in the column direction together with the gates. Although not particularly limited, the memory transistor 21 on the left side of the control transistor 20 that receives the control signal AG0 is the memory transistor (memory 0) of page 0. The memory transistor 22 adjacent to the left side of the control transistor 20 that receives the control signal AG1 is the memory transistor (memory 1) of page 1. The memory transistor 21 adjacent to the left side of the control transistor 20 that receives the control signal AG2 is used as the page 2 memory transistor (memory 2). The memory transistor 21 adjacent to the left side of the control transistor 22 that receives the control signal AG3 is the memory transistor (memory 3) of page 3. Although the control mode of the control transistors 20 and 22 by the control signals AG1 and AG3 will be described later, it depends on the read, write, and erase operation modes. When the first control transistor 20 and the second control transistor 22 are turned on, inversion layers 23 and 24 are formed in a channel formation region in a column direction intersecting with the series direction. The inversion layers 23 and 24 function as local bit lines and source lines.

  FIG. 3 illustrates a vertical cross-sectional structure along the word line of the device. An insulating film 31 is formed on the main surface of the p-type semiconductor substrate 30, and the first electrode 33 and the second electrode are alternately formed on the insulating film 31 in a first direction (the front and back direction in FIG. 3) at predetermined intervals. A plurality of electrodes 34 are formed. The first electrode 33 and the second electrode 34 are made of, for example, a polysilicon gate electrode material and are used as the gate electrodes of the control transistors 20 and 22. A plurality of third electrodes 35 insulated from the first electrode 33 and the second electrode 34 are formed at a predetermined interval in a second direction (left and right direction in FIG. 3) intersecting the first direction. Furthermore, a charge storage region 36 capable of selectively storing charges directly below the third electrode is formed between the first electrode 33 and the second electrode 34. The third electrode 35 is a memory gate (word line WL) of the memory transistor 21 and is formed of, for example, a polysilicon gate electrode material. The charge storage region 36 is a charge trap region made of, for example, a silicon nitride film or a floating gate electrode made of a polysilicon film. The inversion layers 23 and 24 are selectively induced on the surface of the semiconductor substrate 30. What is indicated by 37 is an insulating film between the charge storage region 36 and the semiconductor substrate 30. A diffusion layer as a high concentration impurity region is not formed between the first control transistor 20, the memory transistor 21, and the second control transistor 22 that are repeatedly arranged in series.

<< Selection mode of readout path >>
FIG. 4 shows a signal path selection mode in the read operation. As described above, the inversion layer 23 functions as a local bit line. The inversion layer 23 is connected to the corresponding global bit lines GLB0 to GBL3. As described above, the inversion layer 24 functions as a local source line. The inversion layer 24 is connected to the corresponding common line CD via the selection switch 41.

  In the read operation, the inversion layer 24 of the second control transistor 22 adjacent to the memory transistor 21 to be read is connected to the circuit ground voltage (0 volts (V)), and the first control transistor 20 A signal path is formed by connecting the inversion layer 23 to a read / write circuit described later. When a determination selection level (for example, 0.29 to 5.4 V) is applied to the word line WL, if the threshold voltage of the memory transistor 21 is lower than that, the current of the inversion layer 23 is drawn, and the threshold of the memory transistor 21 If the voltage is higher than that, current does not flow through the inversion layer 23, and the storage information is read out by detecting whether or not a level change occurs in the inversion layer 23 by a read / write circuit described later. Here, since one memory transistor 21 is assumed to be 4-value storage that holds 2-bit storage information, the determination level is set to a plurality of levels. According to FIG. 4, since the memory transistor 21 adjacent to the right side of the second control transistor 22 is to be read, the control signals AG2 and AG1 are set to the selection level of 4V, and the control signals AG0 and AG3 are set to the non-voltage of 0V. Select level. Although not shown, when the memory transistor 21 adjacent to the left side of the second control transistor 22 is to be read, the control signals AG2 and AG3 are set to a non-selection level of 0V, and the control signals AG0 and AG1 are set to a selection level of 4V. Is done.

<< Selection mode of writing path >>
FIG. 5 illustrates a signal path of a write operation by the cell through write method. In this write operation, the first control transistors 20 on the left and right sides of the write target memory transistor 21 are turned on (strongly inverted) so as to have a relatively large conductance to form the inversion layer 23 (GBL0, GBL1 side). The second control transistor 22 is turned on (weakly inverted) so as to have a relatively small conductance to form the inversion layer 24, and a high voltage is applied to the word line WL to turn on the memory transistor 21, thereby changing the current path. Form. For example, a first potential such as 8V is set to the gate of the first control transistor 20 adjacent to the memory transistor 21 to be written (AG2 = 8V), and the first control transistor 20 on the opposite side is set to the first control transistor 20. A second potential such as 5 V lower than the first potential is set (AG0 = 5 V), and the gate of the second control transistor 22 adjacent to the memory transistor 21 to be written is connected to the first potential. Then, a third potential such as 1V lower than the second voltage is applied (AG1 = 1V). In this state, a potential such as 4.5 V is set in the inversion layer 23 (GBL1 side) adjacent to the memory transistor 21 to be written, and the inversion layer 24 by the second control transistor 22 on the opposite side and the inversion layer 24 A ground potential such as 0 V is applied to the inversion layer 23 (BL0 side) of the first control transistor 20 described above. Thereby, a current flows from the inversion layer 23 on the GBL1 side to the inversion layer 23 on the GBL0 side, but the channel of the memory transistor 21 to be written and the weak inversion layer 24 with a small conductance of the second control transistor 22 adjacent thereto. The electric field concentration is generated between the first and second electrodes, and hot electrons are generated on the surface of the semiconductor substrate by the electric field concentration. The hot electrons are injected into the charge storage region 36 of the memory transistor 21 by the electric field generated by the high potential of the word line WL. . By injecting electrons into the charge storage region 36, the threshold voltage of the memory transistor 21 is increased. In order to suppress the write operation, according to the example of FIG. 5, the voltage applied to the inversion layer 23 on the GBL0 side is set to 2V, and the channel of the memory transistor 21 to be written and the second control transistor 22 adjacent thereto are small. What is necessary is just to suppress the hot electrons which generate | occur | produce by the electric field concentration between the weak inversion layers 24 of conductance. A read / write circuit (not shown) controls writing and write inhibition by controlling a voltage applied to the inversion layer 23 on the GBL0 side based on write data. Whether the threshold voltage has reached the target threshold voltage by the write operation is confirmed by the verify operation. Since the verify operation is performed by selecting the read path described with reference to FIG. 4, in the verify operation, the read / write circuit path reads the stored information through the inversion layer 23 on the GBL1 side, and the result is used as write data for the inversion layer on the GBL0 side. 23 must be reflected in the potential control. This is realized by a selection circuit (described later in detail) that controls connection between the read / write circuit and the global bit line.

  Note that the direction of the write current may be reversed in order to make the memory transistor 21 adjacent to the left of the second control transistor 22 a write target. When the memory transistor between GBL1 and GBL2 is to be written, the control signal AG1 is changed to 0V, AG3 is changed to 1V, and the direction of the write current is controlled by the voltage applied to GBL1 and GBL2. What is necessary is just to replace the position of the possible 2nd control transistor with the even number and the odd number.

  Although not shown in particular, in order to initialize the threshold voltage state of the written memory transistor, the first control transistor 20 and the inversion layers 23 and 24 of the second control transistor 22 have a first voltage such as a circuit ground voltage. 5 is set, the semiconductor substrate is set to the ground potential of the circuit, and a sixth potential such as a negative potential of −18V is set to the word line WL. As a result, electrons move from the charge storage region in the emission direction, and the threshold voltage of the memory transistor 21 is lowered. Details of the erasure process and the write-back process associated therewith will be described later.

<< Selection mode by selection circuit >>
6 to 13 illustrate examples of selection of the inversion layer by the selection circuit. In each figure, the control signal 0 is the control signal AG0, the control signal 1 is the control signal AG1, the control signal 2 is the control signal AG2, the control signal 3 is the control signal AG3, and the memory 0 is the left side of the control signal 0 (control signal AG0). Memory transistor 21 (memory transistor of page 0), memory 1 is memory transistor (memory transistor of page 1) 21 right next to control signal 0 (control signal AG0), and memory 2 is control signal 2 (control signal AG2). The memory transistor on the left side (memory transistor on page 2) 21 and the memory 3 mean the memory transistor on the right side (memory transistor on page 3) 21 of the control signal 2 (control signal AG2).

  Reference numeral 50 is a representative read / write circuit, and 51 is a selection circuit. Each figure shows a connection configuration for one read / write circuit 50 (B) and the inversion layer 23 directly below the four first electrodes corresponding to the read / write circuit 50 (B). A connection configuration when the memory 0 is a read target is shown in FIG. 6, and a connection configuration when the memory 0 is a write target is shown in FIG. A connection configuration when the memory 1 is a read target is shown in FIG. 8, and a connection configuration when the memory 1 is a write target is shown in FIG. A connection configuration when the memory 2 is a read target is shown in FIG. 10, and a connection configuration when the memory 2 is a write target is shown in FIG. A connection configuration when the memory 3 is a read target is shown in FIG. 12, and a connection configuration when the memory 3 is a write target is shown in FIG. As apparent from the selection mode of the inversion layer shown in FIGS. 6 to 13, the selection circuit 51 includes one first read / write circuit 50 and four first control transistors that are successively parallel to each other. The four inversion layers 23 according to the position of the memory transistor from which the stored information is to be read or written out of the memory transistors 21 arranged between the four inversion layers. An inversion layer necessary for processing is selected from the above and connected to the one read / write circuit 50. In short, the selection circuit 51 controls the connection between the read / write circuit 50 and the inversion layer 23 by the first control transistor 20 so that the same read / write circuit 50 is used for reading and writing to the same memory transistor 21.

<Write / read circuit and selection circuit>
FIG. 14 shows the write / read circuit 50 and the selection circuit 51. In FIG. 14, a write / read circuit 50 and a selection circuit 51 select a circuit unit 54 for each of two global bit lines GBL <i>, GBL <i + 1> (i is a positive integer) and adjacent circuit units 54. The writing / reading circuit 50 and the selection circuit 51 are shown as a single unit. If the two components are distinguished, the MOS transistor 55, 56, 57, 72, 73 constitutes the selection circuit 51, and the other circuit components constitute the write / read circuit 50. In the figure, a p-channel MOS transistor is marked with an arrow of its base gate to distinguish it from an n-channel MOS transistor.

  The configuration of the circuit unit 54 will be described. The circuit unit 54 includes a static latch 60 having SLP and SLN as operation power supply nodes. One input / output node is a sense node (SL Sense), and the other input / output node is a reference node (SL Ref). The sense node and the reference node can be connected to external interface terminals IOR <n> and IOS <n> through select MOS transistors 61 and 62 that are switch-controlled by a column selection signal YS, and signals RSAS and RSAR. Are connected to the precharge power supply node FRSA via the sense latch set MOS transistors 63 and 64 which are switch-controlled. In the initialization operation of the sense node and the reference node, the levels of the signals RSAS and RSAR are different, so that the reference node is precharged to approximately half the level of the sense node. The sense node is connected to the circuit ground potential via a sense MOS transistor 65 and a sense enable MOS transistor 66 that is switch-controlled by a signal SENSE. The gate of the sense MOS transistor 65 is coupled to a node 67 reaching the global bit line, and the sense MOS transistor 65 is switch-controlled according to the level of the global bit line to be read, thereby selectively selecting the level of the sense node. Invert to low level. As a result, the static latch 60 can detect and latch the stored information of the memory transistor. The static latch 60 can latch write data from the external interface terminals IOR <n> and IOS <n>.

  The reference node is coupled to a node 69 that reaches the global bit line via an isolation MOS transistor 68 that is switch-controlled by a signal TR. The node 69 is a precharge enable MOS transistor for write inhibition that is switch-controlled by a signal PC. 70 and a write-inhibiting precharge MOS transistor 71 to be connected to a precharge power supply FPC. The MOS transistor 71 is switch-controlled according to the level of the reference node. When the reference node is at the high level when the write data is latched in the static latch 60, the node 69 is charged in advance by the precharge power supply FPC and then reaches the high level of the reference node. If the reference node is at the low level when the static latch 60 latches the write data, the node 69 reaches the low level of the reference node.

  The node 69 is connected to the global bit line GBL <i> via a MOS transistor 72 that is switch-controlled by a signal STR0 <0> and a MOS transistor 56 that is switch-controlled by a signal STR1 <0>. The node 67 is connected to the global bit line GBL <i + 1> via a MOS transistor 73 that is switch-controlled by a signal STR0 <1> and a MOS transistor 57 that is switch-controlled by a signal STR1 <1>. The coupling node between the MOS transistors 56 and 72 in the subsequent circuit unit 54 can be selectively connected to the coupling node between the MOS transistors 57 and 73 in the previous circuit unit 54 via the MOS transistor 55 that is switch-controlled by the signal SLTR. Is done. Nodes 67 and 69 are connected by wiring. Therefore, one static latch 60 can be connected to any one selected from the four global bit lines in accordance with the switch control state of the MOS transistors 55, 56, 57, 72, 73. Corresponding to each of the global bit lines GBL <i> and GBL <i + 1>, read and write bit line precharge MOS transistors 74 and 75 are provided. Bit line precharge MOS transistors 74 and 75 are connected to precharge power sources FRPC <0> and FRPC <1>, and are switch-controlled by signals RPC <0> and RPC <1>.

  Note that a MOS transistor indicated by 76 is turned off when data of the memory Vth “H” is latched in the static latch 60, and generates a signal EC indicating completion of writing of the memory transistor at the time of write verification. Used for

  FIG. 15 shows the read operation timing of the circuit unit 54 in the write / read circuit 50 and the selection circuit 51. When the threshold voltage of the memory transistor 21 to be read is low (memory Vth “L”), the global bit line (GBL) is discharged from the precharge level, and the MOS transistor 65 maintains the off state. The node stays high. On the other hand, when the threshold voltage of the memory transistor 21 to be read is high (memory Vth “H”), the GBL maintains the precharge level, the MOS transistor 65 is inverted to the ON state, and the sense node Is inverted to low level.

  FIG. 16 shows a write operation timing of the circuit unit 54 in the write / read circuit 50 and the selection circuit 51. The source side GBL to which the memory transistor to be selected for writing is connected is set to the ground potential of the circuit in response to the low level of the reference node of the static latch 60 that latches the write data, and the drain side GBL is written by the transistor 74. Precharged to voltage. As a result, a write current flows through the memory transistor 21, and hot electrons generated thereby are injected into the charge storage region of the memory transistor 21. The source side GBL to which the memory transistor that is not selected for writing is connected is charged to the write potential in response to the high level of the reference node of the static latch 60 that latches the write data, and the drain side GBL is charged by the transistor 74. Precharged to the write voltage. As a result, a write current does not flow through the memory transistor 21 and injection of electrons into the charge storage region of the memory transistor 21 is suppressed.

  17 to 24 illustrate connection modes of the inversion layer 23 by the write / read circuit 50 and the selection circuit 51 according to the configuration of FIG. A connection configuration when the memory 0 is a read target is shown in FIG. 17, and a connection configuration when the memory 0 is a write target is shown in FIG. A connection configuration when the memory 1 is a read target is shown in FIG. 19, and a connection configuration when the memory 1 is a write target is shown in FIG. A connection configuration when the memory 2 is a read target is shown in FIG. 21, and a connection configuration when the memory 2 is a write target is shown in FIG. A connection configuration when the memory 3 is a read target is shown in FIG. 23, and a connection configuration when the memory 3 is a write target is shown in FIG.

  In the flash memory 1, when writing to one memory transistor 21, the inversion layer 23 of the adjacent first control transistor 20 is used as one current path, and the adjacent second control transistor 22 and another memory transistor 21 are on the opposite side. The inversion layer 23 formed by the other first control transistor 20 located beyond the other is used as the other current path. According to this cell-through write method, when a write current flows from the memory transistor 21 to the second control transistor 22, the second transistor is used to cause a large electric field concentration between the memory transistor 21 and the second control transistor 22. Only the conductance of 22 needs to be reduced. It is not necessary to reduce the conductance of the inversion layer 23 in the first control transistor 20 that functions as a wiring for flowing a write current. Therefore, it is possible to improve the writing performance for the stored information.

  Further, even when the pair of first control transistors 20 used for supplying the write current is separated from each other as in the cell-through write method, the same read / write circuit 50 is used for reading and writing with respect to the same memory transistor. Since the selection circuit for controlling the connection between the read / write circuit 50 and the inversion layer 23 by the first control transistor 20 is employed so as to use, the write operation by the cell-through write method can be guaranteed.

<Write operation>
A write operation in response to a write command will be described. FIG. 25 shows the distribution of threshold voltages set in the memory cell transistors by the write operation. VW0, VW1, VW2, and VW3 are lower skirt verify voltages corresponding to the stored information “11”, “10”, “00”, and “01” at the time of write verify. VEW0, VEW1, and VEW2 are upper base verify voltages corresponding to the stored information “11”, “10”, and “00” at the time of write verify. The threshold voltage distribution corresponding to the stored information “11”, “10”, “00”, “01” is defined by the upper skirt verify voltage and the lower skirt verify voltage. VRW1, VRW2, and VRW3 are read word line voltages that enable determination of stored information “11”, “10”, “00”, and “01” during a read operation. FIG. 26 shows specific examples of the upper skirt verify voltage, the lower skirt verify voltage, and the read word line voltage in FIG.

  27 to 29 show flowcharts of the write operation. As shown in FIG. 27, when a write command is input with a write address (S1) and subsequently write data is input (S2), the internal control circuit 16 starts a control sequence for the write operation. . First, the write page data is saved from the memory array 3 to the data register 5, and the data corresponding to the write address among the saved data is replaced by the write data (S3).

  Next, the write power supply is turned on (S4), and "01" is written according to the write data held by the data register 5. That is, if the value of every 2 bits of the write data is “01” data, “1” is transferred to the corresponding static latch (SL) 60, otherwise “0” is transferred (S5). Thereafter, the word line (program WL) rises (S6), connection selection of the global bit line GBL (S7), precharging of the selected global bit line GBL (S8), and control transistors (AG) 20, 22 of the control lines. Selection (S9) is performed, a high voltage pulse is applied to the word line raised in S6 for a predetermined period, and hot electrons are injected into the "01" data write target memory transistor 21 (S10). Thereafter, the operation power supply is switched to the verify power supply (S11), and the write target memory transistor is verified using the word line voltage VWV3 (S12). In the verify operation, the memory transistor is selected in units of word lines, and if the memory transistor is in the off state, the latch data of the static latch of the global bit line is inverted, thereby turning off the MOS transistor 76 in FIG. Is done. Failing is performed until all memory transistors to be written with “01” are turned off, and the processes of S6 to S11 are repeated for the memory transistors related to the failure. The voltage of the high voltage pulse applied in S10 is constant at 15V.

  When 01 verification is passed, as shown in FIG. 28, “00” is written according to the write sector data held by the data register 5 this time. That is, if the value of every 2 bits of the write sector data is “00” data, “1” is transferred to the corresponding static latch (SL) 60, otherwise “0” is transferred (S13). Thereafter, the word line is raised (S14), the global bit line GBL connection is selected (S15), the selected global bit line GBL is precharged (S16), and the control transistors 20 and 22 are selected (S17). Thus, a high voltage pulse is applied to the word line started up in S14, and hot electrons are injected into the memory transistor 21 to be written with “00” data (S18). The voltage of the high voltage pulse applied in S18 is 15V. Thereafter, the operation power supply is switched to the verify power supply (S19), and the write target memory transistor is verified using the word line voltage VWV2 (S20). If all the memory transistors to be written with “00” are in the OFF state, the verify pass is made. If not, the process proceeds to S21 to S26, and high voltage pulse application processing by the ISPP (Incremental Step Pulse Programming) method is performed. Continue. The ISPP method is a writing method in which the writing high voltage pulse voltage is increased for each pulse to keep the writing pulse length constant. This is because the amount of increase in the memory threshold voltage for each write pulse application gradually decreases as the cumulative write voltage application time increases, and at the initial stage of the write operation, the higher the pulse voltage, the larger the write variation and the write jump failure. This is because it is likely to occur. Thereby, it is possible to contribute to shortening of the writing time and suppression of writing pop-out failure. When verify fails in S20, the word line is raised (S21), the global bit line GBL connection is selected (S22), and self-boost (S23) is performed by selecting the control transistors 20 and 22, and the word line raised in S21 A high voltage pulse is applied to the memory transistor 21 for writing data “00” for a predetermined period of time to inject hot electrons (S24). Thereafter, the operation power supply is switched to the verify power supply (S25), and the write target memory transistor is verified using the word line voltage VWV2 (S26). Failing is performed until all the memory transistors to which “00” is to be written are turned off, and the processes of S21 to S26 are repeated for the memory transistors related to the failure. The write high voltage pulse applied at S24 is a voltage obtained by adding 13.6 V to a voltage 0.2 times the number of loops, and is increased as the number of loops is increased.

  The reason why the S23 self-boost is adopted is as follows. Since “00” write requires a narrower threshold voltage distribution than “01” write, it is inconvenient to increase the threshold voltage change width by one high voltage pulse application. As a result, the number of verify loops increases, and it is not necessary to pass a large write current compared to “00” write. Further, when the verify fail loop is entered, the high voltage pulse voltage is expected to be lower for “00” writing than for “01” writing, so the number of loops is expected to increase. Therefore, by adopting self boost by the selection operation of the selection transistors 20 and 21 for the inversion layer, the processing time can be shortened by the time required for the global bit line precharge operation.

  When the verify pass is made in S20 and S26, as shown in FIG. 29, "10" is written in accordance with the write sector data held by the data register 5 this time. That is, if the value of every 2 bits of the write sector data is “10” data, “1” is transferred to the corresponding static latch 60, otherwise “0” is transferred (S27). Thereafter, the word line is raised (S28), the global bit line GBL connection is selected (S29), the selected global bit line GBL is precharged (S30), and the control transistors 20 and 22 are selected (S31). As a result, a high voltage pulse is applied to the word line raised in S28 for a predetermined period, and hot electrons are injected into the memory transistor 21 to be written with “10” data (S32). The voltage of the high voltage pulse applied in S32 is 15V. Thereafter, the operation power supply is switched to the verify power supply (S33), and the write target memory transistor is switched. Verification using the word line voltage VWV1 is performed (S34). If all memory transistors to be written with “10” are in the OFF state, the verify pass is made. If not, the process proceeds to S35 to S40, and high voltage pulse application processing by the ISPP (Incremental Step Pulse Programming) method is performed. Continue. When verify fails in S34, the word line is raised (S35), the global bit line GBL connection is selected (S36), the self-boost (S37) is selected by selecting the control transistors 20 and 22, and the word line is raised in S35. A high voltage pulse is applied for a predetermined period to inject hot electrons into the “10” data write target memory transistor 21 (S38). Thereafter, the operating power supply is switched to the verify power supply (S39), and the write target memory transistor is verified using the word line voltage VWV1 (S40). “10” is failed until all the memory transistors to be written are turned off, and the processes of S35 to S40 are repeated for the memory transistors related to the failure. The write high voltage pulse applied in S38 is a voltage obtained by adding 12.6V to a voltage 0.2 times the number of loops, and is increased as the number of loops is increased.

  Finally, the upper skirt level of each threshold voltage distribution of “11” data, “10” data, and “00” data is determined (S41). The word line selection voltages VWE0, VWE1, and VWE2 are used for the determination. If it is not detected that the upper base level is lower than the determination level for all the memory transistors to be written, writing is successful, and if detected, writing fails.

<Erase operation>
An erase operation in response to an erase command will be described. FIG. 30 shows a flowchart of the erase operation. In the erasing operation, first, erasing processing (FN tunnel erasing processing) T1 by FN tunneling in units of word lines for the nonvolatile memory transistor 21 to be processed and verification processing T2 and T3 for the erasing processing are performed. Next, a write process (FN tunnel write process) T4 is performed on the nonvolatile memory transistor 21 to be processed by the FN tunnel in units of word lines. Finally, page-by-page write-back processing T5 to T8 for the processing target nonvolatile memory transistor and verify processing T9 to T16 for the write-back processing are performed. When the number of failures reaches the upper limit in any of the verify processes T3, T10, T12, T14, and T16, the process is abandoned and the forced writing process T17 is performed. The forcible write-in process T17 is a process for forcibly increasing the threshold voltage of the non-volatile memory transistor by the “01” write process so that the non-volatile memory transistor that is normally turned on by over-erasing does not remain. . The operation of applying a high voltage pulse is repeated a specified number of times and verification is not performed. Each process of the erase operation is controlled by the internal control circuit 16 in response to an erase command.

  FIG. 31 is a circuit diagram illustrating a voltage application form in the FN tunnel erase process, and FIG. 32 illustrates a voltage application form in the FN tunnel erase process in a device sectional view. In the FN tunnel erasing process, the erasing target word line (WL) is set to −18 V, the semiconductor substrate 30 is set to 0 V, and electrons are transferred from the charge storage region 36 of the nonvolatile memory transistor 21 through the gate insulating film 31 to the semiconductor substrate 30 by the FN tunnel. The process is to pull out. At this time, the control transistors 20 and 22 are turned off, and the inversion layers 23 and 24 are not formed at all. The string means a partial memory array that can share the inversion layer 23 as a local bit line that can be connected to the global bit line GBL by the control signal STS. In the selected string, although not particularly limited, the unselected word line is set to −2V. The extraction of electrons by the FN tunnel to the substrate does not require a large current to flow, so that power consumption is low. FIG. 39 illustrates the operation timing in the FN tunnel erasing process.

  FIG. 33 is a circuit diagram showing a voltage application form in the FN tunnel writing process, and FIG. 34 is a device sectional view showing a voltage application form in the FN tunnel writing process. The FN tunnel writing process is a process in which the erasing target word line (WL) is 16 V, the semiconductor substrate 30 is 0 V, and electrons are injected from the semiconductor substrate 30 into the charge storage region 36 of the nonvolatile memory transistor 21 by the FN tunnel. . At this time, the control transistors 20 and 22 are turned off, and the inversion layers 23 and 24 are not formed at all. The direction of electron movement is reversed with respect to the FN tunnel erasing process. The injection of electrons through the FN tunnel does not require a large current to flow, so that power consumption is low. In the selected string, although not particularly limited, the unselected word line is set to −2V. FIG. 40 illustrates the operation timing of the FN tunnel writing process.

  FIG. 35 is a circuit diagram illustrating a voltage application form in the write-back process, and FIG. 36 is a device cross-sectional view illustrating the voltage application form in the write-back process. The write back process is realized by the same hot electron injection process as the “11” write. As described above, the write current is flowed using self-boost. That is, according to FIG. 35, the control line AG2 is set to 8V, the level of the inversion layer 23 immediately below it is raised, and hot electrons are generated by the current formed thereby. FIG. 41 illustrates the operation timing of the write-back process together with the FN tunnel write process.

  FIG. 37 is a circuit diagram showing a voltage application form in the erase verify process, and FIG. 38 is a device cross-sectional view showing a voltage application form in the erase verify process. In the data read operation for the erase verify process, in the determination of the upper skirt level of the “11” distribution, the voltage of the word line WL is set to the 11 upper skirt verify voltage VWE0 (eg, 1.30 V) in FIGS. In the determination of the lower skirt level of the “11” distribution, the voltage of the word line WL is set to the 11 lower skirt verify voltage VWV0 (for example, 0.29 V) in FIGS. FIG. 42 illustrates the operation timing of the erase verify process.

  43 to 48 show the state of the threshold voltage distribution which is changed by the erase operation according to the flowchart of FIG.

  The threshold voltage distribution in FIG. 43 is a threshold value voltage distribution when the operation ACT1 by the FN tunnel erasing process T1 is completed. The upper skirt is made equal to or lower than the 11 upper skirt verify voltage VWE0. 11 A non-volatile memory transistor having a threshold voltage equal to or lower than the lower skirt verify voltage VWV0 is a memory transistor in an over-erased state.

  The threshold voltage distribution in FIG. 44 is a threshold voltage distribution obtained by FN tunnel writing. The threshold voltage is raised collectively in units of word lines. The positive high voltage pulse for FN tunnel writing is lower in absolute value than the negative high voltage pulse for FN tunnel erase. It is possible to completely eliminate the possibility that the threshold voltage is excessively written back at the pre-write-back stage and the threshold voltage exceeds the 11 upper skirt verify voltage.

  FIG. 45 is a threshold value voltage distribution when the operation ACT2 by the write-back process T5 for the nonvolatile memory transistor of page 0 (Page 0) is completed. The verify voltage is 11 lower skirt verify voltage VWV0. Since the bottom of the threshold voltage distribution has been raised to some extent by the FN tunnel writing process before entering this process, the number of repetitions or the processing time of the T5 process necessary to realize the threshold voltage distribution of FIGS. Is shortened from the state of FIG. 43 to the case of achieving the state of FIG. FIG. 46 shows a threshold value voltage distribution when the operation ACT3 by the write-back process T6 for the nonvolatile memory transistor of page 1 (Page1) is completed. FIG. 47 shows the threshold voltage distribution when the operation ACT4 by the write-back process T7 for the nonvolatile memory transistor of page 2 (Page 2) is completed. FIG. 48 is a threshold value voltage distribution when the operation ACT5 by the write-back process T8 for the nonvolatile memory transistor of Page 3 is completed. In the case of page 1 to page 3 write-back, the processing time is shortened as in the case of page 0.

  As described above, in the erase operation, the FN tunnel write processing T4 in units of word lines is first performed in the write-back after the FN tunnel erase processing operation (ACT1) in units of word lines. Therefore, the threshold voltage distribution of the nonvolatile memory transistor The lower hem is raised as a whole. Since the page-by-page write-back processing T5 to T16 is performed from this stage, the overall write-back processing time is shortened. In short, the number of high voltage application processes for write back can be reduced.

  By adopting the write process T4 by the FN tunnel as the pre-write-back process, the write-back in units of word lines can be easily performed. This is because it is not necessary to form a current path as in hot electron injection. Instead, the electron injection efficiency is lower than that of hot electron injection. The purpose of the write-back is to increase the threshold voltage of the memory transistor having a high erase speed, in other words, to raise the lower tail of the erase distribution that is too low to the target level. It is necessary to completely eliminate the possibility of overwriting. In this respect, pre-writing back by the FN tunnel is preferable. This is especially true when verification is not performed for the FN write processing S4 in units of word lines.

  Further, as represented by FIG. 5, the memory array configuration in which the non-volatile memory cells of different pages are alternately arranged in series is not suitable for the program processing by hot electron injection in units of word lines. This is because it is impossible to secure a current path for performing hot electron injection in parallel to the nonvolatile memory transistors of the four pages. In this regard, in this array configuration, it is necessary to employ a write process using an FN tunnel as a pre-write back process in units of word lines.

  Although the invention made by the present inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof.

  In the above description, the drain terminal and the source terminal of the memory cell transistor are connected in series, and a voltage is applied to the gate terminal of the transistor connected to the source terminal side of the memory cell to be written to turn it on. The non-volatile memory having the memory array structure using the inversion layer formed in step 1 for the source line and the bit line has been described. The present invention is not limited to this, and a configuration using a diffusion wiring layer instead of the inversion layer may be used. The structure is not limited to the write-through method. A structure having a unique bit line for each column of memory transistors may be used. Further, the nonvolatile memory is not limited to a configuration having a plurality of banks that can operate in parallel. The applied voltage for erasing and writing can be changed as appropriate. The present invention can also be applied to a nonvolatile memory having a memory array structure in which memory cell transistors are connected in parallel to a source line or a bit line. Furthermore, the memory transistor is not limited to multi-value storage such as 4-value storage, and may be binary storage. Furthermore, the configuration is not limited to a configuration in which the erase unit is larger than the write unit. The present invention is also applicable when the erase unit and the write unit are equal. The present invention is not limited to the flash memory, but can be widely applied to an EEPROM and other nonvolatile memories of a storage format. The semiconductor device is not limited to a single memory, but can be widely applied to a system LSI or an LSI (Large Scale Integrated Circuit) such as a microcomputer in which a nonvolatile memory is on-chip.

1 is a block diagram of a flash memory according to an example of the present invention. It is a circuit diagram which illustrates transistor arrangement | positioning of a memory array. It is sectional drawing which illustrates the longitudinal cross-section structure along the word line of a device. It is a circuit diagram which illustrates the selection mode of the signal path in read-out operation. It is a circuit diagram which illustrates the signal path | route of the write-in operation | movement by a cell through write system. It is a circuit diagram which shows a connection form when the memory 0 is made into the reading object as a selection mode of the inversion layer by a selection circuit. It is a circuit diagram which shows the connection form when the memory 0 is made into writing object as a selection mode of the inversion layer by a selection circuit. It is a circuit diagram which shows the connection form when the memory 1 is made into the reading object as a selection aspect of the inversion layer by a selection circuit. It is a circuit diagram which shows the connection form when the memory 1 is made into writing object as a selection aspect of the inversion layer by a selection circuit. It is a circuit diagram which shows a connection form when the memory 2 is made into the reading object as a selection mode of the inversion layer by a selection circuit. It is a circuit diagram which shows the connection form when the memory 2 is made into writing object as a selection mode of the inversion layer by a selection circuit. It is a circuit diagram which shows the connection form when the memory 3 is made into the reading object as a selection mode of the inversion layer by a selection circuit. It is a circuit diagram which shows the connection form when the memory 3 is made into writing object as a selection mode of the inversion layer by a selection circuit. It is a circuit diagram which shows a detailed example of a read / write circuit and a selection circuit. It is a timing chart which shows the read-out operation timing of the circuit unit in a write-read circuit and a selection circuit. 6 is a timing chart showing a write operation timing of a circuit unit in a write / read circuit and a selection circuit. FIG. 15 is a circuit diagram showing a connection mode when the memory 0 is a read target as a connection mode of the inversion layer by the write / read circuit and the selection circuit according to the configuration of FIG. 14; FIG. 15 is a circuit diagram showing a connection mode when the memory 0 is a write target as a connection mode of the inversion layer by the write / read circuit and the selection circuit according to the configuration of FIG. 14; FIG. 15 is a circuit diagram showing a connection mode when the memory 1 is a read target as a connection mode of the inversion layer by the write / read circuit and the selection circuit according to the configuration of FIG. 14; FIG. 15 is a circuit diagram showing a connection mode when the memory 1 is a write target as a connection mode of the inversion layer by the write / read circuit and the selection circuit according to the configuration of FIG. 14; FIG. 15 is a circuit diagram showing a connection mode when the memory 2 is a read target as a connection mode of the inversion layer by the write / read circuit and the selection circuit according to the configuration of FIG. 14; FIG. 15 is a circuit diagram showing a connection mode when the memory 2 is a write target as a connection mode of the inversion layer by the write / read circuit and the selection circuit according to the configuration of FIG. 14; FIG. 15 is a circuit diagram showing a connection mode when the memory 3 is a read target as a connection mode of the inversion layer by the write / read circuit and the selection circuit according to the configuration of FIG. 14; FIG. 15 is a circuit diagram showing a connection mode when the memory 3 is a write target as a connection mode of the inversion layer by the write / read circuit and the selection circuit according to the configuration of FIG. 14; It is explanatory drawing which illustrates distribution of the threshold voltage set to a memory cell transistor by write-in operation. FIG. 26 is an explanatory diagram of a specific example of an upper skirt verify voltage, a lower skirt verify voltage, and a read word line voltage. It is a flowchart of a “01” data write operation. It is a flowchart of a “00” data write operation. It is a flowchart of a “10” data write operation. 10 is a flowchart of an erasing operation. It is a circuit diagram which illustrates the voltage application form in FN tunnel erase processing. It is device sectional drawing which illustrates the voltage application form in FN tunnel erasing processing. It is a circuit diagram which illustrates the voltage application form in FN tunnel write-in processing. It is device sectional drawing which illustrates the voltage application form in FN tunnel write-in processing. It is a circuit diagram which illustrates the voltage application form in a write-back process. It is device sectional drawing which illustrates the voltage application form in a write-back process. It is a circuit diagram which illustrates the voltage application form in a verification process. It is device sectional drawing which illustrates the voltage application form in a verify process. It is an operation | movement timing diagram of FN tunnel erase | elimination process. It is an operation | movement timing diagram of a FN tunnel write process. It is a timing diagram which shows the operation | movement of a write-back process with FN tunnel write-in process. It is an operation | movement timing diagram of a verification process. It is a threshold value voltage distribution when the operation by the FN tunnel erasing process is completed. It is a threshold voltage distribution obtained by FN tunnel writing. It is a threshold value voltage distribution when the operation by the write-back process for the nonvolatile memory transistor of page 0 is completed. It is a threshold value voltage distribution when the operation | movement by the write-back process with respect to the non-volatile memory transistor of a page 1 (Page1) is completed. It is a threshold value voltage distribution when the operation by the write-back process for the nonvolatile memory transistor of Page 2 is completed. It is a threshold value voltage distribution when the operation by the write-back process for the non-volatile memory transistor of Page 3 is completed.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Flash memory 3 Memory array 16 Internal control circuit 20 1st control transistor 21 Memory transistor 22 2nd control transistor 23 Inversion layer 24 Inversion layer WL Word line 31 Insulating film 33 1st electrode 34 2nd electrode 35 3rd Electrode 36 charge storage region 37 insulating film 50 read / write circuit 51 selection circuit 52 diffusion layer (diffusion layer wiring)
60 static latch SL Ref reference node SL Sense sense node

Claims (11)

A plurality of pages each having a plurality of nonvolatile memory transistors assigned to one word line;
The non-volatile memory transistor has a charge storage region, the threshold voltage of the non-volatile memory transistor is lowered by an erasing process for releasing electrons from the charge storage region, and the non-volatile memory transistor is programmed by injecting electrons into the charge storage region. The threshold voltage of the memory transistor is increased,
A control circuit for controlling the erasure process and the program process in response to a command;
In response to the initialization command, the control circuit lowers the upper skirt of the threshold voltage distribution below its target level by erasing processing in units of word lines, and then raises the lower skirt of the threshold voltage distribution higher than the target level. Semiconductor device that performs program processing in units of word lines before performing program processing in units of pages. The erasing process in units of word lines is a process of extracting electrons from the charge storage region through a gate insulating film to a semiconductor substrate,
The word line unit program process is a process of injecting electrons from the semiconductor substrate through the gate insulating film to the charge storage region,
The semiconductor device according to claim 1, wherein the program processing for each page is processing for injecting hot electrons into the charge storage region.   The semiconductor device according to claim 2, wherein the control circuit does not verify the program processing in units of word lines.   The control circuit applies a negative high voltage pulse to the word line with the semiconductor substrate as a ground potential in the erasing process in units of word lines, and sets a semiconductor substrate to the ground potential in the program process in units of word lines as a positive high voltage to the word lines. 4. The semiconductor device according to claim 3, wherein a voltage pulse is applied.   The semiconductor device according to claim 4, wherein the positive high voltage pulse has an absolute value lower than that of the negative high voltage pulse. A plurality of nonvolatile memory transistors sharing the word line are connected in series via a control transistor,
The control transistor has a gate electrode capable of forming an inversion layer extending in a direction crossing the series direction,
Having four gate control lines in which every four gate electrodes are commonly connected in the word line direction;
The control circuit controls the level of the four gate control lines, and conducts the non-volatile memory transistor to the inversion layer of the control transistor adjacent to each other at a ratio of one in four to store the stored information in units of pages. Reading can be performed, and current flows from one to the other through the inversion layers of the control transistors on both sides of the adjacent non-volatile memory transistors at a ratio of two to four, and the hot electrons near one non-volatile memory transistor. 2. The semiconductor device according to claim 1, wherein a program process in units of pages that generates data is enabled, and an inversion layer is not formed in the control transistor in the erase process in units of word lines and the program process in units of word lines. An insulating film formed on the main surface of the semiconductor substrate;
A plurality of first electrodes and second electrodes formed alternately in a first direction at predetermined intervals on the insulating film;
A plurality of third electrodes formed on the insulating film at a predetermined interval in a second direction intersecting with the first direction and insulated from the first electrode and the second electrode;
A charge storage region disposed between the first electrode and the second electrode and capable of selectively storing charges directly below the third electrode;
The word line is a third electrode;
The nonvolatile memory transistor has a charge storage region and a third electrode,
The semiconductor device according to claim 6, wherein the control transistor includes a first electrode or a second electrode. A plurality of nonvolatile memory transistors;
The non-volatile memory transistor has a charge storage region, the threshold voltage of the non-volatile memory transistor is lowered by an erasing process for releasing electrons from the charge storage region, and the non-volatile memory transistor is programmed by injecting electrons into the charge storage region. The threshold voltage of the memory transistor is increased,
A control circuit for controlling the erasure process and the program process in response to a command;
In response to the initialization command, the control circuit lowers the upper skirt of the threshold voltage distribution below the target level by the erasing process, and then hots the lower skirt of the threshold voltage distribution above the target level. A semiconductor device that performs program processing by an FN tunnel before performing program processing by electron injection.   The semiconductor device according to claim 8, wherein the control circuit does not verify the program processing in units of word lines. The erasing process is a process of extracting electrons from the charge storage region through a gate insulating film to a semiconductor substrate,
The semiconductor device according to claim 9, wherein the program processing by the FN tunnel is a processing of injecting electrons from the semiconductor substrate to the charge storage region through a gate insulating film. An insulating film formed on the main surface of the semiconductor substrate;
A plurality of first electrodes and second electrodes formed alternately in a first direction at predetermined intervals on the insulating film;
A plurality of third electrodes formed on the insulating film at a predetermined interval in a second direction intersecting with the first direction and insulated from the first electrode and the second electrode;
A charge storage region disposed between the first electrode and the second electrode and capable of selectively storing charges directly below the third electrode;
The nonvolatile memory transistor has a charge storage region and a third electrode,
9. The semiconductor device according to claim 8, wherein the inversion layer immediately below the first electrode and the inversion layer immediately below the second electrode are used as data lines.

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