JPH10261295A - Nonvolatile semiconductor memory and erasing method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress an erase time from becoming longer with the increasing of the number of erasing by setting a read time based on the number of erasing stored in a number of erasing storage area. SOLUTION: In a NAND type flash memory 13, erasure blocks are selected by receiving the instruction inputted from the outside via an input-output circuit with a command resister 22 and by decoding it with a command detector to supply it to a control circuit and by inputting erasure addresses from the outside via the input-output circuit. Then, a read time is set based on the number of erasing stored in the number of erasing storage area. At this time, data of the number of erasing storage area of respective erasure blocks are transferred to a temporary storage part by a page reading operation. A time setting circuit 31 reads out a page by the value of the state flag retained in this circuit to set the read time. Then, the count value of a counter circuit 33 and the output of the time setting circuit 31 are compared in a comparator circuit 34 and when they coincide in the compared result, a completion signal is outputted.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an electrically writable and erasable nonvolatile semiconductor memory device and an erasing method therefor.

[0002]

2. Description of the Related Art In recent years, various flash memories using a cell transistor having a floating gate structure have been proposed. In this type of flash memory, a thin insulating film of about 10 nm is interposed between a substrate and a floating gate, and writing and erasing are performed by injecting and extracting electrons into and from the floating gate through the insulating film. NO for flash memory
R type and NAND type have already been developed. The NAND flash memory has the advantage that the size of the memory cell can be reduced as compared with the NOR flash memory, and the cost is reduced. In addition, since the NAND flash memory has a small write current at the time of writing, it can simultaneously write several k bits of memory cells, and has a feature that the write speed is high. The above NAND
Various documents are known regarding a flash memory of the type described in, for example, U.S. Pat. S. P. 5,297,
029 describes basic operations such as reading, writing, and erasing.

FIG. 10 is a circuit diagram schematically showing a memory cell in the above-mentioned NAND type flash memory and a circuit section related to a read operation in the vicinity thereof. NAND
Type flash memory, a plurality of memory cells MC1 to MC1
The current paths of MCn are connected in series, and a source select gate (select transistor) ST1 and a drain select gate (select transistor) ST2 are connected to the source end and the drain end of the serially connected current paths, respectively. And a plurality of NAND bundles 11. The source end of the current path in the NAND bundle 11 is connected to the power supply Vss, and the drain end is connected to the bit line BL. Between the bit line BL and the voltage supply source VPR, a current path of a precharge transistor PT which is turned on / off by a signal SA is connected. One end of a current path of a transistor DT that is turned on / off by a signal SB is connected to the bit line BL. The other end of the current path of the transistor DT is connected to a sense amplifier composed of inverters INV1 and INV2. Register circuit 12
It is connected to the.

Although not shown, a plurality of NAND bundles are connected to the bit line BL in the row direction, and a plurality of bit lines are arranged in the column direction. Are connected in the row direction. Then, a precharge transistor PT, a transistor DT, and a sense amplifier register circuit 12 are connected to each bit line as in FIG.

The memory cells MC1 to MC1 in the NAND bundle 11
Word lines WL1 to WLn arranged in a direction orthogonal to the bit lines BL are connected to the control gate of MCn for each row, and the selection lines SGS and SGD are connected to the gates of the selection transistors ST1 and ST2. Connected to each other. When the power supply voltage Vcc is applied to these select lines SGS, SGD, the select transistors ST1, ST2
Are turned on, and a group of NAND bundles arranged in the column direction is selected. Also, the selected word line WLm (m
Is any of 1 to n), the power supply voltage Vcc is applied to the unselected word lines in the NAND bundle, in other words, 0 V is applied to the control gate of the selected memory cell, and the control gate of the unselected memory cell. Are applied with a power supply voltage Vcc. Thus, when the threshold voltage of the selected memory cell is positive, the memory cell is turned on,
When negative, the memory cell is turned off. On the other hand, a control gate of a memory cell of a non-selected NAND bundle,
In addition, 0 V is supplied to the gates of the unselected selection transistors.

In the above configuration, the read operation is performed as shown in the timing chart of FIG.
First, at the start of reading (time t0), the signal SA becomes “H”.
(At this time, the signal SB is at the “L” level), the precharge transistor PT is turned on, the transistor DT is turned off, and the bit line BL is connected to the voltage supply source VP.
Precharged with R. Then, at time t1, the signal SA
Becomes "L" level and the precharge transistor PT
Is turned off at a time t2 until the signal SB goes to the “H” level and the transistor DT turns on, according to the threshold voltage of the selected memory cell (the selected memory cell The potential of the bit line BL changes (depending on the state or the erase state). When the signal SB becomes “H” level at time t2, the transistor DT is turned on, the bit line BL is connected to the sense amplifier register circuit 12, and the potential of the bit line BL is amplified and latched by the sense amplifier register circuit 12. .

When electrons are injected into the floating gate of the selected memory cell MCm (write state), the threshold voltage of the memory cell MCm is high, and the memory cell MCm is kept off. I do.
Therefore, no current flows to the power supply Vss via the NAND bundle selected from the bit line BL, and the potential of the bit line BL does not decrease. On the other hand, when electrons are extracted from the floating gate (erased state), the threshold voltage of the selected memory cell MCm is low, so that the memory cell MCm is turned on (at this time, the non-selected state). The memory cell is also on). Therefore, current flows from the bit line BL to the power supply Vss via the selected NAND bundle, and the potential of the bit line BL decreases. The potential of the bit line BL at time t2 is supplied to the sense amplifier register circuit 12 and latched as storage data of the selected memory cell MCm. Here, the operation until the data stored in the memory cell MCm is latched in the sense amplifier register circuit 12 is defined as a page read operation.

Normally, a sense amplifier register circuit 12 is connected to each bit line BL, and a 16 Mbit N
In the case of an AND type EEPROM, about 2,000 sense amplifier register circuits 12 are arranged. The operation of reading out the data of the memory cells stored in the sense amplifier register circuit 12 to the outside is called a serial read operation, and selectively selects a column gate transistor (not shown) connected to the sense amplifier register circuit 12. When turned on, the contents of the sense amplifier register circuit 12 at a predetermined address can be read out to the outside.

In the above-described NAND flash memory, when writing and erasing operations are repeated, electrons are trapped in the insulating film below the floating gate, and the threshold voltage of the erased memory cell becomes shallow. (Approaching 0 V).
FIG. 12 shows the dependence of the threshold voltage after erasing the memory cell on the number of times of writing and erasing. According to FIG. 12, the threshold voltage of the memory cell after the erasing operation increases from about 100,000 times of writing and erasing, and erasing cannot be performed sufficiently deeply. come. Therefore, if 100
To erase to the same threshold voltage as 100,000 times or less after writing and erasing a million times, it is necessary to lengthen the erasing time. For this reason, in the conventional NAND flash memory, when writing and erasing are repeated up to the wear region of the oxide film of the memory cell, there is a problem that the erasing time is greatly lengthened, and it cannot be used up to 1 million times in practice.

FIG. 13 shows the relationship between the threshold voltage after erasing a memory cell and the page read time. Normally, a bit line has a capacitance of about several pF, and the read time is determined by the speed at which electric charges stored in this capacitance are discharged. This discharge speed depends on the threshold voltage of the memory cell in the erased state. Therefore, if the read speed is set to be slow, it is possible to discharge the bit line capacitance of several pF even with a small cell current, and even a memory cell having a shallow threshold voltage is determined to be in the erased state. Conversely, if the read speed is set to be high, a large cell current is required for discharging the bit line capacitance, and a deep threshold voltage is required to be regarded as an erased state.

As described above, in order to prevent the erasing time from becoming long even after one million writing and erasing operations, the reading time is set so that even a memory cell having a shallow threshold voltage is regarded as being in an erased state. Should be set longer. However, if the reading speed is reduced in advance in accordance with the shallow threshold voltage after one million times of writing and erasing, the access time to the memory chip becomes longer, and N
There is a problem that the performance of the AND type flash memory deteriorates.

[0012]

As described above, in the conventional nonvolatile semiconductor memory device and its erasing method, when writing and erasing operations are repeated, the threshold voltage of the memory cell after erasing becomes shallower, and the erasing time becomes longer. There was a problem that it became significantly longer.

An object of the present invention is to provide a nonvolatile semiconductor memory device and an erasing method which can perform optimal erasing in accordance with the number of times of writing and erasing operations and can suppress the erasing time from being lengthened as the number of erasing operations increases. To provide.

[0014]

According to the present invention, the following means have been taken in order to solve the above-mentioned problems. First of the present invention
A nonvolatile semiconductor memory device according to an aspect includes a plurality of nonvolatile memory cells that can be electrically written and erased, and is divided into a plurality of blocks, and the plurality of nonvolatile memory cells included in the plurality of blocks. A block erase circuit for simultaneously erasing each block, an erase count storage unit for storing the erase count of the nonvolatile memory cell simultaneously erased by the block erase circuit; and A read time setting circuit for setting a read time based on the number of times of erasure stored in the number of times of erasure storage section. According to the first aspect, the number of erase operations performed in the past by the nonvolatile semiconductor storage device is stored in the erase count storage unit,
Since the read time is controlled by the read time setting circuit according to the erase count, the read time can be set according to the write and erase counts of the nonvolatile semiconductor memory device.
It is possible to suppress the erasing time from being lengthened.

In the nonvolatile semiconductor memory device according to the first aspect, preferred embodiments are as follows. (1) The erasure count storage unit includes an erasure count counter that is incremented according to the erasure count. (2) The read time setting circuit extends the page read time with an increase in the number of times of erasure stored in the number of erasures storage section.

A nonvolatile semiconductor memory device according to a second aspect of the present invention comprises: a plurality of nonvolatile memory cells which can be electrically written and erased and are divided into a plurality of blocks;
In a block erase circuit for simultaneously erasing the plurality of nonvolatile memory cells included in the plurality of blocks for each block, and in erase verify read, it is determined that all the nonvolatile memory cells included in the erase block have been sufficiently erased. An erase verify count storage unit for storing the number of times of erase operation and verify operation repeated until
When reading storage data of the nonvolatile memory cell,
A read time setting circuit configured to set a read time based on the number of times of the erase operation and the number of verify operations stored in the erase verify number storage unit. According to this configuration, the number of times of the erasing operation and the verifying operation repeated until it is determined that the nonvolatile memory cell is sufficiently erased is stored in the erasing verifying number storage section, and the erasing operation stored in the erasing verifying number storage section is performed. Since the read time is set by the read time setting circuit based on the number of times of the verify operation, the read time can be set according to the time required for erasure, and the erasure time can be prevented from being lengthened.

In the nonvolatile semiconductor memory device according to a second aspect of the present invention, the read time setting circuit extends a page read time with an increase in the number of erases stored in the erase verify number storage unit. Is preferred.

A nonvolatile semiconductor memory device according to a third aspect of the present invention includes a plurality of nonvolatile memory cells which can be electrically written and erased and are divided into a plurality of blocks.
An erase count storage unit that stores the erase count for each of the plurality of blocks; a sense amplifier circuit that senses and amplifies data of the memory cell via a bit line; and a sense amplifier circuit that is connected to the sense amplifier circuit and stores the erase count. And a current supply circuit for supplying a current of a predetermined value to the bit line in accordance with the number of erases stored in the section.

Preferred embodiments of the nonvolatile semiconductor memory device according to the third aspect of the present invention are as follows. (1) A read time setting circuit for setting a read time based on the number of times of erasure stored in the number of times of erasure storage when reading the storage data of the nonvolatile memory cell is further provided. (2) A read time setting circuit for setting a read time based on the number of times of erasure stored in the number of times of erasure storage when reading data stored in the nonvolatile memory cell is further provided. (3) The read time setting circuit extends the page read time with an increase in the number of times of erasure stored in the number of times of erasure storage section.

In the nonvolatile semiconductor memory device according to the first to third aspects, preferred embodiments are as follows. (1) A memory cell array is formed by arranging the nonvolatile memory cells in a matrix, and the memory cell array has a data storage area for storing normal data and a predetermined numerical value related to the number of times the memory cell has been erased in the past. And an erasure count storage area for storing the Since the number of times of erasing is stored in a part of the memory cell array to store the number of times of erasing, an increase in circuit scale can be suppressed. (2) storing, for each block, a predetermined numerical value related to the number of times the memory cell in each block has been erased in the past; Since the number of erasures is stored for each block, the read time can be finely controlled for each block in accordance with the blocks having a large number of erasures and blocks having a small number of erasures. (3) The read time setting circuit generates a basic pulse for a predetermined time, a counter circuit for counting the number of generations of the pulse, and a predetermined circuit corresponding to the output of the counter circuit and the number of past erases. A comparison circuit that outputs a signal for generating the next basic pulse from the pulse generation circuit if the comparison results in a match, and outputs a read end signal if the comparison results match. (5) The read time setting circuit extends the page read time with an increase in the number of erases stored in the number of erases storage unit. When the nonvolatile memory cell starts to deteriorate and the number of times of erasure increases, the page reading time is extended, so that the erasing time can be suppressed from being lengthened.

According to a fourth aspect of the present invention, there is provided a nonvolatile semiconductor memory device in which electrically writable and erasable nonvolatile memory cells are arranged in rows and columns and a data storage area for storing normal data and a data storage area for storing data in the past. Memory cell array having an erase count storage area for storing whether or not erase has been performed, a row address buffer to which a row address signal is supplied, and decoding an output signal of the row address buffer to store nonvolatile memory cells in the memory cell array. A row decoder selected for each page; a sense amplifier register circuit for amplifying and latching page read data from the nonvolatile memory cell selected by the row decoder;
A column address buffer to which a column address signal is supplied, a column decoder that decodes an output signal of the column address buffer and controls the sense amplifier register circuit, and a row decoder and a column decoder based on a control signal input from the outside. A control circuit for controlling a decoder and a sense amplifier register circuit; and an erase operation control circuit for controlling a page read operation of the sense amplifier register circuit based on the erase count stored in the erase count storage area. Features. The number of erase operations performed in the past by the nonvolatile semiconductor memory device is stored in an erase count storage area provided in a part of the memory cell array, and the page read time of the sense amplifier register circuit is lengthened by the erase operation control circuit in accordance with the erase count. As a result, it is possible to prevent the nonvolatile memory cell from starting to deteriorate and the erasing time from being longer even if the number of erasures is increased.

Further, the above-mentioned nonvolatile semiconductor memory device may further include a voltage generating circuit for generating a high voltage, an intermediate voltage, and a write-protected drain voltage by boosting a power supply voltage and supplying the generated voltage to the memory cell array. preferable. Since the voltage generation circuit is provided, voltages necessary for various operations can be generated inside the chip.

In a nonvolatile semiconductor memory device according to a fifth aspect of the present invention, the nonvolatile semiconductor memory device can be electrically written and erased, and is erased simultaneously by a plurality of nonvolatile memory cells divided into a plurality of blocks and an erase circuit. Storage means for storing a predetermined value corresponding to the number of erasures of the nonvolatile memory cell;
The nonvolatile memory cell includes a bit line connected to one end of a current path of the selected nonvolatile memory cell, and a sense amplifier register for reading data stored in the nonvolatile memory read to the bit line. When reading the data, the data of the number storage means is read first, and the timing of reading the data of the bit line into the sense amplifier register is determined based on the read data.

The nonvolatile semiconductor memory stores a predetermined value corresponding to the number of erase operations performed in the past, and controls the read time in accordance with the predetermined value. In addition, when the erasing operation is performed, it is possible to prevent the erasing time from being lengthened by extending the reading time.

[0025]

Embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a schematic configuration of the nonvolatile semiconductor memory device according to the first embodiment of the present invention. FIG. 1 shows a memory cell array 13, a row decoder 14, a row address buffer 15, a sense amplifier register circuit 16, a column decoder 17, a column address buffer 18, an input / output circuit 19, a control circuit 20, Erase operation control circuit 21 and command register 2
2, a command decoder 23, and a voltage generation circuit 24 are shown.

The memory cell array 13 includes, for example, n memory cells with current paths connected in series, and a source select gate and a drain select gate ( One NAND bundle is formed by the selection transistors), and the NAND bundle is arranged in a matrix.

The row address buffer 15 receives a row address signal (page address) R from the input / output circuit 19.
Add is supplied. The row address signal RAdd captured by the row address buffer 15 is
, And the decoded signal is supplied to the memory cell array 13 via the word line and the selection line. Thereby, one NAND bundle in the memory cell array 13
And the memory cells of one row (one page) in these NAND bundles are selected.

The column address buffer 18 is supplied with a column address signal CAdd from the input / output circuit 19. The column address signal CADd taken into the column address buffer 18 is decoded by the column decoder 17, and the decoded signal drives the sense amplifier register circuit 16. Data read from the memory cell array 13 to the sense amplifier register circuit 16 via the bit lines is output via the input / output circuit 19 in page units.

The command register 22 has an input / output circuit 19
Various commands are input from the outside through the command register 22, and the commands fetched into the command register 22 are decoded by the command decoder 23 and supplied to the control circuit 20. Various control signals are input to the control circuit 20 from the outside. Based on these control signals and the command supplied from the command decoder 23, the sense amplifier register circuit 16, the row decoder 14, the column decoder 17 , The voltage generation circuit 24 and the like are controlled.

The voltage generation circuit 24 boosts the power supply voltage to increase the high voltage VPP (about 20 V), the intermediate voltage VPI (about 10 V),
And a write-inhibited drain voltage VDPI (about 10 V) is supplied to the inside of the chip.

In the present invention, the erase operation control circuit 21 is provided in the control circuit 20. This erase operation control circuit 21
Controls the page read time by controlling the sense amplifier register circuit 16 in accordance with the erase count counted by the erase counter, and extends the page read time when the write and erase operations are performed a predetermined number or more.

FIG. 2 shows the memory cell array 1 shown in FIG.
3 is a block diagram illustrating a configuration example of FIG. The memory cell array 13 has a data storage area and an erase count storage area. The data storage area is an area for storing normal data, and is divided into N blocks. The erase count storage area stores the number of times each block corresponding to the data storage area has been erased in the past.

FIG. 3 is a circuit diagram showing a detailed configuration example focusing on one block in FIG. The basic memory cell configuration of the data storage area and the erasure count storage area is the same as that of a normal NAND flash memory, and only the data to be stored is different. That is, the NAND bundles 26-1, 26 and 26 are formed by connecting the current paths of the selection transistor ST1, the memory cells MC1 to MCn and the selection transistor ST2 in series to each bit line BL1, BL2,. 2,... Are connected. Also, the bit lines BLa, BLb in the erase count storage area
Similarly, the NAND bundles 26a and 26 each formed by connecting the current paths of the select transistor ST1, the memory cells MC1 to MCn and the select transistor ST2 in series are connected in series.
6b is connected. A selection line SGS is connected to the gate of each of the selection transistors ST1 arranged in the same row, and the memory cells MC1 to MC arranged in the same row are connected.
Word lines WL1 to WLn are connected to n control gates, and a select line SGD is connected to each of the select transistors ST2 arranged in the same row. The selection line SGS, the word lines WL1 to WLn, and the selection line S
Each of the GDs is driven by a row decoder 14.

Each of the bit lines BL1, BL2,..., BL
a and BLb are respectively connected to the inverters INV1 and INV.
2 and sense amplifier register circuits 16-1 and 16
−2,..., 16a, 16b are connected. Sense amplifier register circuits 16a and 16 in the erase count storage area
The output of b is supplied to the erase operation control circuit 21. The erase operation control circuit 21 includes a temporary storage unit 27, a data input control circuit 28, and a flag data conversion circuit 29. The outputs of the sense amplifier register circuits 16a and 16b are supplied to the temporary storage unit 27. The output signal of the temporary storage unit 27 is supplied to the data input control circuit 28. The data input control circuit 28 controls the sense amplifier register circuit 16 based on the output signal of the flag data conversion circuit 29 for converting the flag data of the status flag and the output signal of the temporary storage unit 27. When the writing and erasing operations are performed more times, the page reading time is extended.

In the first embodiment, the number of erasures stored in one block of the memory cell array 13 is two.
One NAND bundle is allocated. Assuming that one NAND bundle is composed of 16-bit memory cells, two bits of the 32 bits of the two NAND bundles are allocated for storing read time control data, and the remaining 20 bits are allocated for storing the number of erase times. . The 20 bits for storing the number of times of erasing are rewritten each time erasing is performed. In this, the number of times of erasing is stored as binary information. Further, a flag for defining the read time calculated from the erase count is stored in the two bits for storing the read time control data (two bits for read). For example, in the example shown in FIG. 3, four pieces of information are stored using the memory cells MCa and MCb in two bits for reading. The state where the number of block erasures is 100,000 times is assigned to state 1, the state from 100,000 to 300,000 times is assigned to state 2, the state from 300,000 to 1,000,000 times is assigned to state 3, and the state of 1,000,000 or more is assigned to state 4. The number of erasures is stored by associating up to 4 with the data states of the memory cells MCa and MCb.

Next, a method of storing the number of times of erasing and a control method at the time of reading using the nonvolatile semiconductor memory device thus configured will be described. FIG. 4 is a flowchart showing a sequence of an internal operation when performing block erasure. Normally, in the NAND flash memory, a command input from the outside via the input / output circuit 19 is received by the command register 22 and the command decoder 2
3 and supplies it to the control circuit 20 (step A
1) An erasing address is input from the outside via the input / output circuit 19, and the row address is input to the row address buffer 15.
(Step A2). In order to read the information on the number of times of erasure stored in the selected block, first, a page read operation is performed, and the read data is latched in the sense amplifier register circuits 16a and 16b. This operation is repeated to read a total of 32-bit data from the first page to the Nth page. The page read information is transferred each time to a temporary storage unit 27 for temporarily storing this information, and is held in the primary storage unit 27 until the erasing operation is completed. By repeating this operation for the number of erase blocks, the data in the erase count storage area of each erase block is all transferred to the temporary storage unit 27 (step A3). Next, in the case of a NAND flash, erasing is performed by applying a high voltage pulse to the memory cell for about 5 msec (step A4). After the erase operation, the verify mode operation checks whether or not the threshold voltages of all the memory cells in the selected block have been erased to a predetermined negative threshold voltage (step A).
5). If all memory cells have been erased to a predetermined threshold voltage as a result of the verification, a flag signal is output, and the verification operation ends. On the other hand, when there is a memory cell with insufficient erasure, the flow returns to step A4 to perform the erasing operation again, and the erasure and the verification are repeated until the verify operation is performed to obtain a sufficient erasure state. When it is detected that a sufficient erase state has been obtained as a result of the verification, the erase count of the selected block held in the temporary storage unit 27 is incremented by 1 (step A6), and the erase count storage area of the erased block is incremented. (Step A7). In this case, the incremented erasure count information is written in 20 bits for erasure count storage, and a status flag corresponding to the erasure count is stored in two readout bits (memory cells MCa and MCb). . The flag data conversion circuit shown in FIG. 3 is a circuit that generates flag data based on the one incremented erase count storage information. The output data of the flag data conversion circuit 29 and the one incremented erase count information are data. The signal is input to the input control circuit 28. Based on the output data of the data input control circuit 28, the data of the sense amplifier register in the erase count storage area is set, and the erase count and read time control data are stored in the erase count storage area.

Next, the read sequence will be described with reference to the flowchart of FIG. After the input of the read command (step B1), a page address to be read is input from the outside (step B2). First, the status flag data stored in the N page of the block including the page address is read (step B3). The page read time is determined based on the values of the status flags stored in the memory cells MCa and MCb (step B4). For example, when the status flag is "1", the number of erasures is 100,000 or less.
The erased cell has been sufficiently erased to a predetermined threshold voltage Vth, and the page read time is set to Tr. When the status flag is 2, the number of erasures is 300,000 or less. Therefore, by setting the page read time to 2Tr, which is twice, the memory cell having a shallow threshold voltage can be regarded as "1" data. I do. When the status flags are 3 and 4, the page read time is set to 5Tr and 10Tr, respectively.
, Even a memory cell having a shallower threshold voltage can be regarded as “1” data. afterwards,
The page read operation (step B5) and the serial read operation (step B6) are performed based on the page read time set in step B4.

FIG. 6 shows an example of the configuration of a circuit for setting the page read time in accordance with the value of the status flag described above. FIG. 7 is a timing chart of each signal in the circuit shown in FIG. This circuit includes a time control circuit 31 to which a status flag read from each block is input,
Delay circuit 3 to which page read start signal A is input
2. A counter circuit 3 to which a delay signal from the delay circuit 32 is supplied as a counter increment signal B.
3, the time control circuit 31 and the counter circuit 33
And outputs a trigger signal C of the delay circuit 32 or a page read end signal D.

The delay circuit 32 is triggered by the page read start signal A, and the internal signal becomes high level.
The configuration is such that the internal signal goes low after a predetermined time Tr. In response to the low level of the internal signal, the delay circuit 32 outputs a counter increment signal (pulse signal) B. The count value of the counter circuit 33 is incremented by the signal B. The count number is output from the counter circuit 33. The time control circuit 31 reads out the temporary storage unit 2
7 is a circuit for outputting a numerical value for controlling the page read time Tr in accordance with the value of the status flag stored in 7
When the status flag is "1", "1" is output, when the status flag is "2", "2" is output, and when the status flag is 3, 4, 5, 10 is output. Counter circuit 33
And the value of the time control circuit 31 are compared by the comparison circuit 34. If they do not match, the trigger signal C for activating the delay circuit 32 is output again. If they match, a page read end signal D is output from the comparing circuit 34 instead of the trigger signal C, and the data reading of the bit line is completed. The level of the bit line BL is latched by the sense amplifier register circuit 16. You. For example, as shown in FIG. 6, when the status flag N is four, the page read end signal D is output when the output M of the counter circuit 33 becomes ten.

FIG. 8 is a flowchart for explaining a nonvolatile semiconductor memory device according to a second embodiment of the present invention and a method for erasing the same, and is a flowchart showing an erase sequence. Since the configuration of the present embodiment is the same as that of the first embodiment, illustration and description are omitted.

In the first embodiment, the number of erasures performed in the past is stored in the erasure count storage area to set the page read time, whereas in the second embodiment, the time required for erasure (block (The time until all the memory cells in the memory cell are completely erased) is set to set the page read time. That is, after a command is input (step C1), "1" is set as a count value N in an internal counter that temporarily stores the number of erasures (step C2). Thereafter, the address of the erase block is input to select the erase block (step C3). An erase operation is performed for a predetermined time (step C4), and thereafter, verify is performed to determine whether all memory cells have been erased (step C5). In this verify operation, when an insufficiently erased memory cell is detected, the internal counter is incremented by one (step C6), and re-erase is performed. This erase and verify operation is performed until all the memory cells are erased.
If it is determined in the verify operation that all the memory cells have been erased, a predetermined value based on the count value N of the internal counter is stored in the nonvolatile storage unit (Step C7). As this nonvolatile storage unit, a memory cell adjacent to a normal data storage area may be used, or a nonvolatile memory may be provided in a peripheral circuit other than the data storage area to be realized. . This predetermined value is set, for example, as follows. If the number of times of writing and erasing is less than 100,000, the threshold voltage of the memory cell becomes sufficiently deep by one erasing. Therefore, a sufficient erasing state is detected by the first verification, and the count value N of the internal counter is determined. Indicates "1".
If the number of times of writing and erasing is 100,000 or more and less than 300,000, two times of erasing is required, and the count value N of the internal counter indicates 2. If the number of times of writing and erasing is 300,000 or more and less than 1 million, the number of times of erasing is required to be about 3 to 5 times. Therefore, when the count value N is “1”, “1” is stored in the nonvolatile storage unit,
In the case of "2", "2" is stored. When N is 3 to 5, 5 is stored, and when N is 6 or more, 10 is stored. At the time of reading, the data in the nonvolatile storage unit is read,
By providing this read data instead of the output signal of the time control circuit 31 shown in FIG. 6, the page read time can be set according to the number of erases for each block.

In such a configuration and an erasing method, the total number of times of erasing is not counted, but how many times in a certain time until all the memory cells in the block are completely erased. By counting whether or not the erasing operation has been performed, the total number of erasing operations can be estimated, so that the same operation and effect as those of the first embodiment can be obtained.

FIG. 9 shows a schematic configuration according to the third embodiment in which a current detection type sensing method is employed as the sensing method in the first and second embodiments. In FIG. 9, the same portions as those in FIG. 10 are denoted by the same reference numerals, and detailed description will be omitted.

In FIG. 9, an n-channel transistor NT having a gate supplied with a predetermined constant voltage CV is inserted between the bit line and the sense node A. This transistor N
T functions as an amplifying transistor at the node A.
Further, an n-channel transistor PT is connected to the node A as a load transistor for controlling a current flowing through the memory cell. Further, a transistor DT is connected between the node A and the sense amplifier register circuit 12, as in FIG.

In the prior art, only on / off of the precharge transistor PT was controlled, but in the present invention, the voltage applied to the gate of the load transistor PT is changed by the bias voltage setting circuit 17 to control the load transistor PT. The flowing current is controlled. Since the potential of the node A is determined by the balance between the current flowing through the load transistor PT and the current flowing through the memory cell, the current flowing through the load transistor PT can be changed to cope with a change in the threshold value of the memory cell MC. .

For example, by controlling the gate voltage of the load transistor PT, the current flowing through the load transistor
When the current I1 flowing through the memory cell MC in the erased state is larger than I2, the potential of the node A becomes low. Conversely, when data is written to the memory cell MC and the current I1 flowing through the memory cell MC becomes smaller than I2, the potential of the node A becomes high. In this case, if the current flowing through the load transistor PT is made as small as possible, the erased state can be determined even if the current flowing through the memory cell MC is small. However, load transistor PT
If the current I2 is set to be small, the time required to charge the capacitance of the bit line BL becomes longer, and the page read time becomes longer.

To solve this problem, in the present embodiment, the bias voltage by the bias voltage setting circuit 17 for controlling the gate voltage of the load transistor PT is controlled based on the result of the number of times of writing / erasing. The bias voltage setting circuit 17 receives the status flag data shown in the first and second embodiments, and the bias voltage setting circuit 17 changes the gate voltage of the load transistor PT based on the status flag data. Thereby, the current value I2 of the load transistor PT is controlled. While the number of times of writing / erasing is small, the current value I2 of the load transistor PT is set to be relatively large, but when the number of times of writing / erasing exceeds a predetermined value, the current value I2 of the load transistor PT is set to be small. That is, the gate voltage is set by the bias voltage setting circuit 17 so that the current value I2 of the load transistor PT is set to be relatively large while the number of times of writing / erasing is small. Then, the gate voltage is set such that the current value I2 of the load transistor PT decreases. At the same time, the page read time is set long as in the first and second embodiments. As a result, the problem that the erasing time is extended even if the number of writing / erasing increases is solved.

In the above embodiment, when the number of times of writing and erasing is 300,000 or less, the page reading time Tr
Is set to 2 times, 5 times for 1 million times or less, and 10 times for 1 million times or more. However, this value actually varies depending on the oxide film thickness, oxide film quality, etc. of the memory cell. It is preferable to optimize for each device.

As described above, according to the present invention, it is possible to shorten the erasing time even if the nonvolatile memory cell is deteriorated and cannot be sufficiently erased, thereby extending the life of the nonvolatile semiconductor memory device. it can. The present invention is not limited to the above embodiments of the present invention, and it is needless to say that various modifications can be made without departing from the spirit of the present invention.

[0050]

As described above, according to the present invention, it is possible to perform optimal erasing in accordance with the number of times of writing and erasing operations, and to suppress the erasing time from being prolonged as the number of erasing operations increases. A storage device and a method for erasing the same are obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a schematic configuration of a nonvolatile semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration example of a memory cell array shown in FIG. 1;

FIG. 3 is a circuit diagram showing a detailed configuration example focusing on one block in FIG. 2;

FIG. 4 is a flowchart showing a sequence of an internal operation when performing block erasure;

FIG. 5 is a flowchart showing a read sequence.

FIG. 6 is a circuit diagram showing a configuration example of a circuit for setting a page read time based on a value of a status flag.

FIG. 7 is a timing chart of each signal in the circuit shown in FIG. 6;

FIG. 8 is a flowchart for explaining a nonvolatile semiconductor memory device and a method for erasing the same according to a second embodiment of the present invention, and showing an erase sequence.

FIG. 9 In the first and second embodiments of the present invention,
FIG. 9 is a diagram illustrating a schematic configuration of a third embodiment when a current detection type sensing method is adopted as a sensing method.

FIG. 10 is a circuit diagram schematically showing a memory cell in a NAND flash memory and a circuit portion related to a read operation in the periphery thereof;

11 is a timing chart illustrating a read operation in the circuit illustrated in FIG.

FIG. 12 is a graph showing the dependence of the threshold voltage after erasing a memory cell on the number of times of writing and erasing.

FIG. 13 is a diagram showing a relationship between a threshold voltage after erasing a memory cell and a page read time.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 13 ... Memory cell array 14 ... Row decoder 15 ... Row address buffer 16 ... Sense amplifier register circuit 16-1, 16-2, 16a, 16b ... Sense amplifier register 17 ... Column decoder 18 ... Column address buffer 19 ... I / O circuit 20 ... Control circuit 21 Erase operation control circuit 22 Command register 23 Command decoder 24 Voltage generation circuit 26-1, 26-2, 26a, 26b NAND bundle 27 Temporary storage circuit 28 Data input / output circuit 29 Flag data Conversion circuit 31 Time control circuit 32 Delay circuit 33 Counter circuit 34 Comparison circuit MC1 to MCn Memory cells ST1, ST2 Selection transistors (select gate transistors) WL1 to WLn Word lines SGS, SGD Selection lines BL1, BL2, BLa , BLb ... bit line

Claims (13)

[Claims] A plurality of nonvolatile memory cells which are electrically writable and erasable and are divided into a plurality of blocks; and the plurality of nonvolatile memory cells included in the plurality of blocks are simultaneously erased for each block. A block erase circuit, an erase count storage unit that stores an erase count of the nonvolatile memory cell that is erased simultaneously by the block erase circuit, and when reading storage data of the nonvolatile memory cell,
A non-volatile semiconductor memory device, comprising: a read time setting circuit for setting a read time based on the number of erases stored in the erase number storage unit. 2. The nonvolatile semiconductor memory device according to claim 1, wherein said erase count storage unit includes an erase count counter that is incremented according to the erase count. 3. The nonvolatile semiconductor memory device according to claim 1, wherein said read time setting circuit sets a page read time as the number of erases stored in said erase number storage increases. A nonvolatile semiconductor memory device characterized by being extended. 4. A plurality of nonvolatile memory cells which can be electrically written and erased and are divided into a plurality of blocks, and wherein the plurality of nonvolatile memory cells included in the plurality of blocks are simultaneously erased for each block. A block erase circuit, and an erase verify number storage unit for storing the number of erase operations and verify operations repeated until it is determined that all the nonvolatile memory cells included in the erase block have been sufficiently erased in the erase verify read. When reading the storage data of the nonvolatile memory cell,
A non-volatile semiconductor memory device, comprising: a read time setting circuit that sets a read time based on the number of erase operations and the number of verify operations stored in the erase verify number storage unit. 5. The nonvolatile semiconductor memory device according to claim 4, wherein said read time setting circuit extends a page read time with an increase in the number of erases stored in said erase verify number storage unit. A nonvolatile semiconductor memory device characterized by the above-mentioned. 6. A plurality of nonvolatile memory cells which are electrically writable and erasable and are divided into a plurality of blocks, an erasure count storage unit for storing an erasure count for each of the plurality of blocks, and the memory cell Sensed via the bit line,
A sense amplifier circuit that amplifies, and a current supply circuit that is connected to the sense amplifier circuit and supplies a current of a predetermined value to the bit line according to the number of times of erasing stored in the number of erasing times storage unit. A nonvolatile semiconductor memory device characterized by the above-mentioned. 7. The non-volatile semiconductor memory device according to claim 6, wherein a read time is set based on the number of erasures stored in said number-of-erase-times storage unit when data stored in said non-volatile memory cell is read. A nonvolatile semiconductor memory device further comprising a time setting circuit. 8. The nonvolatile semiconductor memory device according to claim 7, wherein said read time setting circuit extends a page read time as the number of erases stored in said erase number storage increases. A nonvolatile semiconductor memory device characterized by the above-mentioned. 9. The non-volatile semiconductor memory device according to claim 1, wherein said non-volatile memory cells are arranged in a matrix to form a memory cell array, and said memory cell array is configured to store normal data. A non-volatile semiconductor storage device, comprising: a data storage area for storing a memory cell number; 10. The nonvolatile semiconductor memory device according to claim 9, wherein a predetermined numerical value related to the number of times the memory cell in each block has been erased in the past is stored for each block. Non-volatile semiconductor storage device. 11. The nonvolatile semiconductor memory device according to claim 1, wherein said read time setting circuit generates a basic pulse for a predetermined time. A generation circuit, a counter circuit that counts the number of times this pulse is generated, and a comparison between the output of this counter circuit and a predetermined number corresponding to the number of past erasures, and outputs a read end signal if the comparison results match. A comparison circuit that outputs a signal for generating the next basic pulse from the pulse generation circuit if they do not match. 12. An electrically writable and erasable non-volatile memory cell is arranged in a matrix, and has a data storage area for storing normal data and an erasure count storage area for storing how many times data has been erased in the past. A row address buffer supplied with a row address signal; a row decoder for decoding an output signal of the row address buffer to select a nonvolatile memory cell in the memory cell array for each page; Amplifier circuit for amplifying and latching the page read data from the non-volatile memory cell selected by the above, a column address buffer to which a column address signal is supplied, and an output signal of the column address buffer to decode and sense Column decoder to control amplifier register circuit A control circuit for controlling the row decoder, the column decoder, and the sense amplifier register circuit based on a control signal input from the outside; and the sense amplifier register circuit based on the erase count stored in the erase count storage area. And a erase operation control circuit for controlling the page read operation of the nonvolatile semiconductor memory device. 13. A plurality of nonvolatile memory cells which can be electrically written and erased and are divided into a plurality of blocks, and a predetermined number corresponding to the number of erasures of said nonvolatile memory cells simultaneously erased by an erase circuit. Storage means for storing a value, a bit line connected to one end of a current path of a selected nonvolatile memory cell, and a sense amplifier register for reading storage data of the nonvolatile memory read to the bit line. When reading the data stored in the nonvolatile memory cell, first, the data of the number-of-times storage means is read, and the timing of reading the data of the bit line to the sense amplifier register is determined based on the read data. Non-volatile semiconductor storage device.