JP2001035176A - Control method for non-volatile semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a control method for non-volatile semiconductor memory capable of storing a lot of irreversible state changes by making one part of a memory area into one-time PROM (OTP) and writing mark data while making clear a boundary between a write area and a non-write area without occurrence of erroneous write or the like in the OTP area. SOLUTION: One block of a NAND type EEPROM flash memory is set as an OTP block capable of writing data just once and concerning the method for writing the mark data into this OTP block, the OTP block is divided into unit areas for each of bytes per page. Then, the mark data of one byte of all '0' are written while an address is incremented in row direction and switching of a page is performed successively byte by byte.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a control method for an electrically rewritable nonvolatile semiconductor memory (EEPROM), and more particularly to a control method useful when applied to a NAND type EEPROM.

[0002]

2. Description of the Related Art An electrically rewritable EEPROM is known as one of semiconductor memories. Above all, a NAND-type EEPROM in which a plurality of memory cells are connected in series to form a NAND cell has attracted attention as a device that can be highly integrated. One memory transistor of the NAND type EEPROM has an FETMOS structure in which a floating gate (charge storage layer) and a control gate are stacked on a semiconductor substrate via an insulating film. Then, a plurality of memory transistors are connected in series so that adjacent ones share a source and a drain to form a NAND cell, which is connected to a bit line as a unit. Such a NAN
D cells are arranged in a matrix to form a memory cell array.

A memory cell array of a NAND type EEPROM is composed of a plurality of blocks. One block is
If one NAND cell has 16 stages, its NA
It includes 16 word lines for selecting ND cells, and memory cells in a range in which these word lines are continuous. This one block is the minimum unit of batch erasing in the flash memory that performs batch erasing of data. The memory transistor array range of one word line in each block is usually called one page.

[0004]

An EEPROM flash memory can rewrite data in the same manner as a DRAM, and can store data in a nonvolatile manner even when the power is turned off. Therefore, various types of portable electronic devices, memory cards, and other information can be used. Attention is being focused on media applications. Such EEPRO
In the application of the M flash memory, there is a demand to restrict the free rewriting of a part of the memory area and to make an OTP (One Time PROM) in which data can be written only once. For example, such a request arises when copying of music data must be restricted to a certain range in a device including a flash memory system that takes in and transfers music data or the like for which copyright is a problem. Specifically, in a memory system using an EEPROM flash memory, every time an access involving data rewriting of the EEPROM flash memory is executed, the OT is regarded as an irreversible state change of the chip.
There is a demand to store mark data in the P area and allow such irreversible state changes a predetermined number of times. In order to meet such demands, technical developments for converting a part of the EEPROM area into the OTP without greatly changing the configuration of the EEPROM flash memory are currently in progress at various places.

According to the present invention, in a nonvolatile semiconductor memory in which a part of a memory area is converted to OTP, mark data is written without erroneous writing in the OTP area while clearly maintaining a boundary between a written area and an unwritten area. It is an object of the present invention to provide a method of controlling a nonvolatile semiconductor memory which enables writing and storing irreversible state changes.

[0006]

According to the present invention, there is provided a memory cell array in which electrically rewritable nonvolatile memory cells are arranged, and a plurality of pages which are a part of the memory cell array can be written only once. A method of controlling a nonvolatile semiconductor memory set as an allowable state change storage area, wherein the state change storage area is divided into a plurality of unit areas for each page, and is all "1" in an initial state. The page is sequentially switched for each state change in each unit area of the state change storage area, and mark data including at least one "0" is written.

In the present invention, preferably, the memory cell array of the nonvolatile semiconductor memory has a memory transistor array along one control gate line as one page, and a plurality of memories selected by different control gate lines. It is assumed that a range of a plurality of pages forming a NAND cell in which transistors are connected in series is configured as one block which is a minimum unit of data erasing. More preferably, in the memory cell array of the nonvolatile semiconductor memory, a memory transistor in which a floating gate and a control gate are stacked is arranged in a matrix, and an arrangement range of the memory transistor along a control gate line commonly connecting the control gate in a column direction is one. A plurality of memory transistors selected by different control gate lines in the row direction are connected to bit lines via select gates, and
It is assumed that the range of a plurality of pages constituting the D cell is configured as one block which is the minimum unit of data erasure.

According to the present invention, the order of writing the mark data to each unit area of the state change storage area is not changed in the column direction within one page, but rather in the column direction.
The page is switched in the row direction to write the mark data. Nonvolatile semiconductor memory is NAND type EEPROM
Taking M as an example, one page is usually in the range of one word line (ie, one control gate line). If it is assumed that mark data is sequentially written in the column direction in one page of the state change storage area, every time mark data is written to the selected unit area, a stress is applied to a non-selected unit area in the same page. Take it. For this reason, erroneous writing to an unselected unit area is likely to occur. On the other hand, when the mark data is written by switching the unit area selected in the row direction, more units are required until the same stress is applied to the memory transistors in the non-selected unit area as compared with the method of sequentially switching in the column direction. Mark data can be written to the area. Therefore, irreversible storage of the state change with high reliability becomes possible.

In the present invention, preferably, each unit area of the state change storage area has a capacity for a plurality of bits, and the mark data is all "0" multi-bit data equal to the capacity of each unit area. More practically, for example, each unit area has a capacity of 1 byte, and the mark data is 1-byte data of all “0”. When the mark data is composed of a plurality of all "0" bits in this manner, the unit area in the state change storage area where the mark data is to be written is sequentially searched, and the number of "0" bits in each unit area is counted. When the count value exceeds a certain value, it is possible to use a routine for determining that the mark data has already been written. Thus, even if there is some erroneous data in the written area or the unwritten area, the written area and the unwritten area can be reliably determined, and a margin can be provided for the determination.

Further, in the present invention, preferably, in the operation of writing mark data to a predetermined unit area of the state change storage area, the stability of data of an unwritten unit area of an adjacent address is determined, and the determination is made to be unstable. The mark data is written in advance to the written unwritten unit area. As a result, the boundary between the already written area and the unwritten area is always kept clear, and the mark data can be reliably written into the state change storage area. In this case, the stability of the data in the unwritten unit area can be determined by counting the number of bits “0” and determining that the data is unstable when the count value exceeds a certain value. .

[0011]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows the NAN according to the embodiment.
1 shows the overall configuration of a D-type EEPROM flash memory,
FIG. 2 shows a block configuration of the memory cell array 1.
FIG. 3 shows the configuration of one of the blocks Bi. N
One memory transistor (memory cell) MC of the AND type EEPROM flash memory has an FETMOS structure in which a floating gate (charge storage layer) and a control gate are stacked on a semiconductor substrate via an insulating film. Then, a plurality of memory transistors MC are connected in series so that adjacent ones share a source and a drain to form a NAND cell, which is connected to the bit line BL as one unit. Such NAND cells are arranged in a matrix to form the memory cell array 1. Memory cell array 1
Are integratedly formed in a p-type substrate or a p-type well.

As shown in FIG. 3, the drains at one end of the NAND cells arranged in the column direction of the memory cell array 1 are connected to bit lines BL via select gate transistors S1, respectively, and the sources at the other end are also selected. It is connected to a common source line via a gate transistor S2. The control gate of the memory transistor MC and the gate electrodes of the select gate transistors S1 and S2 are connected to the control gate line CG in the column direction of the memory cell array 1, respectively.
0 to CG15, and are commonly connected as select gate lines SG1 and SG2. The control gate lines CG0 to CG15 become the normal word lines WL0 to WL15.

In FIG. 3, 16 memory transistors M
C constitutes a 16-stage NAND. This NAN
The D cell performs data writing / erasing / reading by controlling the voltages of the bit line BL, control gate line CG, and selection gate line SG. All of the plurality of NAND cells in FIG. 3 share a control gate. A group of NAND cells sharing such a control gate is called a normal block, and one block is a minimum unit of data erasing. Usually, several hundred to several thousand blocks are arranged in the cell array 1. The range selected by one control gate line in a block is one page, which is the range in which data can be written or read at once.

As shown in FIG. 1, an address is fetched by an address buffer 4 and is decoded by a row decoder 2 and a column decoder 3 so that a control gate line CG and a bit line BL of the memory cell array 1 are selected. The sense amplifier / data latch 5 senses selected data in the memory cell array 1 and latches write data taken in from the outside via the data buffer 6. The control circuit 7 receives commands and generates various control signals such as a data erase control signal, and controls the voltage generation circuit 8. The voltage generation circuit 8 generates a boosted voltage, a negative voltage, and the like necessary for writing and erasing data.

The operation of the NAND type EEPROM is as follows. A high voltage Vpgm (= about 20 V) is applied to the control gate of the selected memory cell, and an intermediate potential Vpass (= about 10 V) is applied to the control gates of the other memory cells.
And 0 V or a power supply voltage VCC (= approximately 3 to 5 V) is applied to the bit line according to the data. When 0 V is applied to the bit line, the potential is transmitted to the drain and the channel of the selected memory cell, and electrons are injected from the drain to the floating gate. As a result, the threshold value of the selected memory cell shifts in the positive direction. This state is set to, for example, “0”. When VCC is applied to the bit line, electron injection does not occur, so that the threshold does not change and remains negative. This state is the initial state of the memory and is "1". The detailed write operation and principle will be described later.

Data erasure is performed simultaneously on all the memory cells in the selected NAND cell block.
That is, all the control gate lines in the selected cell block are set to 0 V, the bit line BL, the source line, the p-type well (or p-type substrate), the control gate line CG in the non-selected NAND cell block and all the selection lines are selected. A high voltage of about 20 V is applied to the gate line SG. As a result, the electrons of the floating gate become p in all the memory cells in the selected NAND cell block.
The threshold voltage shifts in the negative direction and becomes data "1". In the data read operation, the control gate of the selected memory cell is set to 0V
The control is performed by setting the control gate and the selection gate of the other memory cells to the power supply voltage VCC and detecting whether or not a current flows in the selected memory cell.

In this embodiment, of the plurality of NAND cell blocks Bi of the memory cell array 1, for example, one block B0 indicated by oblique lines in FIG. 2 has an OTP as a state change storage area in which data writing is allowed only once.
It is set as a block, that is, an area where data erasure is disabled. In the OTP block, it is necessary to store mark data indicating an irreversible state change without causing erroneous writing or the like, and a control method therefor is important. The specific control method will be described later.

A fuse circuit is added to the row decoder 2 for each block decoding unit in order to prohibit data erasure for the OTP block. FIG. 4 shows a configuration example of the decoding unit RDi corresponding to the block Bi of the row decoder 2. The row decoder 2 selects a block according to an address input to the chip, transfers a voltage generated in a peripheral circuit to a control gate, a selection gate, and the like, and performs data write, data erase, and data read operations. To achieve. The signal RDEC is a start signal of the row decoder 2 and becomes "H" during a write / erase / read operation. The signal ADDRESS is a block address, and only the block whose address is selected becomes “H”,
The output node NA of the decode gate composed of the ND gate G1 and the inverter I1 becomes "H". That is, the node NA is “H” only in the selected block, and is “L” in the other blocks.

The state of the node NA is inverted via the NMOS transistor QN2, and the state of the node
L. During the data erasing, the latch circuit 41
It is provided to hold an erase selection flag indicating that this block has been selected. That is, for the selected block, the latch circuit 41 sets the node NL = “L”,
The node NR holds “H”. However, the NMOS transistor QN2 is connected via the NMOS transistor QN1.
Grounded via fuse F. Whether or not the fuse F is cut determines whether or not the block is changed to the OTP, and is programmed at the wafer stage. That is, in the block in which the fuse F is cut, the NMO
S transistor QN2 is not grounded and latch circuit 41
Indicates that the erase selection flag (NL =
“L”, NR = “H”) cannot be held. Thus, the block from which the fuse F has been cut is set as an OTP block in which data erasure is prohibited.

The data at node NA and the data at node NR of latch circuit 41 are transferred to transfer gates TG 1 and TG 1 controlled by erase control signal ERASE generated from control circuit 7.
The data is selectively transferred to the node N0 by TG2. That is,
When writing and reading data, ERASE = "L"
At this time, the transfer gate TG1 is turned on and TG2 is turned off, and the data at the node NA is transferred to the node N0. When data is erased, the transfer gate TG1 is turned off,
2 is turned on, and the data at the node NR of the latch circuit 41 is transferred to the node N0.

The output voltage VSE (or VCC) of the voltage generation circuit 8 is changed according to the data at the node N0.
2 to transfer to the signal line N1 // N1 as a complementary signal voltage. That is, in the selected block where N0 = “H”, the PMOS transistor QP1 of the transfer switch 42 is turned off,
P2 is turned on, and N1 = VPP (high voltage for realizing writing / erasing / reading) and / N1 = 0V.
Transfer gates TG3 and TG are provided by these signal lines N1 and / N1.
Are turned on, the drive voltage from the peripheral circuit section bus line is transmitted to the control gate line CG and the selection gate line SG of the memory cell array, and data writing / reading is executed. In an unselected block, N1 = 0V, / N1 = V
It becomes PP, and the peripheral circuit section bus line, the control gate line, and the select gate line are not connected.

More specifically, the data erasing operation will be described focusing on the row decoder of FIG. Before the start of the erasing operation, the reset signal RST is “H”, the NMOS transistor QN3 is turned on, and the latch circuit 41 sets the nodes NL and N
R is in the state of “H” and “L”, respectively. When the erase operation is started, the reset signal RST becomes "L", and the address signal AD according to the address input to the chip.
DRESS is set, and the signal LSET becomes "H" for a certain period of time. In the selected block, the node NA is at “H”. At this time, when the fuse F is in the non-cut state, the node NL is connected to 0 V via the fuse F, so that the nodes NL and NR become “L”,
It becomes "H". On the other hand, in a block in which the fuse F is in a cut state, the node N
L and NR maintain the states of “H” and “L”, respectively. Subsequently, the erase control signal ERASE becomes “H”, and the state of the node NR of the latch circuit 41 is transmitted to the node N0 via the transfer gate TG2. That is, data erasure is performed only on the block whose node NR is at the “H” level.

FIG. 5 is a timing chart during a data write operation. The timing diagram of FIG.
This corresponds to the operation when CG2 is selected from the six control gate lines (word lines). When the write operation starts,
First, as shown in FIG. 6, the bit line BL is charged to 0 V or VCC according to the write data, and the select gate line SG1 becomes VCC. At this time, in the NAND cell corresponding to “0” data writing (NAND cell B in FIG. 6), the memory transistor MC is driven via the select gate transistor S1 driven by the select gate line SG1.
0V is transferred to the channel section of B. On the other hand, in a NAND cell (NAND cell A in FIG. 6) corresponding to "1" data writing (that is, "0" data writing prohibition), the selection gate transistor S1 is connected to VCC-Vt (Vt.
Is turned off after voltage transfer to the threshold voltage of the select gate transistor S1), the channel portion of the memory transistor MCA is connected to the NAN on the “0” data write side.
The floating state becomes higher than that of the D cell.

Subsequently, the selected control gate line CG2 changes from 0V to Vpgm = 20V, and the unselected control gate lines CG1, CG3 to CG15 change from 0V to Vpass = 1.
It becomes 0V. As a result, on the NAND cell B side corresponding to “0” data writing, the channel portion of the selected memory transistor MCB is fixed at 0 V, so that a high voltage is applied to the control gate line CG2,
Because a large potential difference of 20 V is created between the channel parts,
Electrons in the channel portion are injected into the floating gate by a tunnel phenomenon. Thereby, the memory transistor MCB
Shifts the threshold voltage in the positive direction. That is,
“0” data is written.

Similarly, in a non-selected memory transistor such as MCC in the NAND cell B corresponding to “0” data writing, the potential difference between the control gate and the channel portion is 10
Since V is not so large, electron injection to the floating gate does not occur, and the threshold voltage of the memory transistor does not change. On the other hand, on the NAND cell A side corresponding to “1” data writing, the control gate voltage is 0 V because the channel portion of the memory transistor MCA is in a floating state.
Even if the voltage rises to 20V, the potential of the channel also rises due to the capacitive coupling with the control gate, and Vboos
t (〜8 V). For this reason, the potential difference between the control gate and the channel portion becomes about 12 V, and electron injection into the floating gate hardly occurs.
Does not change much. Bus voltage Vpas
Writing does not occur even in a memory transistor driven by another unselected control gate line given s.

FIG. 7 is a timing chart of the data read operation. The bit line BL is charged to VCC in advance. Then, VCC is applied to the selection gate lines SG1 and SG2, and V CC is simultaneously applied to the unselected control gate lines CG1 and CG3 to CG15.
Apply CC, and hold the selected control gate line CG2 at 0V. Thus, whether or not a current flows through the bit line BL is determined according to “0” and “1” of the selected memory transistor, and “0” and “1” can be determined.

In this embodiment, the OTP block is all "1" in the initial state, and as much mark data as possible is written therein. In particular,
As will be described later, for example, mark data of all “0” is sequentially written in units of one byte to store a state change. Therefore, the OTP block is subdivided in the row and column directions, and since only the write operation is repeated in each unit area, there is a high risk of erroneous writing. Therefore, the method of writing mark data in the OTP block is as follows.
It is desirable to use a method that can prevent erroneous writing as much as possible. For that purpose, it is necessary to know under what conditions erroneous writing is likely to occur.

First, under the bias conditions for data write shown in FIG. 6, a memory transistor MCA to which a high voltage is applied to the control gate in NAND cell A to which "1" data is applied, and a NAND cell to which "0" data is applied The voltage state is different from the unselected memory transistor MCC in B, and the condition of the erroneous writing is different, and the erroneous writing is more likely to occur in the former. That is, according to the operation example described above, the selected memory transistor M for writing “1” data
This is because the potential difference between the control gate and the channel of CA is 12 V, which is larger than the potential difference between the control gate and the channel of the non-selected memory transistor MCC in the “0” data write NAND cell B. On the other hand, in the data read operation as shown in FIG. 7, the potential difference between the control gate and the channel portion is usually only about VCC at the maximum, so that the erroneous write phenomenon hardly occurs in the read operation.

Therefore, in order to prevent erroneous writing, the potential difference between the control gate and the channel portion of the selected memory transistor for data writing of "1" should be reduced as much as possible (the voltage at the channel portion should be increased as much as possible). 1 "
Reducing the number of times of data writing is a key point.

Further, in consideration of the order of writing data in one NAND cell, the probability of occurrence of an erroneous writing phenomenon can be reduced by writing data in order from the memory transistor close to the cell source line. This will be described with reference to FIGS. As described above, the voltage of the channel portion of the selected memory transistor for writing "1" data is preliminarily charged from the bit line BL to VCC-Vt and becomes floating, and rises due to capacitive coupling when the voltage of the control gate line rises. . Further, the higher the voltage at the start of the potential rise due to the capacitive coupling (that is, the channel voltage when the control gates are all 0 V) is higher, the higher the ultimate voltage of the channel voltage (the highest value of the channel voltage) is. It is also clear.

FIG. 8 shows a state in which "0" data is written in the memory transistor closest to the cell source line of the NAND cell, and VCC is applied to the select gate line SG1 on the bit line side, and 0 V is applied to all control gates. VCC applied to bit line BL
Is transferred to the channel of the NAND cell. On the other hand, FIG. 9 shows a state in which "0" data is written in the memory transistor closest to the bit line of the NAND cell, and VCC is applied to the select gate line SG1 on the bit line side, and 0 V is applied to all control gates. VCC given to BL is NA
It shows a state of being transferred to the channel of the ND cell.

As shown in FIG. 8, "0" is applied to the memory transistor of the control gate line CG0 closest to the cell source line.
When (Vt (cell) = 1V) is written, all the threshold values Vt (cell) of the remaining memory cells on the bit line side are negative (≦ − (VCC−Vt)) “1” state. Then, the potential of Vcc-Vt can be transferred from the bit line BL to the channels of the remaining memory transistors. On the other hand, as shown in FIG. 9, if "0" data is written in the memory transistor closest to the bit line BL, even if VCC is applied to the bit line BL, the memory transistor in which "0" data has already been written is The channel region of the memory transistor on the source line side is limited by the threshold value 1V of the memory transistor in which "0" data is written, and cannot be precharged, and becomes a floating state of about 0V.

As described above, when "0" is first written to the memory transistor on the bit line side, sufficient pre-charging cannot be performed on the channel of the memory transistor below it. This causes the occurrence of erroneous writing. Therefore,
Performing data writing sequentially from the cell source side so as to always keep the memory transistor on the bit line side of the memory transistor to be written in an unwritten (“1”) state in order to prevent unnecessary erroneous writing Becomes important.

FIG. 10 shows a method of writing mark data to an OTP block in this embodiment in consideration of the above-described viewpoint of preventing erroneous writing. In the case of this embodiment, the OTP block is one block which is the minimum unit of data erasing, and the range of one control gate line CG is one.
The page is composed of 16 pages Page0 to Page15. One page is composed of 528 bytes, and the OTP block is one column in the column direction as shown in the figure.
A unit area for writing mark data is delimited in byte units. Then, “00h”, which is all “0”, is sequentially written in byte units as mark data for storing state changes. OPT block is once "0"
When data is written, the data cannot be returned to "1", and in this embodiment, 528 bytes ×
16 pages = about 8000 irreversible state changes can be stored.

Here, the order of writing the mark data “00h” in 1-byte units into each unit area of the OTP block is as shown by an arrow in FIG. ), (Page0, By
te0) to (Page1, Byte0), (Page2, Byte0), ... in that order. After writing up to (Page15, Byte0), return to page Page0 again, (Page0, Byte1), (Page1, Byte0)
1), (Page2, Byte1),..., While writing the mark data “00h” while incrementing the address in the row direction.

As a writing order of the mark data, in principle, Byte0, Byte1,.
The address is incremented in the column direction like…
It is also possible to move to the next page Page1 when writing of all bytes is completed for page Page0. However, in this method, there is a high probability that many erroneous writings occur before storing a large number of state changes. This will be described below, for example, by focusing on (Page0, Byte527).

By the time the mark data is written to (Page 0, Byte 527), the operation of writing “1” data in which a high voltage is applied to the control gate is repeated 527 times for that memory transistor. This is the same condition when incrementing in the row direction and when incrementing in the column direction. However, when the data is incremented in the column direction, one page has not been completed yet until the mark data is written in (Page0, Byte527). On the other hand, in the writing method of this embodiment, which increments in the row direction, the same location (Page
Before receiving the same stress at 0, Byte 527), a state change of 526 × 16 is already stored.

Therefore, according to this embodiment, it is possible to write a large amount of mark data under the condition that unnecessary stress is not applied to the unwritten memory transistor of the OTP block. In this embodiment, Page 0 corresponds to the control gate line CG 0 closest to the cell source line in the OTP block, and data is written from the cell source line side in the NAND cell in the OTP block. Also in this regard, the probability of erroneous writing is low.

FIG. 11 shows an example of a flowchart for incrementing an address for writing mark data to an OTP block. In step S1, first, the page address Page is compared with the maximum page address PageMAX of the OTP block. The current page address is the maximum page address (in the example of FIG. 10, PageM
If AX = 15), the page address is simply incremented (step S2). If it is determined in step S1 that the current page address is the maximum page address, the process jumps to step S3, where it is determined that the column address Col is equal to or less than the maximum column address ColMAX, and the page address is set to 0 (head). (Return to page) (step S4), and the column address is incremented (step S5). Step S
3, the column address is the maximum column address (FIG. 1)
In the example of 0, if it is Byte 527), it cannot be incremented further in the row direction and the column direction, so that an error ends.

Next, an algorithm for improving the reliability of the write operation of the mark data into the OTP block will be described. As described above, the stress for writing "1" data, that is, while writing the mark data "00h" to a certain byte, stress is applied to other memory transistors, and "1" data is converted to "0" data by a bit. Since there is a possibility of erroneous writing, it is preferable to deal with this. However, this routine may not be necessary depending on the reliability level required in the system or the reliability level of the memory transistor itself.

Here, a method is provided for judging whether or not the byte has been written with the mark data "00h" for realizing an irreversible state change. That is, this is determined based on the number of “0” bits in one byte. Specifically, in this embodiment, 6 bytes in one byte (8 bits)
If there is more than "0" bits, it is determined that the mark data is a written byte. The reason why the reliability is improved by making such a determination will be described below.

In the present invention, it is very important that the boundary between the byte where the mark data "00h" is written and the byte where the mark data is not written is located in the OTP block. If this boundary is ambiguous, the reliability is greatly reduced. For example, let us consider a case where a certain bit of a byte for which mark data has not yet been written has been written to “0” due to stress. In this case, even if only one bit is written, the number of “0” bits in the corresponding byte is not more than 6 bits.
This byte is not determined to be a written byte.

A general characteristic of a flash memory is a data holding characteristic. This is a phenomenon in which “0” data that has been written once returns to “1” due to elapse of time after data writing or the like. Generally, a flash memory retains data by injecting electrons into a region surrounded by an insulator called a floating gate by tunnel current or hot electron injection and changing the threshold value of a memory cell. If the quality of the insulator surrounding the floating gate is poor, the electrons which should have been trapped escape to the outside with the passage of time, and as a result, the "0" write state may return to the "1" state before writing. The counting operation of the number of “0” bits is effective also in this failure mode.

For example, it is assumed that one bit of a certain byte in which the writing of the mark data "00h" has returned to "1". In this case, if the determination is simply made based on whether the corresponding byte is “00h”, the corresponding byte is determined as an unwritten byte. However, if the method of counting the number of bits “0” is used, the number of “0” is reduced from 8 to 7, but the condition of 6 bits or more, which is the criterion, is satisfied. It is normally determined that the byte has been written with mark data. As described above, the method of discriminating the boundary between the unwritten area and the written area by counting the number of “0” in byte units is a method of converting “1” data into “0” data due to stress in the unwritten area of the OTP block. It is possible to provide a margin for both the problem of garbled data and the problem of garbled "0" data to "1" data due to the data retention characteristics in the area where the mark data has already been written. Is dramatically improved.

FIGS. 12 and 13 show a control flow for searching the boundary between the mark data writing area and the unwritten area in the OTP block, that is, an example of a flowchart for checking whether or not the area is a free area. Initialize the row address RowAdd and the column address ColAdd to (Page0, By
The search is started from te0) (step S11). In step S12, it is determined whether or not the maximum column address CMAX has been exceeded. The maximum address in the column direction is By
Since it is te527, there is no need to search for a free address beyond that. In step S13, the number of bits of "0" data in one byte is counted. In step S14, it is checked whether the number of bits Num of "0" in one byte is 6 or more. If the number of bits of "0" is 6 bits or more, the column address is incremented by one address to search for the next column (step S15),
Hereinafter, the same operation of counting the number of bits of “0” is repeated.

If a byte having less than 6 bits of "0" is found in step S14, the process proceeds to step S16 in FIG.
Move to It is determined whether the found column address where “00h” has not been written is the first column (Byte 0), and if it is other than the first column address, it is returned to the address obtained by subtracting one address from the column address. (Step S17), the search in the row direction is started. If the found column address where “00h” has not been written is the first column (Byte 0), it is an area where “00h” has not been written yet, so the current address is (Page 0). , Byte0). At step S18 and below, a search in the row direction is started. First, it is determined whether or not the row address RowAdd is the maximum row address RMAX. Count the number. Then, it is determined whether or not the number of bits Num of “0” is 6 or more (S20), and if YES,
The row address is incremented (step S23),
Returning to step S18, the same operation is repeated thereafter.

If a byte having less than 6 bits of "0" is found in step S20, the byte is determined in step S24 as the current row address CRAdd and column address CCAdd (that is, a byte indicating from where data has not been written). Is done. If it is determined in step S18 that a byte with less than 6 bits of “0” is not found even after searching for the last page (here, Page 31), the process proceeds to step S21. Here, the address in the column direction is the maximum column address CMAX (here, Byte52
In the case of 7), all the bytes of this block are filled with the mark data “00h”.
There is no byte defined as the first address where no data has been written, and the process ends as an error (S2).
5). If the column address is not the last page address, it means that the mark data "00h" has been written up to the last page of a certain column. Is set as the current column address CCAdd.

As described above, the method of searching for the starting address of the address where the mark data is not currently written has been described, but the method is not limited to the above operation example. Simply search from Page0 of the first column to Page31, then Byte1
The search may be performed by incrementing one address at a time so as to search from Page 0 to Page 31 of the above. In addition, mark data "0
Other methods may be used as long as the boundary between the address where 0h "is written and the address where the address is not written can be reliably determined.

Next, a description will be given of a method of writing mark data with high reliability in combination with the above-described method of searching for a boundary area for writing mark data to an OTP block by counting the number of bits of "0" data. According to the above example, consider the case where it is determined that a byte is a written byte if there are 6 or more “0” bits in one byte. Here, it is assumed that "0" is erroneously written in 5 bits out of 8 bits due to the stress described above. Although such a case is rare, it is determined that the byte has not been written according to the above criterion. However, there is only one bit difference from the 6 bits of the criterion. Therefore, the state is "0" for 6 bits or more due to the subsequent application of the stress, and the state is unstable. Leaving such an unstable unwritten area byte is extremely problematic from the viewpoint of reliability.

Therefore, in this embodiment, an unstable unwritten area is not left by the following method. That is, when the mark data is written to a certain byte, the byte to be written next is checked and, for example, 4 bytes are written.
If the data is "0" data for more than one bit, this byte also writes the mark data in advance. Therefore, as an unwritten area to be written next, a state is set such that there are only three or less “0” bits in the initial state.
Until the next write, only the read operation is performed in the OTP block, so that the possibility that “0” suddenly changes from a state of 3 bits or less to a state of 6 bits or more is extremely low.
As described above, when writing the mark data, the state of the area where the mark data is to be written next is determined in advance, and the next unwritten area that is unstable is not left. A high system can be realized.

In view of the above points, a preferred method of writing mark data to a specific OTP block will be described. Basically, the mark data “00h” is written at the current address, that is, at the first address where data has not been written. However, in the present embodiment, a method of improving reliability is adopted. First, the basic concept of how to write mark data will be described with reference to FIG. As described above, what is important in the present invention is that the boundary address between the address where the mark data is written and the address where the mark data is not written becomes clear. The definition of the written address is that there are 6 or more bits of “0”, but the number of bits of “0” data is 5 or more even though the mark data writing is not executed due to stress. Assume that bytes are present. In this case, if the bit number of “0” shifts to 6 in some time, the most important present address may be lost.

A specific description will be given with reference to FIG. Here, the OTP block is currently (Byte
2, page 1) has been written with mark data "00h". In order to observe this boundary condition, the state of the byte indicated as Caution 1 and Caution 2 in FIG. 14 is important. If the state of the byte 1 requiring attention is unstable (for example, the number of bits of “0” is 5), the boundary may move. Bytes described as Needs Attention 2 have the same danger. When searching for the current address, the embodiment in which a search in the column direction is performed first has been described. However, if the byte of caution 2 is unstable (it is easy to shift to a byte where "0" has been written), the boundary can move. There is. Thus, for the current address, the next row address (corresponding to the byte of caution 1) and the next column (corresponding to the byte of caution 2)
The two states have important implications.

Therefore, the present embodiment adopts the following method. That is, when writing mark data to a certain address, the next row address (corresponding to the byte of caution 1) of the same column and the first row address of the next column (corresponding to the byte of caution 2) are unstable. In the state, the mark data is simultaneously written to these bytes. As a boundary of the unstable state, "0" is temporarily defined as 4 bits or more. Therefore, if the number of bits of “0” is 0 to 3, the area is held as the next write area. If the number of bits is 4 or more, the mark is changed before the number of bits of “0” changes to 6 or more and the boundary becomes ambiguous. The data is written.

A more specific method of writing mark data will be described with reference to FIGS. In these figures, the numbers of free areas (unwritten areas) not shaded indicate how many bits are currently “0”. In the case of FIG. 15, it is assumed that the writing of the mark data “00h” has been executed in the byte indicated by the area (A). The write area for the next opportunity is the byte indicated by (B). The number of “0” bits in this byte is zero. Also, the position of (C), which is the first page of the next column, has "0" in the number of bits of 0, and is judged to be in a sufficiently stable state. Therefore, in this state,
The mark data writing process ends.

Consider the case of FIG. It is assumed that the writing of the mark data “00h” is performed on the byte indicated by the area (A). The write area for the next opportunity is the byte indicated by (B). The number of "0" bits in this byte is 4, and it is determined that the byte is in an unstable state. Therefore, at the same time as writing the mark data in (A), the mark data is also written in the position in (B). The byte in the area (C) is in a stable state with the number of bits of “0” being 0, and the position of the area (D), which is the first page of the next column, is also normal, so the mark data writing processing ends here.

Next, consider the case of FIG. Area (A)
Suppose that data is written to the byte indicated by. The byte in the next write area (B) is normal. However, since the position of the area (C), which is the first page of the next column, is in an unstable state, the mark data is also written to the area (C) at the same time. Since the next writing area (D) with respect to this area (C) and the area (E) which is the first page of the next column are also in a stable state, the mark data writing processing is ended here.

FIGS. 18 and 19 show the detailed control flow of the mark data writing described with reference to FIGS. 14 to 17, and the control operation will be described. Step S31
, The address of the byte to be written is set as the current row and column address CRAdd and CCAdd. Then, step S3
In step 2, the writing of the mark data "00h" to the current address is executed. Here, the mark data may be written only to that byte, or the mark data may be written to the area where the writing has already been performed. In step S33, it is confirmed whether or not the writing of the mark data has been normally executed.

If the writing is not completed normally,
The process moves to step S42 in FIG. This step S4
In 2, it is determined whether or not the byte that could not be written is the first page. If writing cannot be performed on the first page, an error ends (step S47). If the byte that could not be written is not the first page, the process moves to step S43. Here, it is determined whether or not the column address has reached the maximum column address CMAX, and if not, an error end (S47). If the column address is less than the maximum column address, the process proceeds to step S44. Here, the column address is incremented, and the row address is returned to the first page. Subsequently, mark data writing is executed in step S45. This processing means that, when writing of a certain byte fails, even if the start address of the next column is marked, the byte that could not be written can be ignored.

In step S46, it is determined whether or not the mark data has been written to the first page. If the mark data has failed, the process ends with an error (S47). If the writing has been executed normally, the routine proceeds to a routine for determining whether or not the next writing area and the first page address of the next column are in an unstable state, that is, step S34 in FIG. Here, it is determined whether or not the current row address ROWAdd is less than the maximum row address RMAX. If the current row address is less than the maximum row address RMAX, the row address is incremented in step S35, and the number of bits of “0” is counted in step S36. . Then, in step S37, it is determined whether or not the number of bits Num of "0" is less than 4 bits. If it is less than 4 bits, it is in a stable state. The process proceeds to step S37 in FIG. If it is in an unstable state, the process returns to step S32, and the mark data is written to the corresponding address to eliminate the unstable state.

In step S38, it is determined whether the current column address ColAdd is less than the maximum column address CMAX. If the current position is at the maximum column address, the step for confirming the first page of the next column is unnecessary, and thus the processing ends. If it is less than the maximum column address, the column address is incremented in step S39, and the row address is returned to the first page.
At 40, the number of "0" bits of the byte is counted. Then, it is determined whether or not the number of “0” bits is less than 4 in step S41, and if YES, it is determined to be in a stable state and the process is terminated. If the unstable state is 4 bits or more, the process returns to step S32 to eliminate the unstable state, and the same processing is repeated.

As described above, according to this embodiment,
Many irreversible state changes due to writing of mark data to the OTP block can be created without largely changing the configuration and the like of the NAND flash memory.

The present invention is not limited to the above embodiment. Although the embodiment has been described by taking the NAND flash memory as an example, the type of the flash memory is not limited to this.
A similar method is applicable to a flash memory having a page write mode such as an AND type or a DINOR type. Further, the present invention is not limited to an EEPROM flash memory, and similarly, a ferroelectric memory (FRAM) capable of storing data in a nonvolatile manner and electrically rewriting data is also referred to in the present invention. Semiconductor memory.

In the embodiment, the size of the OTP area is set to one block which is the minimum unit of data erasing.
A plurality of pages that are a part of one block can be set as an OTP area, and a plurality of blocks can be set as an OTP area. Further, the unit area for writing the mark data in the OTP area does not have to be one byte, and may be an arbitrary plurality of bits. In this case, it is preferable that the number of bits be large to some extent in order to provide a margin for the determination of the boundary area (that is, the determination of the empty area). However, in the case of a flash memory with extremely excellent data retention characteristics and no instability in the boundary area,
The mark data can be 1 bit.

Further, in the embodiment, the setting of the OTP area in the EEPROM is performed by providing a fuse circuit in the row decoder section and performing programming of the fuse circuit. PROM, EPROM, EEP
A ROM or the like can be used. Alternatively, it may be a nonvolatile semiconductor memory in which an OTP area is set in a wafer process.

The memory system to which the present invention is applied includes an ATA card, a compact flash card, a memory card equipped with a controller such as a multimedia card, and the like. This is also effective when an irreversible state change is created for the entire card by utilizing the various state changes. Specifically, if a NAND flash memory is mounted as the mounted flash memory, an irreversible state change can be realized by the method described in this embodiment. At this time, an irreversible state change is set or read using a command unique to the vendor, which is not in the ATA standard protocol in the ATA card or the compact flash. As the vendor unique command, only the address corresponding to the current address in the above embodiment may be read or incremented, or the command system may be such that the OTP block of the above embodiment can be read and written as it is. Good. A
Similar effects can be expected with TA cards, compact flash cards, and multimedia cards even if they are not completely irreversible. For example, even if the current address corresponding to the current address in the above-described embodiment is generated by a random number or the like, it is possible to obtain the same effect as a stochastically irreversible state change.

[0066]

As described above, according to the present invention, in a non-volatile semiconductor memory in which a part of a memory area is made OTP, mark data is written and written in the OTP area without causing erroneous writing or the like. It is possible to provide a nonvolatile semiconductor memory control method capable of storing many irreversible state changes while clarifying the boundary between an area and an unwritten area.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a NAND type EEPROM flash memory used in an embodiment of the present invention.

FIG. 2 is a diagram showing a block configuration of a memory cell array of the flash memory.

FIG. 3 is a diagram showing a specific configuration of a block of the flash memory.

FIG. 4 is a diagram showing a configuration of a row decoder of the flash memory.

FIG. 5 is an operation timing chart of data writing in the flash memory.

FIG. 6 is a diagram showing bias conditions at the time of data writing in the flash memory.

FIG. 7 is an operation timing chart of data reading of the flash memory.

FIG. 8 is a diagram for explaining an example of a preferable data write order in a NAND cell of the flash memory.

FIG. 9 is a diagram for explaining an example of an undesired data write order in a NAND cell of the flash memory.

FIG. 10 is a diagram showing the order of writing mark data to an OTP block in this embodiment.

FIG. 11 is a diagram showing a flow of address increment for writing mark data in the embodiment.

FIG. 12 is a diagram showing a control flow (first half) for searching for a free area of an OTP block in the embodiment.

FIG. 13 is a diagram showing a control flow (second half) for searching for a free area of an OTP block in the embodiment.

FIG. 14 is a diagram illustrating a specific method of writing mark data to an OTP block according to the embodiment.

FIG. 15 is a diagram for explaining an example in which a stable boundary area is held when writing mark data to an OTP block.

FIG. 16 is a diagram for explaining a specific example of resolving an unstable boundary region in writing mark data to an OTP block.

FIG. 17 is a diagram for explaining another specific example of resolving an unstable boundary area in writing mark data to an OTP block.

FIG. 18 is a diagram showing a control flow (first half) of writing mark data to an OTP block in this embodiment.

FIG. 19 is a diagram showing a control flow (second half) of writing mark data to an OTP block in this embodiment.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Memory cell array, 2 ... Row decoder, 3 ... Column decoder, 4 ... Address buffer, 5 ... Sense amplifier /
Data latch, 6 Data buffer, 7 Control circuit, 8
... voltage generating circuit, F ... fuse.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Hiroshi Nakamura 1 Kosuka Toshiba-cho, Saiwai-ku, Kawasaki-shi, Kanagawa F-term in the Toshiba Microelectronics Center Co., Ltd. 5B025 AA02 AD04 AD08 AE08

Claims (7)

[Claims] 1. A memory cell array in which electrically rewritable nonvolatile memory cells are arranged, and a plurality of pages which are a part of the memory cell array are used as a state change storage area in which data writing is allowed only once. A method for controlling a set nonvolatile semiconductor memory, wherein the state change storage area is divided into a plurality of unit areas for each page and is all “1” in an initial state. A method for controlling a nonvolatile semiconductor memory, characterized in that a page is sequentially switched in each unit area for each state change and mark data including at least one “0” is written. 2. The memory cell array of the nonvolatile semiconductor memory, wherein an arrangement range of memory transistors along one control gate line is set to one page, and a plurality of memory transistors selected by different control gate lines are connected in series. 2. The method according to claim 1, wherein a range of a plurality of pages connected to form a NAND cell is configured as one block which is a minimum unit of data erasing. 3. The memory cell array of the nonvolatile semiconductor memory, wherein memory transistors each having a floating gate and a control gate stacked thereon are arranged in a matrix, and an array range of the memory transistors along a control gate line commonly connecting the control gates in a column direction. Is defined as one page, and a plurality of memory transistors, each selected by a different control gate line in the row direction, are connected to a bit line via a selection gate to define a range of a plurality of pages constituting a NAND cell in a minimum unit of data erase. 2. The method for controlling a nonvolatile semiconductor memory according to claim 1, wherein the method is configured as a certain block. 4. A method according to claim 1, wherein each unit area of said state change storage area has a capacity of a plurality of bits, and said mark data is a plurality of all-zero bits data equal to the capacity of each unit area. Item 4. The method for controlling a nonvolatile semiconductor memory according to item 2 or 3. 5. A unit area of the state change storage area is sequentially searched, the number of “0” bits in each unit area is counted, and when the count value exceeds a certain value, the mark data has already been written. 5. The method according to claim 4, wherein the area is determined as an area. 6. In the operation of writing mark data to a predetermined unit area of the state change storage area, the stability of data of an unwritten unit area of an adjacent address is determined.
5. The control method for a nonvolatile semiconductor memory according to claim 4, wherein the writing of the mark data is performed in advance on the unwritten unit area determined to be unstable. 7. The data stability of the unwritten unit area is determined by counting the number of bits of “0” and determining that the data is unstable when the counted value exceeds a certain value. 7. The method for controlling a nonvolatile semiconductor memory according to claim 6, wherein: