JP2007102900A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce the influence of a RTS (Random Telegraph Signal) in accordance with characteristic of a non-volatile memory cell. <P>SOLUTION: A flash memory 1 has a memory array 3 and a control circuit 16. The memory array has a semiconductor substrate 30, a gate insulation film 37, and an electric charge accumulation region 36, and has a plurality of memory transistors in which a threshold value can be changed by injecting or discharging electrons for the electric charge accumulation region. Before stored information is read from the memory transistors, the control circuit applies voltage for rejecting temporarily RTS occurrence cause electrons (B) existing in a RTS depending region (A) consisting of boundaries 37A, 37C and a bulk 37B of the gate insulation film and voltage for catching temporarily the RTS occurrence cause electrons in the RTS depending region to selection terminals of the memory transistors. In the control circuit, undesired variation of the threshold voltage by influence of RTS can be reduced by performing read-out operation while adjusting a state of an electric charges of the RTS depending region. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device including a nonvolatile memory cell that stores information by changing a threshold voltage, and relates to a technique effective when applied to, for example, an electrically rewritable AND flash memory.

  The threshold voltage of a nonvolatile memory cell constituting a flash memory or the like is determined according to the amount of charge stored in the charge storage region. For example, information can be stored by an initialization process (erasing) for emitting electrons (electrons) from the charge accumulation region and a program process (writing) for injecting electrons into the charge accumulation region. When rewriting stored information, for example, by applying an erase high voltage to a word line and extracting electrons toward the substrate by an FN (Fowler-Nordheim) tunnel, the threshold voltage of the nonvolatile memory cell is set in units of word lines. It can be initialized to the erased state. Thereafter, a write high voltage is applied to the word line for the nonvolatile memory cell to be written, a write current is passed through the channel, and hot electrons generated thereby are injected into the charge storage region. The electron injection operation is repeated until the threshold voltage is confirmed to be a predetermined level by verify.

  The flash memory can store information by the difference in threshold voltage of the nonvolatile memory cells. However, it is known that the threshold voltage of the nonvolatile memory cell fluctuates undesirably. For example, the threshold voltage is low or high, and the read information is used to make it possible to determine the stored information during the read operation of the stored information. If the word line voltage is straddled, data corruption will occur.

  In a flash memory, an example of a phenomenon in which the threshold voltage of a nonvolatile memory cell fluctuates undesirably is RTS (random telegraph signal). RTS is a phenomenon in which the threshold voltage is observed to vary greatly depending on whether a small number of electrons are present at the interface between the charge storage region and the gate oxide film.

  In Patent Document 1, when a laminated gate insulating film having an insulating film having a dielectric constant higher than that of the silicon oxide film is formed on the silicon oxide film, interface defects are reduced by adding He gas, and low There is a description of a semiconductor device that achieves consumption, high speed, and high reliability. Further, Patent Document 2 discloses a technique for forming a gate insulating film that is hard to induce defects and has high resistance to hydrogen and moisture by containing fluorine in a metal oxide such as Zr, Hf, or Ti. Is described.

JP 2003-297826 A JP 2002-299614 A

  The present inventor examined the variation of the threshold voltage due to the influence of RTS. As a result, it has been found that the influence of RTS becomes more apparent as semiconductor devices such as flash memories become finer, and cannot be ignored, for example, during a read operation of a 90 nm generation flash memory. In addition, the inventor not only affects the influence of RTS but also changes the threshold voltage according to the characteristics of the nonvolatile memory cell, and further increases the influence of RTS according to the characteristics of the nonvolatile memory cell. I also found.

  In RTS, electrons are temporarily trapped (captured) in a region consisting of the interface between the substrate and the gate insulating film, the gate insulating film, and the interface between the gate insulating film and the charge storage region, and the electrons existing in the region. May be released temporarily. Electrons entering or leaving the region are referred to as RTS generation factors. For the charge storage region that originally stores charges, there are characteristics that electrons can easily escape from the charge storage region and characteristics that electrons can easily enter the charge storage region due to the characteristics of the nonvolatile memory cell. .

  The present inventor has found that it is necessary to consider the influence of RTS together with the characteristic that the threshold voltage of a nonvolatile memory cell changes over time. That is, in the write verify operation, it is considered desirable to eliminate the influence of RTS in the sense that the write state is determined first. On the other hand, in the read operation, it is necessary to consider the influence of RTS in a direction that does not further deteriorate the state in which the threshold voltage of the target nonvolatile memory cell has changed over time, or in a direction that compensates for undesired changes. Become.

  However, in the techniques of Patent Documents 1 and 2, it is only possible to reduce the RTS generation-causing electrons that are undesirably captured due to defects in the gate insulating film, and the RTS depending on the characteristics of the nonvolatile memory cell. No consideration has been given to reducing the effects of.

  An object of the present invention is to provide a semiconductor device capable of reducing the influence of RTS in accordance with the characteristics of a nonvolatile memory cell.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The following is a brief description of an outline of typical inventions disclosed in the present application.

  [1] A semiconductor device according to the present invention includes a memory array (3) and a control circuit (16). The memory array includes a substrate (30), a gate insulating film (37), and a charge storage region (36), and a plurality of nonvolatiles capable of changing a threshold voltage by injecting or emitting electrons to the charge storage region. Having a memory cell (21). The control circuit reads the storage information from the nonvolatile memory cell before the interface between the substrate and the gate insulating film (37A), the gate insulating film, and the interface between the gate insulating film and the charge storage region (37C). In order to temporarily capture RTS-causing electrons in at least one of the interface and the gate insulating film, a voltage for temporarily removing RTS-causing electrons (B) existing in at least one of Is applied to the selection terminal of the nonvolatile memory cell.

  From the above, it is possible to obtain a charge state in which the temporary capture of RTS-causing electrons is suppressed or a charge state in which the temporary exclusion of RTS-causing electrons is suppressed with respect to the respective interfaces and the gate insulating film. Before reading the stored information, the charge states of the respective interfaces and the gate insulating film are aligned to one of two charge states. For this reason, it can suppress that the threshold voltage of a non-volatile memory cell fluctuates randomly by the influence of RTS. Therefore, if the write verify operation and the data read operation are performed by aligning the charge states of the respective interfaces and the gate insulating film according to the characteristics of the nonvolatile memory cell, undesired fluctuations in the threshold voltage due to the influence of RTS are reduced. Can be made.

  [2] A semiconductor device according to the present invention includes a memory array and a control circuit. The memory array includes a substrate, a gate insulating film, and a charge storage region, and includes a plurality of nonvolatile memory cells that can change a threshold voltage by injecting or emitting electrons to the charge storage region. The control circuit includes at least one of an interface between the substrate and the gate insulating film, the gate insulating film, and an interface between the gate insulating film and the charge storage region before the read operation for write verification with respect to the nonvolatile memory cell. A predetermined negative voltage for temporarily eliminating electrons that cause RTS is applied to the selection terminal of the nonvolatile memory cell.

  From the above, before the read operation for write verification, the charge state in which the temporary trapping of the RTS generating factor electrons can be suppressed with respect to the respective interfaces and the gate insulating film. The write state can be determined first without being affected. Therefore, the threshold voltage that becomes the verify pass does not change abruptly.

  [3] A semiconductor device according to the present invention includes a memory array and a control circuit. The memory array includes a substrate, a gate insulating film, and a charge storage region, and includes a plurality of nonvolatile memory cells that can change a threshold voltage by injecting or emitting electrons to the charge storage region. The control circuit includes at least one of an interface between the substrate and the gate insulating film, the gate insulating film, and an interface between the gate insulating film and the charge storage region before the read operation for write verification with respect to the nonvolatile memory cell. A predetermined negative voltage for temporarily eliminating the RTS generation factor electrons existing in the non-volatile memory cell is applied to the selection terminal of the non-volatile memory cell, and before the data read operation to the non-volatile memory cell, A predetermined positive voltage for temporarily capturing RTS-generating electrons is applied to at least one of the interface and the gate insulating film to the selection terminal.

  From the above, before the read operation for write verification, the charge state in which the temporary trapping of the RTS generating factor electrons can be suppressed with respect to the respective interfaces and the gate insulating film. The write state can be determined first without being affected. Therefore, the threshold voltage that becomes the verify pass does not change abruptly. Here, attention is focused on the data read operation in the case where the nonvolatile memory cell has a characteristic that electrons escape from the charge accumulation region due to, for example, aging. At this time, before the data read operation, the respective interfaces and the gate insulating film can be brought into a charge state in which the temporary elimination of RTS-causing electrons is suppressed. In addition, it can be avoided that the threshold voltage is further lowered due to the influence of RTS. Therefore, since the data read operation is performed with the charge states aligned according to the characteristics of the nonvolatile memory cell, it is not further worsened that the threshold voltage of the nonvolatile memory cell decreases due to aging.

  [4] A semiconductor device according to the present invention includes a memory array and a control circuit. The memory array includes a substrate, a gate insulating film, and a charge storage region, and includes a plurality of nonvolatile memory cells that can change a threshold voltage by injecting or emitting electrons to the charge storage region. The control circuit includes at least one of an interface between the substrate and the gate insulating film, the gate insulating film, and an interface between the gate insulating film and the charge storage region before the read operation for write verification with respect to the nonvolatile memory cell. A predetermined negative voltage for temporarily eliminating the RTS generation factor electrons existing in the non-volatile memory cell is applied to the selection terminal of the non-volatile memory cell, and before the data read operation to the non-volatile memory cell, A predetermined negative voltage is applied to the selection terminal for temporarily eliminating RTS-causing electrons present in at least one of the interface and the gate insulating film.

  From the above, before the read operation for write verification, the charge state in which the temporary trapping of the RTS generating factor electrons can be suppressed with respect to the respective interfaces and the gate insulating film. The write state can be determined first without being affected. Therefore, the threshold voltage that becomes the verify pass does not change abruptly. Here, attention is focused on the data read operation in the case where the nonvolatile memory cell has a characteristic that electrons enter the charge storage region due to, for example, aging. At this time, before the data read operation, the respective interfaces and the gate insulating film can be brought into a charge state in which the temporary capture of RTS-causing electrons is suppressed. In addition, it can be avoided that the threshold voltage further increases due to the influence of RTS. Therefore, since the data read operation is performed with the charge states aligned according to the characteristics of the nonvolatile memory cell, the increase in the threshold voltage of the nonvolatile memory cell due to secular change is not further deteriorated.

  [5] A semiconductor device according to the present invention includes a memory array and a control circuit. The memory array includes a substrate, a gate insulating film, and a charge storage region, and includes a plurality of nonvolatile memory cells that can change a threshold voltage by injecting or emitting electrons to the charge storage region. The control circuit includes at least one of an interface between the substrate and the gate insulating film, the gate insulating film, and an interface between the gate insulating film and the charge storage region before the read operation for write verification with respect to the nonvolatile memory cell. A predetermined positive voltage for temporarily capturing RTS generation factor electrons is applied to the selection terminal of the non-volatile memory cell, and before the data read operation for the non-volatile memory cell, each of the interfaces, A predetermined positive voltage for temporarily capturing RTS-generating electrons is applied to at least one of the gate insulating films to the selection terminal.

  As described above, before the read operation for write verification, the charge state in which the temporary removal of the RTS-causing electrons is suppressed can be brought into the respective interfaces and the gate insulating film. The write state can be determined first without being affected. Therefore, the threshold voltage that becomes the verify pass does not change abruptly. Here, in the nonvolatile memory cell, for example, RTS constantly occurs due to material change or further miniaturization, a relatively large number of RTS-generating electrons stay, and electrons in the charge storage region pass away over time. Focus on when the trend is strong. At this time, before the data read operation, the respective interface and the gate insulating film can be brought into a charge state in which the temporary elimination of the RTS-causing electrons is suppressed. The RTS-generating electrons do not escape more than necessary from the respective interfaces and the gate insulating film. Accordingly, since the data read operation is performed with the charge states aligned according to the characteristics of the nonvolatile memory cell, even if the threshold voltage of the nonvolatile memory tends to decrease due to aging, the tendency is influenced by the influence of RTS. There is no further deterioration.

  [6] A semiconductor device according to the present invention includes a memory array and a control circuit. The memory array includes a substrate, a gate insulating film, and a charge storage region, and includes a plurality of nonvolatile memory cells that can change a threshold voltage by injecting or emitting electrons to the charge storage region. The control circuit includes at least one of an interface between the substrate and the gate insulating film, the gate insulating film, and an interface between the gate insulating film and the charge storage region before the read operation for write verification with respect to the nonvolatile memory cell. A predetermined positive voltage for temporarily capturing RTS generation factor electrons is applied to the selection terminal of the non-volatile memory cell, and before the data read operation for the non-volatile memory cell, each of the interfaces, A predetermined negative voltage for temporarily eliminating RTS-causing electrons existing in at least one of the gate insulating films is applied to the selection terminal.

  As described above, before the read operation for write verification, the charge state in which the temporary removal of the RTS-causing electrons is suppressed can be brought into the respective interfaces and the gate insulating film. The write state can be determined first without being affected. Therefore, the threshold voltage that becomes the verify pass does not change abruptly. Here, in the nonvolatile memory cell, RTS constantly occurs due to, for example, material change or further miniaturization, a relatively large number of RTS-generating electrons stay, and electrons enter the charge accumulation region over time. Focus on when the trend is strong. At this time, before the data read operation, the respective interfaces and the gate insulating film can be brought into a charge state in which the temporary capture of RTS-causing electrons is suppressed. RTS generating electrons do not enter the interface and the gate insulating film more than necessary. Therefore, since the data read operation is performed with the charge states aligned according to the characteristics of the nonvolatile memory cell, even if the threshold voltage of the nonvolatile memory tends to increase due to aging, the tendency is caused by the influence of RTS. There is no further deterioration.

  As a specific form of the present invention, the predetermined positive voltage has a voltage value lower than the voltage value of the write pulse voltage. From the above, when capturing the electrons that cause RTS, for example, hot electrons are not generated on the substrate surface, and electrons are not injected into the charge storage region, so that the threshold voltage does not increase undesirably.

  As a specific form of the present invention, the predetermined negative voltage has a voltage value higher than the voltage value of the erasing pulse voltage. From the above, when the electrons that cause RTS are excluded, electrons are not extracted from the charge storage region by, for example, the FN tunnel, so that the threshold voltage is not undesirably lowered.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  That is, the influence of RTS can be reduced according to the characteristics of the nonvolatile memory cell.

<Overall configuration of flash memory>
FIG. 1 illustrates a flash memory. The flash memory 1 is formed on a single semiconductor substrate such as single crystal silicon.

  The flash memory 1 is not particularly limited, but has four memory banks BNK0 to BNK3. Each of the memory banks BNK0 to BNK3 has the same configuration and can be operated in parallel. In the figure, the configuration of the memory bank BNK0 is typically illustrated in detail. The memory banks BNK0 to BNK3 include a flash memory array (ARY) 3, an X decoder (XDEC) 4, a data register (DRG) 5, a data control circuit (DCNT) 6, and a Y address control circuit (YACNT) 7.

  The memory array 3 includes a large number of electrically erasable and writable nonvolatile memory transistors. Although the memory transistor is not particularly limited, the memory transistor has a stacked gate structure in which a memory gate is overlapped with a charge storage region via an insulating film. Each memory transistor stores 2 bits of data. In short, information is stored in four values. The four values are, for example, four values “11”, “10”, “00”, and “01”. The stored information “11” is obtained by an erasing process that is initialization for the memory transistor. The erase process is not particularly limited, but the circuit ground potential is applied to the source, drain, and well of the memory transistor, and a negative high voltage is applied to the memory gate to move the electrons in the charge storage region. Thus, the threshold voltage is lowered. The stored information “10”, “00”, “01” is obtained by the writing process. The writing process is not particularly limited, but a current is passed from the drain to the source of the memory transistor, hot electrons are generated on the substrate surface at the source end, and this is injected into the charge storage region by an electric field due to the high voltage of the memory gate. The threshold voltage is increased. The target threshold voltage is different depending on the stored information “10”, “00”, “01”. In the read process, the bit line is precharged in advance, and the memory information is detected by selecting a memory transistor with a predetermined read determination level as the word line selection level and changing the current flowing in the bit line or the voltage level appearing on the bit line. It is supposed to be a process that makes it possible. The word line selection level differs depending on the storage information “11”, “10”, “00”, “01”. The memory array 3 has a read / write circuit connected to the bit line. The read / write circuit latches the storage information read to the bit line in the read process, and controls the bit line potential according to the write data in the write process.

  FIG. 25 shows the distribution of threshold voltages set in the memory cell transistors by the write operation. VW0, VW1, VW2, and VW3 are lower skirt verify voltages corresponding to the stored information “11”, “10”, “00”, and “01” at the time of write verify. VEW0, VEW1, and VEW2 are upper skirt verify voltages corresponding to the stored information “11”, “10”, and “00” at the time of write verify. The threshold voltage distribution corresponding to the stored information “11”, “10”, “00”, “01” is defined by these upper and lower verify voltages. VRW1, VRW2, and VRW3 are read word line voltages that enable determination of stored information “11”, “10”, “00”, and “01” during a read operation. FIG. 26 shows specific examples of the upper skirt verify voltage, the lower skirt verify voltage, and the read word line voltage in FIG.

  The flash memory array 3 and the data register 5 input / output data. For example, the data register 5 is composed of an SRAM and functions as a buffer for write data to be written to the flash memory array 3 and a buffer for data read from the flash memory array 3.

  The data control circuit 6 controls input / output of data to / from the data register 5. The Y address control circuit 7 performs address control for the data register 5.

  The external input / output terminals I / O 1 to I / O 16 are also used as address input terminals, data input terminals, data output terminals, and command input terminals, and are connected to the multiplexer (MPX) 10. The page address input to the external input / output terminals I / O 1 to I / O 16 is input from the multiplexer 10 to the page address buffer (PABUF) 11, and the Y address (column address) is input from the multiplexer 10 to the Y address counter (YACUNT) 12. Preset. Write data input to the external input / output terminals I / O 1 to I / O 16 is supplied from the multiplexer 4 to the data input buffer (DIBUF) 13. Write data supplied to the data input buffer 13 is input to the data control circuit 6 via an input data control circuit (IDCNT) 14. Read data output from the data control circuit 6 is supplied to the multiplexer 10 via the data output buffer (DOBUF) 15 and output from the external input / output terminals I / O1 to I / O16.

  A part of the command code and the address signal supplied to the external input / output terminals I / O1 to I / O16 are supplied from the multiplexer 10 to the internal control circuit (OPCNT) 16.

  The page address supplied to the page address buffer 11 is decoded by the X decoder 4 and a word line is selected from the memory array 3 according to the decoding result. The Y address counter 12 preset with the Y address supplied to the page address buffer 11 performs address counting with the preset value as a starting point, and supplies the Y address counted to the Y address control circuit 7. The counted Y address is used as an address signal when the write data from the input data control circuit (IDCNT) 14 is written into the data register 5 and when the read data to be supplied to the output buffer 15 is selected from the data register 5. The The Y address supplied to the page address buffer 11 is equal to the head address of the counted Y address. This head Y address is referred to as an access head Y address.

  The control signal buffer (CSBUF) 18 includes a chip enable signal / CE, a command latch enable signal CLE, an address latch enable signal ALE, a write enable signal / WE, a read enable signal / RE, and a write protect signal as external access control signals. / WP, power on read enable signal PRE, and reset signal / RES are supplied. The symbol “/” attached to the head of a signal means that the signal is low enable.

  The chip enable signal / CE is a signal for selecting the operation of the flash memory 1, and the flash memory (device) 1 is activated (operable) at a low level, and the flash memory 1 is set to standby (operation stopped) at a high level. The The read enable signal / RE controls the data output timing from the external input / output terminals I / O1 to I / O16, and data is read in synchronization with the clock change of the signal. The write enable signal / WE instructs the flash memory 1 to fetch the command, address, and data at the rising edge. The command latch enable signal CLE is a signal for designating data supplied from the outside to the external input / output terminals I / O1 to I / O16 as a command, and the data of the output terminals I / O1 to I / O16 is CLE = "H". At (high level), it is taken in synchronization with the rising edge of / WE and recognized as a command. The address latch enable signal ALE is a signal for instructing that the data supplied from the outside to the external input / output terminals I / O1 to I / O16 is an address, and the data of the output terminals I / O1 to I / O16 is ALE = When it is “H” (high level), it is fetched in synchronization with the rising edge of / WE and is recognized as an address. When the write protect signal / WP is at a low level, the flash memory 1 is prohibited from being erased and written.

  The internal control circuit 16 performs interface control according to the access control signal and the like, and controls internal operations such as erase processing, write processing, and read processing according to the input command. The internal control circuit 18 outputs a ready / busy signal R / B. The ready / busy signal R / B is set to a low level during the operation of the flash memory 1, thereby notifying the outside of the busy state. Vcc is a power supply voltage, and Vss is a ground voltage. A high voltage necessary for the writing process and the erasing process is generated by an internal booster circuit (not shown) based on the power supply voltage Vcc.

<< Memory array using inversion layer for bit line >>
FIG. 2 illustrates the transistor arrangement of the memory array 3. The memory array 3 includes a plurality of rows of circuits in which the first control transistor 20, the memory transistor 21, the second control transistor 22, and the memory transistor 21 are sequentially and repeatedly connected in series. The selection terminal (memory gate) of the memory transistor 21 is connected to the word line WL for each row. The first control transistor 20 is switch-controlled by control signals AG0 and AG2 sequentially for each column. The second control transistor 22 is switch-controlled by the control signals AG1 and AG3 sequentially for each column. In short, the switch state is controlled by the control signals AG0 to AG3 for a total of four control transistor rows of the first control transistor 20 and the second control transistor 22. Although the control mode will be described later, it follows the operation mode of reading, writing, and erasing. When the first control transistor 20 and the second control transistor 22 are turned on, inversion layers 23 and 24 are formed in a direction crossing the series direction. The inversion layers 23 and 24 function as local bit lines and source lines.

  FIG. 3 illustrates a vertical cross-sectional structure along the word line of the device. An insulating film 31 is formed on the main surface of the p-type semiconductor substrate 30, and the first electrode 33 and the second electrode are alternately formed on the insulating film 31 in a first direction (the front and back direction in FIG. 3) at predetermined intervals. A plurality of electrodes 34 are formed. The semiconductor substrate 30 is a p-type silicon substrate provided with a p-type well region, and a source and a drain are formed in the p-type well region. A channel formation region is formed between the source and the drain. The first electrode 33 and the second electrode 34 are formed of, for example, a polysilicon gate electrode material and are used as the gate electrodes of the control transistors 20 and 22. A plurality of third electrodes 35 insulated from the first electrode 33 and the second electrode 34 are formed at a predetermined interval in a second direction (left and right direction in FIG. 3) intersecting the first direction. Furthermore, a charge storage region 36 capable of selectively storing charges directly below the third electrode is formed between the first electrode 33 and the second electrode 34. The third electrode 35 is a memory gate (word line WL) of the memory transistor 21 and is formed of, for example, a polysilicon gate electrode material. The charge storage region 36 is a charge trap region made of, for example, a silicon nitride film or a floating gate electrode made of a polysilicon film. The inversion layers 23 and 24 are selectively induced on the surface of the semiconductor substrate 30. What is indicated by 37 is a gate insulating film between the charge storage region 36 and the semiconductor substrate 30. Examples of the gate insulating film 37 include a silicon oxide film and a film containing other predetermined metal oxide. If the semiconductor substrate 30 and the charge storage region 36 can be insulated, the gate insulating film 37 may be an oxide film. Not limited. A diffusion layer as a high concentration impurity region is not formed between the first control transistor 20, the memory transistor 21, and the second control transistor 22 that are repeatedly arranged in series.

<< Selection mode of readout path >>
FIG. 4 shows a signal path selection mode in the read operation. As described above, the inversion layer 23 functions as a local bit line. The inversion layer 23 is connected to the corresponding global bit lines GLB0 to GBL3 via the selection switch 40. As described above, the inversion layer 24 functions as a local source line. The inversion layer 24 is connected to the corresponding common line CD via the selection switch 41.

  In the read operation, the inversion layer 24 of the second control transistor 22 adjacent to the memory transistor 21 to be read is connected to the circuit ground voltage (0 volts (V)), and the first control transistor 20 A signal path is formed by connecting the inversion layer 23 to a read / write circuit described later. When a determination selection level (for example, 0.29 to 5.4 V) is applied to the word line WL, if the threshold voltage of the memory transistor 21 is lower than that, the current of the inversion layer 23 is drawn, and the threshold of the memory transistor 21 If the voltage is higher than that, the current does not flow through the inversion layer 23, and the stored information is read out by detecting whether a level change occurs in the inversion layer 23 by a read / write circuit described later. Here, since one memory transistor 21 is assumed to be 4-value storage that holds 2-bit storage information, the determination level is set to a plurality of levels. According to FIG. 4, since the memory transistor 21 adjacent to the right side of the second control transistor 22 is to be read, the control signals AG2 and AG1 are set to the selection level of 4V, and the control signals AG0 and AG3 are set to the non-voltage of 0V. Select level. Although not shown, when the memory transistor 21 adjacent to the left side of the second control transistor 22 is to be read, the control signals AG2 and AG3 are set to a non-selection level of 0V, and the control signals AG0 and AG1 are set to a selection level of 4V. Is done.

<< Selection mode of writing path >>
FIG. 5 illustrates a signal path of a write operation by the cell through write method. In this write operation, the first control transistors 20 on the left and right sides of the write target memory transistor 21 are turned on (strongly inverted) so as to have a relatively large conductance to form the inversion layer 23 (GBL0, GBL1 side). The second control transistor 22 is turned on (weakly inverted) so as to have a relatively small conductance to form the inversion layer 24, and a high voltage is applied to the word line WL to turn on the memory transistor 21, thereby changing the current path. Form. For example, a first potential such as 8V is set to the gate of the first control transistor 20 adjacent to the memory transistor 21 to be written (AG2 = 8V), and the first control transistor 20 on the opposite side is set to the first control transistor 20. A second potential such as 5 V lower than the first potential is set (AG0 = 5 V), and the gate of the second control transistor 22 adjacent to the memory transistor 21 to be written is connected to the first potential. Then, a third potential such as 1V lower than the second voltage is applied (AG1 = 1V). In this state, a potential such as 4.5 V is set in the inversion layer 23 (GBL1 side) adjacent to the memory transistor 21 to be written, and the inversion layer 24 by the second control transistor 22 on the opposite side and the inversion layer 24 A ground potential such as 0 V is applied to the inversion layer 23 (BL0 side) of the first control transistor 20 described above. Thereby, a current flows from the inversion layer 23 on the GBL1 side to the inversion layer 23 on the GBL0 side, but the channel of the memory transistor 21 to be written and the weak inversion layer 24 with a small conductance of the second control transistor 22 adjacent thereto. The electric field concentration is generated between the first and second electrodes, and hot electrons are generated on the surface of the semiconductor substrate by the electric field concentration. The hot electrons are injected into the charge storage region 36 of the memory transistor 21 by the electric field generated by the high potential of the word line WL. . By injecting electrons into the charge storage region 36, the threshold voltage of the memory transistor 21 is increased. In order to suppress the write operation, according to the example of FIG. 5, the voltage applied to the inversion layer 23 on the GBL0 side is set to 2V, and the channel of the memory transistor 21 to be written and the second control transistor 22 adjacent thereto are small. What is necessary is just to suppress the hot electrons which generate | occur | produce by the electric field concentration between the weak inversion layers 24 of conductance. A read / write circuit (not shown) controls writing and write inhibition by controlling a voltage applied to the inversion layer 23 on the GBL0 side based on write data. Whether the threshold voltage has reached the target threshold voltage by the write operation is confirmed by the verify operation. Since the verify operation is performed by selecting the read path described with reference to FIG. 4, in the verify operation, the read / write circuit path reads the stored information through the inversion layer 23 on the GBL1 side, and uses the result as write data for the inversion layer on the GBL0 side. 23 must be reflected in the potential control. This is realized by a selection circuit (described later in detail) that controls connection between the read / write circuit and the global bit line.

  Note that the direction of the write current may be reversed in order to make the memory transistor 21 adjacent to the left of the second control transistor 22 a write target. When the memory transistor between GBL1 and GBL2 is to be written, the control signal AG1 is changed to 0V, AG3 is changed to 1V, and the direction of the write current is controlled by the voltage applied to GBL1 and GBL2. What is necessary is just to replace the position of the possible 2nd control transistor with the even number and the odd number.

  Although not shown in particular, in order to initialize the threshold voltage state of the written memory transistor, the first control transistor 20 and the inversion layers 23 and 24 of the second control transistor 22 have a first voltage such as a circuit ground voltage. 5 is set, the semiconductor substrate is set to the ground potential of the circuit, and a sixth potential such as a negative potential of −12 V is set to the word line WL. As a result, electrons move from the charge storage region in the emission direction, and the threshold voltage of the memory transistor 21 is lowered.

<< Selection mode by selection circuit >>
6 to 13 illustrate examples of selection of the inversion layer by the selection circuit. In each figure, the control signal 0 is the control signal AG0, the control signal 1 is the control signal AG1, the control signal 2 is the control signal AG2, the control signal 3 is the control signal AG3, and the memory 0 is the left side of the control signal 0 (control signal AG0). The memory transistor 21 and the memory 1 are the memory transistor 21 right next to the control signal 0 (control signal AG0), the memory 2 is the memory transistor 21 adjacent to the left of the control signal 2 (control signal AG2), and the memory 3 is the control signal 2 ( It means the memory transistor 21 on the right side of the control signal AG2). Reference numeral 50 is a representative read / write circuit, and 51 is a selection circuit. Each figure shows a connection configuration for one read / write circuit 50 (B) and the inversion layer 23 directly below the four first electrodes corresponding to the read / write circuit 50 (B). A connection configuration when the memory 0 is a read target is shown in FIG. 6, and a connection configuration when the memory 0 is a write target is shown in FIG. A connection configuration when the memory 1 is a read target is shown in FIG. 8, and a connection configuration when the memory 1 is a write target is shown in FIG. A connection configuration when the memory 2 is a read target is shown in FIG. 10, and a connection configuration when the memory 2 is a write target is shown in FIG. A connection configuration when the memory 3 is a read target is shown in FIG. 12, and a connection configuration when the memory 3 is a write target is shown in FIG. As is apparent from the selection mode of the inversion layer shown in FIGS. 6 to 13, the selection circuit 51 includes one first read / write circuit 50 and four first control transistors that are successively parallel to each other. The four inversion layers 23 according to the position of the memory transistor to be read or written of the stored information among the memory transistors 21 arranged between the four inversion layers. An inversion layer necessary for processing is selected from the above and connected to the one read / write circuit 50. In short, the selection circuit 51 controls the connection between the read / write circuit 50 and the inversion layer 23 by the first control transistor 20 so that the same read / write circuit 50 is used for reading and writing to the same memory transistor 21.

<Write / read circuit and selection circuit>
FIG. 14 shows the write / read circuit 50 and the selection circuit 51. In FIG. 14, a write / read circuit 50 and a selection circuit 51 select a circuit unit 54 for each of two global bit lines GBL <i>, GBL <i + 1> (i is a positive integer) and adjacent circuit units 54. The write / read circuit 50 and the selection circuit 51 are shown as a single unit. If the two components are distinguished, the MOS transistor 55, 56, 57, 72, 73 constitutes the selection circuit 51, and the other circuit components constitute the write / read circuit 50. In the figure, a p-channel MOS transistor is marked with an arrow of its base gate to distinguish it from an n-channel MOS transistor.

  The configuration of the circuit unit 54 will be described. The circuit unit 54 includes a static latch 60 having SLP and SLN as operation power supply nodes. One input / output node is a sense node (SL Sense), and the other input / output node is a reference node (SL Ref). The sense node and the reference node can be connected to external interface terminals IOR <n> and IOS <n> through select MOS transistors 61 and 62 which are switch-controlled by a column selection signal YS, and signals RSAS and RSAR. Are connected to the precharge power supply node FRSA via the sense latch set MOS transistors 63 and 64 which are switch-controlled. In the initialization operation of the sense node and the reference node, the levels of the signals RSAS and RSAR are different, so that the reference node is precharged to approximately half the level of the sense node. The sense node is connected to the circuit ground potential via a sense MOS transistor 65 and a sense enable MOS transistor 66 that is switch-controlled by a signal SENSE. The gate of the sense MOS transistor 65 is coupled to a node 67 reaching the global bit line, and the sense MOS transistor 65 is switch-controlled according to the level of the global bit line to be read, thereby selectively selecting the level of the sense node. Invert to low level. As a result, the static latch 60 can detect and latch the stored information of the memory transistor. The static latch 60 can latch write data from the external interface terminals IOR <n> and IOS <n>.

  The sense node is coupled to a node 69 that reaches the global bit line via an isolation MOS transistor 68 that is switch-controlled by a signal TR. The node 69 is a precharge enable MOS transistor for write inhibition that is switch-controlled by a signal PC. 70 and a write-inhibiting precharge MOS transistor 71 to be connected to a precharge power supply FPC. The MOS transistor 71 is switch-controlled according to the level of the sense node. When the reference node is at the high level when the write data is latched in the static latch 60, the node 69 is charged in advance by the precharge power supply FPC and then reaches the high level of the reference node. If the reference node is at the low level when the static latch 60 latches the write data, the node 69 reaches the low level of the reference node.

  The node 69 is connected to the global bit line GBL <i> via a MOS transistor 72 that is switch-controlled by a signal STR0 <0> and a MOS transistor 56 that is switch-controlled by a signal STR1 <0>. The node 67 is connected to the global bit line GBL <i + 1> via a MOS transistor 73 that is switch-controlled by a signal STR0 <1> and a MOS transistor 57 that is switch-controlled by a signal STR1 <1>. The coupling node between the MOS transistors 56 and 72 in the subsequent circuit unit 54 can be selectively connected to the coupling node between the MOS transistors 57 and 73 in the previous circuit unit 54 via the MOS transistor 55 that is switch-controlled by the signal SLTR. Is done. Nodes 67 and 69 are connected by wiring. Therefore, the static latch 60 can be connected to any one selected from the four global bit lines in accordance with the switch control state of the MOS transistors 55, 56, 57, 72, 73. Corresponding to each of the global bit lines GBL <i> and GBL <i + 1>, read and write bit line precharge MOS transistors 74 and 75 are provided. Bit line precharge MOS transistors 74 and 75 are connected to precharge power sources FRPC <0> and FRPC <1>, and are switch-controlled by signals RPC <0> and RPC <1>.

  The MOS transistor 76 is turned off when data of the memory Vth “H” is latched in the static latch 60, and generates a signal EC indicating the completion of writing of the memory transistor at the time of write verification. Used for

  FIG. 15 shows the read operation timing of the circuit unit 54 in the write / read circuit 50 and the selection circuit 51. In the erase state where the threshold voltage of the memory transistor 21 to be read is low (memory Vth “L”), the global bit line (GBL) is discharged from the precharge level, the MOS transistor 65 maintains the off state, and the sense The node stays high. In contrast, when the threshold voltage of the memory transistor 21 to be read is high (memory Vth “H”), GBL maintains the precharge level, the MOS transistor 65 is inverted to the ON state, and the sense node Is inverted to low level.

  FIG. 16 shows a write operation timing of the circuit unit 54 in the write / read circuit 50 and the selection circuit 51. The source side GBL to which the memory transistor selected for writing is connected is set to the ground potential of the circuit in response to the low level of the reference node of the static latch 60 that latches the write data, and the drain side GBL is written by the transistor 74. Precharged to voltage. As a result, a write current flows through the memory transistor 21, and hot electrons generated thereby are injected into the charge storage region of the memory transistor 21. The source side GBL to which the memory transistor that is not selected for writing is connected is charged to the write potential in response to the high level of the reference node of the static latch 60 that latches the write data, and the drain side GBL is charged by the transistor 74. Precharged to the write voltage. As a result, a write current does not flow through the memory transistor 21 and injection of electrons into the charge storage region of the memory transistor 21 is suppressed.

  17 to 24 illustrate connection modes of the inversion layer 23 by the write / read circuit 50 and the selection circuit 51 according to the configuration of FIG. A connection configuration when the memory 0 is a read target is shown in FIG. 17, and a connection configuration when the memory 0 is a write target is shown in FIG. A connection configuration when the memory 1 is a read target is shown in FIG. 19, and a connection configuration when the memory 1 is a write target is shown in FIG. A connection configuration when the memory 2 is a read target is shown in FIG. 21, and a connection configuration when the memory 2 is a write target is shown in FIG. A connection configuration when the memory 3 is a read target is shown in FIG. 23, and a connection configuration when the memory 3 is a write target is shown in FIG.

  In the flash memory 1, when writing to one memory transistor 21, the inversion layer 23 of the adjacent first control transistor 20 is used as one current path, and the adjacent second control transistor 22 and another memory transistor 21 are on the opposite side. The inversion layer 23 formed by the other first control transistor 20 located beyond the other is used as the other current path. According to this cell-through write method, when a write current flows from the memory transistor 21 to the second control transistor 22, the second transistor is used to cause a large electric field concentration between the memory transistor 21 and the second control transistor 22. Only the conductance of 22 needs to be reduced. It is not necessary to reduce the conductance of the inversion layer 23 in the first control transistor 20 that functions as a wiring for flowing a write current. Therefore, it is possible to improve the writing performance for the stored information.

  Further, even when the pair of first control transistors 20 used for supplying the write current is separated from each other as in the cell-through write method, the same read / write circuit 50 is used for reading and writing to the same memory transistor. Since the selection circuit for controlling the connection between the read / write circuit 50 and the inversion layer 23 by the first control transistor 20 is used so that the write-in circuit is used, the write operation by the cell-through write method can be guaranteed.

<Suppression of threshold voltage fluctuation>
Here, RTS, which is one of the factors that cause the threshold voltage of the memory transistor 21 to vary undesirably, will be described with reference to FIGS. The main symbols in the figure correspond to those in FIG. The memory transistor 21 has an RTS dependent region A between the semiconductor substrate 30 and the charge storage region 36. The RTS-dependent region A is a region formed by an interface 37A between the semiconductor substrate 30 and the gate insulating film 37, a bulk 37B of the gate insulating film 37, and an interface 37C between the gate insulating film 37 and the charge storage region 36. In the RTS dependent area A, for example, RTS generation factor electrons B that cause RTS are temporarily accumulated. In the RTS, when the RTS generation factor electrons B are temporarily captured in the RTS dependency region A and the threshold voltage becomes high, the RTS generation factor electrons B present in the RTS dependency region A are temporarily released, and the threshold voltage May be lower. Although the behavior of the RTS generation factor electron B is not sufficiently elucidated, by applying a predetermined negative voltage or positive voltage to the third electrode 35 serving as a memory gate, the behavior with respect to the RTS dependent region A is improved. Can be controlled. When a predetermined negative voltage is applied to the third electrode 35 of the memory transistor 21 by the control circuit 16, the RTS generation factor electrons B are temporarily excluded from the RTS dependent region A as shown in FIG. . At this time, the RTS dependent region A is in a charge state in which the temporary capture of the RTS generating factor electrons B is suppressed. In addition, when a predetermined positive voltage is applied to the third electrode 35 by the control circuit 16, the RTS generation factor electrons B are temporarily captured in the RTS dependent region A as shown in FIG. 28. At this time, the RTS dependent region A is in a charge state in which the temporary removal of the RTS generating factor electrons B is suppressed.

  That is, before reading the stored information, the control circuit 16 removes the charge state of the RTS dependent region A from the charge state in which the temporary capture of the RTS generation factor electrons B is suppressed, or the RTS generation factor electrons B from being temporarily excluded. Since the charge states are suppressed, the threshold voltage of the memory transistor 21 can be prevented from changing randomly due to the influence of RTS.

  In addition, it is necessary to consider the characteristics of the memory transistor 21 to determine which of the two charge states the charge state of the RTS-dependent region A is made equal to. This is because one of the factors that cause the threshold voltage of the memory transistor 21 to change undesirably is the characteristic of the memory transistor 21, and the influence of RTS may be increased according to this characteristic. is there. The memory transistor 21 has, for example, a characteristic that electrons are removed from the charge accumulation region 36 over time and the threshold voltage is lowered, and a characteristic that electrons are entered into the charge accumulation region 36 over time and the threshold voltage is increased. There is. Therefore, in the memory transistor 21 having a characteristic that the threshold voltage is lowered with time, if the charge state of the RTS dependent region A is changed to a charge state in which the temporary capture of the RTS generation factor electrons B is suppressed, the threshold value is thereby increased. The voltage will be even lower. Further, in the memory transistor 21 having a characteristic that the threshold voltage becomes higher with time, if the charge state of the RTS dependent region A is changed to a charge state in which the temporary removal of the RTS generation factor electrons B is suppressed, the threshold value is thereby increased. The voltage will be higher. In other words, if the charge state of the RTS dependent region A is not made uniform in consideration of the characteristics of the memory transistor 21, the influence of RTS is increased according to this characteristic.

  Hereinafter, the control circuit 16 applies the negative voltage or the positive voltage to the third electrode 35 according to the characteristics of the memory transistor 21 before the read operation, thereby eliminating the influence of the RTS and the influence of the RTS. A specific example of preventing the increase will be described. Here, in order to facilitate understanding of the influence removal of RTS and the suppression of the increase in characteristic deterioration due to RTS, an extreme case division is performed, and a voltage application form for that purpose will be exemplarily described. The read operation includes a read operation in a write verify operation (hereinafter referred to as a write verify read operation) and a normal data read operation.

  First, attention is focused on the read operation for write verification with respect to the memory transistor 21 having the characteristic that RTS does not occur constantly. The fact that RTS does not occur constantly means that the phenomenon that RTS generation factor electrons B stay in the RTS dependent region A does not always occur. For this reason, the flash memory 1 is designed in a normal state in which there is no influence of RTS, so it is necessary to eliminate the influence of RTS. In other words, it is necessary to prevent the RTS generation factor electrons B from staying in the RTS dependent region A. At this time, the control circuit 16 applies a predetermined negative voltage to the third electrode 35 of the memory transistor 21 before the write verify read operation. For this reason, before the read operation for write verification, the RTS dependent region A is in a charge state in which the temporary capture of the RTS generation factor electrons B is suppressed. Therefore, the first write operation is not affected by the RTS in the write verify operation. The state can be determined. Therefore, the threshold voltage that becomes the verify pass does not change abruptly.

  Further, attention is focused on the read operation for data verification and the data read operation for the memory transistor 21 which has a characteristic that electrons do not constantly occur from the charge storage region 36 and RTS does not occur constantly. Since the control circuit 16 applies a predetermined negative voltage in the same manner as described above before the read operation for write verification, the description is omitted. At this time, the control circuit 16 applies a predetermined positive voltage to the third electrode 35 of the memory transistor 21 before the data read operation. For this reason, before the data read operation, the RTS dependent region A is in a charge state in which the temporary elimination of the RTS generation factor electrons B is suppressed. Therefore, in addition to the characteristics of the memory transistor 21, the threshold voltage is affected by the influence of RTS. There is no further reduction. Therefore, the influence of RTS is not increased according to the characteristics of the memory transistor 21.

  Further, attention is focused on the read operation for data verification and the data read operation for the memory transistor 21 which has a characteristic that electrons do not constantly occur and electrons enter the charge accumulation region 36 over time. Since the control circuit 16 applies a predetermined negative voltage in the same manner as described above before the read operation for write verification, the description is omitted. At this time, the control circuit 16 applies a predetermined negative voltage to the third electrode 35 of the memory transistor 21 before the data read operation. For this reason, before the data read operation, the RTS dependent region A is in a charge state in which the temporary capture of the RTS generation factor electrons B is suppressed. Therefore, in addition to the characteristics of the memory transistor 21, the threshold voltage is affected by the influence of RTS. It will not be even higher. Therefore, the influence of RTS is not increased according to the characteristics of the memory transistor 21.

  Next, RTS is constantly generated by changing the material of the memory transistor 21 or by further miniaturization of, for example, 90 nm or less, and a relatively large amount of RTS-causing electrons B stay in the RTS-dependent region A. Attention is focused on the read operation for data verification and the data read operation for the case where electrons tend to escape from the charge storage region 36. In this case, since it is considered that the flash memory 1 is designed with the RTS-affected state as a normal state, it is necessary to consider the RTS effect after assuming the RTS. In other words, it is necessary that the RTS generation factor electrons B stay in the RTS dependent area A. Therefore, the control circuit 16 applies a predetermined positive voltage to the third electrode 35 of the memory transistor 21 before the write verify read operation. For this reason, before the read operation for write verification, the RTS dependent region A is in a charge state in which the RTS generation factor electrons B are temporarily prevented from being excluded. The write state can be determined first without being affected. Therefore, the threshold voltage that becomes the verify pass does not change abruptly. The control circuit 16 applies a predetermined positive voltage to the third electrode 35 of the memory transistor 21 before the data read operation. Therefore, before the data read operation, the RTS dependent region A is in a charge state in which the temporary elimination of the RTS generation factor electrons B is suppressed. Therefore, in addition to the characteristics of the memory transistor 21, the RTS generation factor is affected by the RTS effect. There is no possibility that the electrons B escape more than necessary and the threshold voltage is further lowered. Therefore, the influence of RTS is not increased according to the characteristics of the memory transistor 21.

  In addition, RTS is constantly generated due to a change in material of the memory transistor 21 or further miniaturization of, for example, 90 nm or less, and a relatively large amount of RTS-generating electrons B stay in the RTS-dependent region A. Attention is focused on a read operation for data verification and a data read operation for a case where electrons tend to enter the charge storage region 36. Since the control circuit 16 applies a predetermined positive voltage in the same manner as described above before the read operation for write verification, the description is omitted. At this time, the control circuit 16 applies a predetermined negative voltage to the third electrode 35 of the memory transistor 21 before the data read operation. For this reason, before the data read operation, the RTS dependent region A is in a charge state in which the temporary capture of the RTS generation factor electrons B is suppressed. Therefore, in addition to the characteristics of the memory transistor 21, the RTS generation factor is affected by the influence of RTS. Electron B does not enter more than necessary and the threshold voltage does not increase further. Therefore, the influence of RTS is not increased according to the characteristics of the memory transistor 21.

  Here, the predetermined negative voltage and positive voltage applied to the third electrode 35 will be described in detail. FIG. 29 shows the read operation timing by applying a predetermined negative voltage. FIG. 30 shows the read operation timing by applying a predetermined positive voltage. Note that the timing charts shown in FIGS. 29 and 30 are based on the connection state of the inversion layer 23 when the memory 2 shown in FIG. 21 is a read target, and the memory 2 has a constant RTS. It has a characteristic that electrons are removed from the charge storage region 36 over time. In the figure, STS is a voltage applied to the selection switch 40 disposed between the inversion layer 23 functioning as a local bit line and the corresponding global bit lines GLB0 to GBL3. The STD is a voltage applied to the selection switch 41 disposed between the inversion layer 24 functioning as a local source line and the corresponding common line CD.

  First, as shown in FIG. 29, the control circuit 16 precharges the global bit lines GLB1, 3 and then sets the potential of the control signals AG1, 2 to 4.2V and the potential of the control signal AG3 to -2V. Then, the control circuit 16 sets the potential of STS to 4V, switches the selection switch 40, connects the GLBs 1, 3 and the inversion layer 23, and then sets the potential to 0V. At time t0, the control circuit 16 discharges the GLBs 1 and 3 from the precharge level and applies a predetermined negative voltage to the memory 2. The predetermined negative voltage has a voltage value higher than the voltage value (for example, -18V) of the erasing pulse voltage, and is set to, for example, -3V to -2V. For this reason, when the RTS generation factor electrons B are eliminated, the electrons are not removed from the charge storage region 36 by the FN tunnel, so that the threshold voltage is not initialized to the erased state. Furthermore, at time t0, some negative voltage is also applied to non-selected memory cells that are not to be read. Thereby, the leakage current from the non-selected memory cell adjacent to the read target memory cell can be reduced, and erroneous reading can be prevented. At time t1, the control circuit 16 finishes applying the negative voltage to the memory 2 and sets the potential to 0V. The pulse width of the negative voltage may be such that the charge state of the RTS-dependent region A is aligned with the charge state in which the temporary capture of the RTS generation factor electrons B is suppressed, and the disturbance is not generated in the unselected memory cells. Although not particularly limited, for example, 10 μs is set. Disturbance is a phenomenon in which the threshold voltage of unselected memory cells connected to a selected word line or selected data line fluctuates undesirably.

  At time t2, the control circuit 16 applies a read pulse voltage to the memory 2 by a write verify operation to set the potential to 5.5V. Next, the control circuit 16 sets the STD potential to 4V, switches the selection switch 41, connects the inversion layer 24 and the corresponding common line CD, and then sets the potential to 0V. At time t3, the control circuit 16 ends the application of the read pulse voltage to the memory 2, sets the potential to 0V, and sets the potential of the unselected memory cells to 0V. Finally, the control circuit 16 sets the potentials of AG1 to AG3 to 0V.

  The read operation timing shown in FIG. 30 is different from that shown in FIG. 29 in that the control circuit 16 applies a predetermined positive voltage to the memory 2 at time t0 to t1 before the data read operation. The difference is that a read word line voltage is applied to the gate. The predetermined positive voltage has a voltage value lower than the voltage value (for example, 10V to 15V) of the writing pulse voltage, and is set to 8V, for example. For this reason, when the RTS generation factor electrons B are captured, for example, hot electrons are not generated on the surface of the semiconductor substrate 30, so that electrons are not injected into the charge storage region 36 and a writing operation is not performed. The pulse width of the positive voltage may be such that the charge state in the RTS dependent region A is aligned with the charge state in which the temporary elimination of the RTS generation factor electrons B is suppressed, and the disturbance is not generated in the unselected memory cells. Although not particularly limited, for example, 50 μs is set.

  FIG. 31 shows changes in threshold voltage distribution during a data read operation depending on whether or not a predetermined positive voltage is applied. In the figure, the horizontal axis represents the threshold voltage Vth of the memory 2 described above, and the vertical axis represents the frequency σ. In the figure, attention is focused on the lower skirt portion of one specific threshold voltage distribution. In the figure, the threshold voltage distribution obtained by the data read operation when a predetermined positive voltage is not applied is indicated by a dotted line. The threshold voltage distribution obtained when a predetermined positive voltage is applied is indicated by a solid line.

  As shown in the figure, the threshold voltage distribution is reduced in its spread by applying a predetermined positive voltage. In short, before the data read operation, the control circuit 16 applies a predetermined positive voltage to the memory 2 having such a characteristic that RTS does not occur constantly and electrons escape from the charge storage region 36 over time. Thus, the width of the threshold voltage distribution can be reduced, so that the threshold voltage is not further lowered due to the influence of RTS in addition to the characteristics of the memory 2.

  Next, other negative voltages and positive voltages having waveforms and timings different from those of the predetermined negative voltage and positive voltage described above will be described. FIG. 32 shows the read operation timing by application of another negative voltage different from the predetermined negative voltage shown in FIG. FIG. 33 shows the read operation timing by applying another positive voltage different from the predetermined positive voltage shown in FIG. As shown in FIG. 32, the control circuit 16 applies a predetermined negative voltage to the memory 2 at time t0, ends application of the negative voltage to the memory 2 at time t1, and does not set the potential to 0V. A read pulse voltage is applied to the memory 2 to set the potential to 5.5V. At time t2, the control circuit 16 finishes applying the read pulse voltage to the memory 2 and sets the potential to 0V. Further, the read operation timing shown in FIG. 33 is different from that in FIG. 32 in that the control circuit 16 applies a predetermined positive voltage to the memory 2 at time t0 and sets the potential to 0 V at time t1 before the data read operation. The difference is that the read word line voltage is applied to the memory 2 without doing so. In this way, the control circuit 16 may directly transition the potential of the memory 2 at time t1, as shown in FIGS. In this way, when switching from a negative voltage power supply to a positive voltage power supply is unnecessary, or when a positive voltage necessary to suppress RTS can be supplied by a positive power supply circuit for reading even with a positive voltage, By performing the operation, it is possible to shorten the time until the read operation, and in particular, it is possible to enhance the effect of suppressing the threshold voltage fluctuation for the RTS having a short transition time.

  FIG. 34 shows the read operation timing by applying another negative voltage different from the predetermined negative voltage shown in FIG. FIG. 35 shows the read operation timing by applying another positive voltage different from the predetermined positive voltage shown in FIG. As shown in FIG. 34, the control circuit 16 applies a predetermined negative voltage to the memory 2 at time t0 before precharging the global bit lines GLB1 and 3, and the negative voltage with respect to the memory 2 at time t1. Is finished, and the potential is set to 0V. At time t2, the control circuit 16 discharges the GLBs 1 and 3 from the precharge level and applies a read pulse voltage to the memory 2 to set the potential to 5.5V. At time t3, the control circuit 16 finishes applying the read pulse voltage to the memory 2 and sets the potential to 0V. Also, the read operation timing shown in FIG. 35 differs from that in FIG. 34 in that the control circuit 16 applies a predetermined positive voltage to the memory 2 at times t0 to t1 before the data read operation. In this way, the control circuit 16 can appropriately change the length of the times t1 to t2 as shown in FIGS. This is because optimization is required depending on the transition time of electron capture and emission by RTS. In addition, when the transition time is long, restrictions on circuit operation can be reduced.

  Although the invention made by the present inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof.

  For example, the memory transistor 21 has a characteristic that electrons escape from the charge storage region 36 over time and a characteristic that electrons enter the charge storage region 36 over time. However, the present invention is not limited to this. For example, the threshold voltage can be lowered in a very short time of about several μs to 1 s after writing. Such characteristics are considered to be caused by defects or miniaturization of the charge storage region 36. In this case, since these electrons also cause the threshold voltage to fluctuate undesirably, it is considered that these electrons are unnecessary components for the original memory operation. Therefore, assuming that there is no influence of RTS, the control circuit 16 forcibly removes these electrons by applying a negative voltage before the read operation for write verification, thereby removing unnecessary components for the memory operation. May be eliminated. At this time, the control circuit 16 applies a positive voltage to forcibly take in these electrons, which are unnecessary components, into the charge region 36, thereby making these electrons effective components for the memory operation. It may be. Even if there is an influence of RTS during the read operation for write verification, the control circuit 16 applies a predetermined negative voltage or positive voltage to the third electrode 35 of the memory transistor 21, thereby Since the charge states are aligned, it is possible to suppress the threshold voltage from fluctuating randomly due to the influence of RTS.

  Further, the pulse widths of the predetermined negative voltage and positive voltage described above are smaller than the pulse width of the read pulse voltage in the read operation for write verification and the read word line voltage in the data read operation, as shown in the figure. However, the present invention is not limited to this, and the pulse width may be larger than the pulse width of the read pulse voltage or the read word line voltage. At this time, since RTS and disturb are in a trade-off relationship, the pulse widths of predetermined negative voltage and positive voltage are appropriately set in consideration of which effect is reduced according to the required specifications of the flash memory 1. Adjust it.

  In the embodiment, a nonvolatile memory having a memory array structure in which memory cell transistors are connected in parallel to a source line and the source line is formed of an inversion layer has been described. However, the source line has a high resistance. Considering that the source potential floats, the drain terminal and the source terminal of the memory cell transistor are connected in series, and a high voltage is applied to the gate terminal of the memory cell transistor connected to the source terminal side of the memory cell to be written. The present invention can also be applied to a nonvolatile memory having a memory array structure in which a source line is formed by applying and turning on. In the case of a non-volatile memory having such a memory array structure, the on-resistance of the memory cell transistor in the on state makes the source line in a high resistance state, and the number of memory cell transistors connected in series to the source terminal Accordingly, since the resistance connected to the source terminal is different, the source potential floats. Therefore, the present invention can be applied to the case where writing is performed by passing a current through the memory cell transistor.

  Furthermore, for example, the memory transistor is not limited to four-value storage, and may be eight-value storage. The structure of the memory array is not limited to the structure in which writing is performed by the write-through method. A structure having a unique bit line for each column of memory transistors may be used. Even in the structure in which writing is performed by the write-through method, the bit line and the source line are not limited to the structure using the inversion layer, and may be the structure using the diffusion layer wiring. Further, the nonvolatile memory is not limited to a configuration having a plurality of banks that can operate in parallel. The applied voltage for erasing and writing can be changed as appropriate. The nonvolatile memory can be applied to an on-chip memory such as a system LSI or a microcomputer. Furthermore, the present invention is not limited to the flash memory, but can be widely applied to an EEPROM and other storage-type nonvolatile memories.

1 is a block diagram of a flash memory according to an example of the present invention. It is a circuit diagram which illustrates transistor arrangement | positioning of a memory array. It is sectional drawing which illustrates the longitudinal cross-section structure along the word line of a device. It is a circuit diagram which illustrates the selection mode of the signal path in read-out operation. It is a circuit diagram which illustrates the signal path | route of the write-in operation | movement by a cell through write system. It is a circuit diagram which shows a connection form when the memory 0 is made into reading object as a selection mode of the inversion layer by a selection circuit. It is a circuit diagram which shows the connection form when the memory 0 is made into writing object as a selection mode of the inversion layer by a selection circuit. It is a circuit diagram which shows the connection form when the memory 1 is made into the reading object as a selection aspect of the inversion layer by a selection circuit. It is a circuit diagram which shows the connection form when the memory 1 is made into writing object as a selection aspect of the inversion layer by a selection circuit. It is a circuit diagram which shows a connection form when the memory 2 is made into reading object as a selection aspect of the inversion layer by a selection circuit. It is a circuit diagram which shows the connection form when the memory 2 is made into writing object as a selection mode of the inversion layer by a selection circuit. It is a circuit diagram which shows the connection form when the memory 3 is made into the reading object as a selection mode of the inversion layer by a selection circuit. It is a circuit diagram which shows the connection form when the memory 3 is made into writing object as a selection mode of the inversion layer by a selection circuit. It is a circuit diagram which shows a detailed example of a read / write circuit and a selection circuit. It is a timing chart which shows the read-out operation timing of the circuit unit in a write-read circuit and a selection circuit. 6 is a timing chart showing a write operation timing of a circuit unit in a write / read circuit and a selection circuit. FIG. 15 is a circuit diagram showing a connection mode when the memory 0 is a read target as a connection mode of the inversion layer by the write / read circuit and the selection circuit according to the configuration of FIG. 14; FIG. 15 is a circuit diagram showing a connection mode when the memory 0 is a write target as a connection mode of the inversion layer by the write / read circuit and the selection circuit according to the configuration of FIG. 14; FIG. 15 is a circuit diagram showing a connection mode when the memory 1 is a read target as a connection mode of the inversion layer by the write / read circuit and the selection circuit according to the configuration of FIG. 14; FIG. 15 is a circuit diagram showing a connection mode when the memory 1 is a write target as a connection mode of the inversion layer by the write / read circuit and the selection circuit according to the configuration of FIG. 14; FIG. 15 is a circuit diagram showing a connection mode when the memory 2 is a read target as a connection mode of the inversion layer by the write / read circuit and the selection circuit according to the configuration of FIG. 14; FIG. 15 is a circuit diagram showing a connection mode when the memory 2 is a write target as a connection mode of the inversion layer by the write / read circuit and the selection circuit according to the configuration of FIG. 14; FIG. 15 is a circuit diagram showing a connection mode when the memory 3 is a read target as a connection mode of the inversion layer by the write / read circuit and the selection circuit according to the configuration of FIG. 14; FIG. 15 is a circuit diagram showing a connection mode when the memory 3 is a write target as a connection mode of the inversion layer by the write / read circuit and the selection circuit according to the configuration of FIG. 14; It is explanatory drawing which illustrates distribution of the threshold voltage set to a memory cell transistor by write-in operation. FIG. 26 is an explanatory diagram of a specific example of the upper skirt verify voltage, the lower skirt verify voltage, and the read word line voltage. It is a conceptual diagram which illustrates the state which applies a negative voltage and excludes RTS generation factor electron B from RTS dependence area A temporarily. It is a conceptual diagram which illustrates a state in which a positive voltage is applied and RTS generation factor electrons B are temporarily captured in the RTS dependent region A. It is a timing chart which shows the read-out operation timing by application of a predetermined negative voltage. It is a timing chart which shows the read-out operation timing by application of a predetermined positive voltage. It is explanatory drawing which shows the change of threshold voltage distribution at the time of the data read-out operation | movement by the presence or absence of predetermined positive voltage application. FIG. 30 is a timing chart showing a read operation timing by application of another negative voltage different from the predetermined negative voltage shown in FIG. 29. FIG. FIG. 31 is a timing chart showing a read operation timing due to application of another positive voltage different from the predetermined positive voltage shown in FIG. 30. FIG. FIG. 30 is a timing chart showing a read operation timing by applying another negative voltage different from the predetermined negative voltage shown in FIG. 29. FIG. FIG. 31 is a timing chart showing a read operation timing by applying another positive voltage different from the predetermined positive voltage shown in FIG. 30. FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Flash memory 3 Memory array 20 1st control transistor 21 Memory transistor 22 2nd control transistor 23 Inversion layer 24 Inversion layer WL Word line 30 Semiconductor substrate 31 Insulating film 33 1st electrode 34 2nd electrode 35 3rd Electrode 36 Charge storage region 37 Gate insulating film 37A Interface between semiconductor substrate and gate insulating film 37B Bulk of gate insulating film 37C Interface between gate insulating film and charge storage region 50 Read / write circuit 51 Selection circuit 52 Diffusion layer (diffusion layer wiring)
60 static latch A RTS dependent region B RTS generation factor electron SL Ref reference node SL Sense sense node

Claims (8)

A memory array and a control circuit;
The memory array has a substrate, a gate insulating film, and a charge storage region, and has a plurality of nonvolatile memory cells capable of changing a threshold voltage by injecting or emitting electrons to the charge storage region,
The control circuit exists in at least one of the interface between the substrate and the gate insulating film, the gate insulating film, and the interface between the gate insulating film and the charge storage region before reading stored information from the nonvolatile memory cell. A voltage for temporarily eliminating RTS-causing electrons, or a voltage for temporarily capturing RTS-causing electrons in at least one of the interface and the gate insulating film, the nonvolatile memory cell Device applied to the selection terminal. A memory array and a control circuit;
The memory array has a substrate, a gate insulating film, and a charge storage region, and has a plurality of nonvolatile memory cells capable of changing a threshold voltage by injecting or emitting electrons to the charge storage region,
The control circuit includes at least one of an interface between the substrate and the gate insulating film, the gate insulating film, and an interface between the gate insulating film and the charge storage region before the read operation for write verification with respect to the nonvolatile memory cell. A semiconductor device that applies a predetermined negative voltage for temporarily removing RTS generation-causing electrons existing in the selection terminal of the nonvolatile memory cell. A memory array and a control circuit;
The memory array has a substrate, a gate insulating film, and a charge storage region, and has a plurality of nonvolatile memory cells capable of changing a threshold voltage by injecting or emitting electrons to the charge storage region,
The control circuit includes at least one of an interface between the substrate and the gate insulating film, the gate insulating film, and an interface between the gate insulating film and the charge storage region before the read operation for write verification with respect to the nonvolatile memory cell. A predetermined negative voltage for temporarily eliminating the RTS generation factor electrons existing in the non-volatile memory cell,
Prior to a data read operation for the nonvolatile memory cell, a predetermined positive voltage for temporarily capturing RTS-causing electrons at at least one of the interface and the gate insulating film is applied to the selection terminal. Semiconductor device. A memory array and a control circuit;
The memory array has a substrate, a gate insulating film, and a charge storage region, and has a plurality of nonvolatile memory cells capable of changing a threshold voltage by injecting or emitting electrons to the charge storage region,
The control circuit includes at least one of an interface between the substrate and the gate insulating film, the gate insulating film, and an interface between the gate insulating film and the charge storage region before the read operation for write verification with respect to the nonvolatile memory cell. A predetermined negative voltage for temporarily eliminating the RTS generation factor electrons existing in the non-volatile memory cell,
Prior to a data read operation for the nonvolatile memory cell, a predetermined negative voltage for temporarily eliminating RTS-causing electrons existing at at least one of the interface and the gate insulating film is supplied to the selection terminal. Semiconductor device to be applied to. A memory array and a control circuit;
The memory array has a substrate, a gate insulating film, and a charge storage region, and has a plurality of nonvolatile memory cells capable of changing a threshold voltage by injecting or emitting electrons to the charge storage region,
The control circuit includes at least one of an interface between the substrate and the gate insulating film, the gate insulating film, and an interface between the gate insulating film and the charge storage region before the read operation for write verification with respect to the nonvolatile memory cell. A predetermined positive voltage for temporarily capturing RTS generation factor electrons is applied to the selection terminal of the nonvolatile memory cell,
Prior to a data read operation for the nonvolatile memory cell, a predetermined positive voltage for temporarily capturing RTS-causing electrons at at least one of the interface and the gate insulating film is applied to the selection terminal. Semiconductor device. A memory array and a control circuit;
The memory array has a substrate, a gate insulating film, and a charge storage region, and has a plurality of nonvolatile memory cells capable of changing a threshold voltage by injecting or emitting electrons to the charge storage region,
The control circuit includes at least one of an interface between the substrate and the gate insulating film, the gate insulating film, and an interface between the gate insulating film and the charge storage region before the read operation for write verification with respect to the nonvolatile memory cell. A predetermined positive voltage for temporarily capturing RTS generation factor electrons is applied to the selection terminal of the nonvolatile memory cell,
Prior to a data read operation for the nonvolatile memory cell, a predetermined negative voltage for temporarily eliminating RTS-causing electrons existing at at least one of the interface and the gate insulating film is supplied to the selection terminal. Semiconductor device to be applied to.   The semiconductor device according to claim 3, 5 or 6, wherein the predetermined positive voltage has a voltage value lower than a voltage value of a write pulse voltage.   The semiconductor device according to claim 2, wherein the predetermined negative voltage has a voltage value higher than a voltage value of an erasing pulse voltage.

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