KR101610176B1 - Semiconductor memory apparatus and method for erasing the same - Google Patents

Abstract

A flash memory is disclosed that has low power consumption and high speed operations. The flash memory includes a memory array of memory cells, a word line selection circuit for selecting a row of cells, A current sensing circuit coupled to the array, and an erase circuit for erasing the cells in the selected block of the array. Wherein the erase sequence comprises erasing the erase sequence to determine whether the current of each bit line in the erased block is greater than a first value and to terminate the erase if the determination result is passable, Program sequence for applying a voltage and determining whether the current of each bit line is lower than a second value, and for terminating soft programming if the result of the determination is passable.

Description

Semiconductor memory device and method for erasing same [0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device that reads data from a flash memory in a current sensing manner and a method of erasing the semiconductor memory device.

1 illustrates an example of a bit line select circuit and page buffer / sense circuit of a conventional flash memory and illustrates a pair of bit lines including an even bit line GBL_e and an odd bit line GBL_o in FIG. It is plotted as enemy. The bit line selection circuit 10 includes an even selection transistor SEL_e electrically connected to the even bit line GBL_e, an odd selection transistor SEL_o electrically connected to the odd bit line GBL_o, an even bit line GBL_e, An even-numbered bias selection transistor YSEL_e electrically connected between a potential VIR and an odd-numbered selection transistor YSEL_o electrically connected between an odd-numbered bit line GBL_o and a virtual potential VIR; And a bit line select transistor (BLS) electrically connected to a common node (N1) electrically connected to the odd select transistor (SEL_o).

Each of the even-numbered bit line GBL_e and the odd-numbered bit line GBL_o is electrically connected to the NAND string NU. Each NAND string NU includes a plurality of memory cells connected in series in a column direction and a drain select transistor and a source select transistor electrically connected to both ends thereof. The drain select transistor is electrically connected to the even bit line GBL_e or the odd bit line GBL_o and the source select transistor is electrically connected to the common source line SL.

The sensing circuit 20 includes a pre-charge transistor BLPRE for providing a pre-charge potential to each bit line, a sense amplifier circuit 14 formed between the pre-charge transistor BLPRE and the bit line select transistor BLS A capacitor C electrically connected to the node SN and a transfer transistor BLCD for transferring the potential of the sense node SN to the latch circuit 22. [

When the even-numbered bit line GBL_e is selected and the odd-numbered bit line GBL_o is not selected, the even-numbered selection transistor SEL_e and the bit-line selection transistor BLS are turned on, Off. The odd selection transistor SEL_o and the bit line selection transistor BLS are turned on and the even selection transistor SEL_e is turned on when the odd bit line GBL_o is selected and the even bit line GBL_e is not selected, Off. By doing so, one sensing circuit 20 is shared by two bit lines, i.e., the bit lines GBL_e and GBL_o.

When the even bit line GBL_e is selected and the odd bit line GBL_o is not selected in a read operation, the even bias select transistor YSEL_e is turned off and the odd bias select transistor YSEL_o is turned- And the odd bit line GBL_o is supplied with the ground potential from the virtual potential VIR. Alternatively, when the even bit line GBL_e is not selected and the odd bit line GBL_o is selected, the even bias select transistor YSEL_e is turned on, the odd bias select transistor YSEL_o_ is turned off, And the even bit line GBL_e is supplied with the ground potential from the virtual potential VIR. By providing the ground potential to the even-numbered bit lines and the ground potential to the even-numbered bit lines, which dock the odd-numbered bit lines in this manner, the bit line shielding as described in Japanese Patent Publication No. 11-176177 a shielding effect may be provided to mitigate noise caused by capacitive coupling between neighboring bit lines.

In that the pre-charge potential is provided to the even or the odd bit line GBL_e or GBL_o by the pre-charge transistor BLPRE, the sense circuit 20 illustrated in FIG. 1 is a so-called voltage-sensitive sense circuit . The sensing circuit 20 then discharges the bit line corresponding to the storage state of the selected memory cell and detects the discharge state of the sense node SN. However, since the reduction of the bit line linewidth results in an increase in the resistance of the bit lines, and the increase in the number of memory cells constituting the NAND string results in an increase in the capacitance between the bit lines, The constant increases and the charging / discharging time of the bit lines becomes longer, so that the time for reading the data becomes longer. Therefore, the voltage sensing circuit is no longer applied to a highly integrated flash memory.

In view of the foregoing, currently used sensing circuits use current sensing instead. The current sensing circuit detects the cell current of the memory cell corresponding to the storage state through the bit line. Compared to the voltage type, the current sensing circuit can achieve high-speed sensing. The current sensing circuit may utilize, for example, a cascode circuit that performs current-to-voltage conversion, or the like.

However, the conventional current sensing circuit has the following problems. In a flash memory, electrons are accumulated in the floating gate during programming to positively move the threshold voltage of the memory cell, and electrons are floated during erase to move the threshold voltage of the memory cell negatively. And is discharged from the gate. However, the threshold voltage of the memory cell at the time of programming or erasing may be within the range of the "0" or "1" storage state, or "00", "01", "10" Should be controlled within the distribution range of the " 11 " storage state. In order to precisely control the threshold voltage of the memory cell, an initial erase pulse Vers0 is applied to the memory cells in the selected block, and when it is determined by erase verification that the erase is not successful, Vers0) is applied and an incremental step pulse erase (ISPE) mode is adopted in which an erase voltage gradually increases until erasure of all the memory cells in the block is judged to be successful.

Due to such factors as the size and shape of each memory cell varying due to variations in fabrication process indicators and deterioration of the tunnel oxide layer resulting from a large number of program / erase cycles, each memory cell is more easily or difficultly They are different in that they are erased. More specifically, some memory cells have a high conductance allowing more easily flowing currents, while some memory cells have a low conductivity with less likelihood of currents flowing. Since the erase verify determines whether the erase of the entire block is succeeded by each bit line unit without judging the erase states of the memory cells one by one, the bit line has high conductivity and the memory cells having high conductivity When concurrently connected to memory cells, memory cells with low conductivity will be the basis for determining if erase is successful, and memory cells with high conductivity will be over-erased. Therefore, data poisoned, over-erased memory cells have relatively large currents, thus increasing power-consumption. In the meantime, the sense circuit must also be able to provide a lot of current, which limits its miniaturization to the sense circuit.

Therefore, the present invention provides a semiconductor memory device capable of reducing power consumption and operating at high speed.

The present invention also provides a method for erasing a semiconductor memory device having NAND nonvolatile memory cells.

The semiconductor memory device of the present invention includes a memory array having a plurality of memory cells, a word line select circuit configured to select a row of memory cells, Type sensing circuit, and a means for canceling data in the memory cells of the selected block of the memory array. The erasure rejection includes an erasure sequence and a soft-program sequence. The erase sequence includes erase verification to determine whether the current of each bit line in the erased block is greater than a first value, and terminates the erase if the result is pass. The soft-program sequence includes soft-program verification to apply a soft-program voltage to all word lines in the erased block and determine whether the current of each bit line is lower than a second value that is lower than the first value , And if the result is acceptable, the soft programming is terminated.

In an embodiment of the present invention, the soft-program verify is performed by applying a bias voltage applied to word lines that are not selected in a read operation to all word lines and determining whether the current of each bit line is lower than a second value do. The soft-program sequence can perform soft programming on memory cells electrically connected to bit lines that are capable of applying a write protection voltage to bit lines that are less current than a second value and that are currents that are greater than a second value have.

In an embodiment of the present invention, the semiconductor memory device further includes a plurality of pre-charge circuits. Each of the pre-charge circuits provides a pre-charge voltage to the bit lines and is configured between the blocks. Each of the pre-charge circuits provides a pre-charge voltage to the bit lines before currents are supplied to the bit lines through the sense circuit. The sensing circuit includes a first sensing circuit electrically connected to the even bit lines and a second sensing circuit electrically connected to the odd bit lines. The first sensing circuit is disposed next to one end of the memory array, the second sensing circuit is disposed next to the other end of the memory array, and a plurality of pre-charging circuits are disposed between the first sensing circuit and the second sensing circuit do. Each of the pre-charge circuits includes a conductive line extending from the word line selection circuit along the row direction of the memory array and electrically connected to the bit lines.

A method for erasing a semiconductor memory device comprising NAND nonvolatile memory cells of the present invention includes an erase sequence and a soft-program sequence. The erase sequence includes erase verification to determine whether the current of each bit line in the erased block is greater than a first value, and terminates the erase if the result is pass. The soft-program sequence includes soft-program verification to apply a soft-program voltage to all word lines in the erased block and determine whether the current of each bit line is lower than a second value that is lower than the first value , And if the result is acceptable, the soft programming is terminated.

As the present invention, a semiconductor memory device using a current sensing circuit for achieving power-consumption reduction and high-speed operation can be provided.

In order that the above-recited features, advantages, and other features and advantages of the present invention may be better understood, several embodiments together with the drawings are described below.

Figure 1 illustrates an example of a bit line select circuit and page buffer / sense circuit of a conventional flash memory.
2 is a block diagram illustrating an exemplary structure of a flash memory in accordance with an embodiment of the present invention.
Figure 3 illustrates a circuit diagram of pre-charge circuits and NAND string structures in accordance with an embodiment of the present invention.
4 illustrates an exemplary structure of a page buffer / sense circuit in accordance with an embodiment of the present invention.
Figure 5 lists the voltage relationship between the components of the flash memory in accordance with an embodiment of the present invention in each mode of operation.
6 illustrates a flow diagram of a method for erasing a flash memory in accordance with an embodiment of the present invention.
7 illustrates a time chart for waveforms of signals applied in an erase mode according to an embodiment of the present invention.
Figure 8 illustrates the distribution states of threshold voltages in erase verify, soft-program verify, and page-program verify.
9 illustrates a flowchart of a soft program / verify operation in accordance with an embodiment of the present invention.
Figure 10 illustrates another exemplary structure of a flash memory in accordance with an embodiment of the present invention.

The flash memory of the present invention uses a current sensing circuit for determining whether a current flows through a memory cell. An operating strategy that can control negative threshold voltages of memory cells higher than or equal to a certain value to reduce poWer power consumption is employed to erase the data of the memory cells. By doing so, the currents provided to the bit lines by the current sensing circuit can be suppressed below a certain value to reduce power consumption. Embodiments of the present invention will be described in detail with reference to the accompanying drawings. Particular emphasis is placed on the fact that some components are emphasized for better understanding, and have actual size accumulations.

2 is a block diagram illustrating an exemplary structure of a flash memory in accordance with an embodiment of the present invention. The exemplary structure is merely exemplary and is not intended to limit the scope of the invention.

The flash memory 100 of an exemplary embodiment of the present invention includes a memory array 110 having a plurality of memory cells arranged in rows and columns, a memory array 110 for input / output (I / O) data electrically coupled to an external I / An address register 130 for obtaining address data from the I / O buffer 120; a data register 140 for storing I / O data; an I / O buffer 120; Controller 150 configured to provide control signals (C1, C2, C3) configured to control respective components based on command data from external control signals (not shown) (not shown, chip enable or address latch enable) A word line selection circuit 160 for selecting blocks and word lines based on the decoding results of row address information Ax from the address register 130, From selected page Page buffer / sense circuits 170 configured to store read data and write data of a selected page, pre-charge circuits 180 for providing pre-charge voltages to bit lines, A column selection circuit 190 for selecting column data to the page buffer / sense circuit 170 based on the decoding results of the column address information Ay, (E.g., program voltage Vpgm, pass voltage Vpass, read pass voltage Vread, erase voltage Vers, soft-program voltage Vsoft, and unselected read voltage VPASSR) And a generation circuit (200).

The memory array 110 has a plurality of blocks BLK (0), BLK (1), ..., BLK (m) arranged along the column direction and the page buffer / And a plurality of pre-charge circuits 180 are arranged along the column direction of the blocks.

Figure 3 illustrates NAND string structures formed in memory blocks and a pre-charge circuit disposed between the blocks. Each of the memory blocks has a plurality of NAND strings NU formed therein, and each of the NAND strings NU includes a plurality of memory cells serially connected in a column direction. In the example illustrated in Fig. 3, there are n + 1 NAND strings NU arranged in the column direction in one memory block.

Each of the NAND strings NU includes a plurality of memory cells MCi (i = 0,1, ..., 31) connected in series in the column direction, a drain side of the memory cell MC31 at one end of the NAND string NU, And a selection transistor TR2 electrically connected to the source side of the memory cell MC0 at the other end of the NAND string NU The drain of the selection transistor TR1 is connected to the corresponding bit Line GBL, and the source of the selection transistor TR2 is electrically connected to the common source line SL.

The control gate of the memory cell MCi is electrically connected to the word line WLi and the gates of the selection transistors TR1 and TR2 are connected to the selection gate lines SGD and SGS parallel to the word lines WL, Respectively. When the memory blocks are selected based on the row address information Ax, the word line selection circuit 160 selectively outputs the selection transistor TR1 or TR2 as a signal from the selection gate lines SGD or SGS of the memory block .

Generally, P-wells are formed in a semiconductor substrate and a semiconductor layer, and blocks are formed in respective P-wells. Each memory cell has a source and a drain, a tunnel oxide layer on the channel region between the source and drain as N-type diffusion, a floating gate (or charge storage layer) for storing charges on the tunnel oxide layer, And a control gate formed with a dielectric layer interposed therebetween. If the charges are not stored or erased, the floating gate remains in the " 1 " state and has a negative threshold voltage, so that the memory cell is in a normally on state. If the charges are stored or programmed, the floating gate remains in a " 0 " state and has a positive threshold voltage so that the memory cell is normally off.

3, the pre-charge circuit 180 includes a block BLK (i) and a block BLK (i + 1) to provide a pre-charge voltage to each bit line GBL. . The pre-charge circuits 180 may be inserted in any number and in any number, but preferably the number of blocks included between the pre-charge circuit 180 and the page buffer / sense circuit 170 is Charge-up circuits 180. The pre- With the arrangement of pre-charge circuits 180, the time required to pre-charge the bit lines can be shortened.

In a preferred embodiment, the pre-charge circuit 180 includes an even-numbered pre-charge transistor PRE_e electrically connected to even bit lines GBL_e, an odd pre-charge transistor electrically connected to odd bit lines GBL_o PRE_o). The even pre-charge transistor PRE_e and the odd pre-charge transistor PRE_o are formed in the word line selection circuit 160 and are operated based on the control signals from the controller 150. [ The metal leads WP_e and WP_o electrically connected to the even pre-charge transistor PRE_e and the odd pre-charge transistor PRE_o extend along the row direction of the memory array 110, respectively. The metal wire WP_e is electrically connected to the even bit lines GBL_e and the metal wire WP_o is electrically connected to the odd bit lines GBL_o. Preferably, the metal leads WP_e, WP_o extend into the space above the common source line SL. Charge read operation is performed, for example, the even-numbered pre-charge transistor PRE_e or the odd-numbered pre-charge transistor PRE_o supplies the pre-charge potential Vpre to the even bit lines GBL_e or the odd bit lines GBL_o To turn it on.

The bit lines GBL0, GBL1, ..., and GBLn are electrically coupled to the NAND strings NU and electrically coupled to the page buffer / sense circuit 170 via a bit line select circuit. During a read and / or program operation, the bit line select circuit selects an even or odd bit line to be electrically coupled to the page buffer / sense circuit 170. For example, if an even bit line is selected, the even bit line is electrically coupled to the page buffer / sense circuit 170 at the top of the memory array 110 of FIG. When an odd bit line is selected, the odd bit line is electrically coupled to the page buffer / sense circuit 170 at the bottom of the memory array 110 of FIG.

FIG. 4 illustrates a circuit diagram for an exemplary structure of a page buffer / sense circuit in accordance with an embodiment of the present invention, as an example, a page buffer / sense circuit 170 electrically connected to one even bit line GBL_e. The page buffer / sense circuit 170 includes a sense circuit for detecting the current of the read even bit line GBL_e and a latch circuit for storing read data or data obtained during programming.

The sensing circuit of this embodiment is of a current type and can be formed by known circuits. Figure 4 illustrates a simplified cascode circuit only, but a circuit comprising a reference cascode circuit and configured to amplify the converted signal through a current-to-voltage conversion by using a differential amplification circuit based on two cascode circuits May be used. 4 includes a P-channel metal oxide semiconductor (PMOS) transistor M1 electrically connected to a power supply Vdd, a resistor R electrically connected to the PMOS transistor M1 in the column direction, Channel metal oxide semiconductor (NMOS) transistor M2 electrically connected to the resistor R and a CMOS inverter IN connected to the gate of the NMOS transistor M2.

The signal " Active " for turning on the sensing circuit is input to the gate of the transistor M1, and the transistor M1 functions as a power source. The gate of the transistor M2 is electrically connected to the output of the inverter IN so that the inverter IN applies the reverse potential of the bit line GBL_e to the transistor M2. That is, the node N2 is electrically connected to the even-numbered bit line GBL_e via the bit line selection circuit to detect the current of the even-numbered bit line GBL_e. If there is a current in the bit line GBL_e, the node N2 has a low potential and the transistor M2 is turned on so that the detection current flows through the transistor M1, (Such as the product of the resistance of the resistor R and the detection detection current flowing through the resistor R) and the sensing node SN outputs the voltage corresponding to the detection detection current. The transistor M2 is turned off so that the detection detection current does not flow through the resistor R and the output (Out) of the sense node SN is turned off, Becomes a spirit. In addition, a shielded read operation may be performed such that when the even bit line is read, the odd bit line has the reference potential and the even bit line has the reference potential when the odd bit line is read. The current sensing circuit of this embodiment can limit the maximum current during operation below a predetermined level in order to suppress power consumption at the time of reading or verification as described below.

Next, the flash memory operation of the present embodiment is described. FIG. 5 shows exemplary bias configurations of the voltages to be erased, written and read, respectively, and F denotes floating. Controller 150 controls word line select circuitry 160, line select circuitry 190 and internal voltage generation circuitry 200 to perform various operations.

The flash memory of this embodiment implements an erase operation including the process illustrated in Fig. After receiving the erase command, the controller 150 performs erasure as shown in FIG. The erase operation includes an ISPE erase operation S100 for applying an erase pulse to a selected block to erase data in the memory cells, an erase verify S110 for determining whether the threshold voltages of the memory cells are below the erase- Program operation (S120) and soft-program verify (S130) that narrows the distribution of the threshold voltages of the cells.

Figure 7 illustrates a timing chart for waveforms of signals applied in erasure verification (ERV) and soft programming (SPGM). Typically, the flash memory is erased in such a way that the data of all the memory cells in the selected block is erased at one time. The erase method may include, for example, applying 0 V to all bit lines of the selected block under the control of the controller 150, floating the select gate lines SGD, SGS, and applying an erase voltage Vers Lt; RTI ID = 0.0 > P-well < / RTI >

7, all the word lines WL_SEL in the selected block are applied with 0 V and the selection gate lines SGD and SGS are applied with the power source voltage Vdd, The erase verify (ERV) is performed under the control of the controller 150, by applying a voltage (e.g., 0.8 V) In erase verification, when the pre-charge voltage Vpre is provided to the bit lines from the pre-charge circuit 180 and the bit lines are coupled to the sense circuit 170, the voltage of the bit lines does not change. That is, the even-numbered pre-charge transistor PRE_e or the odd-numbered pre-charge transistor PRE_o shown in FIG. 3 is turned on for a specific time period before the sensing circuit 170 is connected to the bit lines. It can be expected that the pre-charge voltage Vpre coincides with the voltage provided by the sense circuit 170 since the voltage fluctuation is reduced at the time the bit line is connected to the sense circuit 170. [

When the charges of the memory cells in the selected block are erased, the threshold voltage is shifted to negative, and the memory cells change to the " 1 " state. However, there is a difference between the threshold voltages of the memory cells due to the deterioration of the tunnel oxide layer of the memory cells or the like. The erase verify is configured to determine whether the threshold voltage of the memory cell in the selected block is below the verify threshold voltage Vth. In this embodiment, since sense circuit 160170 is current type, it is determined that the erase is successful if the current in each of the bit lines is greater than or equal to a threshold current of, for example, 1 μA. When the sensing circuit shown in Fig. 4 senses that the current of the transistor M1 is equal to or greater than the threshold current, the sense node SN shows a relatively high voltage corresponding to the threshold current. If the memory cells corresponding to the bit lines have no current or have a current lower than the threshold voltage, the sense node SN shows a relatively low voltage corresponding to the threshold current. Whether the erasure is acceptable may be judged based on the voltage output by the sense node SN. If erasing is determined to be unsuccessful, an erase pulse higher than previously applied to a particular value is applied to the P-well, and the threshold voltage of the memory cells is further shifted to negative. Thus, by repeating the erase and erase verify until all the erase is confirmed to be successful by the erase verify, it is ensured that the maximum voltage Vmax of the threshold voltage distribution of the memory cells in the block is below the verify threshold voltage Vth do. Figure 8 (a) illustrates the threshold voltage distribution of memory cells when the erase verify is complete. The maximum voltage Vmax of the threshold voltage distribution is lower than the threshold voltage corresponding to the erase-verify threshold current. The current of the memory cells referred to herein is the drain current (Id) which can specify the threshold voltage of the memory cells.

A soft program / verify operation is then performed to narrow the threshold voltage distribution of the memory cells. Although the maximum voltage Vmax of the distribution is formed to be lower than the threshold voltage Vth in the previously performed data erase / erase verify, the minimum voltage Vmin of the distribution is not yet considered. Because the ISPE erase / erase verify applies the erase pulse to the entire block for currents that are most difficult to flow through, there are memory cells that are over-erased in the block, i.e., memory cells where the threshold voltage is excessively negative. The soft programming referred to here includes the step of applying a soft-program voltage Vsoftl that is lower than the normally applied voltage Vpgm in normal program operation to provide a force to inject charges into the memory cells to move the threshold voltage in the positive direction .

9 is a flowchart of the soft program / verify operation of the present embodiment. During soft programming, a predetermined initial soft-program voltage V soft1 is set for the memory (S200) and a soft program voltage V soft1 is applied to all the word lines in the selected block, as shown in Figure 7, (Vdd) is applied to the selection gate lines SGD and SGS, and 0 V is applied to all the bit lines to enable writing (S202). At this time, the pre-charge circuit 180 also provides the pre-charge voltage Vpre to the bit lines as it did in the erase verify. The soft-program voltage Vsoft1 is, for example, lower than a relatively normal program voltage, so that the charges are injected more easily into the under-erased memory cells than the memory cells with threshold voltages near the maximum voltage. Thus, the threshold voltages of the memory cells distributed in the vicinity of the minimum voltage as shown in FIG. 8 (b) are shifted in the positive direction to narrow the threshold voltage distribution.

In soft-program verification, a pass voltage VPASSR (e.g., enumerated as 4.5 V in the example of FIG. 5) applied to the non-selected word lines is applied to all the word lines in the selected block (S 204) . As in the case of erase verify, the pre-charge circuit 180 is used for charging and the same bias voltage is applied to the select gate lines SGD, SGS in soft-program verify. The sense circuit 170 is then used to detect whether the current on the bit lines is below the threshold current (i.e., Id < 1 μA?), And if the result is pass, soft programming is determined to be successful (S206). In other words, when the sense node SN shown in Fig. 4 outputs a lower voltage, it is determined that the program operation is successful. If it is determined that the soft programming is not successful, the soft programming is performed again (S208). At this time, a soft-program voltage Vsoft2 higher than the previous soft-program voltage V soft1 is applied to the non-successful bit lines. In the meantime, the bit lines whose soft program is determined to be successful are provided with a write protection voltage obtained by a boost operation using, for example, a boost circuit. By doing so, the threshold voltages of the memory cells corresponding to the fail bit lines move in a positive direction. Soft programming and verification are repeated until all bit lines are accepted (S210). Finally, the current of each bit line of the soft-programmed block is converged to about 1 μA. In addition, Figure 8 (c) illustrates the threshold voltage distribution in program verification. For example, when 1.5V is applied to the selected word line, the current Id of the bit line is lower than 0.15A.

In this embodiment, the minimum voltage of the threshold voltage distribution may be shifted in an amount to narrow the threshold voltage distribution of the memory cells. Accordingly, the maximum value of the current supplied from the sense circuit via the read bit line can be limited to suppress power consumption. Specifically, in soft-program verification, a pass voltage (VPASSR) applied to the word lines that are not selected for readout is applied to all word lines so that the maximum current provided from the readout sense circuit is suppressed, It is determined that the bit lines having currents are detected and passed. This also relates to miniaturization of the sensing circuit. On the other hand, since the pre-charge voltage is provided to the bit lines starting from the sense circuit at random places between the NAND strings NU, the time required for the sense circuit to charge the bit lines can be significantly reduced And the read or program operation can be speeded up.

Although a pair of page buffer / sense circuits disposed on both the top and bottom of the memory array are illustratively illustrated in FIG. 2 and each of the page buffer / sense circuits is electrically connected to the even or odd bit lines, One page buffer / sense circuit may be shared in common by even bit lines and odd bit lines. 10, the page buffer / sense circuit 170 selectively connects the even-numbered bit line GBL_e and the odd-numbered bit line GBL_o via the bit line selection circuit 10, do. Furthermore, in an environment in which the pair of page buffer / sense circuits are electrically connected to these even and odd bit lines, a bit line shielding operation can be performed as described in this embodiment, When the bit lines are being read, the odd bit lines have a reference potential, for example, GND, and when the odd bit lines are being read, the even bit lines have a reference potential such as GND.

Although the erase mode described in the above embodiments includes the steps shown in Fig. 6, the erase mode of the present invention may further include steps different from those shown in Fig. In addition, although each memory cell stores one bit of data in the above embodiments, the present invention is also applicable to memory cells storing multi-bit data. Moreover, each of the values mentioned in the above embodiments is provided by way of example only.

Although the invention has been described with reference to the above embodiments, it will be apparent to those skilled in the art that modifications may be made to the embodiments described without departing from the spirit of the invention.

Claims (10)

A memory array including a plurality of memory cells;
A word line selection circuit configured to select a row of memory cells;
A current sensing circuit electrically connected to each bit line of the memory array to sense the current of the selected bit line; And
And erase the data of the memory cells in a selected block of the memory array, the erase sequence including a erase sequence and a soft-program sequence,
Wherein the erase sequence comprises an erase verify configured to determine whether a current of each bit line of the erased block is greater than a first value and to terminate the erase if the result of the determination is pass,
Wherein the soft-program sequence comprises soft-program verify configured to apply a soft-program voltage to all word lines in the erased block, wherein the current of each bit line is less than a second value lower than the first value And if the result of the determination is affirmative, ends the soft-program verification,
Wherein the soft-program verify is to apply a bias voltage applied to unselected word lines to all of the word lines during a read operation and to determine whether the current of each bit line is lower than the second value . delete The method according to claim 1,
Characterized in that the soft-program sequence applies a write protection voltage to bit lines whose currents are less than the second value, and performs soft programming for the memory cells whose currents are connected to bit lines larger than the second value . The method according to claim 1,
Charge voltage to each of the bit lines and a plurality of pre-charge circuits disposed between the blocks of the memory array. 5. The method of claim 4,
Wherein each of the pre-charge circuits provides the pre-charge voltage to the bit lines prior to supplying currents to the bit lines through the sense circuit. 5. The method of claim 4,
Wherein the sense circuit comprises a first sense circuit electrically connected to the even bit lines and a second sense circuit electrically connected to the odd bit lines,
Wherein the first sensing circuit is disposed next to one end of the memory array,
The second sense circuit is disposed next to the other end of the memory array,
Wherein the plurality of pre-charge circuits are disposed between the first sensing circuit and the second sensing circuit. 5. The method of claim 4,
Wherein each of the pre-charge circuits comprises a conductive line extending from the word line selection circuit in a row direction of the memory array and electrically connected to the bit lines. CLAIMS 1. A method for erasing a semiconductor memory device comprising NAND nonvolatile memory cells,
An erase sequence for determining whether a current of each bit line of the erased block is greater than a first value and terminating the erase if the determination result is passable; And
Performing soft-programming comprising applying a soft-program voltage to all word lines of the erased block, and determining whether the current of each bit line is less than a second value less than the first value And a soft-program sequence to be terminated when the determination result is affirmative,
Wherein the soft-program sequence applies a bias voltage to all the word lines applied to unselected word lines during a read operation and determines whether the current of each bit line is lower than the second value Lt; / RTI &gt; delete 9. The method of claim 8,
The soft-program sequence is characterized in that the soft-program sequence applies a write-protect voltage to the bit lines, where the currents are less than the second value, and further soft programming for the memory cells electrically connected to the bit lines, &Lt; / RTI &gt;

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