JP4832835B2 - Read / write control method for nonvolatile semiconductor memory device - Google Patents

Description

The present invention relates to a read / write control method for a nonvolatile semiconductor memory device in which the gate length of a nonvolatile semiconductor memory cell is shortened.

  In recent years, there has been a growing concern about the limitations of scaling of a so-called code storage NOR flash memory capable of random access reading.

  According to ITRS (International Technology Roadmap for Semiconductors) technology forecast in 2004, the gate length of memory cells of NOR type flash memory is expected even in 2018 when semiconductor technology is expected to be in the age of 20 nm process. It is pointed out that it is difficult to realize 130 nm.

  One of the major factors that the gate length of the NOR flash memory cannot be scaled is that channel hot electron (CHE) injection is used for the write operation. That is, in order to efficiently generate channel hot electrons, a relatively large potential difference higher than the barrier voltage of the tunnel insulating film (silicon oxide film) is required between the source and drain of the memory cell. Because of this potential difference, a relatively large depletion layer is formed from the drain to the source. If the gate length is shortened, the depletion layer is connected from the drain to the source (punch-through), and hot electrons are not generated. This is because there is a problem of end.

On the other hand, a proposal has been made to reduce the potential difference Vds between the source and the drain by using a material having a barrier voltage lower than that of the silicon oxide film as the tunnel insulating film (for example, Patent Document 1). In addition, a NOR flash memory that performs a write operation by a method other than channel hot electron injection has been proposed (for example, Patent Document 2).
JP 2001-237330 A JP 9-008153 A

  However, the material of Patent Document 1 has not been put into practical use as a tunnel insulating film of a nonvolatile semiconductor memory because the charge leakage characteristic of the material is inferior to that of a silicon oxide film.

  Further, in Patent Document 2, writing is performed by hot electron (BBHE) injection induced by band-to-band tunneling instead of channel hot electron injection. Even in this method, the energy of hot electrons is tunneled. In order to make it higher than the barrier potential of the insulating film, it is necessary to set the potential difference Vds between the source and the drain to a relatively large value (for example, 4 V), which causes a problem that the shortening of the gate length is restricted.

SUMMARY OF THE INVENTION Accordingly, the present invention provides a nonvolatile semiconductor memory device and a writing method thereof which can reduce the potential difference Vds between the source and the drain to shorten the gate length of the memory cell and increase the speed . Objective.

A well formed in a semiconductor substrate; a source and a drain formed in the well;
A channel region formed between the source and drain; a charge storage layer formed above the channel region via a tunnel insulating film; and a gate electrode formed above the charge storage layer via an insulating film A method for reading and writing memory cells of a nonvolatile semiconductor memory device, comprising:
When writing, the power supply voltage is represented by VCC,
“VP>VSB>Vs> Vd” “VSB> 0 V” “Vd ≦ VCC”
Voltage VP to have a relationship, VSB, the Vs and Vd, respectively the gate electrodes, the well electrode, by applying to the source electrode and the drain electrode, hot electrons are generated by band-to-band tunneling in the vicinity of the drain, the hot electrons Injecting into the charge storage layer to write bit data to the memory cell,
The same verify voltage is applied to all the word lines in the selected block at the time of erase verify following the erase .

According to the present invention, the relation of “VP>VSB>Vs> Vd”, “VSB> 0V”, “Vd ≦ VCC” is set at the time of writing, that is, the source voltage Vs is set to the well voltage VSB and the drain. By setting the voltage between the voltages Vd , hot electrons or hot holes can be generated efficiently by band-to-band tunneling, the potential difference between the source and drain can be reduced, and the gate length is shortened accordingly. it can.

For high-speed writing, the potential difference between the well voltage VSB and the drain voltage Vd is preferably equal to or higher than the barrier potential of the tunnel insulating film.

Further, at the time of erase verify following erase, by applying the same verify voltage to the word lines for all in the selected block, all the memory cells in the block can be verified by a single read, and the erase verify time can be shortened. .

Embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a diagram showing the structure of a p-channel MONOS memory cell to which the present invention is applied. This memory cell includes an n-type well (cell well) 12 formed on a p-type semiconductor substrate 11, a p + region (source) 13 and a p + region formed at a predetermined interval near the surface of the n-type well 12. (Drain) 14, channel region 20 formed between these two p-type regions 13, 14, ONO film and gate electrode 18 formed so as to cover channel region 20 above channel region 20 Have.

  The ONO film includes a tunnel insulating film 15 made of silicon oxide, a charge trap layer 16 made of silicon nitride for accumulating injected charges (electrons), and an insulating film 17 made of silicon oxide. The thickness of these three layers is about 2.5 to 5 nm for the tunnel insulating film 15, about 10 nm for the charge trap layer 16, and about 5 nm for the insulating film 17. The gate electrode 18 is made of polysilicon. Note that the gate length can be extremely shortened by a write potential arrangement described later, and can be 60 nm or less.

Next, the architecture of a nonvolatile semiconductor memory device having a structure in which the p-channel MONOS memory cells are connected in an NOR-connected array will be described with reference to FIG.
In this nonvolatile semiconductor memory device, two cell wells 12 are paired. In each cell well 12, 1kB = 8k (8192) in the X direction × 64 in the Y direction = 512k (524288) memory cells are formed. The number of main bit lines 21 is 8k, and is connected to one sub bit line 25 of the two cell wells 12 through a select gate 24. A column latch is connected to each of the 8k main bit lines 21. This column latch is also used for verifying the write operation. The select gate 24 is formed in a select gate well (n-type well) 20 different from the cell well 12, and is composed of a p-channel MOS transistor. The potential of select gate well 20 is normally set to VCC (for example, 1.8 V). VCC is applied to the gate electrode of the select gate 24 when not selected, and −2.2 V is applied when selected. When −2.2 V is applied, the gate becomes conductive and connects the main bit line 21 to the sub bit line 25 connected to the drain of each memory cell. The word lines connect the gate electrodes of the memory cells in the X direction, and 64 word lines are provided for each cell well 12. The source line is common to 512 k memory cells in each cell well 12.

  The voltage VCC and the voltage GND (ground voltage) are supplied from a power supply circuit outside the memory cell.

Next, in the NOR-connected non-volatile semiconductor memory device of FIG. 2, operations for performing program, program verify, erase, erase verify, and read will be described with reference to FIGS.
FIG. 3 shows the voltage applied to each part during each operation. Here, the meaning of each symbol is as follows.

MBL: main bit line SG: select gate SBL: sub-bit line WL: word line SL: source line WEL: well WELSG: well of select gate sub: substrate Further, FIGS. It shows the potential change of each part.

<Program operation>
FIG. 4 is a diagram showing the potential arrangement and operation principle during the program operation.
In this nonvolatile semiconductor memory device, when writing by BBHE injection, the source voltage Vs is made lower than the cell well voltage VSB so as to be close to the drain voltage Vd, and the potential difference between the drain and the source is reduced. By making the threshold voltage Vth (absolute value) equivalently higher by the back gate effect due to the application of the back gate voltage, it is difficult to punch through between the source and the drain. This realizes a cell structure in which the gate length is reduced to 0.1 μm or less, for example, about 60 nm.

  Further, by applying an appropriate back gate voltage to the cell well, the bit line that requires the highest speed operation at the time of writing and reading can be operated by GND-VCC. As a result, the bit line control circuit can be configured with a high-speed standard positive VCC circuit, which enables high-speed and simplified configuration.

First, the program operation of the write operation will be described. As described above, in the MONOS memory cell, since the nitride film having low conductivity is used as the charge trap layer 16, the trapped electrons do not move in the film but remain in the trapped position.
Writing (programming) into the memory cell is performed by injecting electrons into the charge trap layer 16. Electrons are injected by BBHE injection by applying a positive and negative high voltage between the gate electrode 18 and the drain 14 shown in FIG. 1, and electrons are injected into the charge trap layer 16.

  Charge injection into the charge trap layer 16 is performed by hot electrons (BBHE: Band-to-Band) by band-to-band tunneling using a high electric field of a depletion layer generated by a high potential difference between a positive potential gate electrode 18 and a negative potential drain 14. tunneling induced hot electron) However, a positive back gate voltage is applied to the cell well 12 so that the drain (= bit line) can be controlled within a positive potential range. As a result, the ground potential of the drain becomes a relatively negative potential.

  Specifically, as shown in FIGS. 2 to 5, +4 V is applied as the back gate voltage VSB to the cell well 12, and the bit line BL (however, in the example of FIG. 4, the bit line is divided for each cell well). Since the main bit line MBL and the select gate SG are provided, the main bit line MBL) is set to the ground potential GND (= 0V). Then, 10V is applied as the gate voltage VP to the word line WL. At this time, VCC (= 1.8 V) is applied to the source line SL.

This program operation will be described with reference to FIGS.
FIG. 15 is a diagram showing the configuration of the column latch. FIG. 12 is a voltage waveform diagram of each part of FIG. 15 during the program operation.

  First, write data is set in advance in the column latch shown in FIG. 15. For the bit line to be written (selected MBL), node NA = L, node NB = H state (L is low level, H is high level) The bit lines (non-selected MBL) that are not written and are not written are set to NA = H and NB = L.

  From the standby state, first, at t1, the selection WEL is set to 4V. This is realized by activating a positive charge pump circuit connected to the WEL driver circuit via a distributor circuit.

  At t2, the selection SG is set to -2.2V. This can be realized by activating a negative charge pump circuit connected to the SG driver circuit via a distributor. As a result, the selected SBL is connected to MBL and charged to VCC.

At t3, the non-selected WL is set to GND. Until now, both selected WL and non-selected WL have been set to VCC. Detailed description will be made separately when the WL driver circuit is described.
At t4, the selection WL is set to 10V. This is realized by activating a positive charge pump circuit connected to the WL driver circuit via a distributor circuit.

At t5, / BLH = H is set, the transistor P9 is turned off, and MBL is set in the H floating state.
At t6, DDRV = H and / DDRV = L. Thereby, for the bit line to be written, since node NB = H, MBL is set to L (GND level). On the other hand, MBL is set to H (VCC level) because NB = L for a bit line not to be written.

  In the state of t7, 4V is applied to the cell well of the selected memory cell, 0V is applied to the drain, 10V is applied to the gate, and VCC (= 1.8V) is applied to the source.

  With this voltage arrangement, a depletion layer region is generated at the junction between the drain and the cell well. Electron / hole pairs are generated in the drain by band-to-band tunneling (BTBT). These electrons are accelerated by the strong electric field in the depletion region and become hot electrons having high energy, and a part of the electrons are attracted to the positive voltage applied to the gate electrode and injected into the charge trap layer over the tunnel oxide film. .

  After maintaining the state in the latter half of the predetermined time t7 (this state is called program pulse application), the applied voltage is returned by the following procedure.

At t8, DDRV = L and / DDRV = H are set, and the transistors P5 and N5 are turned off.
At t9, / BLH = L.
Thereby, the selection MBL returns to VCC in the state of t10.

At t11, the selection WL is returned to VCC. This is realized by deactivating the positive charge pump circuit connected to the WL driver circuit via the distributor.
At t12, the selected WL is set to GND and the non-selected WL is set to VCC.

<Program verify operation>
Next, the program verify operation will be described with reference to FIG. 2, FIG. 3, FIG. 6, and FIG. Program verify is performed by confirming whether the threshold value of the cell to be programmed is a predetermined potential. Therefore, the operation is repeatedly executed alternately with the program.

In order to realize high-speed writing, it is necessary to switch between the program and verify operations at high speed. In the program operation, the back gate voltage VSB is applied to the cell well 12, and it takes a long time to change the voltage of the cell well having a large parasitic capacitance from 4V to VCC at the time of program / verify switching. Therefore, verification is performed while the back gate voltage VSB (= 4 V) is applied to the cell well 12.
In the verify operation, since the voltage of the cell well 12 remains 4 V, the word line WL is set to a voltage higher than a normal read voltage (−2.2 V; described later), for example, −5 V. In this state, after the source line SL and the bit line MBL are charged to VCC, the source line SL is driven to GND. When the program is completed, the channel becomes conductive, so that the bit line MBL is discharged and becomes GND. If the program is not completed, the bit line MBL remains at VCC. The potential of the bit line MBL is taken into the column latch, and based on this, the bit line MBL voltage when the next program pulse is applied is determined. That is, only the bit line whose latched potential is VCC is to inject electrons again at the next program pulse.

  As described above, since the verify is performed while the back gate voltage VSB (= 4 V) is applied to the cell well 12, the program / verify switching can be performed at high speed, and high-speed writing of bits is realized. it can.

This program verify operation will be described with reference to FIG.
First, at t13, the selection WL is set to −5V. This is realized by activating a negative charge pump circuit connected to the WL driver circuit via a distributor circuit.

  In the verify operation, since the cell well voltage remains at 4V, the word line is set to a voltage (−5V) whose absolute value is higher than a normal read voltage (−2.2V described later).

At t14, / BLH = H is set, and MBL is set in the H floating state.
Subsequently, VRFR is set to = H at t15. At this time, if NA is H, MBL is discharged to GND through the transistors N7 and N8. The state of NA = H indicates that the column latch has succeeded in writing, and the corresponding MBL is discharged through the transistors N7 and N8 before being discharged through the memory cell in which writing is completed.

At t16, the selection SL is set to GND.
When the program is completed, since the channel of the selected memory cell becomes conductive, SBL and MBL are discharged. On the other hand, if the program is not complete, SBL and MBL remain at VCC.

At t17, / SENSE = L.
If MBL is discharged, the transistor P3 is turned on, the node NA is set to H, and the writing is successful. In this state, when the next program pulse is applied (t7), MBL becomes H and no program pulse is applied.

  On the other hand, if MBL is not discharged and remains H, the transistor P3 is turned off and the node NA remains L. In this state, when the next program pulse is applied (t7), MBL becomes L and the program pulse is applied. That is, it is determined whether or not to inject electrons again when the next program pulse is applied according to the latched potential.

At t18, VRFR is returned to L, and / SENSE is returned to H.
At t19, / BLH is set to L.
Thereby, MBL returns to VCC in the state of t20.

  At t21, the selection WL is returned to GND. This can be realized by deactivating a negative charge pump circuit connected to the WL driver circuit via a distributor circuit.

This completes the program verify operation. At this time, the state of the column latch is confirmed. If the program is completed, the process proceeds to t22. If not completed, the process returns to t3.
The operation from t3 to t21 is repeated until the program is completed.

At t22, the non-selected WL is set to VCC.
At t23, the selection SG is set to VCC. As a result, SBL is electrically disconnected from MBL, and SBL enters a floating state.

At t24, the selection WEL is set to VCC. This can be realized by deactivating a positive charge pump circuit connected to the WEL driver circuit via a distributor circuit.
This returns to the standby state.

  As described above, the operation of performing verification while applying the back gate voltage VSB (= 4 V) to the cell well 12 has been described. However, the potential of the cell well 12 is changed from VSB (= 4 V) to VCC (= 1.8 V) at t12 in FIG. You may return and operate.

  A state in which a high voltage is applied to the cell well 12 and a negative voltage is applied to the gate electrode is the same as the potential relationship at the time of erasure described later.

  Depending on the manufacturing process, an erasing operation may occur in the cell even when the verify potential is related. In order to solve such a problem, the cell well potential must be returned to VCC for verification.

  When operated in this way, the effect that the time required for charging and discharging the well can be shortened cannot be obtained. On the other hand, the potential (VVR) of the gate electrode at the time of verification can be changed from -5V to -2.2V. . These voltages are normally generated from the charge pump, but the power consumption of the charge pump is proportional to the absolute value of the generated voltage. Therefore, when the voltage is changed from -5V to -2.2V, the power consumption of the charge pump is correspondingly changed. Can be reduced.

<Read operation>
On the other hand, the read (read) operation requires a higher speed operation than the write operation, and it is necessary to switch not only the bit line but also the word line at a high speed. (VCC = 1.8V), and the read voltage applied to the word line WL is -2.2V.

  Here, the read operation will be described with reference to FIG. 2, FIG. 3, FIG. 8, and FIG. At the time of reading, VCC is applied to the cell well 12 as a back gate voltage, and VCC is similarly applied to the source line SL. After the bit lines 21 and 25 to be read (the drain 14 shown in FIG. 1) are set to GND, the word line WL to be read is changed from VCC to the read voltage VR = −2.2V. As a result, if the cell is in the programmed state in this potential arrangement, the bit line MBL rises to VCC, and remains in GND if in the non-programmed state.

This read operation will be described with reference to FIG.
From the standby state, first, at t1, / BLH is set to H and / BLL is set to H. At the same time, READ = H is set to turn on the transistor N3. At this time, since / SENSE is H and the transistor N4 is also in the ON state, the node NA is set to L. Further, the selection WL is set to GND, and the selection SG is set to GND.

In response to / BLL = H, MBL becomes L in the t2 state.
At t3, the negative charge pump connected to the SG driver circuit via the distributor circuit is activated to set the selected SG to −2.2V. As a result, the selected MBL and the selected SBL are electrically connected, and the selected SBL also becomes L.
At t4, / BLL is set to L and MBL is set to L floating.
At t5, the negative charge pump circuit connected to the WL driver circuit via the distributor is activated to set the selection WL to −2.2V.

  If the selected memory cell is in the programmed state, the channel becomes conductive and the selected SBL is charged to VCC, and the selected MBL is charged to VCC accordingly.

  On the other hand, if the selected memory cell is in the erased state, the channel is non-conductive, and the selected SBL and the selected MBL maintain L floating.

  At t6, / SENSE is set to L. If MBL is H, since the transistor P3 is in the OFF state, the node NA remains L, indicating that the selected memory cell is in the programmed state.

On the other hand, when MBL remains L, the transistor P3 is turned on, the node NA is set to H, and the selected memory cell is in the erased state. This value is output as read data from the chip. (Output circuit not shown)
At t7, / SENSE = H. At this time, since READ = H, the node NA is set to L.
At t8, the selected WL is returned to GND by deactivating the negative charge pump circuit connected to the WL driver circuit via the distributor circuit. At the same time, the selection SL is returned to GND by deactivating the negative charge pump circuit connected to the SG driver circuit via the distributor circuit.

  At t9, / BLH is set to L. Thereby, MBL returns to VCC in the state of t10.

At t11, READ is returned to L, selection WL is returned to VCC, and selection SG is returned to VCC.
This returns to the standby state.

<Erase operation>
Next, the erase operation will be described. As an erasing method, there are an FN (Fowler-Nordheim) tunnel extraction and a substrate hot hole injection erasing method.

  Here, extraction by the FN tunnel will be described with reference to FIGS. Erasing is performed in units of 12 cell wells. The cell well 12 and the source line SL are set to 6V, a high voltage of −8V is applied to the word line WL, and the bit line MBL is floated. As a result, a large potential difference is generated between the gate 18 and the cell well 12, and electrons trapped in the charge trap layer 16 are extracted by jumping to the cell well 12 through the tunnel insulating film 15 by the FN tunnel effect.

  With the above-described potential arrangement and operation, the Y-system circuit can be configured with a high-speed circuit operating at GND-VCC.

This erase operation will be described with reference to FIG.
From the standby state, first, at t1, the selection WL is set to GND. Since erasing is performed in units of blocks, the selected WL is all WLs in the corresponding block. For example, in the case of a memory array as shown in FIG. 24, the number of memory cells is 64 from WL (0) to WL (63).

  At t2, the positive charge pump circuit connected to the WEL driver circuit, the SG driver circuit, the WELSG driver circuit, and the SL driver circuit via the distributor circuit is activated and connected to the WL driver circuit via the distributor circuit. The negative charge pump circuit is activated. Thereby, the selection WEL, the selection SG, the selection WELSG, and the selection SL become 6V, and the selection WL becomes −8V. In addition, since the channel of the selected memory cell is conductive, the selected SBL becomes 6V having the same potential as SL.

  With this potential arrangement, a large potential difference is generated between the gate and the rain of the selected memory cell (in this case, 14V), and electrons trapped in the charge trap layer pass through the tunnel oxide film by the FN tunnel effect and drain. It is pulled out by jumping to.

  After maintaining the state in the latter half of the predetermined time t2 (this state is called erase pulse application), the applied voltage is returned by the following procedure.

  At t3, the positive charge pump circuit connected to the WEL driver circuit, the SG driver circuit, the WELSG driver circuit, and the SL driver circuit via the distributor circuit is deactivated. Thereby, selection WEL, selection SG, selection WELSG, and selection SL return to VCC. Since the selected WL remains at -8V, the channel of the selected memory cell is still conductive, and SBL returns to the same VCC as SL.

At t4, the negative charge pump circuit connected to the WL driver circuit via the distributor circuit is deactivated. As a result, the selection WL becomes GND.
At t5, the selection SG is set to GND.
Thereafter, the process proceeds to the erase verify operation. The erase verify is an operation for confirming whether the threshold value of the cell to be erased is at a predetermined potential.

  At t6, the negative charge pump connected to the WL driver circuit via the distributor circuit is activated to set the selected WL to −6V. At the same time, the negative charge pump connected to the SG driver circuit via the distributor circuit is activated to make the selection SG −2.2V.

At t7, when READ = H and the transistor N3 is turned on , the transistor NA4 is already turned on, so that the node NA is set to L. When the node NA becomes L, the node NB becomes H.

At t8, / BLH = H. As a result, the transistor P9 is turned OFF and the MBL is in the H floating state.
At t9, the selection SL is set to GND.

  Since the channel is cut off when erasing is completed, SBL and MBL are not discharged. On the other hand, if there is even one programmed cell, SBL and MBL are discharged through the channel of that cell.

  At t10, / SENSE = L. If MBL is not discharged and remains H, since the transistor P3 is in the OFF state, the node NA remains L, indicating that the target memory cell is in the erased state. On the other hand, when MBL is discharged and falls to L, the transistor P3 is turned on and the node NA is set to H, indicating that the target memory cell is in the write state.

  If the target memory cell is in a write state, the next erase pulse is applied. Since all the WLs in the block are selected and verified, the verify operation can be performed by one reading.

At t11, / SENSE = H. At this time, since READ = H, the node NA is set to L.
At t12, / BLH = L and READ = L.
At t13, MBL becomes VCC in response to / BLH = L.
At t14, the selected WL is returned to GND by deactivating the negative charge pump circuit connected to the WL driver circuit via the distributor circuit.

At t15, the selection SG is returned to GND by deactivating the negative charge pump circuit connected to the SG driver circuit via the distributor circuit.
At t16, the selection SG is returned to VCC.

This completes the erase verify operation. At this time, the state of the column latch is confirmed. If erasing is completed, the process proceeds to t17, but if completed, the process returns to t2.

The operation from t2 to t16 is repeated until the erasure is completed.
At t17, the selection WL is returned to VCC.
This returns to the standby state.

Next, the configuration of each driver circuit and distributor circuit will be described.
<WL driver circuit>
When the program pulse is applied, the selected WL is set to 10 V, and the non-selected WL is set to GND (see t7 during the program operation in FIG. 12).

  When the erase pulse is applied, the selection WL is set to -6V, and the non-selection WL is set to VCC (= 1.8V) (see t2 during the erase operation in FIG. 14).

  An example of a decoder circuit that supplies positive and negative voltages to the selection WL is disclosed in Japanese Patent No. 3223877.

  However, in this configuration, the non-selected WL is fixed at 0V, which is not suitable for the current WL decoder operation. Therefore, a circuit capable of changing the non-selected WL to VCC and GND is realized by the configuration shown in FIG.

  FIG. 16 shows a WL driver circuit. In FIG. 16, VPWL is a positive high voltage equal to or higher than VCC, and receives a voltage from the positive charge pump circuit via a distributor circuit described later.

  On the other hand, VNWL is a negative high voltage equal to or lower than GND, and receives a voltage from a negative charge pump circuit via a distributor circuit described later. A level shift circuit 17 including transistors N6, N7, P6, P7 and an inverter 15 converts a binary signal of [VCC, GND] of the input signal SELWL into [VPWL, GND].

  The level shift circuit 18 that has received a signal from the level shift circuit 17 comprises transistors N5, N4, P5, and P4. The level shift circuit 18 converts the binary signal of the input signals [VPWL, GND] into [VPWL, VNWL] and supplies it to the node VSELWL. To do.

  On the other hand, a level shift circuit 19 comprising transistors N12, N13, P12, P13 and an inverter 16 receives a binary signal [VPWL, GND] of the output [VCC, GND] of the AND gate 17 that decodes the WL selection address signal. Convert to

  The level shift circuit 20 that receives the signal from the level shift circuit 19 includes transistors N10, N11, P10, and P11. The level shift circuit 20 converts the binary signal of the input signal [VPWL, GND] into [VPWL, VNWL]. Supply to the inverter consisting of P9.

The output of the inverter composed of the transistors N9 and P9 is DECWL1.

  DECWL1 is input to an inverter composed of transistors N8 and P8, and the inverter outputs DECWL0.

  When the address is selected and the output of the AND gate 17 is VCC, DECWL1 becomes VPWL and DECWL0 becomes VNWL. At this time, since the transistors N2 and P1 are turned on and the transistors N1 and P2 are turned off, the voltage VSELWL propagates to WL. This is the WL selection state.

As described above, when SELWL = VCC, VSELWL = VPWL, and a positive high voltage is applied to the selected WL.
Further, when SELWL = GND, VSELWL = VNWL, and a negative high voltage is applied to the selected WL.
Thereby, a positive and negative high voltage can be applied to the selection WL.

  On the other hand, when the address is in a non-selected state and the output of the AND gate 17 is GND, DECWL1 becomes VNWL and DECWL0 becomes VPWL.

  At this time, since the transistors N2 and P1 are turned off and the transistors N1 and P2 are turned on, the voltage VUSELWL propagates to WL. This is the WL non-selected state.

When USELWL is GND, VUSELWL is set to VCC by the inverter 14, and non-selected WL is set to VCC.

  When USELWL is VCC, VUSEWL is set to GND by the inverter 14, and the non-selected WL is set to GND.

  According to the above configuration, the selected WL can be set to a positive and negative high voltage, and the non-selected WL can be set to VCC / GND.

<SG driver circuit>
FIG. 17 is a diagram showing the configuration of the SG driver circuit. The symbol of the element corresponds to each element of the WL driver circuit. The configuration of the SG driver circuit is the same as that of the WL driver circuit, but the portion corresponding to the VUSELWL signal in the WL driver circuit is VCC. This is because in SG, the level of the non-selected SG is always VCC in each operating condition.

  According to such a configuration, the selection SG can be set to a positive and negative high voltage VPSG, and the non-selection WL can be set to VCC.

<WEL driver circuit>
FIG. 18 is a diagram showing the configuration of the WEL driver circuit.
According to this configuration, the VPWEL level is supplied to the selected WEL, and VCC is supplied to the non-selected WEL.

<WELSG driver circuit>
FIG. 19 is a diagram showing the configuration of the WELSG driver circuit.
According to this configuration, the VPWELSG level is supplied to the selected WELSG, and VCC is supplied to the non-selected WELSG.

<SL driver circuit>
FIG. 20 is a diagram illustrating a configuration of the SL driver circuit.
VCC, GND and 6V at the time of erasing are applied to SL. A high voltage of 6V is supplied to VPSL. When selected by the decode signal, the transistors P1 and N2 are turned on, the transistor N1 is turned off, and VSELSL is propagated to SL.

  On the other hand, in the non-selected state, the transistors P1 and N2 are turned off, the transistor N1 is turned on, and GND is propagated to SL.

  At the time of erase verify (t9) and program verify (t16), the selected SL is changed to GND, and SBL and MBL are discharged through the memory cell group in the programmed state connected to the SL.

  The selection SL is changed to GND by setting / SETH to H.

<Distributor circuit>
As shown in FIG. 16, the WL driver circuit receives VPWL as a positive high voltage equal to or higher than VCC and VNWL as a negative high voltage equal to or lower than GND from the distributor circuit.

Hereinafter, the distributor circuit will be described.
FIG. 21 is a diagram showing the configuration of the distributor circuit. VPH is a first positive charge pump circuit, VPL is a second positive charge pump circuit, VNH is a first negative charge pump circuit, and VNL is a second negative charge pump circuit.

  The charge pump circuit is a high voltage generating circuit disclosed in, for example, Japanese Patent No. 2141320, and receives an activation signal (not shown) and applies a high voltage to an output terminal.

The charge pump disclosed in Japanese Patent No. 2141320 can generate a desired voltage level by sensing the level of the output voltage and hooding it back.
The output of the charge pump VPH is connected to VPWL through the positive switching circuit SP1.

  Positive switching circuit SP1 has a mode for electrically connecting the output of VPH and VPWL and a mode for electrically connecting power supplies VCC and VPWL in accordance with a control signal (not shown). Specifically, for example, the circuit shown in FIG. 22 similar to the circuit disclosed in Japanese Patent No. 2658916 can be realized.

  Here, when the output of VPH and VPWL are electrically connected, SELVPH is set to H. At this time, the transistor P16 is turned on by the level shift circuit composed of the transistors N13, N14, P13, and P14, and the transistor P15 is turned on by the level shift circuit composed of the transistors N11, N12, P11, and P12. .

  On the other hand, the transistor N16 is in an OFF state. Thereby, VPH and VPWL are electrically connected.

  When electrically connecting VCC and VPWL, SELVCC is set to H. At this time, the transistor P6 is turned on by the level shift circuit composed of the transistors N3, N4, P3, and P4, and the transistor P5 is turned on by the level shift circuit composed of the transistors N1, N2, P1, and P2. .

On the other hand, the transistor N6 is in an OFF state. Thereby, VCC and VPWL are electrically connected.
The output of the charge pump VNH is connected to VNWL through the negative switching circuit SN1.

  The negative switching circuit SN1 has a mode for electrically connecting the output of VNH and VNWL and a mode for electrically connecting power supplies GND and VNWL in accordance with a control signal (not shown).

A specific circuit can be realized by the configuration of FIG. 23 similar to the circuit disclosed in, for example, Japanese Patent No. 2658916.

  When electrically connecting the output of VNH and VNWL, SELVNH is set to L.

At this time, the transistor N16 is turned on by the level shift circuit composed of the transistors N13, N14, P13, and P14, and the transistor N15 is turned on by the level shift circuit composed of the transistors N11, N12, P11, and P12. .

On the other hand, the transistor P16 is in an OFF state.
Thereby, VNH and VNWL are electrically connected.

To electrically connect GND and VNWL, SELGND is set to L. At this time, the transistor N6 is turned on by the level shift circuit composed of the transistors N3, N4, P3, and P4, and the transistor N5 is turned on by the level shift circuit composed of the transistors N1, N2, P1, and P2. . On the other hand, the transistor P6 is in an OFF state.
Thereby, GND and VNWL are electrically connected.

  With the above configuration, either VPH or VCC is transmitted to VPWL, and either VNH or GND is transmitted to VNWL.

  As shown in FIG. 17, the SG driver circuit receives VPSG as a positive high voltage equal to or higher than VCC and VNSG as a negative high voltage equal to or lower than GND from the high voltage switching circuit.

  In FIG. 21, the output of the charge pump VPH is connected to VPSG through the positive switching circuit SP2. The output of the charge pump VNL is connected to VNSG through the negative switching circuit SN2.

  With such a configuration, either VPH or VCC voltage is propagated to VPSG, and either VNL or GND voltage is propagated to VNSG.

  The output of the charge pump VPL is connected to VPSL, VPWEL, and VPWELSG via positive switching circuits SP3, SP4 and SP5, respectively.

  As described above, in this embodiment, by applying a back gate voltage and applying a voltage between the drain voltage and the source voltage to the source, the voltage applied between the drain and the source decreases, and the back gate effect Therefore, Vth (absolute value) is equivalently increased, so that punch-through is difficult, which makes it possible to greatly improve the scalability of the gate length (short gate). It is no longer difficult to realize a gate length of 1 μm or less.

Further, in this embodiment, at the time of erase verify, all the memory cells in the block can be verified by a single read operation by applying the same verify voltage to the word lines in all of the selected blocks, thereby shortening the time of erase verify. it can.

  In this embodiment, a writing method for a memory cell having a p-channel MONOS structure has been described. However, the present invention is applied to an n-channel MONOS memory by inverting the polarity of the potential arrangement in FIG. Is also possible.

  In this embodiment, the writing method for the memory cell having the MONOS structure shown in FIG. 1 is described. However, in addition to this, the floating gate type nonvolatile semiconductor memory holds charges in the nanocrystal layer. The present invention can be applied to a nonvolatile semiconductor memory or the like.

  Note that the voltage values shown in FIG. 3 and the like are merely examples, and any voltage may be used as long as the voltage meets the conditions of the present invention.

It is a figure which shows the structure of the p channel MONOS memory cell to which this invention is applied. FIG. 3 is an equivalent circuit diagram showing an architecture when a NOR connection array is configured by arranging the p-channel MONOS memory cells in XY. It is a figure which shows each potential arrangement | positioning at the time of the program operation | movement in the same NOR connection array, the program verify operation | movement, the erase operation | movement, the erase verification operation | movement, and the read operation | movement. It is a figure which shows the electric potential arrangement | positioning in the equivalent circuit at the time of program operation | movement. It is a figure which shows the electric potential arrangement | positioning in the cross-section at the time of program operation. It is a figure which shows the electric potential arrangement | positioning in the equivalent circuit at the time of program verification operation | movement. It is a figure which shows the electric potential arrangement | positioning in the cross-section at the time of program verification operation | movement. It is a figure which shows the electric potential arrangement | positioning in the equivalent circuit at the time of read-operation. It is a figure which shows the electric potential arrangement | positioning in the cross-sectional structure at the time of read-operation. It is a figure which shows the electric potential arrangement | positioning in the equivalent circuit at the time of the erase operation by FN tunnel. It is a figure which shows the electric potential arrangement | positioning in the cross-section at the time of the erase operation by FN tunnel. It is a voltage waveform diagram at the time of program operation. It is a voltage waveform diagram at the time of a read operation. It is a voltage waveform diagram at the time of erase operation. It is a figure which shows the structure of a column latch. It is a figure which shows the structure of WL driver. It is a figure which shows the structure of SG driver. It is a figure which shows the structure of a WEL driver. It is a figure which shows the structure of a WELSG driver. It is a figure which shows the structure of SL driver. It is a figure which shows the structure of a distributor circuit. It is a figure which shows the structure of a positive / high voltage switching circuit. It is a figure which shows the structure of a negative high voltage switching circuit. It is a figure which shows the structure of a memory cell array.

Explanation of symbols

11 ... p-type semiconductor substrate 12 ... n-type well (cell well)
13 ... Source (p + region)
14 ... Drain (p + region)
15 ... Tunnel insulating film 16 ... Charge trap layer (nitride film)
17 ... Upper insulating layer 18 ... Gate 20 ... Select gate well (n-type well)
21 ... Main bit line 22 ... Word line 23 ... Source line 24 ... Select gate 25 ... Sub bit line

Claims (1)

An n-type well formed in a semiconductor substrate, a source and a drain formed in the n-type well,
A channel region formed between the source and drain; a charge storage layer formed above the channel region via a tunnel insulating film; and a gate electrode formed above the charge storage layer via an insulating film A method for reading and writing memory cells of a nonvolatile semiconductor memory device, comprising:
When writing, the power supply voltage is represented by VCC,
“VP>VSB>Vs> Vd” “VSB> 0 V” “Vd ≦ VCC”
Are applied to the gate electrode, the n-type well electrode, the source electrode, and the drain electrode, respectively, thereby generating hot electrons due to band-to-band tunneling near the drain. Injecting electrons into the charge storage layer to write bit data to the memory cell,
A read / write control method for a nonvolatile semiconductor memory device, wherein the same verify voltage is applied to all word lines in a selected block at the time of erase verify following erase.

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