JPH11134879A - Nonvolatile semiconductor storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a nonvolatile semiconductor storage device which can be optimized and which prevents an erroneous write operation by a method wherein a first write voltage is applied across a control gate and a semiconductor layer in a first write cycle used to write data '1' to a memory cell, a second write voltage is applied in a second write cycle used to write data '2' and the potential difference between both is made nearly equal to verify voltages of the respective data. SOLUTION: When data '1' is written, data in a latch circuit LT1 is output to a bit line BL1. A HIGH voltage Vpp for a write operation is applied to a control gate CG1. A voltage VM10 is applied to other control gates CG2 to CG8. When the write operation is finished, a voltage is applied to the control gate CG1, and a verify read operation is started. When a voltage VL2 becomes a HIGH level, data in the bit line BL1 is latched by the latch circuit LT1. Data '2' is written. After that, a data write operation and a verify operation are performed a plurality of numbers of times. A voltage which can be written is given to a memory cell which is written most quickly, and an erroneous write operation is prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to, for example, an electrically rewritable nonvolatile semiconductor memory device (EEPROM), and more particularly to a nonvolatile semiconductor memory device capable of storing multi-value data.

[0002]

2. Description of the Related Art In recent years, a NAND cell type EEPROM has been used as one of electrically rewritable nonvolatile semiconductor memory devices.
M has been proposed. This NAND cell type EEPROM
Are connected in series by sharing the source and drain of a plurality of memory cells with adjacent ones, and connecting them to a bit line as a unit. Each memory cell is connected to a floating gate as a charge storage layer. , And an n-channel FET MOS structure in which control gates are stacked.

FIGS. 14A and 14B are a plan view and an equivalent circuit diagram of one NAND cell portion of a memory cell array.
FIG. 15A is a sectional view taken along line 15a-15a shown in FIG. 14A, and FIG. 15B is a sectional view taken along line 15b-15b shown in FIG. 14A.

On a p-type silicon substrate (or p-type well) 71 surrounded by an element isolation oxide film 72, a memory cell array composed of a plurality of NAND cells is formed. In this example, one NAND cell has eight memory cells M
1 to M8 are connected in series. In each memory cell, the floating gate 74 (74 ₁ , 74 ₂ ... 74)
₈ ) is formed on a substrate 71 with a gate insulating film 73 interposed therebetween. Adjacent ones of the n-type diffusion layers 79 as the source and drain of these memory cells are connected in series.

[0005] The drain side of the NAND cell, a first selection gate 74 ₉ to the source side, 76 _9, and the second selection gate 74 _10, 76 ₁₀ are provided. Each first select gate 74 _9, 76 _9, and the second selection gate 74 _10, 76 ₁₀ floating gates 74 of memory cells (74 ₁ ... 74 _8), the control gate 76 (76 ₁ ... 76 ₈₎ formed simultaneously with Is done. The first selection gate 74 _9, 76 _9, and the second selection gate 74 _10, 76 ₁₀ are both in the desired portion (not shown) 1
The second layer and the second layer are electrically connected. The substrate on which the elements are formed is covered with a CVD oxide film 77, on which bit lines 78 are provided. NAND cell control gate 76
_{1, 76 2 ... 76 8 (} CG 1, CG 2 ... CG 8) is a word line, the select gate 74 _9, 76 ₉ and 74 _10,
76 ₁₀ (SG ₁ , SG ₂ ) are arranged in the row direction, and serve as select gate lines.

FIG. 16 shows an equivalent circuit of a memory cell array in which NAND cells having the above configuration are arranged in a matrix. In this example, the source line is connected to a reference potential wiring made of aluminum, polysilicon, or the like via a contact, for example, at one place for every 64 bit lines. This reference potential wiring is connected to a peripheral circuit. The control gate and the first and second select gates of the memory cell are arranged continuously in the row direction. Usually, a set of memory cells to which control gates are commonly connected is called one page, and is arranged between a pair of select gates on the drain side (first select gate) and the source side (second select gate). A set of pages that have been set is called one NAND block or simply one block. 1
The page is composed of, for example, 256 bytes (256 × 8) memory cells. Writing is performed almost simultaneously on the memory cells for one page. One block is, for example, 2048
It is composed of byte (2048 × 8) memory cells. Memory cells for one block are erased almost simultaneously.

The operation of the NAND type EEPROM is as follows, for example. Data writing is performed sequentially from the memory cell farthest from the bit line. A boosted write voltage Vpp (= about 20 V) is applied to the control gate of the selected memory cell, and an intermediate potential (about 10 V) is applied to the control gate and the first select gate of the other unselected memory cells. 0 V ("0" write) or an intermediate potential ("1" write) is applied to the bit line according to the data. At this time, the potential of the bit line is transmitted to the selected memory cell. When writing data “0”, a high voltage is applied between the floating gate and the channel of the selected memory cell, electrons are tunnel-injected from the channel to the floating gate, and the threshold voltage moves in the positive direction. When writing data “1”, the threshold voltage does not change.

Data erasure is performed almost simultaneously in block units. That is, all control gates and select gates of the block to be erased are set to 0 V, and a boosted potential VppE (about 20 V) is applied to the p-type well and the n-type substrate.
VppE is also applied to the control gate and select gate of the block that is not erased. As a result, the floating gate electrons are released to the wells in the memory cells of the block to be erased,
The threshold voltage moves in the negative direction.

In the data reading operation, the bit line is precharged and then floated, the control gate of the selected memory cell is set to 0 V, the control gates of the other memory cells and the selection gate are set to the power supply voltage Vcc (for example, 3 V),
This is performed by setting the source line to 0 V and detecting whether or not a current flows in the selected memory cell, on the bit line. That is, if the data written in the memory cell is “0” (memory cell threshold Vth> 0), the memory cell is turned off, and the bit line maintains the precharge potential, but “1” (memory cell threshold Vth). If <0), the memory cell is turned on, and the bit line drops by ΔV from the precharge potential. By detecting these bit line potentials with a sense amplifier, data in a memory cell is read.

Incidentally, as one of the techniques for realizing the large capacity of the EEPROM, a multi-value storage cell in which three or more values of information are stored in one cell is known. FIG. 17 shows that, by setting four write states in the memory cell,
The threshold voltage of the memory cell when storing quaternary data and four write states (four-level data “0”,
"1", "2", "3"). The data "0" is the same as the state after erasing, for example, has a negative threshold value, and the data "1" has, for example, a threshold value between 0.5V and 0.8V. Data "2" has a threshold value between 1.5V and 1.8V, for example, and data "3" has a threshold value between 2.5V and 2.8V, for example. A read voltage VCG2R is applied to the control gate of the memory cell, and depending on whether the memory cell is turned “ON” or “OFF”, the data of the memory cell is either “0” or “1”,
Either “2” or “3” can be detected. Subsequently, by applying the read voltages VCG3R and VCG1R, any one of data “0” to “3” in the memory cell is completely detected. Read voltage VCG1R, VCG2
R and VCG3R are set to, for example, 0 V, 1 V, and 2 V, respectively. The voltages VCG1V, VCG2V, and VCG3V are called verify voltages, and when data is written, these verify voltages are applied to the control gate to detect the state of the memory cell and check whether data is sufficiently written. These verify voltages VCG1V, VCG2V,
VCG3V is, for example, 0.5V, 1.5V,
2.5V.

[0011]

By the way, in a multivalued memory cell in which a threshold voltage is set as shown in FIG. 17, for example, "1", "2", and "3" are written at the time of writing.
For example, the publicly known document IEEE Journal of Solid-state Circuit
In the description of s, vol. 31, no. 11, 1996, pp. 1575-1582, first,
After writing data "1", write data "2" and then write data "3". In this case, when the voltage Vpp applied to the control gate at the time of writing is set to the same potential in, for example, writing of data “1”, writing of data “2”, and writing of data “3”, a state where the threshold voltage is high It takes time to write (“2”, “3”),
Although the writing speed is slow, data "2",
If Vpp is set too high in writing "3", the writing speed will be increased, but on the other hand, for example, a memory cell to which data "2" is to be written will be written to data "3" by the first writing pulse, causing a problem of erroneous writing. is there. That is, there are memory cells that are easy to write and memory cells that are hard to write due to variations in the thickness and the like of the tunnel oxide film, and thus erroneous writing occurs in the memory cells that are easy to write.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems. It is an object of the present invention to apply an optimum write voltage in data writing, and to prevent erroneous writing. It is an object of the present invention to provide a nonvolatile semiconductor memory device which can perform writing at high speed.

[0013]

A nonvolatile semiconductor memory device according to the present invention is formed by stacking a charge storage layer and a control gate on a semiconductor layer, and includes n-value (n is a natural number of 3 or more) data. A memory cell array in which electrically rewritable memory cells storing one of the following are arranged in a matrix;
In order to change the threshold voltage of the memory cell according to the data, threshold changing means for applying a voltage between the control gate and the semiconductor layer, and applying a verify voltage to the control gate of the memory cell, Verify read means for verifying whether or not the data has been sufficiently written in the memory cell, wherein the threshold value changing means is configured to connect the control gate with the control gate in a first write cycle of writing data "1" to the memory cell. A first write voltage is applied between the semiconductor layers, and data “2” is applied to the memory cell.
In a second write cycle for writing data, a second write voltage is applied between the control gate and the semiconductor layer, and the potential difference between the first write voltage and the second write voltage is equal to the verify voltage of data “1” and the data voltage. The potential difference is substantially equal to the verify voltage of “2”.

A nonvolatile semiconductor memory device according to the present invention is formed by stacking a charge storage layer and a control gate on a semiconductor layer, and stores one of n-valued data (n is a natural number of 3 or more). A memory cell array in which electrically rewritable memory cells are arranged in a matrix, and a threshold for applying a voltage between the control gate and the semiconductor layer in order to change a threshold voltage of the memory cell according to the data. Changing means; and verify reading means for applying a verify voltage to a control gate of the memory cell to verify whether the data is sufficiently written in the memory cell. A first write cycle for writing data “1” to a cell, applying a first write voltage between the control gate and the semiconductor layer; The second write data "2" in Le
In a write cycle, applying a second write voltage between the control gate and the semiconductor layer, wherein the second write voltage is greater than or equal to the first write voltage, and wherein the first write voltage and the second write voltage Is less than or equal to the potential difference between the verify voltage of data "1" and the verify voltage of data "2".

A nonvolatile semiconductor memory device according to the present invention is formed by stacking a charge storage layer and a control gate on a semiconductor layer, and stores one of n-value (n is a natural number of 3 or more) data. A memory cell array in which electrically rewritable memory cells are arranged in a matrix, and a threshold for applying a voltage between the control gate and the semiconductor layer in order to change a threshold voltage of the memory cell according to the data. Changing means; and verify reading means for applying a verify voltage to a control gate of the memory cell to verify whether the data is sufficiently written in the memory cell. A first write cycle for writing data “1” to a cell, applying a first write voltage between the control gate and the semiconductor layer; The second write data "2" in Le
In a write cycle, a second write voltage is applied between the control gate and the semiconductor layer, and in a third write cycle for writing data “3” to the memory cell, a third write voltage is applied between the control gate and the semiconductor layer. And applying a j-th write voltage between the control gate and the semiconductor layer in a j-th write cycle in which data “j” is written to the memory cell, and applying a first write voltage and a second write voltage The potential difference is substantially equal to the potential difference between the verify voltage of data “1” and the verify voltage of data “2”, and the potential difference between the second write voltage and the third write voltage is equal to the verify voltage of data “2” and the data “2”. 3 ″ is substantially equal to the potential difference of the verify voltage,
(J is a natural number equal to or less than n-1) and the (j + 1) th write voltage
Is substantially equal to the potential difference between the verify voltage of data "j" and the verify voltage of data "j + 1".

A nonvolatile semiconductor memory device according to the present invention is formed by stacking a charge storage layer and a control gate on a semiconductor layer, and stores one of n-value (n is a natural number of 3 or more) data. A memory cell array in which electrically rewritable memory cells are arranged in a matrix, and a threshold for applying a voltage between the control gate and the semiconductor layer in order to change a threshold voltage of the memory cell according to the data. Changing means; and verify reading means for applying a verify voltage to a control gate of the memory cell to verify whether the data is sufficiently written in the memory cell. A first write cycle for writing data “1” to a cell, applying a first write voltage between the control gate and the semiconductor layer; The second write data "2" in Le
In a write cycle, a second write voltage is applied between the control gate and the semiconductor layer, and in a third write cycle for writing data “3” to the memory cell, a third write voltage is applied between the control gate and the semiconductor layer. And applying a j-th write voltage between the control gate and the semiconductor layer in a j-th write cycle for writing data “j” to the memory cell, wherein the second write voltage is the first write voltage. As described above, the potential difference between the first write voltage and the second write voltage is the data “1”.
And the third write voltage is equal to or higher than the second write voltage, and the potential difference between the second write voltage and the third write voltage is: The potential difference between the verify voltage of the data “2” and the verify voltage of the data “3” is equal to or less than the potential, and the (j + 1) th (j is a natural number equal to or less than n−1) write voltage is equal to or more than the jth write voltage and the jth Is less than or equal to the potential difference between the verify voltage for data "j" and the verify voltage for data "j + 1".

A nonvolatile semiconductor memory device according to the present invention is formed by stacking a charge storage layer and a control gate on a semiconductor layer, and stores one of n-value (n is a natural number of 3 or more) data. A memory cell array in which electrically rewritable memory cells are arranged in a matrix, and a threshold for applying a voltage between the control gate and the semiconductor layer in order to change a threshold voltage of the memory cell according to the data. Varying means; and verify reading means for applying a verify voltage to a control gate of the memory cell to verify whether the data is sufficiently written in the memory cell. A first write cycle in which a first write voltage is applied between the control gate and the semiconductor layer by the threshold value changing means in a first write cycle for writing "". The write operation and the first verify read operation are repeated until data “1” is sufficiently written in the memory cell, and the threshold change is performed in a second write cycle in which data “2” is written in the memory cell. A second write operation for applying a second write voltage between the control gate and the semiconductor layer by means;
Repeating the second verify read operation until data "2" is sufficiently written in the memory cell;
The first write voltage is a first initial write voltage Vpp
The second write voltage increases from the second initial write voltage Vpp2 by the voltage ΔVpp2 each time a write voltage is applied from 1 to the first initial write voltage, and the second initial write voltage increases by the voltage ΔVpp1 each time the write voltage is applied. 2 is substantially equal to the potential difference between the first verify voltage and the second verify voltage.

A nonvolatile semiconductor memory device according to the present invention is formed by stacking a charge storage layer and a control gate on a semiconductor layer, and stores one of n-value (n is a natural number of 3 or more) data. A memory cell array in which electrically rewritable memory cells are arranged in a matrix, and a threshold for applying a voltage between the control gate and the semiconductor layer in order to change a threshold voltage of the memory cell according to the data. Varying means; and verify reading means for applying a verify voltage to a control gate of the memory cell to verify whether the data is sufficiently written in the memory cell. A first write cycle in which a first write voltage is applied between the control gate and the semiconductor layer by the threshold value changing means in a first write cycle for writing "". The write operation and the first verify read operation are repeated until data “1” is sufficiently written in the memory cell, and the threshold change is performed in a second write cycle in which data “2” is written in the memory cell. A second write operation for applying a second write voltage between the control gate and the semiconductor layer by means;
Repeating the second verify read operation until data "2" is sufficiently written in the memory cell;
The first write voltage is a first initial write voltage Vpp
From 1 to the voltage ΔVpp1 each time a write voltage is applied, the second write voltage increases from a second initial write voltage Vpp2 by a voltage ΔVpp2 each time a write voltage is applied, and the second initial write voltage is The potential difference between the first initial write voltage and the first initial write voltage and the second initial write voltage is equal to or less than the potential difference between the first verify voltage and the second verify voltage.

The voltages ΔVpp1 and ΔVpp2 are substantially equal.
Before applying the first initial write voltage, a plurality of dummy pulses are applied, and the potential difference between the dummy pulses is the voltage ΔVpp1.

Before the application of the first and second initial write voltages, first and second dummy pulses are applied, respectively, and the initial potentials of the first and second dummy pulses are substantially equal.

At least one of the voltages ΔVpp1 and ΔVpp2 is a voltage equal to or smaller than the threshold distribution width of each data. The nonvolatile semiconductor memory device according to the present invention is formed by stacking a charge storage layer and a control gate on a semiconductor layer, and electrically rewrites one of n-valued data (n is a natural number of 3 or more). A memory cell array in which possible memory cells are arranged in a matrix, and a threshold varying means for applying a voltage between the control gate and the semiconductor layer to vary a threshold voltage of the memory cell according to the data. The threshold varying means applies a first write voltage between the control gate and the semiconductor layer during a first period in which data “1” is written to the memory cell, and applies data “2” to the memory cell. A second write voltage is applied between the control gate and the semiconductor layer during a second period of writing data, and a potential difference between the first write voltage and the second write voltage is set to a threshold value of data “1”. Approximately equal to the potential difference between the substantial lower limit of the threshold distribution of the substantial lower limit of the distribution and the data "2".

A nonvolatile semiconductor memory device according to the present invention is formed by stacking a charge storage layer and a control gate on a semiconductor layer, and stores one of n-value (n is a natural number of 3 or more) data. A memory cell array in which electrically rewritable memory cells are arranged in a matrix, and a threshold for applying a voltage between the control gate and the semiconductor layer in order to change a threshold voltage of the memory cell according to the data. And a threshold change unit that applies a first write voltage between the control gate and the semiconductor layer during a first period of writing data “1” to the memory cell, In the second period of writing “2”,
A second write voltage is applied between the control gate and the semiconductor layer, the second write voltage is equal to or higher than the first write voltage, and a potential difference between the first write voltage and the second write voltage is: It is equal to or less than the potential difference between the substantial lower limit of the threshold distribution of data “1” and the substantial lower limit of the threshold distribution of data “2”.

The value of the write voltage is set independently of the first write voltage. The first write voltage is increased by the voltage ΔVpp1 every time a write voltage is applied from the first initial write voltage Vpp1 to a first write end voltage, and the second initial write voltage Vpp2 is increased by the first write voltage Vpp1. Is set independently of the write end voltage. The write voltage is set by changing the potential of the control gate. The write voltage is set by changing the potential of the semiconductor layer.

[0024]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a part of a memory cell and a read / write circuit of the present invention.
1 shows an overall configuration diagram of the present invention, and FIG. 3 shows a threshold voltage distribution of the memory cell of the present invention.

In FIG. 2, a memory cell array 1 has a multi-level nonvolatile memory cell having a floating gate and a control gate (not shown) connected in a NAND type to form a cell unit, which is arranged in an array.

The bit line control circuit 2 includes a sense amplifier / data latch circuit as a main part of the present invention, and controls a bit line for writing, verifying, and reading stored data in the memory cell array 1.
In particular, the bit line control circuit 2 constitutes verify read means together with the program / verify control circuit 8.

The column decoder 3 includes an address buffer 4
, And sends the decoded address signal to the bit line. The row decoder 5 receives the signal of the address buffer 4 and sends the decoded signal to the word line of the memory cell array 1. At the time of writing data, for example, a write voltage is supplied to a selected word line a plurality of times for each data, as described later.

The data input / output buffer circuit 6 exchanges data with the sense latch circuit. The verify batch detection circuit 7 detects the result of the verify operation collectively for each page. A program / verify control circuit 8 as a memory cell threshold variation unit controls each operation such as data writing to the memory cell array 1 and write verification. The program end flag output unit 9 detects the end of the program.

FIG. 1 shows a specific configuration of the memory cell array 1 and the bit line control circuit 2, and shows a configuration of bit lines BL1 and BL2. Each of the NAND type EEPROM cells 11a and 11b includes 16 EEPROM cells and two select gates connected in series. Each NAND type EEPROM
One ends of the cells 11a and 11b are connected to bit lines BL1 and BL2, and the other ends are connected to a source line Vsource.
A transistor Q is connected to one end of each of the bit lines BL1 and BL2.
1, a power supply voltage Vcc is supplied via Q2. The gates of these transistors Q1 and Q2 are connected to the signal Vh1,
Vh2 is supplied. One ends of the bit lines BL1 and BL2 are connected to one ends of transistors Q7 and Q8 via transistors Q3 and Q4, respectively. Signals SS1 and SS2 are supplied to the gates of the transistors Q3 and Q4, respectively, and signals Vpg1 and Vpg2 are supplied to the gates of the transistors Q7 and Q8, respectively. A transistor Q5 is provided between the transistors Q3 and Q7.
The power supply voltage Vcc is supplied via a (P-channel MOSFET). The signal Vre is applied to the gate of the transistor Q5.
f is supplied. A connection node between the transistors Q3 and Q7 and a connection node N3 between the transistors Q4 and Q8 are connected to each other, and these connection nodes are grounded via a transistor Q6. This transistor Q6
Is supplied with a signal Vreset. The transistors Q7 and Q8 are connected to data lines IO1 and IO2 via transistors Q9 and Q10. The gates of these transistors Q9 and Q10 have column selection signals CSL.
Is supplied.

A connection node between the transistors Q7 and Q9 is connected to one end of a latch circuit LT1 including inverter circuits I11 and I12. This latch circuit LT1
The other end N1 is grounded via transistors Q11, Q12 and Q13. The gate of the transistor Q11 is connected to the connection node N3 of the transistors Q4 and Q8, and the gate of the transistor Q12 is connected to the connection node of the transistors Q8 and Q10. The signal VL2 is supplied to the gate of the transistor Q13.

A connection point between the transistors Q8 and Q10 is connected to a latch circuit L including inverter circuits I21 and I22.
One end of T2 is connected. The other end N2 of the latch circuit LT2 is grounded via transistors Q14 and Q15. The gate of the transistor Q14 is connected to the connection node N3, and the gate of the transistor Q15 is supplied with the signal VL3.

Further, the transistors Q11 and Q12
Transistors Q16, Q17
Are connected in series. The gate of the transistor Q16 is connected to the other end N2 of the latch circuit LT2, and the signal VL1 is supplied to the gate of the transistor Q17.

The operation of the bit line control circuit 2 in the above configuration will be described. The bit line control circuit 2 is shared by the two bit lines (BL1, BL2). For example, when selecting the memory cell MC1 connected to the bit line BL1, the signal SS1 is selected and the signal SS2 is not selected. , And the bit line BL1 is connected to the bit line control circuit 2.

<Data Read> FIG.
FIG. 5 shows a read timing diagram of C1. First, at time t1R, the transistor Q6 is turned on in response to the signal Vreset, and the latch circuits LT1 and LT2 are reset.
Thereafter, at time t2R, the control gate CG1 is set to 2.4 V to detect whether or not the stored data is "3".
, The data of the memory cell MC1 is read to the bit line BL1. At this time, when the stored data is “3”, the potential of the bit line BL1 becomes high level, and the transistor Q
14, Q11 is turned on. Since the node N2 of the latch circuit LT2 is at a high level, the transistor Q1
6 is also on. When the signal VL1 goes high at time t3R, the transistor Q17 turns on,
The node N1 of the latch circuit LT1 is grounded, and the latch data of the latch circuit LT1 is inverted. In this manner, the data read to bit line BL1 is applied to latch circuit LT1.
Latched.

Next, at time t4R, to detect whether the data stored in the memory cell is "0" or "1" or "2" or "3", the control gate CG1 is turned on. The voltage is set to 1.2 V, and the data of the memory cell is read to the bit line BL1. At this time, when the data stored in the memory cell is “2” or “3”, the potential of the bit line BL1 becomes high level. Thereafter, at time t5R, when the signal VL3 goes high, the transistor Q15 turns on. Therefore, the node N2 of the latch circuit LT2 is grounded, and the latch circuit LT
2 is inverted and the data on the bit line BL1 is
Latched at T2.

Subsequently, the control gate C is used to detect whether the data stored in the memory cell is "0".
When G1 is set to 0V, the data of the memory cell is changed to the bit line BL1.
Is read out. At this time, when the signal VL1 goes high at time t6R, data is latched in the latch circuit LT1. By doing so, the data of the memory cell is read out to the latch circuits LT1 and LT2.

As described above, the latch data of the latch circuits LT1 and LT2 is changed according to the level of the data read to the bit line, and the data of the memory cell is latched by the latch circuits LT1 and LT2. These latch circuits LT
1, the data finally latched at one end (V2, V1) of LT2 is, as shown in FIG. 4, when the data of the memory cell is "1"("L","H") (where " L is low level, “H” is high level), “2” (“H”, “L”), “3” (“H”,
“H”) and “0” (“L”, “L”).

<Data Writing> FIG. 5 shows a flowchart of data writing, FIG. 6 shows a timing chart thereof, and FIG. 7 shows a waveform diagram of a writing voltage. As shown in FIG. 5, first, as shown in FIG. 5, writing of data "1" and verify reading of data "1" are performed until the memory cell to which data "1" is written is sufficiently written (ST1 to ST1). ST
3). Subsequently, writing of data “2” and verify reading of data “2” are performed until the memory cell to which data “2” is written is sufficiently written (ST).
4-ST6). Finally, writing of data "3" and verify reading of data "3" are performed until the memory cell to which data "3" is written is sufficiently written (ST7 to ST9).

The write operation will be described with reference to FIG. In FIG. 6, the write and verify read operations are performed once each in the first to third write cycles, but in reality, as shown in FIGS. 5 and 7, they are repeated as necessary. The latch circuit LT
1. Write data is input to LT2 prior to writing. The potentials (V1 and V2) at one ends of the latch circuits LT1 and LT2 are “H” and “H” when data “0” is written (write non-selection), and when data “1” is written (“L”). , "H"), writing data "2"("H","L"), and writing data "3"("L","L").

Hereinafter, a case in which writing is performed to the memory cell MC1 in FIG. 1 will be described as an example. However, the threshold voltage distribution of the memory cell MC1 to which writing is performed is as shown in FIG. <Write of Data “1”> First, at time tp1,
Data "1" is written. At this time, data of the latch circuit LT1 is output to the bit line BL1. A high voltage Vpp for writing is applied to the control gate CG1,
The other control gates CG2, CG3,.
(About 10 V) is applied. The waveform of the high voltage Vpp is specifically as shown in FIG. That is, the first write voltage Vpp is the voltage Vpp1 at which the memory cell that is most easily written in the first write operation, that is, the memory cell to which the fastest write is performed is sufficiently written with data “1”. The reason why there are memory cells that are easy to write and memory cells that are difficult to write is that the thickness of the tunnel oxide film and the like vary. This voltage Vpp1 is, for example, 16V
Should be fine.

At time tp2, when the writing with the voltage Vpp1 ends, at time tp3, a voltage of 0.4 V is applied to the control gate CG1 to start verify reading. At time tp4, when the signal VL2 goes high, the data on the bit line is sensed and latched by the latch circuit LT1. That is, when writing is sufficient and the potential of the bit line BL1 is higher than the verify voltage 0.4V, the transistor Q1
1 turns on. Further, the transistor Q12 is turned on because the voltage V2 at one end of the latch circuit LT2 is at a high level, and the transistor Q13 is turned on because the signal VL2 is at a high level. Therefore, the latch circuit LT1
Of the transistors Q11, Q12, Q
13, the voltage V1 at one end of the latch circuit LT1 is at a high level. As described above, when writing is sufficient, additional writing is not performed.

When writing is insufficient, the voltage V1 at one end of the latch circuit LT1 remains at low level,
Additional writing is performed. With each additional write, the write voltage Vpp is increased by ΔVpp1 as shown in FIG. Data “1” writing and “1” verification are performed until all the memory cells to which data “1” is written are sufficiently written. That is, the operation is performed until all the voltages V1 of the latch circuits LT1 to which the memory cells to which the data “1” is written are connected are at the high level.

In an ideal case where the write voltage Vpp does not depend on the power supply voltage and there is no array noise at the time of reading, the threshold voltage distribution of the data “1” becomes approximately ΔVpp1. Therefore, in order to obtain a threshold voltage distribution of 0.4 V as shown in FIG. 3, ΔVpp1 should ideally be set to 0.4 V. Actually, ΔVpp1 may be set to 0.2 V because the write voltage Vpp has power dependency and array noise at the time of reading. That is, in the first write, V
pp is 16V, 16.2V in the second writing, 16.4V in the third writing, and the voltage may be increased by 0.2V from the initial value Vpp1.

<Write of Data "2"> Data "2" is subsequently written. Initial value Vpp2 of write voltage Vpp when writing data "2" (see FIG. 7)
Is the difference between the control gate voltage (verify voltage) at the time of “1” verification and “2” verification,
In other words, 1.2 V (corresponding to V12 in FIG. 3) which is the difference between the substantial lower limit of the threshold voltage distribution of data “1” and the substantial lower limit of the threshold voltage distribution of data “2” in FIG. Only a high voltage is sufficient. That is, it is sufficient that Vpp2 = Vpp1 + V12. Therefore, when Vpp1 is 16 V, V
pp2 may be set to 17.2V. The voltage Vpp2 is a voltage at which the memory cell to which the fastest writing is performed is sufficiently written to the data "2". By setting Vpp2 to Vpp1 + V12 in this manner, the memory cell that is most easily written is
That is, the memory cell to be written fastest is sufficiently written by the first write pulse.

It should be noted that Vpp2 must be less than Vpp1 + V12 (Vpp2
<Vpp1 + V12). In this case, since the voltage applied to the oxide film decreases, the reliability of the memory cell can be improved. When Vpp2 is made larger than Vpp1 + V12, the memory cell to which data "2" is to be written becomes
The data is written to a threshold higher than the data “2”, which may cause a writing failure.

Referring to the timing chart shown in FIG. 6, at time tp5, writing of data "2" is performed. At this time, the data of the latch circuit LT2 is output to the bit line. The write voltage V is applied to the control gate CG1.
pp is applied. Other control gates CG2, CG3 ... CG
8, a VM 10 (approximately 10 V) is applied. Time tp
At 6, the write is completed, and at time tp7, a verify voltage of 1.6 V is applied to the control gate CG1, and verify read is started. Time tp8
When the signal VL3 goes high, the data on the bit line BL1 is sensed and latched by the latch circuit LT2.

That is, when writing is sufficient and the potential of the bit line BL1 is higher than the verify voltage 1.6V, the transistor Q14 is turned on. further,
The transistor Q15 is turned on because the signal VL3 is at a high level. Therefore, since the node N2 of the latch circuit LT2 is grounded via these transistors Q14 and Q15, the voltage V2 at one end of the latch circuit LT2 becomes high level. As described above, when writing is sufficient, additional writing is not performed. If writing is insufficient, V2 is at low level, and additional writing is performed. With each additional write, the write voltage Vpp increases by ΔVpp2 as shown in FIG. The writing of the data “2” and the verification of the data “2” are repeated until all the memory cells to which the data “2” is written are sufficiently written. That is, the operation is performed until all the voltages V2 of the latch circuits LT2 to which the memory cells into which the data “2” is written are connected are at the high level. As shown in FIG. 3, in order to obtain a threshold voltage distribution of 0.4 V, ΔVpp2 may be set to 0.2 V as in the case of writing data “1”. Here, the increase width ΔVpp of the write voltage Vpp in the first write cycle (first period) for writing data “1” and the second write cycle (second period) for writing data “2”.
Are set to be equal (ΔVpp =) ΔVpp1 = ΔVpp2, but ΔVpp1 and ΔVpp2 may be set to values different from each other.

<Writing of Data "3"> Subsequently, writing of data "3" is performed. When data "3" is written, the initial value Vpp3 of the write voltage Vpp shown in FIG.
Compared with pp1, the difference between the control gate voltage (verify voltage) at the time of "1" verify and the "3" verify, in other words, the substantially lower limit of the threshold voltage distribution of data "1" in FIG. It is sufficient that the voltage is higher by 2.4 V (V13 in FIG. 3) which is the difference between the substantial lower limit value of the threshold voltage distribution of 3 ″. That is, Vpp3 = Vpp1 + V13. At the same time, Vpp3 is different from Vpp2 in the difference between the control gate voltage (verify voltage) at "2" verify and "3" verify, in other words, the data "2" in FIG.
Vpp3 = Vpp2 + V23, which is higher by 1.2V (V23 in FIG. 3) which is the difference between the substantial lower limit of the threshold voltage distribution of the data "3" and the substantial lower limit of the threshold voltage distribution of the data "3". Therefore, if Vpp1 is 16V, Vpp3
Should be 18.4V. Thus, the write voltage V
By setting the initial value of pp, the memory cell that is easiest to write (that is, the memory cell that is written fastest)
Are sufficiently written by the first write pulse. That is, the voltage Vpp3 is a voltage at which the fastest-written memory cell is sufficiently written with data "3".

Vpp3 is Vpp1 + V13 (Vpp2 + V2
3) less than (Vpp3 <Vpp1 + V13, Vpp3 <Vpp2 +
V23). In this case, since the voltage applied to the oxide film decreases, the reliability of the memory cell improves. If Vpp3 is made larger than Vpp1 + V13 (Vpp2 + V23), a memory cell to which data "3" is to be written is written to a value higher than data "3", which may cause a writing failure.

Referring to the timing chart shown in FIG. 6, at time tp9, data "3" is written. At this time, data of the latch circuit LT1 is output to the bit line BL1. A write voltage Vpp is applied to the control gate CG1. VM10 (about 10 V) is applied to the other CG2, CG3,... CG8. Time tp10
At the end of writing, and at time tp11,
The verify read is started by applying a voltage of 2.8 V to the control gate CG1. At time tp12, the signal V
When L2 becomes high level, the data on the bit line BL1 is sensed and latched by the latch circuit LT1, as in the case of writing the data "1". When writing is sufficient, the voltage V1 at one end of the latch circuit LT1 becomes high level, and no additional writing is performed.

On the other hand, when writing is insufficient, the voltage V1
Is low level, and is additionally written. For each additional write, the write voltage Vpp is, as shown in FIG.
Incremented by 3. Write data “3” and “3”
The verification is performed until all the memory cells to which data "3" is written are sufficiently written. That is, the operation is performed until the potential V1 at one end of the latch circuit LT1 corresponding to the memory cell to which the data “3” is written becomes all high. As shown in FIG. 7, in order to obtain a threshold voltage distribution of 0.4 V, as in the case of writing data “1”, Δpp
3 may be set to 0.2 V, and the value of Δpp3 is Δpp
There is no problem if it is set to a value different from 1 or Δpp2.

According to the first embodiment, each data write and verify operation is divided into a plurality of times, and in each data write, the initial value of the write voltage is set to the most of the memory cells to which the data is written. The voltage is set so that a memory cell to be written quickly can write sufficiently. Therefore, data can be written at high speed without erroneous writing.

The above is the substantial lower limit of the threshold voltage distribution of data "1", "2", and "3" after writing data "1", writing data "2", and writing data "3". Control gate CG1 of a memory cell selected as a verify voltage of 0.4V, 1.6V and 2.8V
, And verify read is performed.
The method of the verify operation is not limited to this. For example, by detecting the cell voltage without applying the verify voltage to the control gate CG1, until the data is sufficiently written,
Control may be performed such that a high voltage is applied to the memory cell. In this case, the initial values Vpp1, Vpp2, Vpp3 of the write voltage Vpp when writing the data "1", "2", "3".
Is data "1" set at the time of data writing.
As described above, Vpp2 ≦ Vpp1 + V12 and Vpp3 ≦ Vpp1 + V1 based on the difference between the substantially lower limit values of the threshold voltage distribution of “2” and “3” (V12, V13, V23 in FIG. 3).
3. It suffices to satisfy Vpp3 ≦ Vpp2 + V23. However, the substantial lower limit value of the threshold voltage distribution of each of the data “1”, “2”, and “3” does not fall within the threshold voltage range shown in FIG. Are defined excluding the threshold voltages of the memory cells.

FIG. 8 shows a second embodiment of the present invention, and shows another example of the write voltage. With the write voltage shown in FIG. 8, in the first write cycle,
Two dummy pulses DP are first applied during the first write voltage. Vpp1 is a voltage for writing data "1" to the memory cell which is most easily written. As described above, by applying the dummy pulse DP having a voltage lower than Vpp1 to the control gate in a plurality of times, the electric field applied to the oxide film of the memory cell is weakened, and the breakdown of the oxide film can be prevented. Therefore, the reliability of the memory cell can be improved. Here, the increase width of the voltage of the dummy pulse DP may be set, for example, to be equal to the increase width ΔVpp of the write voltage Vpp.

In the second write cycle, Vpp2 = Vpp
1 + V12. With this configuration, data “2” is written to the memory cell which is most easily written at the first pulse of the second write cycle. In the third write cycle, Vpp3 = Vpp1 + V13. In this way, data "3" can be written to the memory cell which is most easily written by the first pulse of the third write cycle. If Vpp2 is made lower, the electric field applied to the memory cell becomes weaker, so that the reliability of the memory cell can be improved. Similarly, if Vpp3 is made lower, the electric field applied to the memory cell becomes weaker, so that the reliability of the memory cell can be improved.

In the second embodiment,
The data “1” “2” by the dummy pulse DP shown in FIG.
An electric field may be applied to the oxide films of all the memory cells for writing “3”. FIG. 9 is a circuit diagram of a bit line control circuit suitably used at this time. Specifically, during the application of the dummy pulse DP to the control gate, the potential of Vpre1 in the figure is set to 0 V, so that the channel of each memory cell is collectively transmitted through the bit line BL1 selected by the signal SS1. What is necessary is just to supply 0V. Thus, the voltage of the dummy pulse DP can be applied to the oxide films of all the memory cells into which the data “1”, “2”, and “3” are written, and the reliability of the memory cells can be further improved.

Even when such a dummy pulse DP is applied, it is not possible to sufficiently write the memory cells with the dummy pulse DP. Therefore, it is not necessary to perform the verify read after the application of the dummy pulse DP.

FIG. 10 shows a third embodiment of the present invention, and shows another example of the write voltage.
In FIG. 10, two dummy pulses DP are applied during the first write pulse in each of the first write cycle, the second write cycle, and the third write cycle. The voltage Vpp1H is a voltage at which data "1" is written to the memory cell which is most easily written. Vpp2H is a voltage for writing data “2” to the memory cell which is most easily written, and Vpp2H = Vpp1H + V12. Vpp3H is a voltage Vpg3 for writing data “3” to the memory cell which is most easily written.
= Vpg1 + V13. By applying such a dummy pulse, the electric field applied to the oxide film of the memory cell is reduced for all the memory cells in which data "1", "2", and "3" are written using the circuit shown in FIG. And the reliability of the memory cell is further improved. The voltage of each dummy pulse DP is, for example, Vpp2L = Vpp1L + V12,
Vpp3L = Vpp1L + V13 may be set. Since the memory cell is not sufficiently written by the dummy pulse, it is not necessary to perform the verify read after the application of the dummy pulse.

FIG. 11 shows a fourth embodiment of the present invention, and shows another example of the write voltage.
In FIG. 11, similarly to FIG. 10, the dummy pulse DP is applied during the first write pulse in each of the first to third write cycles. However, in FIG. 11, the initial value of the dummy pulse DP in the second and third write cycles is the same as in the first write cycle, and the number of dummy pulses DP in the second and third write cycles is
More than the first write cycle is set.

According to the present embodiment, the first to third
The same effect as that of the embodiment can be obtained. Moreover, according to this embodiment, since the initial values of the dummy pulses DP are all the same, it is not necessary to generate a plurality of dummy pulses having different voltages. Therefore, a circuit for generating a dummy pulse can be simplified.

In each of the above embodiments, the present invention is applied to a NAND
The case where the present invention is applied to the type EEPROM is described. However, the present invention is not limited to this, and the NOR type flash memory, the AND type (K.Kum
e etal .; IEDM Tech.Dig., Dec. 1992, pp. 991-993), D
INOR type (S.Kobayashi et al .; ISSCC Tech.Dig., 1995,
pp.122) and a virtual ground-type array (R. Cemea et al .; ISS
It is also possible to apply to CC Tech.Dig, 1995, pp.126).

Further, in the above embodiment, the case where 0 V is applied from the bit line to the channel of the memory cell and the write voltage Vpp is applied to the control gate at the time of writing has been described. However, the present invention is not limited to this. , A
When writing like ND type cell and DINOR type cell,
By applying a positive voltage to the bit line and a negative voltage to the word line, the present invention can be applied to a method of tunneling electrons from the floating gate to the drain connected to the bit line.

For example, as shown in FIG. 12, a positive voltage Vd is applied from a bit line to a drain of a memory cell, a negative voltage Vg is applied to a control gate, a source is a floating Vs, and a threshold voltage distribution is shown in FIG. It is assumed that it is as shown in FIG.

In this case, data "0" is in the erased state, and the threshold voltage is equal to or higher than Vcc (3.3 V). Writing is performed as shown in FIG. The write pulse of data “1” fixes the voltage Vd at 5 V, sets the voltage Vg at −9 V,
It may be changed by -0.2 V, -9.4 V,... In 0.2 V steps. Alternatively, the voltage Vg is fixed at −9 V and the voltage Vg
d may be changed in steps of 5 V, 5.2 V, 5.4 V, 5.6 V... 0.2 V. At the time of verify reading of data "1", it is determined whether the memory cell is turned on by setting the voltage Vg of the control gate to 2.8 V to determine whether writing is sufficient.

After the writing of the data “1” is completed, the writing of the data “2” is performed. The write pulse of the data “2” fixes the voltage Vd to 6 V which is larger than the write of the data “1” by the voltage V12 shown in FIG. 13, and sets the control gate voltage Vg to −9V, −9.2V, −9. 4V, ...
And 0.2 V at a time. At this time, when the value of the voltage Vd is set to a value lower than 6 V, for example, 5.5 V, the electric field applied to the tunnel oxide film is weakened and the reliability of the memory cell is improved, as in the case of the NAND flash memory. is there. Further, the voltage Vd is fixed to 5 V, which is the same as that for writing the data “1”, and the voltage Vg of the control gate is made lower by the voltage V12 than the writing of the data “1”, so that −1
0V, -10.2V-10.4V,... May be changed in 0.2V steps. Alternatively, the control gate voltage Vg is
The voltage Vd is fixed to 9 V, and the voltage Vd is set to 6 V, 6.2 V, 6.4 V,
It may be changed by 6.6V and 0.2V at a time. Further, the voltage Vg of the control gate is fixed at -10 V, and
d is 5V, 5.2V, 5.4V, 5.6V ... and 0.2V
It may be changed at a time. At the time of verify reading of data "2", it is determined whether or not the writing is sufficient by setting the voltage Vg of the control gate to 1.8 V and turning on the memory cell.

After the writing of the data “2” is completed, the writing of the data “3” is performed. The data “3” write pulse makes the voltage Vd higher than the data “1” write in FIG.
May be fixed to 7V which is larger by the voltage V13, and the voltage Vg of the control gate may be changed by -9V, -9.2V, -9.4V,. The voltage Vd is fixed to 5 V, which is the same as that for writing the data “1”, and the voltage Vg of the control gate is made lower than the writing of the data “1” by V13, so that −11 V, −11.2 V, −11.4 V, ... and may be changed by 0.2 V at a time. Alternatively, the voltage Vg of the control gate is fixed to −9 V, and the voltage Vd is set to 7 V, 7.2.
V, 7.4 V, 7.6 V,... Further, the voltage Vg of the control gate may be fixed at −11 V, and Vd may be changed by 5 V, 5.2 V, 5.4 V, 5.6 V,. At the time of verify reading of data "3", it is determined whether or not writing is sufficient by setting the voltage Vg of the control gate to 0.8 V and turning on the memory cell.

The present invention is not limited to the above embodiments, and can be variously modified. The point is that an optimal electric field applied to the tunnel oxide film when performing writing / erasing using the tunnel effect may be set without departing from the gist of the present invention. Therefore, "1" is written to set the optimal electric field,
The potential of the word line or the potential of the bit line may be changed with respect to the first write pulse of the “2” write or the “3” write. Alternatively, both the potentials of the bit line and the word line may be changed.

[0068]

As described above in detail, according to the present invention, when writing or erasing a multi-valued memory cell, it is possible to prevent excessive writing and to minimize the writing time. A storage device can be provided.

[Brief description of the drawings]

FIG. 1 shows a first embodiment of the present invention;
FIG. 3 is a circuit diagram showing a memory cell and a bit line control circuit.

FIG. 2 is a configuration diagram showing a nonvolatile semiconductor memory device to which the present invention is applied;

FIG. 3 is a diagram showing a threshold voltage distribution of a memory cell of the present invention.

FIG. 4 is a timing chart showing a read operation of FIG. 1;

FIG. 5 is a flowchart illustrating a write operation of the present invention.

FIG. 6 is a timing chart showing write and verify read operations of FIG. 1;

FIG. 7 is a waveform chart showing a write voltage according to the first embodiment of the present invention.

FIG. 8 is a waveform chart showing a write voltage according to the second embodiment of the present invention.

FIG. 9 is a circuit diagram showing a modification of FIG. 1;

FIG. 10 is a waveform chart showing a write voltage according to a third embodiment of the present invention.

FIG. 11 is a waveform chart showing a write voltage according to a fourth embodiment of the present invention.

FIG. 12 shows a modification of the present invention and is a view for explaining a method of applying a write voltage.

FIG. 13 is a diagram showing a threshold voltage distribution corresponding to the modification of FIG. 12;

14A is a plan view showing a NAND type EEPROM, and FIG. 14B is an equivalent circuit diagram of FIG. 14A.

FIG. 15 (a) is a sectional view taken along line 15a- shown in FIG. 14 (a).
15B is a cross-sectional view taken along the line 15a, and FIG.
Sectional drawing along 15b-15b line shown in FIG.

FIG. 16 is a circuit diagram showing a cell array of a NAND type EEPROM.

FIG. 17 is a diagram showing a threshold voltage distribution of a multi-level NAND type EEPROM.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Memory cell array, 2 ... Bit line control circuit, 5 ... Row decoder, 8 ... Program / verify control circuit, LT1, LT2 ... Latch circuit, MC1: Memory cell, BL1, BL2 ... Bit line.

Claims (16)

[Claims] 1. An electrically rewritable memory cell which is formed by stacking a charge storage layer and a control gate on a semiconductor layer and stores one of n-valued data (n is a natural number of 3 or more). A memory cell array arranged in a matrix, threshold varying means for applying a voltage between the control gate and the semiconductor layer to vary a threshold voltage of the memory cell according to the data, Verify read means for applying a verify voltage to a control gate to verify whether or not the data is sufficiently written in the memory cell, wherein the threshold varying means writes data "1" to the memory cell In a first write cycle, a second write voltage is applied between the control gate and the semiconductor layer to write data “2” into the memory cell. In a write cycle, a second write voltage is applied between the control gate and the semiconductor layer, and a potential difference between the first write voltage and the second write voltage is a difference between a verify voltage of data “1” and a data “2”. A nonvolatile semiconductor memory device, wherein the potential difference is substantially equal to the verify voltage. 2. An electrically rewritable memory cell which is formed by stacking a charge storage layer and a control gate on a semiconductor layer and stores one of n-valued data (n is a natural number of 3 or more). A memory cell array arranged in a matrix, threshold varying means for applying a voltage between the control gate and the semiconductor layer to vary a threshold voltage of the memory cell according to the data, Verify read means for applying a verify voltage to a control gate to verify whether or not the data is sufficiently written in the memory cell, wherein the threshold varying means writes data "1" to the memory cell In a first write cycle, a second write voltage is applied between the control gate and the semiconductor layer to write data “2” into the memory cell. Applying a second write voltage between the control gate and the semiconductor layer in the write cycle, wherein the second write voltage is equal to or higher than the first write voltage, and the first write voltage and the second write voltage The nonvolatile semiconductor memory device according to claim 1, wherein a potential difference between the voltages is equal to or less than a potential difference between a verify voltage of data "1" and a verify voltage of data "2". 3. An electrically rewritable memory cell which is formed by stacking a charge storage layer and a control gate on a semiconductor layer and stores one of n-valued data (n is a natural number of 3 or more). A memory cell array arranged in a matrix, threshold varying means for applying a voltage between the control gate and the semiconductor layer to vary a threshold voltage of the memory cell according to the data, Verify read means for applying a verify voltage to a control gate to verify whether or not the data is sufficiently written in the memory cell, wherein the threshold varying means writes data "1" to the memory cell In a first write cycle, a second write voltage is applied between the control gate and the semiconductor layer to write data “2” into the memory cell. In a write cycle, a second write voltage is applied between the control gate and the semiconductor layer, and in a third write cycle in which data “3” is written in the memory cell, a third write cycle is performed between the control gate and the semiconductor layer. Applying a voltage, applying a j-th write voltage between the control gate and the semiconductor layer in a j-th write cycle for writing data “j” to the memory cell, wherein the first write voltage and the second write voltage Is substantially equal to the potential difference between the verify voltage of data "1" and the verify voltage of data "2", and the potential difference between the second write voltage and the third write voltage is the same as the verify voltage of data "2". The potential difference between the verify voltage of “3” and the voltage of the j-th (j is a natural number equal to or less than n−1) write voltage and the (j + 1) -th write voltage Difference data "j" substantially non-volatile semiconductor memory device, characterized in that equal to the potential difference between the verify voltage of the verify voltage and the data "j + 1" of. 4. An electrically rewritable memory cell which is formed by stacking a charge storage layer and a control gate on a semiconductor layer and stores one of n-valued data (n is a natural number of 3 or more). A memory cell array arranged in a matrix, threshold varying means for applying a voltage between the control gate and the semiconductor layer to vary a threshold voltage of the memory cell according to the data, Verify read means for applying a verify voltage to a control gate to verify whether or not the data is sufficiently written in the memory cell, wherein the threshold varying means writes data "1" to the memory cell In a first write cycle, a second write voltage is applied between the control gate and the semiconductor layer to write data “2” into the memory cell. In a write cycle, a second write voltage is applied between the control gate and the semiconductor layer, and in a third write cycle in which data “3” is written in the memory cell, a third write cycle is performed between the control gate and the semiconductor layer. Applying a voltage, applying a j-th write voltage between the control gate and the semiconductor layer in a j-th write cycle for writing data “j” to the memory cell, wherein the second write voltage is the first write voltage. Voltage and a potential difference between the first write voltage and the second write voltage is equal to or less than a potential difference between the verify voltage of the data “1” and the verify voltage of the data “2”, and the third write voltage is The potential difference between the second write voltage and the third write voltage which is equal to or higher than the second write voltage is equal to the verify voltage of the data “2” and the data “2”. J + 1 (j is a natural number equal to or less than n-1), and the potential difference between the j-th programming voltage and the (j + 1) -th programming voltage. Is a potential difference between a verify voltage of data "j" and a verify voltage of data "j + 1" or less. 5. An electrically rewritable memory cell which is formed by stacking a charge storage layer and a control gate on a semiconductor layer and stores one of n-valued data (n is a natural number of 3 or more). A memory cell array arranged in a matrix, threshold varying means for applying a voltage between the control gate and the semiconductor layer to vary a threshold voltage of the memory cell according to the data, Verify read means for applying a verify voltage to the control gate and verifying whether or not the data is sufficiently written in the memory cell, wherein a first write cycle for writing data "1" to the memory cell A first write operation of applying a first write voltage between the control gate and the semiconductor layer by the threshold varying means, and a first verify read And the movement
The above operation is repeated until data “1” is sufficiently written in the memory cell. In a second write cycle of writing data “2” in the memory cell, a second write cycle is performed between the control gate and the semiconductor layer by the threshold varying means. A second write operation for applying a voltage and a second verify read operation
The operation is repeatedly performed until data “2” is sufficiently written in the memory cell, and the first write voltage is a first initial write voltage Vpp.
From 1 to a voltage ΔVpp1 every time a write voltage is applied, and the second write voltage is changed to a second initial write voltage Vpp.
2, the voltage ΔVpp2 is increased every time a write voltage is applied, and the potential difference between the first initial write voltage and the second initial write voltage is substantially equal to the potential difference between the first verify voltage and the second verify voltage. A nonvolatile semiconductor memory device characterized by the above-mentioned. 6. An electrically rewritable memory cell which is formed by stacking a charge storage layer and a control gate on a semiconductor layer and stores one of n-valued data (n is a natural number of 3 or more). A memory cell array arranged in a matrix, threshold varying means for applying a voltage between the control gate and the semiconductor layer to vary a threshold voltage of the memory cell according to the data, Verify read means for applying a verify voltage to the control gate and verifying whether or not the data has been sufficiently written in the memory cell; and in a first write cycle for writing data "1" to the memory cell. A first write operation of applying a first write voltage between the control gate and the semiconductor layer by the threshold varying means, and a first verify read And the movement
The above operation is repeated until data “1” is sufficiently written in the memory cell. In a second write cycle of writing data “2” in the memory cell, a second write cycle is performed between the control gate and the semiconductor layer by the threshold varying means. A second write operation for applying a voltage and a second verify read operation
The operation is repeatedly performed until data “2” is sufficiently written in the memory cell, and the first write voltage is a first initial write voltage Vpp.
From 1 to a voltage ΔVpp1 every time a write voltage is applied, and the second write voltage is changed to a second initial write voltage Vpp.
From 2 to the voltage ΔVpp2 every time a write voltage is applied, the second initial write voltage is equal to or higher than the first initial write voltage, and the potential difference between the first initial write voltage and the second initial write voltage is A non-volatile semiconductor memory device having a potential difference equal to or less than a potential difference between a first verify voltage and a second verify voltage. 7. The nonvolatile semiconductor memory device according to claim 5, wherein said voltages ΔVpp1 and ΔVpp2 are substantially equal. 8. Before applying the first initial write voltage,
7. The nonvolatile semiconductor memory device according to claim 5, wherein a plurality of dummy pulses are applied, and a potential difference between the dummy pulses is the voltage .DELTA.Vpp1. 9. Prior to the application of the first and second initial write voltages, first and second dummy pulses are applied, respectively, and the initial potentials of the first and second dummy pulses are substantially equal. 7. The nonvolatile semiconductor memory device according to claim 1, 2, 5, or 6. 10. The nonvolatile semiconductor memory device according to claim 5, wherein at least one of the voltages ΔVpp1 and ΔVpp2 is a voltage equal to or smaller than a threshold distribution width of each of the data. 11. An electrically rewritable memory cell which is formed by stacking a charge storage layer and a control gate on a semiconductor layer and stores one of n-valued (n is a natural number of 3 or more) data. A memory cell array arranged in a matrix, and a threshold varying unit that applies a voltage between the control gate and the semiconductor layer to vary a threshold voltage of the memory cell according to the data; The threshold change unit applies a first write voltage between the control gate and the semiconductor layer during a first period of writing data “1” to the memory cell, and writes a second data to the memory cell. Applying a second write voltage between the control gate and the semiconductor layer during a period, wherein a potential difference between the first write voltage and the second write voltage is substantially below a threshold distribution of data “1”. Value data "2" nonvolatile semiconductor memory device, characterized in that substantially equal to the potential difference between the substantial lower limit of the threshold distribution of. 12. An electrically rewritable memory cell which is formed by stacking a charge storage layer and a control gate on a semiconductor layer and stores one of n-value (n is a natural number of 3 or more) data. A memory cell array arranged in a matrix, and a threshold varying unit that applies a voltage between the control gate and the semiconductor layer to vary a threshold voltage of the memory cell according to the data; The threshold change unit applies a first write voltage between the control gate and the semiconductor layer during a first period of writing data “1” to the memory cell, and writes a second data to the memory cell. Applying a second write voltage between the control gate and the semiconductor layer during the period, wherein the second write voltage is equal to or higher than the first write voltage, and the second write voltage is equal to the second write voltage. The potential difference can inclusive voltage data "1" substantially the lower value and the data "2" nonvolatile semiconductor memory device, characterized in that the threshold distribution is less than the potential difference of a substantial lower limit of the threshold distribution of. 13. The nonvolatile semiconductor memory device according to claim 1, wherein a value of said write voltage is set independently of said first write voltage. 14. The method according to claim 1, wherein the first write voltage is the first write voltage.
Increases from the initial write voltage Vpp1 to the first write end voltage by the voltage ΔVpp1 every time the write voltage is applied, and the second initial write voltage Vpp2 has its value independent of the first write end voltage. 11. The nonvolatile semiconductor memory device according to claim 5, wherein the following is set. 15. The nonvolatile semiconductor memory device according to claim 1, wherein said write voltage is set by changing a potential of a control gate. 16. The nonvolatile semiconductor memory device according to claim 1, wherein said write voltage is set by changing a potential of a semiconductor layer.