JPH11306771A - Semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To ensure a sufficient margin in the operation for storing a multi- valued data in a memory cell and reading/writing the multi-valued data. SOLUTION: At the time of storing a three-valued data ('0', '1', '2') in a memory cell, a plurality of data values ('0', '1') are made to correspond each other in a same potential region where the cell current value Id is invariant for the variation of the floating gate potential Vfg. In the read out mode of these data values, bias voltage of a bit line connected with a memory cell to be read out is inverted and the Vfg-Id characteristic curve is shifted to plus side. The cell current value Id is varied in the region of the floating gate potential Vfg corresponding to the data values ('0', '1') and thereby these data values can be determined.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor memory, and more particularly, to a flash EEPROM (ElectricalEras).
The present invention relates to a technique for multi-valued memory data in an "able and programmable read only memory".

[0002]

2. Description of the Related Art In recent years, attention has been paid to a flash EEPROM capable of erasing data in the entire memory chip or in each block obtained by dividing a memory cell array into arbitrary blocks.

On the other hand, in such a flash EEPROM, the amount of information stored in a memory cell is reduced by one bit (2 bits) in order to reduce the cost per memory capacity.
There is also known a technique of increasing from (value) / cell to multiple bits / cell, that is, multiplying the data value stored per unit memory cell to three or more values. In this multi-level operation, how to secure a sufficient margin in the range of the floating gate potential of the memory cell corresponding to each data value and the range of the read current corresponding to the potential is determined by:
This is an important point in improving the reliability of stored data.

[0004] A conventional multi-level memory cell method will be described with reference to FIGS. 16 and 17. FIG.
2 shows a cross-sectional structure of a split gate memory cell. ,
As shown in FIG. 16, in the memory cell 201, an N-type source S and a drain D of the memory cell 201 are formed on a P-type single crystal silicon substrate 202. In addition, a floating gate FG is formed on a channel CH interposed between the source S and the drain D via a first insulating film 203. A control gate CG is formed on the floating gate FG via a second insulating film 204. A part of the control gate CG is arranged on the channel CH via the first insulating film 203, and forms a select gate 205.

FIG. 17 shows the characteristics of the potential Vfg of the floating gate FG and the cell current value Id in the memory cell 201. Note that the cell current value Id is
At the time of the read operation, a predetermined bias voltage is applied to the drain D shown in FIG. 16 and the value of the current flowing between the drain D and the source S at that time, and the floating gate potential Vfg is the source S at that time. Floating gate F for
G potential. Hereinafter, a diagram showing the correspondence between the potential Vfg of the floating gate FG and the cell current value Id as shown in FIG. 17 is simply referred to as a Vfg-Id characteristic diagram.

In such a memory cell 201, the floating gate potential Vfg is, in detail, a potential Vfgw generated by charges accumulated in the floating gate FG in a write operation and a potential Vfgw from a drain D in a read operation. The sum with the potential Vfgc generated by the coupling is obtained (Vfg = Vfgw + Vfgc). However, since the potential Vfgc is constant during the read operation,
The cell current value Id is uniquely determined by a potential Vfgw determined during a write operation. Further, at the time of the write operation, if the potential Vfgw is controlled by adjusting the write time and controlling the charge amount of the floating gate FG, the floating gate potential Vfg can be controlled. As a result, the cell current value Id at the time of reading can be arbitrarily set.

Usually, these floating gate potentials Vf
As shown in FIG. 17, the relation between g and the cell current value Id is the threshold voltage Vth (= 0.5 V) of the memory cell 201.
In the above, the transistor characteristics are such that the higher the floating gate potential Vfg, the higher the cell current value Id.
In the region where the floating gate potential Vfg exceeds 3.5 V, the characteristic of the constant resistance composed of the channel CH immediately below the control gate CG becomes dominant, and the cell current value Id is saturated.
Therefore, at the time of the read operation, 0.5V ≦ Vfg ≦
The data value written in the memory cell 201 can be detected by detecting the value of the cell current value Id in the region of 3.5 V.

Therefore, as shown in FIG. 17, for example, an area where the cell current value Id is less than 40 μA is defined as a data value “11”.
The data value of “10” is defined as an area of 40 μA or more and less than 80 μA.
An area of 80 μA or more and less than 120 μA has a data value “0”.
1 "and the area of 120 μA or more correspond to the data value" 00 ", respectively.
One can store four-valued (= 2 bits) data and can read it out.

When the flash EEPROM is multi-valued, only the region where the change in the cell current value Id with respect to the change in the floating gate potential Vfg is large in the Vfg-Id characteristic diagram is used.

[0010]

In order to prevent erroneous writing at the time of writing operation and erroneous reading at the time of reading operation, the floating gate potential corresponding to each of the multi-valued data values is required. It is desirable to provide a sufficient margin in the range of Vfg and the range of the cell current value Id. However, as shown in FIG. 17, according to the conventional multi-valued method, such a margin cannot be sufficiently secured as the number of multi-valued values increases, and the multi-valued number naturally increases. Limits will arise. By the way,
In the example of FIG. 17, the range of the cell current value Id corresponding to each data value is 40 μA, the range of the floating gate potential Vfg corresponding to the data value “10” is 0.5 V, and the range of the floating gate potential Vfg corresponds to the data value “01”. The range of the floating gate potential Vfg is 1
V.

The problem of securing a margin becomes more remarkable as the number of values increases. In other words, in the case of octalization or 16-valued conversion, the range of the floating gate potential Vfg and the range of the cell current value Id corresponding to each multi-valued data value are reduced as compared with the case of quaternary conversion, It is more difficult to secure the margin.

The present invention has been made in view of such circumstances, and has as its object to store multi-valued data in a memory cell and provide a sufficient margin in the writing and reading operations of the multi-valued data. It is to provide a semiconductor memory that can be secured.

[0013]

In order to achieve the above object, in a semiconductor memory according to the present invention, when reading data stored in a memory cell, a pair of bit lines connected to the memory cell are read. The purpose is to extend the range of the readable floating gate potential by dynamically changing the setting of the voltage applied to the floating gate.

According to a second aspect of the present invention, there is provided a semiconductor memory having a structure having a floating gate, a control gate, a source, and a drain, and capable of dynamically setting a voltage applied to a pair of bit lines connected thereto. A plurality of memory cells, a data writing unit for storing a plurality of data in each of the memory cells by controlling an amount of charge stored in the floating gate, and controlling the floating gate potential for each memory cell. And data reading means for reading a plurality of data stored in each of the memory cells.

According to a third aspect of the present invention, in the semiconductor memory according to the second aspect, the data read means changes the floating gate potential in accordance with a storage data value of a memory cell. The gist of the present invention is to shift the characteristic curve between the potential and the cell current value to shift the range of the floating gate potential to be read to a desired region.

According to a fourth aspect of the present invention, in the semiconductor memory according to the third aspect, the data read means shifts a characteristic curve between the floating gate potential and a cell current value, and shifts a characteristic curve of the memory cell. The point is that the bias voltage applied to each bit line connected to the source and the drain of each of these is alternately switched.

According to a fifth aspect of the present invention, in the semiconductor memory according to the fourth aspect, the data read means sets all bit lines on one side of the read target cell to the same read target cell. A bias is applied to the same potential as one of the connected bit lines, and all the bit lines on the other side are biased to the same potential as the other bit line connected to the same read target cell. This is the gist.

According to a sixth aspect of the present invention, in the semiconductor memory according to any one of the first to fifth aspects,
The memory cell is a split gate type cell, and the gist of the invention is to control the floating gate potential by coupling via a capacitance between a drain or a source and the floating gate.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment in which a semiconductor memory according to the present invention is applied to a flash EEPROM will be described in detail with reference to FIGS.

FIG. 2A is a partial cross-sectional view showing a memory cell array 110 of a flash EEPROM according to the present embodiment. The memory cell (transistor) 1 shown in FIG. 2A belongs to a so-called split gate type and includes a source / drain region 3, a channel region 4, a floating gate electrode 5, a control gate electrode 7, and the like. I have.

Here, an N-type source / drain region 3 is formed on a P-type single crystal silicon substrate 2. A floating gate electrode 5 is formed on a channel region 4 sandwiched between source / drain regions 3 having a symmetric structure with a gate insulating film 8 interposed therebetween. The control gate electrode 7 is formed on the floating gate electrode 5 via an insulating film 9 and a tunnel insulating film 10 formed by the LOCOS method. Due to the insulating film 9, a protrusion 5 a is formed above each floating gate electrode 5. Further, a part of the control gate electrode 7 is disposed on the channel region 4 via the respective insulating films 8 and 10, and forms a select gate 7a. Here, the memory cell array (transistor array) 110 includes a plurality of memory cells 1 formed on the substrate 2. Substrate 2
In order to reduce the occupied area on the upper side, each adjacent memory cell 1 is arranged so that the source / drain regions 3 are shared.

FIG. 2B is a partial plan view of the memory cell array 110. FIG. 2A is a sectional view taken along line YY in FIG. 2B. A field insulating film 6 is formed on the substrate 2, and element isolation between the memory cells 1 is performed by the field insulating film 6.

The source / drain regions 3 of the respective memory cells 1 arranged in the vertical direction in FIG.
The source / drain region 3 forms a bit line. The control gate electrode 7 of each memory cell 1 arranged in the horizontal direction in FIG. 2B is common, and the control gate electrode 7 forms a word line.

FIG. 1 shows the overall configuration of a flash EEPROM 101 using the above-mentioned memory cell 1. The memory cell array 110 is configured by arranging a plurality of the memory cells 1 in a matrix of m × n. By the control gate electrodes 7 of the memory cells 1 arranged in the row direction,
Common word lines WL1 to WLm are formed. Further, common bit lines BL1 to BLn + 1 are formed by the source / drain regions 3 of each memory cell 1 arranged in the column direction. The connection configuration of each memory cell 1 here is a so-called virtual ground type configuration in which the source S of each memory cell 1 is not connected to the common source ground line.

Each of the word lines WL1 to WLm is connected to a row decoder 123, and each of the bit lines BL1 to BLn + 1 is connected.
Are connected to the column decoder 124. The row address and the column address specified from the outside are input to the address pad 125. The row address and the column address are transferred from the address pad 125 to the address latch 126. And address latch 1
Among the addresses latched by 26, the row address is transferred to the row decoder 123 via the address buffer 127, and the column address is transferred to the column decoder 124 via the address buffer 127. Note that the address latch 126 may be omitted as appropriate.

The row decoder 123 has an address latch 1
One word line WL (for example, WL2) corresponding to the row address latched at 26 is selected, and the potential of each of the word lines WL1 to WLm is controlled in accordance with each operation mode described later. That is, each of the word lines WL1 to WL
By controlling the potential of m, the potential of the control gate electrode 7 of each memory cell 1 is controlled.

On the other hand, the column decoder 124 selects one bit line BL (for example, BL3) corresponding to the column address latched by the address latch 126, and describes the potentials of the bit lines BL1 to BLn + 1 later. Is controlled in accordance with each operation mode. That is, each bit line B
By controlling the potentials of L1 to BLn + 1, the potentials of the source / drain regions 3 of each memory cell 1 are controlled.

Input data specified externally is input to input / output (I / O) pads 130a to 130c. In the present embodiment, the storage data for each memory cell 1 has three values (“0”, “1”, “2”), respectively.
When a logic high level is input to the I / O pad 130a, data "0" is stored in the memory cell 1, and similarly,
When a logical high level is input to the O pad 130b, data "1" is stored in the memory cell 1, and the I / O pad 1
When a logical high level is input to 30c, memory cell 1
Is stored in the data "2". Data input to the I / O pads 130a to 130c is input to input / output (I / O) latches 140a to 140c and latched. The input data is read / write amplifier 1
The data is converted into a predetermined bias voltage corresponding to the input data via the data 50 and transferred to the column decoder 124. The column decoder 124 controls the switching of the bit lines BL1 to BLn + 1 to the bias potential or zero (0) V as described later in accordance with the data.

The above circuits (123 to 127,
The operation of 150) is controlled by the global control circuit 160. Next, the configuration of the read / write amplifier 150 will be described with reference to FIG.

As shown in FIG. 3, the read / write amplifier 150 includes two current sense amplifiers 51 (a memory cell current sense amplifier 51a and a reference cell current sense amplifier 51b), a comparison amplifier 52, and a write voltage source 5
3. Reference cell unit 54 and local control circuit 55
And so on. The reference cell section 54 includes a reference selector 54a, a reference voltage generator 54b, a reference cell 54c, and the like. Each of the plurality of reference cells 54c has the same dimensional structure as the memory cell 1.

Here, the memory cell current sense amplifier 51
a and the reference cell current sense amplifier 51b convert the sense currents of the memory cell 1 and the reference cell 54c to voltages and output the voltages to the comparison amplifier 52, respectively. Then, the comparison amplifier 52 outputs the judgment data (logic high or low) based on the difference between these voltage values to the I / O latch 140a.
To 140c. The sense amplifier 51a
And 51b are well-known current sense amplifiers of, for example, a feedback type. Further, the memory cell current sense amplifier 51a applies a predetermined bias voltage based on a reference voltage generating circuit (not shown) to the memory cell 1 via the column decoder 124 based on a command from the local control circuit 55.

The reference voltage generating section 54b of the reference cell section 54 generates a plurality of reference voltages in the read mode and in the verify read operation in the write mode, and applies the respective reference voltages to the floating gate FG of the reference cell 54c. Apply. The reference selector 54a operates in synchronization with the row decoder 123 and the column decoder 124, selects one of the reference cells 54c in the read mode or the write mode, and connects its drain or source to the reference cell current sense amplifier 51b. And connect.

The local control circuit 55 controls each part of the read / write amplifier 150 based on the control of the global control circuit 160. Next, each operation mode (erase operation, write operation, read operation) of the flash EEPROM 101 thus configured will be described with reference to FIGS. FIGS. 5, 7, 11, and 13 show only the main parts of FIG. 2A, and FIGS. 4, 6, 10, and 12 show only the main parts of FIG. It was done. Each operation mode will be described, focusing on the memory cell 1A surrounded by a dotted ellipse in the figure.

(A) Erasing operation mode (see FIGS. 4 and 5) In this erasing operation mode, erasing of data stored in each memory cell 1 is performed in word line units. Here, a case will be described in which, for example, data stored in each floating gate electrode 5 of the memory cell 1 connected to the word line WL2 is erased.

At this time, as shown in FIG. 4, the potentials of all bit lines BL1 to BLn + 1 are
4, and the potential of the word line WL2 is set to 15V by the row decoder 123. In addition, each word line (WL1, WL3 other than the word line WL2)
.. WLm) are similarly set to 0 V by the row decoder 123.

At this time, the capacitance between each source / drain region 3 and the substrate 2 shown in FIG. 5 and each floating gate electrode 5 and the capacitance between the control gate electrode 7 and each floating gate electrode 5 are set. Compared with the capacity, the former is overwhelmingly large. That is, each floating gate electrode 5 is strongly coupled to each source / drain region 3 and substrate 2. Therefore, even if the control gate electrode 7 becomes 15V and each source / drain region 3 becomes 0V, the potential of each floating gate electrode 5 does not change much from 0V, and the potential difference between the control gate electrode 7 and each floating gate electrode 5 becomes smaller. Control gate electrode 7
And a high electric field is generated between each floating gate electrode 5.

As a result, a tunnel current flows, and as shown by an arrow D in FIG. 5, electrons in each floating gate electrode 5 are extracted to the control gate electrode 7 side, and the data stored in each memory cell 1 Erasure is performed. At this time, since the projection 5a is formed on each floating gate electrode 5, the electrons in each floating gate electrode 5 jump out of the projection 5a and move to the control gate electrode 7 side. Therefore, the movement of the electrons is facilitated, and the electrons in each floating gate electrode 5 can be efficiently extracted.

By simultaneously selecting a plurality of word lines WL1 to WLm, an erasing operation can be performed on all the memory cells 1 connected to each word line. As described above, the erasing operation for dividing the memory cell array 110 into arbitrary blocks for each of a plurality of sets of word lines WL1 to WLm and erasing data in each block unit is as follows.
This is called block erase.

(B) Write operation mode (see FIGS. 6 to 9) FIG. 6 shows bias conditions in the write operation mode. As shown in FIG. 6, the bit line BL3 = 12V, the bit line BL4 = 0V, and the word line WL2 = 2V. At this time, the source / drain region 3 connected to the bit line BL3 and the floating gate electrode 5 of the memory cell 1A shown in FIG.
Due to the coupling between the floating gate electrode 5A and the floating gate electrode 5A, the potential of the floating gate electrode 5A is raised to near 12V. Therefore, a high electric field is generated between the channel region 4 and the floating gate electrode 5A, and the electrons in the channel region 4 are accelerated to become hot electrons, which are injected into the floating gate electrode 5A as shown by an arrow C in FIG. As a result, the potential of the floating gate electrode 5A decreases, and the writing operation is performed.

FIG. 8A shows the relationship between the three values (“0”, “1”, “2”) of the write (stored) data and the potential Vfg of the floating gate electrode 5 in this embodiment. As shown in FIG. 8A, −1.5 V ≦ Vfg <0
It is assumed that V corresponds to data “0”, 0V ≦ Vfg <1.5V corresponds to data “1”, and 1.5V ≦ Vfg corresponds to data “2”. Data “2” corresponds to the erased state of memory cell 1.

Hereinafter, the processing procedure in the write operation mode will be described with reference to the flowchart shown in FIG. It is assumed that the erasing operation is performed before the writing operation. The processing of these write operations is performed by the global control circuit 150 and the local control circuit 55.
It is performed based on the control of.

First, in step S1, a row address and a column address are input via the address pad 125. Then, the process proceeds to step S2. In step S2, address decoding is performed. That is, of the addresses latched by the address latch 126, the row address is transferred to the row decoder 123, and the column address is transferred to the column decoder 124. The row decoder 123 selects the word line WL2 corresponding to the row address, and applies 2V to the word line WL2.
And other word lines WL1 and WL3 to WL3
The potential of m is set to the ground level (0 V). The column decoder 124 selects the bit line BL3 corresponding to the column address, supplies 12V to each bit line BL3, and sets the other bit lines BL1 and BL2 to 12V,
4 to BLn + 1 are set to the ground level. And
Move to step S3.

In step S3, memory cell 1A
Data to be stored in the I / O pads 130a to 130c
, And the data is latched by the I / O latches 140a to 140c. Then, control goes to a step S4.

In step S4, it is determined whether or not the data value of the input data is "2". If the input data value is not "2", the flow shifts to step S5. On the other hand, when the input data value is “2”, the write mode is ended. That is, before entering the write mode, all the memory cells 1 are erased and their data values are "2". Therefore, when the input data is "2", it is not necessary to perform the write operation. Then, the write mode is ended as it is.

In step S5, it is determined whether or not the data value of the input data is "1". If the input data value is not "1", that is, if the input data value is "0", the flow proceeds to step S9. I do. On the other hand, when the input data value is “1”, the process proceeds to step S6.

In step S6, a write operation is performed. That is, during the write operation, the column decoder 1
24 connects the bit lines BL1 to BL3 to the read / write amplifier 150, and 12 V is applied to the bit lines BL1 to BL3 by the write voltage source 53.
In addition, the potentials of BL4 to BLn + 1 are
4 applies a ground level (0 V).

Then, the floating gate potential Vfg of the memory cell 1A is raised by coupling from the source / drain region 3 (bit line BL3). As described above, electrons in the channel region 4 are accelerated to become hot electrons, which are injected into the floating gate electrode 5, and a write operation is performed. Note that this write operation is performed for a fixed time (several hundreds of nsec to several μsec). And step S
Move to 7.

In step S7, a read operation for verification (verify read operation) when the input data value is "1" is performed. At this time, the input data is controlled in the area “1” shown in FIG. 8A by the verify read operation. Specifically, the write operation for a certain period of time and the read operation by the reference cell 54c corresponding to the bias condition refw (Vfg = 0.75V) in the reference cell 54 are alternately repeated.

Subsequently, in step S8, it is determined whether or not the writing operation is to be terminated. This is performed by comparing the cell current Id with the reference current Iref. That is, cell current Id <reference current Ir
At the point of time ef, the write operation is terminated, and the floating gate voltage Vfg is controlled to be around 0.75V. On the other hand, if the cell current Id> the reference current Iref, the process returns to step S6 and repeats steps S6 to S8.

In step S9, step S6
A write operation is performed in the same manner as in the above. However, step S9
Is performed for a time sufficient for the input data of data "0" to be written to the memory cell 1A. Then, the write mode ends.

(C) Read operation (see FIGS. 10 to 14) In the read mode, the bias condition is a bias condition R1.
10 and a bias condition R2.
And FIG.

First, as shown in FIG. 10, the bias condition R1 is such that the bit line BL3 = 0V and the bit line BL4
= 2V and word line WL2 = 3V. At this time, FIG.
As shown in FIG. 1, a cell current Id corresponding to the floating gate potential Vfg flows from the source / drain region 3 connected to the bit line BL4 to the source / drain region 3 connected to the bit line BL3 in the channel region 4. Flowing towards.
The relationship between the floating gate potential Vfg and the cell current Id at this time, that is, the Vfg-Id characteristic diagram is shown in FIG.

Next, as shown in FIG. 12, the bias condition R2 is such that the bit line BL3 = 2V and the bit line BL4 = 0.
V and the word line WL2 = 3V. At this time, the cell current Id according to the floating gate potential Vfg flows through the channel region 4 in the bit line B, contrary to the bias condition R1.
The current flows from the L3 side toward the bit line BL4 side. The Vfg-Id characteristic diagram at this time is shown in FIG. At the time of the bias under the bias condition R2, the floating gate potential Vf
g rises due to the coupling from the source / drain region 3 connected to the bit line BL3 (2V). This is shown in FIG. 8 assuming that the coupling ratio is 100%.
The dotted ellipse shown in FIG. 8A is shifted to the right by 2V in FIG. 8A, which is substantially equivalent to the dotted ellipse shown in FIG. 8B.

When the bias condition R1 and the bias condition R2 are switched, the read / write amplifier 15
0 (memory cell current sense amplifier 51a) and the switching of the bit line is performed in the column decoder 124, for example.

Hereinafter, the processing procedure in the read operation mode will be described with reference to the flowchart shown in FIG. In FIG. 14, the same processes as those in the write mode flowchart shown in FIG. 9 have the same step numbers, and a description thereof will be omitted. The processing of these read operations is also performed based on the control of the global control circuit 160 and the local control circuit 55.

In the read operation mode, first, in FIG.
After performing the processing of step S2 following step S1 shown in (1), the process proceeds to step S10. However, step S
In 2, the row decoder 123 selects the word line WL2 corresponding to the row address, and assigns 3 to the word line WL2.
V, and the other word lines WL1, WL3 to WL
The potential of m is set to the ground level.

In step S10, in subsequent step S11, it is determined whether or not the read data is "2".
That is, the bias condition R1 is set as a precondition for determining whether the data is “0 or 1” or “2”. Here, based on the bias condition R1,
The bit line BL3 may be set to 0V and the bit line BL4 may be set to 2V. In order to prevent a through current in another unselected cell 1 connected to the same word line WL2, as shown in FIG. In addition, the bit lines BL1 and BL2 located on the left side of the bit line BL3 also have 0V like the bit line BL3.
And a bit line B located on the right side of the bit line BL4.
L5 to BLn + 1 are also set to 2V similarly to the bit line BL4. Therefore, the bit lines BL1 to BL3 are set to 0V by the column decoder, and the bit lines BL4 to BLn + 1 are connected to the read / write amplifier 150 by the column decoder 124 and set to 2V. That is, here, all the bit lines on the one (left) side of the read target cell (memory cell 1A) are biased to the same potential as one bit line (bit BL3) connected to the memory cell 1A. At the same time, all bit lines on the other (right) side of the memory cell 1A are biased to the same potential as the other bit line (bit BL4) connected to the memory cell 1A.

Here, the memory cell current sense amplifier 51
a drives the bit lines BL4 to BLn + 1 to 2V, converts the cell current Id flowing through the selected cell 1A into a cell voltage Vcell, and sends the cell voltage Vcell to the comparison amplifier 52. on the other hand,
The reference current sense amplifier 51b is connected to a reference cell 54 connected by a reference selector 54a.
c, the cell current Iref flowing through the reference cell voltage V
The signal is converted to ref and sent to the comparison amplifier 32. Note that 1.5 V is applied to the floating gate FG of the reference cell 54c by the reference voltage generator 54b.

Then, the comparison amplifier 52 compares the cell voltage Vcell with the reference cell voltage Vref to determine the read data, and determines the read data.
a to 140c. In this step S10,
As described above, the reference cell 54c with the bias condition ref1 (Vfgr = 1.5 V) in the reference unit 54 is selected by the reference selector 54a.

In the following step S11, it is determined whether or not the read data is "2". If the read data is not “2”, that is, if the read data is “0 or 1”, the process proceeds to step S12. On the other hand, when the read data is “2”, the read ends. This determination is based on the comparison data of the comparison amplifier 52 based on the condition described in the step S10, and when the reference cell voltage Vref ≦ the cell voltage Vcell (reference cell current Iref ≦ cell current Id), the read data is “2”. Is determined.

In step S12, as a prerequisite for determining in step S13 whether the read data is "0" or "1", the bias condition R
2 is set.

That is, the reference cell voltage Vref
> Cell voltage Vcell (reference cell current Iref
> Cell current Id), it is necessary to continuously determine whether the read data is “0” or “1”. However, as shown in FIG. 8A, the floating gate potential Vfg = 0V, which is the determination level of “0 or 1”,
In the region where the cell current Id = 0, the bias condition R1
It is difficult to determine whether the read data is "0" or "1". Therefore, here, the floating gate potential Vfg is changed according to the read bias condition R2 as shown in FIG.
At the right side (plus side), the determination levels of the data “0” and “1” are set to Vf shown in FIG.
By shifting to the linear region of the g-Id characteristic diagram, the same data “0” and “1” are read. In FIG. 8B, a Vfg-Id characteristic diagram before shifting is indicated by a dotted line.

Here, as described above, the read bias condition R2 is obtained by inverting the read bias condition R1 for the selected cell 1A in FIG. That is, as shown in FIG.
1 to BL3 are connected to the read / write amplifier 150 by the column decoder 124 and set to 2 V, and the bit line BL4
BLn + 1 is set to 0 V by the column decoder. The bias condition ref2 in the reference unit 54
Reference cell 54c corresponding to (Vrfg = 2V)
Is read and the data is determined.

In step S13, it is determined whether the read data is "0" or "1". Under the condition of step S12, if the reference cell voltage Vref ≦ the cell voltage Vcell (the reference cell current Iref ≦ the cell current Id) by the comparison of the comparison amplifier 52, as shown in FIG. The data is determined to be "1". On the other hand, when the reference cell voltage Vref> the cell voltage Vcell, the read data is determined to be “0”. That is, in the present embodiment, in the read mode, the bit line pair BL
3, the bias condition of BL4 is reversed left and right (dynamic setting change) to widen the range of the readable floating gate potential Vfg.

These read results, including the step S11, are stored in the I / O latches 140a to 140c. When the read data is "0", the I / O pad 150a
When the signal is "1", the signal is output to the I / O pad 150b, and when the signal is "2", the signal is output to the I / O pad 150c as a logical high level. Then, the read mode ends.

As described above, according to the semiconductor memory of the present embodiment, the following operations and effects can be obtained. (1) Even in a region where the cell current value Id does not change in response to a change in the floating gate potential Vfg (a region where the floating gate potential Vfg is equal to or lower than the threshold voltage Vth), a plurality of data values (“0” and “1”) are set. Can correspond. That is, when multi-leveling is performed, it is possible to use a region where the cell current value Id does not change with respect to the change in the floating gate potential Vfg. Then, the range of the floating gate potential Vfg corresponding to each data value can be increased to 1.5 V as compared with the conventional embodiment.

(2) According to the above (1), it is possible to take a sufficient margin for accurately setting the floating gate potential Vfg in the write operation. As a result, erroneous writing can be reliably prevented.

(3) In the read mode, the bias voltage of a pair of bit lines connected to the read memory cell 1 is inverted to shift the Vfg-Id characteristic diagram to the plus side. At this time, it is possible to determine a plurality of stored data set in a region where the cell current value Id does not change with respect to the change in the floating gate potential Vfg.

(4) According to the above (3), it is possible to provide a sufficient margin for accurately reading the cell current value Id in the read operation. As a result, erroneous reading can be reliably prevented.

(5) In the read mode, when inverting the bias voltage of a pair of bit lines connected to the read memory cell 1, the column decoder 124
The bit line connected to the read / write amplifier 150 (memory cell current sense amplifier 51a) is switched. Therefore, when changing the bias voltage of the bit line, that is, changing the bias voltage of the memory cell 1 at the time of reading, the same memory cell current sense amplifier can be shared, and it is not necessary to increase the number of the memory cell current sense amplifiers 51a.

The embodiment of the present invention may be modified as follows. In the above embodiment, the bit line bias condition R1 and the inversion bias condition R2 in the read mode are (2V-0V) and (0V-2V), respectively. However, the present invention is not limited to this. Each (3
V-0V) and (0V-3V). At that time, the Vfg-Id characteristic diagram shown in FIG. 8B shifts rightward and shifts upward in the Vfg region higher than Vth due to the characteristics of the split gate type memory cell. At this time, the predetermined floating gate potential Vf
The amount of change of the read cell current Id with respect to the g width is larger than the bias conditions (2V-0V) and (0V-2V), and the margin of the read cell current Id with respect to storage data can be increased.

In addition, "(2V-0V), (0V-2
V) "and" (3V-0V), (0V-3V) ", the bit line bias condition R1 and its inversion bias condition R1.
2 has an inversion relationship, for example, “(2V−
0V) and (0V-3V). In the above embodiment, the storage data per memory cell is ternary (“0”,
Although an example of “1”, “2”) is shown, the present invention is not limited to this. For example, as shown in FIG. 15A, the storage data is set to four values (“0”, “1”, “2”, “3”), and at the time of reading, the data shown in FIG. V
The stored data may be read by shifting the fg-Id characteristic diagram by 2 V to the right. In this case, for example, first, at the threshold voltage Vth (0.5 V), data (“0”, “1”) and data (“2”, “3”) are determined, and then, at the floating gate potential Vfg = 2 V, A determination is made between data "2" and data "3". And Vf
The g-Id characteristic diagram is shifted to the right by 2 V so that data "0" and data "1" are discriminated.

That is, as the number of values increases, it becomes more difficult to secure a margin as the range of the floating gate potential Vfg and the range of the cell current value Id corresponding to each of the multivalued data values become narrower. Therefore, the effect of the present invention is more apparent when storing three or more values of data in one memory cell in the above embodiment than when storing two-value (one bit) data. become.

In the above embodiment, the example of the flash EEPROM constituted by the split gate type memory cells 1 has been described, but the present invention is not limited to this.
For example, the present invention may be applied to an EEPROM including the split gate type memory cells 1. Further, the memory cell is not limited to the split gate type, and may be, for example, a stacked gate type memory cell.

In the above embodiment, Vfg−
Although the example in which the Id characteristic diagram is shifted to the right and multi-valued is shown, the Vfg-Id characteristic diagram may be shifted left and right to be multi-valued.

[0076]

According to the invention as set forth in any one of the first to sixth aspects, a multi-level data is stored in a memory cell, and a sufficient margin is secured in a write operation and a read operation of the multi-level data. And a semiconductor memory capable of performing such operations.

According to the invention described in any one of claims 3 to 6, the range of the floating gate potential that can be used for the write operation is expanded, and the number of levels and the margin in the write operation can be further increased. it can.

According to the fourth aspect of the present invention, multi-valued data values can be achieved without increasing the number of sense amplifiers for reading data. According to the invention described in claim 5, it is possible to prevent a through current in an unselected cell when reading data.

According to the sixth aspect of the present invention, in the semiconductor memory of the split gate type cell, multi-valued data values can be suitably achieved.

[Brief description of the drawings]

FIG. 1 is a flash EEPROM according to an embodiment;
FIG.

FIG. 2 is a partial cross-sectional view and a plan view for explaining the cell structure.

FIG. 3 is a schematic block circuit diagram of a read / write amplifier.

FIG. 4 is an explanatory diagram for explaining a cell bias in an erase mode.

FIG. 5 is an explanatory diagram for explaining a cell operation in the erase mode.

FIG. 6 is an explanatory diagram for explaining a cell bias in a write mode.

FIG. 7 is an explanatory diagram for explaining a cell operation in the write mode.

FIG. 8 is a diagram showing a relationship between a cell current and a floating gate potential.

FIG. 9 is a flowchart illustrating a processing procedure in a writing mode.

FIG. 10 is an explanatory diagram for explaining a cell bias in a read mode.

FIG. 11 is an explanatory diagram for explaining a cell operation in a read mode.

FIG. 12 is an explanatory diagram for explaining a cell bias in a read mode.

FIG. 13 is an explanatory diagram for explaining a cell operation in a read mode.

FIG. 14 is a flowchart illustrating a processing procedure in a read mode.

FIG. 15 is a diagram showing a relationship between a cell current and a floating gate potential in another embodiment.

FIG. 16 is an explanatory diagram for explaining a cell operation in a conventional mode.

FIG. 17 is a diagram showing a relationship between a conventional cell current and a floating gate potential.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Memory cell 3 ... Source / drain area 5 ... Floating gate 7 ... Control gate 150 ... Read / write amplifier which comprises reading and writing means 160 ... Global control circuit which comprises reading and writing means 123 ... It comprises reading and writing means Row decoders 124... Column decoders BL1 to BLn + 1... Bit lines constituting reading and writing means

Claims (6)

[Claims] When reading data stored in a memory cell, a voltage applied to a pair of bit lines connected to the memory cell is dynamically changed to set a range of a readable floating gate potential. Expanding semiconductor memory. 2. A plurality of memory cells each having a floating gate, a control gate, a source and a drain, and having a structure capable of dynamically setting a voltage applied to a pair of bit lines connected thereto, and the floating gate. A data writing unit that stores a plurality of data in each of the memory cells by controlling an amount of charge stored in the memory cell; and a plurality of data that is stored in each of the memory cells by controlling the floating gate potential for each memory cell. And a data reading means for reading the data. 3. The semiconductor memory according to claim 2, wherein said data read means changes said floating gate potential according to a storage data value of a memory cell, and a characteristic curve between said floating gate potential and a cell current value. By shifting
A semiconductor memory in which the range of the floating gate potential to be read is moved to a desired region. 4. The semiconductor memory according to claim 3, wherein said data read means shifts a characteristic curve between said floating gate potential and a cell current value, said data read means being connected to a source and a drain of said memory cell. A semiconductor memory that alternately switches bias voltages applied to bit lines. 5. The semiconductor memory according to claim 4, wherein said data read means sets all bit lines on one side of the read target cell as the same as one bit line connected to the read target cell. A semiconductor memory which is biased to a potential and biases all bit lines on the other side to the same potential as the other bit line connected to the read target cell with the read target cell as a boundary. 6. The semiconductor memory according to claim 1, wherein said memory cell is a split gate type cell, and is coupled by a coupling between a drain or a source and a floating gate via a capacitance. A semiconductor memory for controlling the floating gate potential.