JP2016212938A - Semiconductor storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor storage device such as a multiple value DRAM and the like that allow a small area to form the multiple value DRAM with respect to the same storage capacity.SOLUTION: A semiconductor device, which includes a plurality of memory cells each having a multiple value DRAM including a selection transistor connected to a word line, and a first storage capacitor connected to a beat line via the selection transistor and storing a plurality of values, comprises: a plurality of sample hold circuits that is provided corresponding to a plurality of beat lines, and includes a second storage capacitor; a plurality of single slope type AD converters that is provided in a latter stage of each of the sample hold circuits corresponding to the plurality of beat lines, and reads out data from each memory cell via the sample hold circuit to convert the data into a digital value; and a memory controller that applies a voltage corresponding to the digital value to each memory cell for refreshing each memory cell, and applies a voltage corresponding to the digital value of writing data to each memory cell.SELECTED DRAWING: Figure 5

Description

  The present invention relates to a semiconductor memory device such as a dynamic random access memory (hereinafter referred to as DRAM) that stores multi-value data in one memory cell.

  FIG. 1 is a block diagram showing a configuration of a DRAM according to Conventional Example 1 disclosed in Patent Document 1, for example. In FIG. 1, a memory cell MC comprising a selection MOS transistor Q and a data holding capacitor C is connected near the intersection of a bit line BL and a word line WL. When reading data from the memory cell MC, the word line WL is switched to high level, the bit line BL is precharged, and the voltage of the capacitor C is sensed by the latch type sense amplifier 101 via the parasitic capacitance of the bit line BL. Read the read data with. On the other hand, write data is written to the capacitor C via the bit line BL. Here, in order to hold the data of the capacitor C, a predetermined value is written and held in the capacitor Q in accordance with the refresh signal.

  FIG. 2 is a block diagram showing a configuration of a multi-value DRAM according to Conventional Example 2 disclosed in Patent Document 2, for example. In FIG. 2, for example, five different voltage levels are used to charge the storage capacitor 131. Here, the difference between the five voltage levels is 0.5V. This provides the ability to store five different logic values in one DRAM cell ranging from 0V to 2V.

  The multiplexer circuit 130 charges the storage capacitor 131 at one of the five voltage levels. The circuit further includes a constant current source 125 for supplying a current for charging the storage capacitor 131, an amplifier 132 including a transistor, and a switch 133 for activating a read operation. An analog-to-digital converter (hereinafter referred to as AD converter) 134 converts the voltage level Vc of the storage capacitor 131 representing five different logic values into a digital value between “0” and “4”. The multiplexer circuit 130 includes five switches SW1 to SW5 for activating any of the five voltage levels during a write or refresh operation. In the example of FIG. 2, a voltage level of 1.0 V is applied to the storage capacitor 131 and charged.

JP-A-9-008251 US Patent Application Publication No. 2005/0018501

  Conventional example 2 discloses a multi-value DRAM, but still has a problem that the area to be formed is relatively large.

  An object of the present invention is to solve the above problems and to provide a semiconductor memory device such as a multi-value DRAM which can be formed with a smaller area for the same storage capacity as compared with the prior art.

A semiconductor memory device according to the present invention includes:
A selection transistor connected to one word line of a plurality of word lines and a plurality of values respectively connected to one bit line of the plurality of bit lines via the selection transistor. A semiconductor memory device that is a multi-value DRAM having a plurality of memory cells each having a first storage capacitor
A plurality of sample and hold circuits each provided corresponding to the plurality of bit lines and including a second storage capacitor;
A plurality of single-slope ADs corresponding to the plurality of bit lines, which are provided in the subsequent stages of the sample-and-hold circuits, respectively, for reading data from the memory cells via the sample-and-hold circuits and converting them into digital values A converter,
A voltage corresponding to the converted digital value is applied and written to each memory cell to refresh each memory cell, and a voltage corresponding to a digital value of predetermined write data is applied to each memory cell. And control means for writing.

  The semiconductor memory device further includes a bit converter that converts the converted digital value into binary data and outputs it as read data, and converts the write data into a multi-value digital value and outputs it to the control means. It is characterized by that.

  In the semiconductor memory device, the control means includes voltage generating means for generating a plurality of different voltages corresponding to the digital value.

  Further, the first storage capacitor and the second storage capacitor are formed by the same process.

  Therefore, according to the semiconductor memory device of the present invention, it is possible to provide a semiconductor memory device such as a multi-value DRAM that can be formed with a smaller area with respect to the same storage capacity as compared with the prior art.

It is a block diagram which shows the structure of DRAM concerning the prior art example 1. FIG. It is a block diagram which shows the structure of the multi-value DRAM concerning the prior art example 2. FIG. 1 is a block diagram showing a configuration of a multi-level DRAM according to an embodiment of the present invention. FIG. 4 is a circuit diagram showing a configuration of the memory array 10 of FIG. 3. FIG. 4 is a circuit diagram showing a detailed configuration of the AD converter and input / output gate circuit 11 of FIG. 3. 4 is a timing chart showing operations in a data holding period and a reading period by the DRAM of FIG. 3. FIG. 6 is a block diagram showing a configuration of a 2-bit AD converter 32 in FIG. 5. It is a timing chart which shows the voltage waveform and binary counter value which show operation | movement of the 2-bit AD converter 32 of FIG. 7A. It is explanatory drawing which shows the operation | movement of the bit conversion of the bit converter 13 of FIG. 4 is a timing chart showing the overall operation of the DRAM of FIG. 3.

  Hereinafter, embodiments according to the present invention will be described with reference to the drawings. In addition, in each following embodiment, the same code | symbol is attached | subjected about the same component.

  FIG. 3 is a block diagram showing the configuration of the multi-level DRAM according to the embodiment of the present invention. Here, an example of a four-value DRAM will be described below as a multi-value DRAM. However, the present invention is not limited to this, and a multi-value DRAM that stores a plurality of digital values (multi-values) of three or more values in each memory cell MC. It can be applied to the semiconductor memory device.

  3, the multi-value DRAM according to the present embodiment includes a memory array 10, an AD converter and an input / output gate circuit (hereinafter referred to as an ADC and an I / O gate circuit) 11, a constant voltage generation circuit 12, Bit converter 13, data input buffer 14, data output buffer 15, AND gates 16 and 17 with inverting input terminals, column address strobe (CAS) clock generator 18, and row address strobe (RAS) clock generator 19 A refresh controller 20, a refresh counter 21, a row address buffer 22, a column address buffer 23, a row decoder 24, a column decoder 25, an address input terminal 61, and a data input / output terminal 62. Is done.

  FIG. 4 is a circuit diagram showing a configuration of the memory array 10 of FIG. 4, the memory array 10 includes a plurality of N word lines WLn (n = 1, 2,..., N) and a plurality of M bit lines m (m = 1, 2,..., M). . Each word line WLn and each bit line BLm are arranged in a lattice shape, and a gate connected to one word line WLn of the plurality of word lines is provided in the vicinity where each word line WLn and each bit line BLm intersect. A selection transistor Q, and a storage capacitor Q that is connected to one bit line WLm of the plurality of bit lines via the source and drain of the selection transistor Q and stores a plurality of values, respectively. A plurality of memory cells MC are provided.

  In FIG. 3, the data input buffer 14 receives and temporarily stores the digital data IO 0 to IOp input from the data input / output terminal 62, and then outputs them to the bit converter 13. The data output buffer 15 temporarily stores the read digital data IO0 to IOp after conversion from the bit converter 13 and outputs the digital data to the data input / output terminal 62. The output enable signal / OE is input to the first inverting input terminal of the AND gate 17 with the inverting input terminal. The write enable signal / WE is input to the first input terminal of the AND gate 16 with an inverting input terminal. The column address strobe signal / CAS is input to the second input terminal of the AND gate 16 with an inverting input terminal and the CAS clock generator 18. An output signal from the AND gate 16 is input to the second input terminal of the AND gate 17 with an inverting input terminal and the data input buffer 14. The output signal from the AND gate 17 is input to the data output buffer 15.

  The CAS clock generator 18 generates a CAS clock based on the column address strobe signal / CAS and outputs it to the data output buffer 15, the column address buffer 23 and the refresh controller 20. The RAS clock generator 19 generates a RAS clock based on the row address strobe signal / RAS and outputs it to the CAS clock generator 18, the ADC and I / O gate circuit 11, and the row decoder 24. The refresh controller 20 generates a refresh signal based on the CAS clock and outputs it to the refresh counter 21. The refresh counter 21 increments the refresh counter value based on the refresh signal and outputs the counter value to the row address buffer 22.

  The input addresses A0 to Aq are input to the row address buffer 22 and the column address buffer 23. The row address buffer 22 temporarily stores a row address of a predetermined bit among the input addresses A0 to Aq, and then outputs the row address to the row decoder 24. The row decoder 24 generates and outputs a word line selection signal for selecting one word line WLn based on the input row address. The column address buffer 23 temporarily stores a column address of a predetermined bit among the input addresses A0 to Aq, and then outputs the column address to the column decoder 25. The column decoder 25 generates and outputs a bit line selection signal for selecting one bit line BLm based on the input column address.

  In FIG. 3, the ADC and I / O gate circuit 11 is connected to the bit lines BL1 to BLM of the memory array 10, the RAS clock generator 19, the column decoder 25, the bit converter 13, and the constant voltage generating circuit 12, and the RAS clock generator. Based on the RAS clock from 19, using the constant voltage from the constant voltage generation circuit 12, data is read from each memory cell MC of the bit line BLm corresponding to the column address from the column decoder 25, refreshed, and Write. Here, the constant voltage generation circuit 12 generates four constant voltages of voltage Vdd, (3/4) Vdd, (1/2) Vdd, and (1/4) Vdd. The selection transistor Q is a pass transistor formed of, for example, a natural transistor and is turned on when the storage capacitor C is accessed.

  FIG. 5 is a circuit diagram showing a detailed configuration of the AD converter and the input / output gate circuit 11 of FIG. In FIG. 5, a selection transistor Q10, a sample and hold circuit 31, a 2-bit AD converter 32, and the like are provided corresponding to one bit line BLm.

  In FIG. 5, the word line Wln is connected to the gate of the selection transistor Q, one end of the data storage capacitor C is connected to the bit line Blm via the drain / source of the selection transistor Q, and the other end is, for example, It is connected to a voltage source of voltage Vdd / 2. The bit line BLm is connected to the sample and hold circuit 31 via a bit line selection transistor Q10 that is turned on when accessing the bit line BLm. The sample and hold circuit 31 includes a sample and hold storage capacitor Csh and a buffer amplification operational amplifier A1. The sample and hold circuit 31 samples and holds the bit line voltage Vb read from the bit line BLm, and then outputs it to the 2-bit AD converter 32. . The 2-bit AD converter 32 converts the input bit line voltage into 2-bit digital value data and outputs it to the bit converter 13 and the memory controller 30. The memory controller 30 responds by turning on one corresponding transistor of the four selection transistors Q11 to Q14 based on the converted digital value or the digital value of the write data from the bit converter 13. The applied voltage is applied to the storage capacitor C to write or refresh. Here, for example, the voltage Vdd is written corresponding to the digital value “11”, the voltage (3/4) Vdd is written corresponding to the digital value “10”, and the voltage (1/1 / 2) Write Vdd and write voltage (1/4) Vdd corresponding to the digital value “00”.

  In FIG. 5, the memory cell MC includes a storage capacitor Q and a selection transistor Q. However, the present invention is not limited to this, and is not limited to this as long as it includes the storage capacitor Q.

  FIG. 6 is a timing chart showing the operation of the data holding period and the reading period by the DRAM of FIG. In FIG. 6, when the voltage corresponding to each digital value is held in the data holding period and slightly decreases with the passage of time, and then the word line voltage changes from low level to high level, The relationship shows that the voltage corresponding to each digital value is different from each other, but the voltage difference between adjacent ones is reduced.

  5 and 6, four voltages Vdd, (3/4) Vdd, (1/2) Vdd, and (1/4) Vdd are used to write 2-bit digital data to one memory cell MC. However, the present invention is not limited to this, and writing may be performed using four different voltages. Further, as described above, digital data of 3 bits or more may be written in one memory cell MC.

  FIG. 7A is a block diagram showing a configuration of the 2-bit AD converter 32 of FIG. FIG. 7B is a timing chart showing voltage waveforms and binary counter values indicating the operation of the 2-bit AD converter 32 of FIG. 7A.

  7A, the 2-bit AD converter 32 of FIG. 5 includes a column AD converter 40 and an ADC control 50 provided for one memory array 10 for each bit line. 7A, the ADC controller 50 includes a binary counter 51 and a ramp voltage generator 52. The column AD converter 40 includes a comparator 41 and a latch 42. The ramp voltage generator 52 generates a single slope ramp voltage Vramp having a predetermined slope as shown in FIG. 7B based on the count value from the binary counter 51 based on the timing control signal from the RAS clock generator 19. And output to the inverting input terminal of the comparator 41. The bit line voltage Vb sampled and held by the sample hold circuit 31 is input to the non-inverting input terminal of the comparator 41. When the comparator 41 satisfies Vramp ≧ Vb (time t11 in FIG. 7B), a high level signal is output to the latch 42. To do. In response to this, the latch 42 outputs the count values B2 and B1 at that time as read data to the memory controller 30 to perform refresh.

  FIG. 8 is an explanatory diagram showing the bit conversion operation of the bit converter 13 of FIG. As shown in FIG. 8, for example, at the time of writing, binary 8 bits are converted into quaternary 4 bits and the digital value of each bit is written to each memory cell MC, while at the time of reading, quaternary 4 bits are converted to 2 bits. Convert to 8 bits and read.

  FIG. 9 is a timing chart showing the overall operation of the DRAM of FIG. As shown in FIG. 9, after the row address strobe signal / RAS becomes low level at time t1, the row address is determined and output, and then the column address strobe signal / CAS becomes low level. Is output and the column address is output. Then, the read data Dout is output at the final stage when the output enable signal / OE is at a low level.

  According to the embodiment configured as described above, each sample-and-hold circuit 31 is provided in a subsequent stage corresponding to the plurality of bit lines BL1 to BLm, and data is transferred from each memory cell MC via each sample-and-hold circuit 31. A plurality of single slope AD converters 32 that respectively read out and convert to digital values, and a voltage corresponding to the converted digital value is applied and written in order to refresh each memory cell, and also corresponds to predetermined write data And a memory controller 30 for writing data to be applied by applying each memory cell. Here, the memory controller 30 includes a constant voltage generation circuit 12 that generates four different voltages corresponding to digital values. Further, a bit converter 13 is further provided which converts the converted digital value into binary data and outputs it as read data, and converts the write data into a multi-value digital value and outputs it to the control means.

  In the above embodiment, each bit line corresponding portion of the ADC and the I / O gate circuit 11 including the selection transistor Q10, the sample hold circuit 31, and the 2-bit AD converter 32 is formed in each bit line width. In particular, the sample-and-hold storage capacitor Csh of the sample-and-hold circuit 31 is formed in each bit line width by the same CMOS process as the data storage storage capacitor C, thereby comparing with the conventional technique using the sense amplifier 101. The occupied area can be reduced, and the area required for the same storage capacity can be greatly reduced by storing the memory cells MC in multiple values.

  In the above specification, the natural transistor has a threshold value of about 0 V, for example, and can be formed by not injecting a threshold adjusting impurity into the channel. A pass transistor is a switching transistor that selectively switches between ON and OFF between a source and a drain depending on a gate voltage.

  As described above in detail, according to the semiconductor memory device of the present invention, it is possible to provide a semiconductor memory device such as a multi-value DRAM that can be formed with a smaller area with respect to the same memory capacity as compared with the prior art. .

10 ... Memory array,
11: AD converter and input / output gate circuit (ADC and I / O gate circuit),
12 ... Constant voltage generation circuit,
13: Bit converter,
14: Data input buffer,
15: Data output buffer,
16, 17 ... Andgate,
18 ... CAS clock generator,
19 ... RAS clock generator,
20 ... Refresh controller,
21 ... Refresh counter,
22: Row address buffer,
23: Column address buffer,
24. Row decoder,
25 ... column decoder,
30 ... Memory controller,
31 ... Sample and hold circuit,
32 ... 2-bit AD converter,
40 ... Column AD converter,
41 ... Comparator,
42 ... Latch,
50 ... ADC controller,
51 ... Binary counter,
52 ... Ramp voltage generator,
61: Address input terminal,
62: Data input / output terminal,
A1 ... Operational amplifier
BL, BL1 to BLM, bit lines,
C, Csh: storage capacitor,
MC: Memory cell.
Q, Q10 to Q14 ... MOS transistors,
WL, WL1 to WLN: word lines.

Claims (4)

A selection transistor connected to one word line of a plurality of word lines and a plurality of values respectively connected to one bit line of the plurality of bit lines via the selection transistor. A semiconductor memory device that is a multi-value DRAM having a plurality of memory cells each having a first storage capacitor
A plurality of sample and hold circuits each provided corresponding to the plurality of bit lines and including a second storage capacitor;
A plurality of single-slope ADs corresponding to the plurality of bit lines, which are provided in the subsequent stages of the sample-and-hold circuits, respectively, for reading data from the memory cells via the sample-and-hold circuits and converting them into digital values A converter,
A voltage corresponding to the converted digital value is applied and written to each memory cell to refresh each memory cell, and a voltage corresponding to a digital value of predetermined write data is applied to each memory cell. And a control unit for writing data.   A bit converter for converting the converted digital value into binary data and outputting it as read data, and converting the write data into a multi-value digital value and outputting it to the control means; The semiconductor memory device according to claim 1.   3. The semiconductor memory device according to claim 1, wherein the control means includes voltage generation means for generating a plurality of different voltages corresponding to the digital value.   4. The semiconductor memory device according to claim 1, wherein the first storage capacitor and the second storage capacitor are formed by the same process.

Images