TW201640501A - Semiconductor memory device - Google Patents

Abstract

The multi-value DRAM, includes: a plurality of memory cells, in each of which including a selective transistor, which is connected to a word line; a first storage capacitor, which is connected to bit line via selective transistor and memory complex values, wherein the semiconductor memory device, comprising: a plurality of sample and hold circuit, which is containing a second storage capacitor and is disposed corresponding to multi-bit line; a plurality of single slope integrating A/D converter, which is correspond to multi-bit line and is disposed in the back section of the sample and hold circuit, which convert the data to a digital value from the reading via sample and hold circuit; and a memory controller, which applying a voltage of digital value to each memory cells for refreshing each memory cells, and applying a voltage of digital value to each memory cells which is corresponding to the writing data.

Description

Semiconductor memory device

The present invention relates to a semiconductor memory device such as a dynamic random access memory (hereinafter referred to as DRAM) in which a plurality of values of data are memorized by a single memory cell.

1 is a block diagram showing the structure of a DRAM according to Conventional Example 1 as disclosed in Patent Document 1. In FIG. 1, a memory cell MC is connected in the vicinity of the intersection of the bit line BL and the word line WL, and this memory cell MC is composed of a selection MOS transistor Q and a data holding capacitor C. When the data is read from the memory cell MC, after the word line WL is switched to the high level and the bit line BL is precharged, the voltage of the capacitor C passes through the parasitic capacitance of the bit line BL, by the latch type sense amplifier 101. Sensing is performed to read the read data. In addition, the write data is written to the capacitor C through the bit line BL. Here, in order to maintain the data of the capacitor C, the corresponding renewed signal will be written and held with respect to the predetermined value of the capacitor C.

2 is a block diagram showing the constitution of a multi-value DRAM according to the conventional example 2 as disclosed in Patent Document 2. In FIG. 2, for example, in order to charge the storage capacitor 131, five different voltage levels are used. Here, the five voltage level differences are each 0.5V. Accordingly, the ability to store 5 distinct logic values in one DRAM cell from 0V to 2V is obtained.

The multiplexer circuit 130 charges the storage capacitor 131 at one of five voltage levels. The circuit further includes a constant current source 125 that supplies a current for charging the storage capacitor 131, an amplifier 132 including a transistor, and a switch 133 for starting a reading operation. An analog-to-digital converter (hereinafter referred to as an AD converter) 134 converts the voltage level Vc of the storage capacitor 131 that displays five different logical values between "0" and "4". The multiplexer circuit 130 includes five switches SW1 to SW5 in order to activate any of the five voltage levels during writing or re-operation. In the example of FIG. 2, a voltage level of 1.0 V is applied to the storage capacitor 131 to be charged. [Prior Technical Literature] [Patent Literature]

[Patent Document 1] Japanese Patent Laid-Open Publication No. Hei 9-008251 [Patent Document 2] US Patent Application Publication No. 2005/0018501

[Problems to be solved by the invention]

Although the multi-value DRAM has been disclosed in the conventional example 2, there is still a problem that the formation area is large.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor memory device of a multi-value DRAM or the like which can be formed in a small area with respect to the same memory capacity as compared with the prior art. [Means for solving the problem]

Regarding the semiconductor memory device of the present invention, it is a multi-value DRAM having a plurality of memory cells. Each of the plurality of memory cells includes: a selection transistor connected to one of the plurality of word lines; and a first storage capacitor that memorizes each multivalue and is connected to the plurality of bit lines via the selection transistor 1 bit line. The semiconductor memory device includes: a plurality of sample and hold circuits each including a second power storage capacitor and correspondingly disposed corresponding to the plurality of bit lines; and a plurality of single slope type AD converters corresponding to the plurality of bit lines And each is disposed in a subsequent stage of each of the sample and hold circuits, and each of the data is read out from each of the memory cells via each of the sample and hold circuits, and converted into a digital value; and a control device, in order to make each of the memory cells Further, a voltage corresponding to the converted digital value is applied to each of the memory cells for writing, and a voltage corresponding to the digital value of the predetermined write data is applied to each of the memory cells for writing In.

In the semiconductor memory device, a bit converter is further included. The bit converter converts the converted digital value into two-bit data and outputs as read data, and converts the written data into a multi-valued digital value and outputs the same to the control device bit converter .

Further, in the semiconductor memory device, the control device includes a voltage generating device. The voltage generating device generates a plurality of voltages different from each other corresponding to the number of the digit values.

Further, the first storage capacitor and the second storage capacitor are formed in the same process.

Based on the above, according to the semiconductor memory device of the present invention, it is possible to provide a semiconductor memory device of a multi-value DRAM or the like which can be formed in a small area with respect to the same memory capacity as in the prior art.

Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In the following embodiments, the same components are denoted by the same reference numerals.

3 is a block diagram showing the construction of a multi-value DRAM according to an embodiment of the present invention. Here, as a multi-value DRAM, an example of a 4-bit DRAM is described below, but the present invention is not limited thereto, and is applicable to storing a plurality of digit values (multi-values) of 3 bits or more in each memory cell MC. A semiconductor memory device such as a multi-value DRAM.

In FIG. 3, the multi-value DRAM according to the present embodiment includes a memory array 10, an AD converter, and input and output gate circuits (hereinafter referred to as ADC and I/O gate circuits) 11, a constant voltage generating circuit 12, Bit converter 13, data input buffer 14, data output buffer 15, gate 16 with inverting input terminal, gate 17 with inverting input terminal, row address strobe (CAS) clock generation 18, column address strobe (RAS) clock generator 19, re-new controller 20, re-counter 21, column address buffer 22, row address buffer 23, column decoder 24, row decoder 25 The address input terminal 61 and the data input and output terminal 62 are configured.

4 is a circuit diagram showing the structure of the memory array 10 of FIG. In FIG. 4, the memory array 10 is provided with a plurality of N word lines WLn (n = 1, 2, ..., N) and a plurality of M bit lines BLm (m = 1, 2, ..., M). Each of the word line WLn and each of the bit lines BLm is arranged in a lattice shape, and a plurality of memory cells MC are provided in the vicinity of the intersection of each word line and each of the bit lines, and the plurality of memory cells are each provided with a plurality of characters connected thereto. a selection transistor Q having a gate of one word line in the line, and a source and a drain via the selection transistor Q are each connected to one bit line BLm of the plurality of bit lines and memorize each Multi-valued storage capacitor C.

In FIG. 3, the data input buffer 14 receives the input digital data IO0~IOp from the data input and output terminal 62, and outputs it to the bit converter 13 after temporary storage. The data output buffer 15 temporarily memorizes the read digit data IO0 to IOp converted from the bit converter 13, and outputs it to the data input and output terminal 62. The output enable signal /OE is input to the first inverting input terminal of the AND gate 17 with the inverting input terminal. The write enable signal /WE is input to the first input terminal of the AND gate 16 with the inverting input terminal. The row address strobe signal /CAS is input to the second input terminal of the AND gate 16 with the inverting input terminal and the CAS clock generator 18. The output signal from the gate 16 is input to the second input terminal and the data input buffer 14 of the AND gate 17 to which the inverting input terminal is attached. Further, the output signal from the AND gate 17 is input to the data output buffer 15.

The CAS clock generator 18 generates a CAS clock in accordance with the row address strobe signal /CAS, and outputs it to the data output buffer 15, the row address buffer 23, and the renew controller 20. The RAS clock generator 19 generates a RAS clock in accordance with the column address strobe signal /RAS, and outputs it to the CAS clock generator 18, the ADC and I/O gate circuit 11, and the column decoder 24. The new controller 20 generates a renewed signal based on the CAS clock and outputs it to the renew counter 21. The re-counter 21 increments the re-count value according to the re-new signal, and outputs the count value to the column address buffer 22.

The input address A0~Aq is input to the column address buffer 22 and the row address buffer 23. The column address buffer 22 temporarily stores the column address of the predetermined bit in the input addresses A0 to Aq, and outputs it to the column decoder 24. The column decoder 24 generates and outputs a word line selection signal for selecting one word line WLn in accordance with the input column address. Further, the row address buffer 23 temporarily memorizes the row address of the predetermined bit in the input addresses A0 to Aq, and outputs it to the row decoder 25. The row decoder 25 generates a bit line selection signal for selecting one bit line BLm and outputs it according to the input row address.

In FIG. 3, the ADC and the I/O gate circuit 11 are connected to the bit lines BL1 to BLM of the memory array 10, the RAS clock generator 19, the row decoder 25, the bit converter 13, and the constant voltage generating circuit 12, according to The RAS clock of the RAS clock generator 19 uses the constant voltage from the constant voltage generating circuit 12 to read, renew, and re-read the data with respect to the respective memory cells MC of the bit line BLm corresponding to the row address of the self-decoder 25. Write. Here, the constant voltage generating circuit 12 generates four fixed voltages of voltage Vdd, (3/4) Vdd, (1/2) Vdd, and (1/4) Vdd. Further, the selection transistor Q is, for example, a native transistor or a pass transistor, and is turned on when the storage capacitor C is connected.

FIG. 5 is a circuit diagram showing the detailed construction of the AD converter and the input and output gate circuits 11 of FIG. In FIG. 5, one bit line BLm is provided and each is provided with a selection transistor Q, a sample and hold circuit 31, a 2-bit AD converter 32, and the like.

In FIG. 5, the word line WLn is connected to the gate of the selection transistor Q, and one end of the data storage storage capacitor C is connected to the bit line BLm via the drain ‧ source of the selection transistor Q, and the other end is connected to For example, a voltage source of voltage Vdd/2. The bit line BLm is connected to the sample-and-hold circuit 31 by the bit line selection transistor Q10 which becomes turned on when connected to the bit line BLm. The sample-and-hold circuit 31 includes a sample-and-hold storage capacitor Csh and a buffer amplification amplifier A1, and samples and holds the bit line voltage Vb read from the bit line BLm, and outputs it to the 2-bit AD converter 32. The bit AD converter 32 converts the input bit line voltage into a data of a 2-bit digital value, and outputs it to the bit converter 13 and the memory controller 30. The memory controller 30 applies the corresponding applied voltage according to the converted digital value or the digital value written from the bit converter 13 by turning on one of the four selected transistors Q11~Q14. The capacitor C is stored and written or renewed. Here, for example, the digital value "11" is written and the voltage Vdd is written, the corresponding digital value "10" is written, and the voltage (3/4) Vdd is written, the corresponding digital value "01" is input, and the voltage (1/2) Vdd is written. Write, corresponding to the digit value "00" and write the voltage (1/4) Vdd.

In FIG. 5, the memory cell MC is configured to include the transistor Q with the storage capacitor C. However, the present invention is not limited thereto, and the configuration including the storage capacitor C is not limited thereto.

FIG. 6 is a diagram showing the operation time of the DRAM data holding period and the reading period according to FIG. 3. FIG. In FIG. 6, the voltages corresponding to the respective digit values are maintained during the data retention period and slightly decreased with time. Thereafter, when the word line voltage changes from the low level to the high level, during the reading, due to the bit line capacity In the relationship, the voltages corresponding to the respective digit values are different from each other, but the voltage difference between the adjacent ones is reduced.

In FIGS. 5 and 6, in one memory cell MC, four voltages Vdd, (3/4) Vdd, (1/2) Vdd, and (1/4) Vdd are used in order to write 2-bit digital data. However, the present invention is not limited thereto, and may be configured to use four voltage writings different from each other. Further, as described above, it is also possible to write a digital data of three or more bits in one memory cell MC.

FIG. 7A is a block diagram showing the configuration of the 2-bit AD converter 32 of FIG. 5. In addition, FIG. 7B is a timing chart showing voltage waveforms and binary count values of the operation of the 2-bit AD converter 32 of FIG. 7A.

In FIG. 7A, the 2-bit AD converter 32 of FIG. 5 is configured by an AD converter 40 having bit lines per line and an ADC controller 50 provided for one memory array 10. In FIG. 7A, the ADC controller 50 is configured to include a binary counter 51 and a ramp voltage generator 52. Further, the row AD converter 40 is configured to include a comparator 41 and a latch 42. The ramp voltage generator 52 generates a ramp voltage Vramp having a single slope of a predetermined inclination as shown in FIG. 7B in accordance with the timing control signal from the RAS clock generator 19, based on the count value from the binary counter 51, and outputs it to The inverting input terminal of the comparator 41. In the sample-and-hold circuit 31, the sample-and-hold bit line voltage Vb is input to the non-inverting input terminal of the comparator 41, and when the voltage of the comparator 41 is Vramp ≧ Vb (time t11 of FIG. 7B), the high-level signal is output. To the latch 42. After the latch 42 responds to this, the count values B2 and B1 at this time are output as read data to the memory controller 30 and renewed.

FIG. 8 is an operation explanatory diagram showing bit conversion of the bit converter 13 of FIG. As shown in FIG. 8, for example, at the time of writing, binary octets are converted to quaternary 4 bits, and the digit values of the respective elements are written to the respective memory cells MC, and, at the time of reading, The four-valued 4-bit is converted to a binary 8-bit and read out.

FIG. 9 is a timing chart showing the entire operation of the DRAM of FIG. 3. FIG. As shown in FIG. 9, when the address strobe signal /RAS becomes a low level at time t1, the column address is determined and after the output, the row address strobe signal /CAS becomes a low level, the row address is determined and the row address is determined. Output. Next, the output enable signal /OE will output the data Dout at the final stage of the low level.

According to the embodiment configured as described above, the plurality of bit lines BL1 to BLm are further provided, and each of the plurality of bit lines BL1 to BLm is provided in the subsequent stage of each of the sample and hold circuits 31, and each of the memory cells MC reads the data by the respective sample and hold circuits 31. a plurality of single-slope AD converters 32 converted into digital values, and voltages corresponding to the converted digital values are applied and written in order to renew the memory cells, and data corresponding to the predetermined write data is applied to the respective memory cells. Write to memory controller 30. Here, the memory controller 30 includes a constant voltage generating circuit 12 that generates four voltages having mutually different values corresponding to the digital values. Further, it is further provided with a bit converter 13 that converts the converted digit value into binary data and outputs it as read data, and converts the written data into a multi-valued digital value to the control device.

In the above embodiment, the transistor Q10, the sample and hold circuit 31, and the ADC including the binary AD converter 32, and the corresponding portions of the I/O gate circuits 11 are in the bit line width. In particular, the sample-and-hold storage capacitor Csh of the sample-and-hold circuit 31 is formed in the same CMOS process as the data storage storage capacitor C in the line width of each bit line, and the prior art using the detection amplification 101 In comparison, the occupied area can be reduced, and the required area can be greatly reduced with respect to the same memory capacity by being memorized in the memory cell MC with multiple values.

In the above description, the native transistor has a critical value of, for example, about 0 V, which can be formed by not injecting impurities for adjustment with respect to the channel threshold. In addition, the channel transistor is a switchable transistor that can be selectively switched on or off depending on the gate voltage between the source and the drain. [Industry use possibility]

As described in detail above, according to the semiconductor memory device of the present invention, it is possible to provide a semiconductor memory device of a multi-value DRAM or the like which can be formed in a small area with respect to the same memory capacity as compared with the prior art.

10‧‧‧ memory array
11‧‧‧AD converter and input and output gate circuits (ADC and I/O gate circuits)
12‧‧‧ Constant voltage generating circuit
13‧‧‧ bit converter
14‧‧‧Data input buffer
15‧‧‧ Data output buffer
16,17‧‧‧ and gate
18‧‧‧CAS clock generator
19‧‧‧RAS clock generator
20‧‧‧Renew controller
21‧‧‧ new counter
22‧‧‧ column address buffer
23‧‧‧ row address buffer
24‧‧‧ column decoder
25‧‧‧ line decoder
30‧‧‧Memory Controller
31‧‧‧Sampling and holding circuit
32‧‧‧2 bit AD converter
40‧‧‧ row AD converter
41‧‧‧ Comparator
42‧‧‧Locker
50‧‧‧ADC controller
51‧‧‧ binary counter
52‧‧‧ ramp voltage generator
61‧‧‧ address input terminal
62‧‧‧data output terminal
A1‧‧‧Operational Amplifier
BL, BL1~BLm‧‧‧ bit line
C, Csh‧‧‧ storage capacitor
MC‧‧‧ memory cell
Q, Q10~Q14‧‧‧MOS transistor
WL, WL1~WLN‧‧‧ character line

FIG. 1 is a block diagram showing the structure of a DRAM according to Conventional Example 1. 2 is a block diagram showing the construction of a multi-value DRAM according to Conventional Example 2. 3 is a block diagram showing the construction of a multi-value DRAM according to an embodiment of the present invention. 4 is a circuit diagram showing the structure of the memory array 10 of FIG. FIG. 5 is a circuit diagram showing the detailed construction of the AD converter and the input and output gate circuits 11 of FIG. FIG. 6 is a diagram showing the operation time of the DRAM data holding period and the reading period according to FIG. 3. FIG. FIG. 7A is a block diagram showing the configuration of the 2-bit AD converter 32 of FIG. 5. FIG. 7B is a timing diagram showing voltage waveforms and binary count values of the operation of the 2-bit AD converter 32 of FIG. 7A. FIG. 8 is an operation explanatory diagram showing bit conversion of the bit converter 13 of FIG. FIG. 9 is a timing chart showing the entire operation of the DRAM of FIG. 3. FIG.

10‧‧‧ memory array

11‧‧‧AD converter and input and output gate circuits (ADC and I/O gate circuits)

12‧‧‧ Constant voltage generating circuit

13‧‧‧ bit converter

30‧‧‧Memory Controller

31‧‧‧Sampling and holding circuit

32‧‧‧2 bit AD converter

A1‧‧‧Operational Amplifier

BLm‧‧‧ bit line

C, Csh‧‧‧ storage capacitor

MC‧‧‧ memory cell

Q, Q10~Q14‧‧‧MOS transistor

WLn‧‧‧ character line

Claims (5)

A semiconductor memory device, which is a multi-value DRAM, comprising: a plurality of memory cells each comprising: a selection transistor connected to one word line of the plurality of word lines; and a first storage capacitor Respecting each of the plurality of values, and connecting to one of the plurality of bit lines via the selection transistor; the plurality of sample and hold circuits each including the second storage capacitor and corresponding to the plurality of bit lines Each of the plurality of single-slope type AD converters is disposed in a subsequent stage of each of the sample and hold circuits corresponding to the plurality of bit lines, and each of the data is read from each of the memory cells via each of the sample and hold circuits Extracted and converted into a digital value; and a control device that, in order to renew each of the memory cells, applies a voltage corresponding to the converted digital value to each of the memory cells for writing, and will correspond to a predetermined A voltage of the digital value written to the data is applied to each of the memory cells for writing. The semiconductor memory device of claim 1, further comprising: a bit converter that converts the converted digital value into two-bit data and outputs the data as read data, and writes the data Converted to a multi-valued digit value for output to the control device. The semiconductor memory device according to claim 1 or 2, wherein the control device comprises: a voltage generating device that generates a plurality of voltages different from each other corresponding to the number of the digit values. The semiconductor memory device according to claim 1 or 2, wherein the first storage capacitor and the second storage capacitor are formed in the same process. The semiconductor memory device according to claim 3, wherein the first storage capacitor and the second storage capacitor are formed in the same process.