JPH0766304A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To increase the capacity of a semiconductor storage device without increasing the number of memory cells by storing multilevel data in the memory cells. CONSTITUTION:Each two adjacent memory cell transistors X and Y sharing work lines WL1-WL4 are paired and each pair is used as a basic cell. Each cell transistor can store multilevel data. NAND cells are constituted by arranging multiple basic cells 20 and the NAND cells are connected to each other through four bit lines BL1-BL4. A line decoder 21 is connected to the word lines WL and a row decoder 22 is connected to the bit lines BL through sense amplifiers 25. Data conversion circuits 23 which convert binary data into ternary data and latch circuits 24 which latch the ternary data are connected between the row decoder 22 and sense amplifiers 25. Therefore, the storing capacity of a semiconductor device can be increased without making memory cells finer.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device using memory cells capable of storing three-valued data or more.

[0002]

2. Description of the Related Art In recent years, electrically rewritable nonvolatile R
As an OM (EEPROM) that can be highly integrated, a NAND cell type EEPROM in which a plurality of memory cells are connected in series is known. One memory cell has a FETMOS structure in which a floating gate and a control gate are stacked on a semiconductor substrate via an insulating film, and a plurality of memory cells adjacent to each other are connected in series to share a source and a drain. Connected to form a NAND cell. Such NAND cells are arranged in a matrix to form a memory cell array.

FIG. 13 shows the NAN of such an EEPROM.
A part of the D cell array is shown. One end of a NAND cell in which memory cells M211 to M214 each having a floating gate and a control gate are connected in series is connected to the bit line BL21 via a selection gate S1, and the other end of the NAND cell is connected to a source potential Vss.
It is connected to (ground). The same applies to the bit line BL22.

In this EEPROM, first, one or more N
Data is erased by emitting electrons from the memory cell for each AND block. After that, data writing is performed by electron injection in order from the memory cell farther from the bit line. That is, for data erasing, the bit lines BL21 and BL22 are floated, the select gate line SD1 is set to "H" level (for example, 20V), the word line WL1 connected to the control gate is set to "L" level (for example, 0V), and the substrate is further processed. Is set to the "H" level, and electrons are emitted from the floating gate to the substrate by the tunnel current in the memory cells M211 and M221. Next, leave the bit line and select gate line as they are.
An intermediate potential is applied to the word line WL1 and an "L" level potential is applied to the word line WL2, so that the memory cells M212 and M222.
Erase the data in. Data is erased sequentially from the bit line side in the same manner. By this data erasing, the memory cell can obtain a state in which the threshold value is moved in the negative direction (for example, "1").

Next, regarding writing of data, regarding the memory cell M213, for example, an "L" level (for example, 0 V) or an intermediate potential (for example, for example) is applied to the bit line BL21 depending on the data.
6V), select gate line SD1, word line WL1, W
L2 and WL4 are set to an intermediate potential (for example, 10V), and "H" level (for example, 20V) is applied to the selected word line WL3. As a result, in the memory cell M213, a high voltage is applied between the drain and the floating gate, electrons are injected from the substrate to the floating gate, and the threshold value shifts to the positive direction, resulting in a "0" state. By keeping the non-selected bit lines at the intermediate potential,
The "1" state is maintained.

In FIG. 12, the intermediate potential VM is applied to the unselected bit lines.
In the write mode given by, the memory cell 1 is in the half-selective injection mode (a), the memory cell 2 is in the half-selective emission mode (b), and the intermediate potential VM is set to an appropriate value to make it useless. It shows that injection and release are prevented.

According to the above operation principle, by setting the threshold value of each memory cell to 0 V or less and 0 V to 5 V, data of "1" and "0" can be obtained as shown in FIG. . In this way, as a binary memory cell, by assembling the cell array in the NAND type EEPROM structure, high integration and large capacity can be achieved.

By the way, in the semiconductor memory device, the element size tends to be further miniaturized in order to increase the storage capacity, but there is a limit to the miniaturization of this element. NAN
Even in the D-type EEPROM, it is necessary to miniaturize the cell size in order to further increase the capacity, but the capacity increase due to the miniaturization of the cell size is near the limit. Therefore, it is desired to increase the capacity by a new method that does not depend on the miniaturization of the cell size.

On the other hand, there is a multi-level memory, and there is a multi-level memory in which n bits are stored in one memory cell with multi-value of 2 ⁿ (n is an integer of 2 or more). In this case, the state of 4 levels or more must be created in the memory cell.
Have difficulty. Moreover, even if three levels are made into one memory cell, it does not become two bits.

[0010]

As described above, in the conventional semiconductor memory device, the increase of the storage capacity due to the miniaturization of the cell size is near the limit, and the increase of the storage capacity by the new method is desired. There is.

The present invention has been made in consideration of the above circumstances, and an object of the present invention is to minimize the difficulty of controllability of a memory cell without requiring miniaturization of the memory cell. Another object of the present invention is to provide a semiconductor memory device capable of increasing the storage capacity by suppressing multi-value storage.

[0012]

SUMMARY OF THE INVENTION The essence of the present invention is to increase the capacity without increasing the number of memory cells by incorporating multivalued data of three or more values in one memory cell. is there. That is, according to the present invention (Claim 1), in a semiconductor memory device, a basic cell is formed by setting n memory cells capable of storing m-value (m ≧ 3) data as one set.
It is characterized in that it is provided with a cell array in which a plurality of basic cells are arranged, and means for storing k (2 ^k ≤m ⁿ ) bits of data in each basic cell.

According to the present invention (claim 2), in a semiconductor memory device, a basic cell is formed by setting two memory cells capable of storing three-valued data as one set, and a plurality of the basic cells are arranged. And a means for converting 3-bit binary data into two sets of ternary data and storing them in each basic cell, and two sets of ternary data read from each basic cell into 3-bit 2 data. And a means for converting and outputting the value data.

Further, according to the present invention (claim 3), in a semiconductor memory device in which a non-volatile memory cell having a charge storage layer and a control gate laminated on a substrate is integrated, one memory cell has three values (H, (M, L) data is stored so that the storage amount at the time of writing is H, and when H, the cell threshold is yV.
As described above, in the case of M, a voltage difference is provided between the drain and the source of the cell at the time of reading, and the means for controlling so that the voltage is xV or more and less than yV and the value is less than xV in the case of L. L when the line current flows
And a means for detecting the threshold value of the memory cell when the current flows for the first time when yV is applied to the control gate and the H level when the current does not flow. It is characterized in that data of 3 bits is stored in each one unit.

[0015]

According to the present invention, three memory cells are provided for each memory cell.
By storing a value equal to or larger than the value, the area occupied by a unit bit can be reduced, and thus the storage capacity can be increased. Especially EEPR
In the case of the OM memory cell in which the threshold value of the cell transistor changes depending on the amount of accumulated charge, the threshold value can be set to 3 without changing the configuration of the memory cell.
Values greater than or equal to the value can be stored.

Further, when the memory cell is configured to be able to store ternary data and the basic cell is composed of two memory cells, the basic cell can take 3 ² = 9 kinds of values. If the 8 values are used as data, 3 bits = 2 ³
The value of can be stored. In this case, since two memory cells can store 3 bits, it is possible to increase the storage capacity by a factor of 1.5 compared to the conventional case by suppressing the multilevel level to a minimum of 3.

[0017]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1A is an EEPR according to an embodiment of the present invention.
FIG. 1 is a plan view showing the configuration of one set of NAND cells of OM.
(B) is the equivalent circuit diagram. In this embodiment, eight memory cells M1 to M8 are connected in series to form one NA.
It constitutes an ND cell. Further, the selection transistor S1 is arranged on the drain side of the NAND cell, and the selection transistor S2 is arranged on the source side.

2 (a) and 2 (b) are respectively shown in FIG. 1 (a).
FIG. 7 is a cross-sectional view taken along the line AA ′ and the line BB ′ of FIG. A p-type substrate (actually, a p-type well formed on an n-type substrate) 11 surrounded by an element isolation oxide film 12 is formed with a plurality of memory cells, that is, a memory cell array having a plurality of NAND cells. Hereinafter, description will be made focusing on one NAND cell.

A tunnel insulating film 1 is formed on the p-type substrate 11.
Floating gate 14 (14 ₁
~ 14 ₈ ) are formed. These floating gates 14
A control gate 16 is formed on the upper surface of the control gate 16 via a gate insulating film 15.
(16 _{1 to} 16 ₈ ) are formed. Each n-type diffusion layer 1
9 is shared as a source in one of two adjacent memory cells and a drain in the other.
As a result, the memory cells are connected in series.

Select gates 14 ₉ and 1 formed on the drain side and the source side of the NAND cell by the same process as the floating gate and the control gate of the memory cell, respectively.
6 ₉ and 14 ₁₀ , 16 ₁₀ are provided. The upper part of the substrate on which the elements are formed as described above is covered with the CVD oxide film 17. A bit line 18 is formed on the CVD oxide film 17.
And the bit line 18 is in contact with the drain diffusion layer 19 at one end of the NAND cell.

Control gates 16 in the same row of a plurality of NAND cells arranged in the row direction are connected in common and arranged as control gate lines CG1 to CG8 running in the row direction. These control gate lines are so-called word lines.
The select gates 16 ₉ and 16 ₁₀ are also arranged as select gate lines SG1 and SG2 running in the row direction, respectively.

FIG. 3 shows eight NAND cells connected to four bit lines and their peripheral circuits. The word line WL is connected to the row decoder 21. The bit line BL is connected to the column decoder 22 via a sense amplifier (S / A) 25. In this embodiment, the column decoder 22 and S / A2 are connected.
A data conversion circuit 23 and a latch circuit 24 are provided between the data conversion circuit 5 and the control circuit 5. The data conversion circuit 23 converts binary data into ternary data and vice versa. The latch circuit 24 latches ternary data. Reference numeral 20 in the figure denotes a basic cell composed of two memory cells X and Y.

FIG. 4 shows two adjacent NAND cell parts connected to two bit lines BL1 and BL2.
The operation of the EEPROM will be described using this. Here, as an example, a case where one NAND cell portion includes four memory cells is shown, but in general, it may include 2n powers. At this time, first, a case where the information stored in one memory cell transistor is ternary will be described.

When the ternary memory cell transistor is used, as shown in FIG. 5A, two adjacent memory cell transistors X and Y sharing the word line WL are used as a pair, and this is basically used. Let it be a cell. Since three values can be stored in each cell transistor, nine values can be stored in the basic cell that uses them in pairs. Therefore, 3 bits are made to correspond to these.

FIG. 5B shows the relationship between the data of the ternary memory cells X and Y and the binary data (3 bits). Since 8 bits are required for 3 bits, the remaining 1 value is not used as data. Hereafter, the ternary data is “−1”,
Symbolically named “0” and “1”.

These three-valued data are associated with three states having different threshold values of the cell transistor. For example, data of "-1" for 0V or less, 0V to 1.
The data up to 2V is “0” data, and the data up to 1.2V to 2.4V is “1” data.

Next, the operation of this embodiment will be described.
First, in data erasing, block erasing is performed on the memory cells forming the NAND cell. Here, the minimum unit of a block indicates the area of the broken line shown in FIG. In FIG. 4, each control gate is connected to one word line. Therefore, in this embodiment, the gate electrode SGD of the drain side select gate and the gate electrode SGS of the source side select gate in the selected block and the control gates CG1 to CG4 of all the memory cells in the NAND cell are set to 0V, and n High potential Vpp boosted to the mold substrate and the p-type well 11 (for example, 18
V) is given. The high potential Vpp is also applied to the bit lines BL1 and BL2.

As a result, an electric field is applied between the control gate 16 and the p-type well 11 of all the memory cells in the selected block, and electrons are emitted from the floating gate 14 to the p-type well 11 by a tunnel current. As a result, the threshold values of all the memory cells (M1 to M8 in FIG. 1) in the selected block are moved in the negative direction, and become "-1".

Next, data writing is sequentially performed from the memory cell on the source line side in the NAND cell, that is, the memory cell farther from the bit line. Now, memory cell M4
Explaining the case of selectively writing "0" and "1" data in (cell A surrounded by a broken line in FIG. 4), the gate electrode SGS of the source side select gate is set to 0V and the control gate CG4 is set to a high voltage. A potential Vpp (for example, 16 to 18 V) is applied, and the power source potential V is applied to the remaining control gates CG1 to CG3.
Intermediate potential VM between cc and high potential Vpp (for example, (1 /
2) Vpp) is applied, and VM is also applied to the gate electrode SGD of the drain side select gate. Further, 0V is applied to the selected bit line BL1 and VM is also applied to the non-selected bit line BL2. The p-type well 11 is set to 0V and the n-type substrate is set to Vcc.

As a result, in the selected cell X, 0 V of the bit line BL1 is transmitted to the drain and a high electric field is applied between the bit line BL1 and the control gate 16, and the floating gate 14
Electrons are injected into. As a result, in the cell X, the threshold value moves in the positive direction, and "0" is written. Further, when writing is continued to the cell transistor in the “0” state, the threshold value moves further in the positive direction and becomes the “1” state.

The other memory cells M1 to M3 connected to the bit line BL1 are in the write mode, but the electric field is small and there is no threshold change. In the memory cells M5 to M7 on the non-selected (or "0" write) bit line BL2 side,
The control gate has the intermediate potential VM and the channel potential has VH, and there is almost no potential difference between them, and the threshold value does not change. Similarly, the memory cell M8 on the side of the bit line BL2 is also in the write mode, but its electric field is still small and the threshold value does not change.

When the writing to the cell X is completed in this manner, next writing is similarly performed to the memory cell M3 one above in the NAND cell, and further writing is sequentially performed to the memory cells M2 and M1. .

The above operation is an operation for storing three values in one cell transistor. However, when actually writing data, two 3-bit data are written in two data before writing in the cell transistor. It is necessary to convert to a combination of values stored in the cell transistor. At the time of writing to the cell transistor, the value to be written to each cell transistor may be latched once and then written in order, but it is more efficient to write two cell transistors in a pair as described later.

In the above write operation, the high potential Vpp and the intermediate potential VM are applied to the control gate 16 of the memory cell, but since the flowing current is only the tunnel current,
It is 1 μA or less at most. Further, at the time of batch erasing, the n-type substrate and the p-type well 11 are raised to the high potential Vpp. The current flowing at this time is the tunnel current and the leak between the p-type well 11 and the n-type substrate of the peripheral circuit which is kept at 0V. It is a current, which is also 10 μA or less. Therefore, the high potential Vpp used for writing and erasing can be sufficiently covered by the booster circuit provided inside the chip.

Further, since the current flowing due to the high potential at the time of selective writing is minute as described above, it is possible to simultaneously write data to all the memory cells connected to one control gate line (word line). That is, page mode writing can be performed, and high speed writing can be performed accordingly.

To read data, the memory cells connected to one word line are read simultaneously. At that time, the gate of the selection transistor of the selected NAND cell array is 3V which is a power supply voltage, and the control gate (word line) of the non-selected cell in the selected NAND cell array is also 3V, all bit lines intersecting the selected word line. Also, 3V, 0V is applied to the source line and the word line connected to the select gate and control gate of the non-selected NAND cell array. First, 0V is applied to the selected word line. At that time, a current flows through the bit line in the memory cell having “−1” data,
It does not flow with "0" and "1" data. Next, when 1.2 V is applied to the word line, a bit line current flows in "-1" and "0" data, and flows in "1" data. This is read by the sense amplifier 25 connected to each bit line. Each sense amplifier 25 is provided with a latch circuit 24 for storing ternary data, and the latch circuit 24 serially sends the data to the I / O.

At this time, when the data is transferred from the latch circuit 24 to the I / O, the 9-value data of the pair of memory cells is converted into binary 3
A conversion circuit 23 for converting into bits is provided for each of the two ternary latch circuits 24.

It should be noted that two memory cells of a pair are replaced by one N
It can be provided in the AND cell. Further, although one of the nine values of the pair of cells is discarded, the following effective use of the discarded one value may be performed. For example,
Write data when both cells of a pair are "1" data is prohibited. If both "1" data are output during reading, one of the pair is regarded as a defective cell and the data of that pair is written. A data detection circuit for invalidating is added to each data conversion circuit. This will increase the reliability of the data.

Next, a method of writing and reading two cell transistors in pairs will be described. Figure 6
(A) shows an example of writing to a ternary cell by 2-step writing. Further, FIG. 7A shows the potential of each part at the time of writing. Here, "-1" is "L" and "0"
Corresponds to "M", "1" corresponds to "H", and memory cell M4 and M8 of FIG. 3 are written to "M" and "H", respectively.

First, in the first step, CG4 is set to 20V, C
G1 to CG3 is 10V, SGS is 0V, SGD is 10V
V and BL1 are set to 0V and BL2 is set to 0V. This allows
The threshold values of M4 and M8 both rise to M. And
In the second step, by changing BL1 from 0V to 10V, the threshold value of M4 does not change and the threshold value of M8 rises to H. In this way, M4 becomes "M", M
8 can be written to "H". In the second step,
It is effective to increase Vpp. In other words, if the voltage of CG4 is raised from 20V to 21V, writing can be done at high speed.

As shown by the alternate long and short dash line in FIG. 6 (a), in step 1, only the threshold value of M8 is raised, and in step 2, both the threshold values of M4 and M8 are raised. Good. Further, as shown in FIG. 6B, writing can be completed in one step. in this case,
The threshold value (H or M) to be raised can be selected depending on the magnitude of the voltage applied between the control gate and the substrate. In the embodiment, the bit line potential may be set in the order of 10V, 1V, 0V according to the data L, M, H, for example.

Further, as shown in FIG. 7B, the read operation is performed on the bit line by changing the voltage applied to the control gate (CG4 in this example) between step 1 and step 2. Memory cell M from incoming data
4, M8 data can be determined. In this embodiment, when the voltage of the control gate CG4 is 0V, BL1 is "H", BL2 is "H", and the voltage of CG4 is 1.5.
When V is V, BL1 is "L" and BL2 is "H". Therefore, it is determined that M4 is "M" and M8 is "H".

FIG. 8 shows a specific example of the peripheral circuit.
It is a block diagram in the case of converting from value data to ternary data and then latching. In the figure, 30 is a memory cell, 31 is a sense amplifier, 32 is a row decoder, and 33 is binary data.
A data conversion circuit for converting ternary data into binary data while converting it into value data, 34 a latch circuit for latching ternary data, 35 a read / write control circuit of the sense amplifier 31, and 36 a row decoder 32. This is a read / write control circuit.

FIG. 9 is a diagram showing a correspondence table of I / O data, latch data, and cell data. FIG. 10 is a flowchart showing the operation of the W / R control circuit when performing the two-step writing. The binary I / O data is converted into ternary data by the data conversion circuit 33, and the latch data at this time is A1 and A2 for the cell X and B1 and B for the cell Y.
It becomes like 2.

Here, the cell X will be described. When writing is started, as shown in FIG. 10, A1 = 0
If so, writing in step 1 is performed, and if A1 = 1, writing in step 1 is not performed. And A1 = 0
If so, writing in step 2 is performed, and if A2 = 1, writing in step 2 is not performed. By performing the write operation in this manner, the cell data becomes “L” when both A1 and A2 are 0, as shown in FIG.
If one of A1 and A2 is 0 and the other is 1, it becomes "M",
When both A1 and A2 are 1, it becomes "H".

FIG. 11 shows another specific example of the peripheral circuit and is a block diagram in the case where the binary data is converted into the ternary data and then latched. In the figure, 44 is a latch circuit for latching binary data, 45 is a data conversion / read / write control circuit of the sense amplifier 31, and 46 is a word line data conversion / read / write control circuit. In this example, the read / write control circuit is provided with a data conversion function to realize the same function as in FIG.

As described above, 9 states are created by two memory cells, and 8 bits are used to store 3 bits. It is convenient to use the remaining 1 state as data management information. The data management information is a pointer indicating the start address of a series of large amounts of data, a FAT mark indicating a management area file, or the like.

The present invention is not limited to the above embodiment. In the embodiments, the memory cells store three-valued data, but the present invention can be applied to any memory cells that store three-valued data or more. Further, it is applicable not only to the NAND cell type but also to the OR type. Further, the present invention can be applied not only to nonvolatile memory cells but also to DRAM. Further, the memory cell is not limited to the n-channel transistor, but may be a p-channel transistor. In addition, various modifications can be made without departing from the scope of the present invention.

[0049]

As described above in detail, according to the present invention, 1
By incorporating multi-valued data of three or more values in each memory cell, it is possible to increase the storage capacity without requiring miniaturization of the memory cell. In particular,
The memory cell is configured so that it can store ternary data, and
When one memory cell constitutes a basic cell, waste of the memory cell can be minimized to store 3 bits. Further, in the case where the threshold value of the cell transistor changes depending on the amount of accumulated charge, such as an EEPROM memory cell, the present invention can be realized without changing the configuration of the memory cell, and its usefulness is great. is there.

[Brief description of drawings]

FIG. 1 is a plan view and an equivalent circuit diagram showing a cell array configuration of an EEPROM according to an embodiment of the present invention.

FIG. 2 is a sectional view taken along the line AA ′ and BB ′ of FIG.

FIG. 3 is a circuit configuration diagram showing eight NAND cells connected to four bit lines and peripheral circuits thereof.

FIG. 4 shows two adjacent NAs connected to two bit lines.
FIG. 3 is a circuit configuration diagram showing an ND cell section.

FIG. 5 is a diagram showing the relationship between the configuration of one unit of memory cell and the data stored therein.

FIG. 6 is a schematic diagram for explaining a write operation of a basic cell.

FIG. 7 is a diagram showing the potential of each part at the time of writing and reading.

FIG. 8 is a block diagram showing a circuit example in the case where binary data is converted to ternary data and latched.

FIG. 9 is for explaining the operation of the circuit of FIG.
The figure which shows correspondence of / O data, latch data, and cell data.

10 is a flow chart for explaining the operation of the circuit of FIG.

FIG. 11 is a block diagram showing a circuit example in the case of latching binary data as it is.

FIG. 12 is a diagram showing write characteristics in a conventional EEPROM.

FIG. 13 is a diagram showing a cell array configuration of a conventional EEPROM.

FIG. 14 is a diagram showing a threshold distribution of cells in a conventional EEPROM.

[Explanation of symbols]

11 ... P-type substrate (p-type well formed on n-substrate) 12 ... Element isolation oxide film 13 ... Tunnel insulating film 14 ... Floating gate (charge storage layer) 15 ... Gate insulating film 16 ... Control gate 17 ... CVD Oxide film 18 ... Bit line 19 ... Drain diffusion layer 21 ... Row decoder 22 ... Column decoder 23 ... Data conversion circuit 24 ... Latch circuit 25 ... Sense amplifier

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Tomoharu Tanaka, 1 Komukai Toshiba Town, Saiwai-ku, Kawasaki City, Kanagawa Prefecture Corporate R & D Center, Toshiba Corporation (72) Riichiro Shirata Komukai Toshiba, Saiwai-ku, Kawasaki City, Kanagawa Town No. 1 In stock company Toshiba Research & Development Center (72) Inventor Masaki Tomomi Komukai, Saiwai-ku, Kawasaki City, Kanagawa Prefecture No. 1 Toshiba Town Co. Ltd. Research & Development Center (72) Inventor Hiroshi Nakamura Kawasaki City, Kanagawa Prefecture Komukai-Toshiba-cho, No. 1 in Toshiba Research & Development Center, Ltd. (72) Inventor Shigeka Watanabe Komukai-Toshiba, No. 1 in Saiwai-ku, Kawasaki, Kanagawa

Claims (4)

[Claims] 1. A cell array in which a basic cell is formed by setting n memory cells capable of storing data of m values (m ≧ 3) as one set, and a plurality of the basic cells are arranged, and each basic cell. And a means for respectively storing k (2 ^k ≤m ⁿ ) bits of data. 2. A memory cell capable of storing ternary data.
A basic cell is made up of one set of cells and a plurality of basic cells are arranged, and two 3-bit binary data are stored.
Means for converting into a set of three-valued data and storing in each basic cell, and two sets of three-valued data read from each basic cell into three.
A semiconductor memory device comprising: means for converting into binary data of bits and outputting. 3. A semiconductor memory device in which a non-volatile memory cell in which a charge storage layer and a control gate are laminated on a substrate is integrated, in which one memory cell incorporates ternary (H, M, L) data. As described above, the means for controlling the storage amount at the time of writing so that the threshold value of the cell becomes yV or more in the case of H, xV or more and less than yV in the case of M, and becomes less than xV in the case of L, and reading. Sometimes a potential difference is provided between the drain and source of the cell, and the control line is first supplied with xV to allow the bit line current to flow, and then the control gate is supplied with yV to allow the current to flow for the first time. The case is H
Means for detecting a threshold value of a memory cell as a level, each of the memory cells being one unit,
A semiconductor memory device characterized in that data of 3 bits is stored in each unit. 4. The semiconductor according to claim 2, wherein data is stored in 8 states out of 9 states stored by the basic cell, and the remaining 1 state is stored as data management area information. Storage device.