JP3400214B2 - Nonvolatile semiconductor memory device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device.

[0002]

2. Description of the Related Art In recent years, a NAND cell type EEPROM has been proposed as one of electrically rewritable non-volatile semiconductor devices (EEPROMs). This EEPROM
Is, for example, a plurality of memory cells having an n-channel FETMOS structure in which a floating gate and a control gate as a charge storage layer are stacked, connected in series in such a manner that their sources and drains are shared by adjacent ones. It is connected to the bit line as a unit.

FIGS. 19A and 19B are a plan view and an equivalent circuit diagram of one NAND cell portion of the memory cell array. 20 (a) and 20 (b) respectively show A in FIG. 19 (a).
FIG. 6 is a cross-sectional view taken along line A-A 'and line BB'.

A memory cell array composed of a plurality of NAND cells is formed on a p-type silicon substrate (or p-type well) 11 surrounded by an element isolation oxide film 12. One N
Explaining the AND cells, in this example, eight memory cells M1 to M8 are connected in series to form one NAND.
Make up a cell. Each memory cell has a substrate 11
The floating gate 14 (14
₁ , 14 ₂ , ..., 14 ₈ ) are formed, and the control gate 16 (16 ₁ , 16 ₂ ,
, 16 ₈ ) are formed and configured. The n-type diffusion layer 19 serving as the source and drain of these memory cells
Are connected in such a manner that adjacent ones are shared with each other, whereby the memory cells are connected in series.

First selection gates 14 ₉ and 16 ₉ and second selection gates 14 ₁₀ and 16 ₁₀ formed simultaneously with the floating gate and control gate of the memory cell are provided on the drain side and the source side of the NAND cell, respectively. It is provided. The substrate on which the elements are formed is covered with the CVD oxide film 17, and the bit line 18 is disposed on the CVD oxide film 17. The control gates 14 of the NAND cells are commonly used as control gates CG1, CG2, ..., CG.
It is arranged as 8. These control gate lines become word lines. Select gates 14 ₉ , 16 ₉ and 14 ₁₀ , 1
6 ₁₀ are also select gates SG1 and S continuously in the row direction.
It is arranged as G2.

FIG. 21 shows an equivalent circuit of a memory cell array in which such NAND cells are arranged in a matrix. The source line is connected to a reference potential wiring such as Al or poly-Si via a contact at one location for every 64 bit lines, for example. This reference potential wiring is connected to the peripheral circuit. The control gate of the memory cell and the first and second selection gates are continuously arranged in the row direction. Usually, a set of memory cells connected to a control gate is called one page, and a set of pages sandwiched by a set of drain-side (first select gate) and source-side (second select gate) select gates is one NAND. It is called a block or simply one block.

The operation of the NAND cell type EEPROM is as follows. Data writing is performed in order from the memory cell farther from the bit line. The boosted write voltage Vpp (= about 20V) is applied to the control gate of the selected memory cell, and the intermediate potential (about 10V) is applied to the control gates of the other non-selected memory cells and the first select gate. Then, 0 V (“0” write) or an intermediate potential (“1” write) is applied to the bit line according to the data. At this time, the potential of the bit line is transmitted to the selected memory cell.
When the data is "0", a high voltage is applied between the floating gate of the selected memory cell and the substrate, and electrons are tunnel-injected from the substrate to the floating gate to shift the threshold voltage in the positive direction. When the data is "1", the threshold voltage does not change.

Data erasing is performed in block units at substantially the same time. That is, All the control gates and select gates of the block to be erased are set to 0 V, and the boosted potential VppE (about 20 V) is applied to the p-type well and the n-type substrate.
VppE is also applied to the control gate and select gate of the block that is not erased. As a result, in the memory cell of the block to be erased, electrons in the floating gate are emitted to the well, and the threshold voltage moves in the negative direction.

In the data read operation, the control gate of the selected memory cell is set to 0V and the control gates of the other memory cells are set to the power supply voltage Vcc (for example, 3V) to detect whether or not a current flows in the selected memory cell. It is done by doing. In the NAND cell type EEPROM, since a plurality of memory cells are connected in cascade, the cell current during reading is small. Also, the control gate of the memory cell and the first and
Since the second selection gates are continuously arranged in the row direction, data for one page is read out to the bit lines at the same time.

However, this type of device has the following problems. (Problem 1) In the NAND cell type EEPROM, the control gate of the memory cell selected at the time of reading data is set to 0.
The control gates of the memory cells other than V and Vcc are set to Vcc (for example, 3V) to detect whether or not the cell current Icell flows. The magnitude of the cell current is not limited to the threshold voltage of the cell to be read but is connected in series. It also depends on the threshold voltage of all remaining cells. Considering the case where eight memory cells are connected in series to form one NAND cell, when Icell is the largest (when the resistance is the smallest).
Icell (Best) is when the threshold voltages of eight cells connected in series are all negative (“1” state). Icell (Wor) when Icell is the smallest (when resistance is the largest)
st) is the memory cell closest to the bit line contact side (for example, MC1 in FIG. 21) set to “1” when the threshold voltage of all other cells connected in series to the read cell is positive (“0” state). Is the case of reading.

The cell current flows from the bit line to the source line via the memory cell, but in the conventional memory cell array, the source line is shared by the NAND cells for one page to be read simultaneously (FIG. 21). When reading the memory cell (memory cell MC1 in FIG. 21) farthest from the contact between the source line and the reference potential wiring, the threshold voltage of the other seven cells connected in series to the memory cell MC1 is positive (that is, the cell current). Is the minimum Icell (Worst)), and the resistance of the other NAND string sharing the source line is the minimum (that is, the maximum cell current Ic
Consider the case of ell (Best)). In this case, since the cell current flows from the NAND string having a small resistance in the initial reading and the resistance of the source line is large, the potential of the source line of the NAND cell to which the memory cell MC1 belongs is I × R (I: Flowing cell current, R: resistance of source line).

That is, a NAND including the memory cell MC1
Since the source of the memory cell in the column floats from the ground potential Vss, the source-drain voltage and the source-gate voltage of the memory cell decrease, and the floating source also causes the substrate bias effect. Including N
The conductance of the memory cell in the AND cell column is lowered.
As described above, when the resistance of the source line is large, the source line floats from the ground potential, so that the cell current is small.
In the column, it becomes more difficult for cell current to flow.

If the bit line capacitance is CB and the threshold voltage of the memory cell is negative (that is, "1" state), it is necessary that the bit line potential be lowered from the precharge potential by .DELTA.VB. The maximum value of the bit line discharge time TRWL is determined when the cell current is the smallest, but when the source line does not float, TRWL = CB / Icell (Worst). Since the line floats, the TRWL becomes longer, and the random access time becomes longer. (Problem 2) In the conventional NAND cell type EEPROM,
As shown in FIG. 21, as many bit lines as memory cell columns are arranged in the column direction. Since memory cells will be reduced in the column direction by trench element isolation technology (Aritome et. Al. IEDM Tech. Dig. Pp. 61 (1994)), bit lines will be processed at the same pitch as memory cell rows. Becomes difficult.

[0014]

As described above, the conventional EE
In the PROM, when the resistance of the source line is large, the source line floats from the ground potential, so that the bit line discharge time becomes long and the random access time becomes long. Also, the same number of bit lines as the memory cell columns are arranged in the column direction, but when the memory cells are reduced in the column direction by trench element isolation technology, etc., the bit lines are processed at the same pitch as the memory cell columns. There was a problem that it was difficult to do.

The present invention has been made in view of the above problems, and an object of the present invention is to reduce the resistance of the source line to reduce the floating of the source line and to speed up random access. It is to provide a nonvolatile semiconductor memory device to be obtained.

Another object of the present invention is to share a bit line among a plurality of memory cell columns to relax the pitch between bit lines in the column direction and realize a high density memory cell structure. To provide a conductive semiconductor memory device.

[0017]

(Structure) In order to solve the above problems, the present invention adopts the following structure. That is, the present invention (Claim 1) is a non-volatile memory.
A memory cell, a first selection transistor, and a first selection transistor
Second selection transistor with a different threshold than the transistor
1 to 1, each of which is configured of
The fourth memory cell unit and these memory cell units
A first to a third bit line connected to the bit line.
That a nonvolatile semiconductor memory device having a memory cell array, the first memory cell unit is the first bi
The first bit line and the second bit line,
From the bit line, the first select transistor and the
1 select transistor, the memory cell, the first select
Selection transistor, the second selection transistor is connected in series
Are continued to reach the second bit line, and the second memory
The cell unit includes the first bit line and the second bit line.
A first bit line connected to the first bit line in order from the first bit line.
Select transistor, the first select transistor, before
The memory cell, the second selection transistor, the first
Select transistors are serially connected to the second bit
Line, and the third memory cell unit is connected to the second memory cell unit.
A second line connected between the bit line and the third bit line;
From the bit line of the first selection transistor,
A first select transistor, the memory cell, the second
Selection transistor, the first selection transistor is in series
Connected to the third bit line, the fourth memo
The re-cell unit includes the second bit line and the third bit line.
Connected from the second bit line in order from the second bit line.
One selection transistor, the first selection transistor,
The memory cell, the first select transistor, the
The second select transistor is connected in series and the third bit is connected.
Leading to preparative line, characterized in that.

According to the present invention (claim 4 ), a memory cell portion composed of one or a plurality of non-volatile memory cells and two memory cells connected in series to one end side of the memory cell portion.
A select transistor and the other end of the memory cell section in series
A non-volatile semiconductor memory device having a memory cell array in which memory cell units each composed of two connected selection transistors are arranged in a matrix.
Two memory cell units are connected in parallel to form a plurality of parallel connection units. One side of an arbitrary parallel connection unit shares a word line and a select line, and the other side of the parallel connection unit has a contour.
The two parallel connection units that do not share the same connection share a contact and are connected to the first common signal line, and the other end side
Shares the word lines and select line, in one end is connected to the second common signal line shared contact in two parallel connecting units to each other that do not share contacts, each of the notes
3 out of 4 select transistors in the recell unit
Have the same threshold, the other one is different from the other
Have four values and are connected to the same common signal line.
Connect to the same selection line in the memory cell unit 4
Three of the select transistors have the same threshold
The remaining one has a threshold value different from that of the other .

[0019]

Further, by appropriately selecting E type, I type, and D type as the selection MOS transistors for connecting one end side and the other end side of the memory cell unit to the common signal line, the chip area is not increased. The above memory cell array capable of high-speed random access can be realized.

[0021]

DETAILED DESCRIPTION OF THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. [First Embodiment] In the present invention, a memory cell or a memory cell unit including a memory cell and a selection transistor is arranged as shown in FIG. 1 to form a sub-array. That is, one end of the memory cell unit is connected to the common signal line by sharing contacts with the four memory cell units. The other end of the memory cell unit is also connected to the common signal line by sharing contacts with the four memory cell units as shown in FIG.

More specifically, one end of an arbitrary memory cell unit (for example, the third unit 3 from the top in FIG. 1) has four memory cell units sharing the word line (from the first from the top). The fourth units 1 to 4) share a contact and are connected to the first common signal line (common signal line 1), and the other end side of the memory cell unit (the third unit 3 from the top) is a word line. Of the memory cell unit and two memory cell units (5th and 6th units 1 and 2 from the top) which share a contact with one end side of the memory cell unit, The two memory cell units sharing the contact with one end side (the third and fourth units 3 and 4 from the top) share the contact and are connected to the second common signal line (common signal line 2). It is.

In other words, two memory cell units are connected in parallel to form a plurality of parallel connection units, and one parallel connection unit has two parallel connection units sharing a word line on one end side. Are connected to the first common signal line by sharing a contact with each other, and the other end of the parallel connection unit shares a word line with one parallel connection unit that does not share the contact with another parallel connection unit. Then, it is connected to the second common signal line.

Then, such sub-arrays are continuously arranged to form a memory cell array as shown in FIG. As shown in FIGS. 3 and 4, the memory cell unit is composed of a memory cell portion composed of memory cells and a selection transistor. The memory cell unit A shown in FIGS.
Each of B, C and D corresponds to one of the memory cell units 1, 2, 3, 4 of FIG. 1 and FIG. 2, and the corresponding method is arbitrary, so there are 24 ways (for example, A; 1, B). ;
2, C; 3, D; 4 may be used, or A; 4, B; 3, C;
1, D; 2). In FIG. 4, the threshold value Vt1 of the E type selection gate may be larger than the threshold value Vt2 of the I type selection gate, for example, Vt1 = 2V and Vt2 = 0.5V. In FIG. 3, the threshold of the E type selection gate may be 0.7V, for example, and the threshold of the D type selection gate may be −2V, for example.

When selecting the memory cell of FIG. 3, there are two kinds of voltages applied to the select gates SG1, SG2, SG3 in the selected block, and the voltage Vsgh (for example, Vcc = 3V) for turning on both the E type and the D type. ), And D type is a voltage Vsgl (for example, 0V) which is turned on but E type is turned off. Among the four memory cell units, for example, when selecting the memory cell unit A, SG2, SG3, SG
4 is Vsgh, SG1 is Vsgl, and when selecting the memory cell unit B, SG2 is Vsgl, SG1, SG3, S
G4 should be Vsgh. Similarly, when selecting the memory cell unit C, SG1, SG2 and SG4 are set to Vsg.
h and SG3 may be set to Vsgl. When selecting the memory cell unit D, set SG1, SG2, SG3 to Vsgh
, SG4 may be set to Vsgl.

When 0V is applied to the select gate in the non-selected block, the bit line does not leak through the non-selected block. When the memory cell unit is the one shown in FIG. 4, the method of selecting the memory cell unit is almost the same as that in the case of the above-described FIG. Value is 0.5V
Then, Vsgl applied in the selected block is 1.5V
Good. As a result, the E type selection gate is turned off and I
The type selection gate turns on.

There are various variations in the configuration of the memory cell section. An example is shown in FIGS. For example, in FIG.
If it is as in (a), it is a NOR cell type EEPROM, and in FIG. 5 (b), it is an AND cell type EEPROM (H.
Kume el al.; IEDM Tech.Dig., Dec.1992, pp.991-993),
If it is FIG.5 (c), it is a NAND cell type. It may be as shown in FIG. Further, the present invention is not limited to the EEPROM and is also effective for so-called EPROM and mask ROM. [Second Embodiment] Next, the present invention will be described in detail by taking a NAND cell type EEPROM as an example.

FIG. 7 is a block diagram showing the basic structure of the NAND cell type EEPROM according to this embodiment. In the figure, reference numeral 1 denotes a memory cell array serving as a memory means, which is an open bit line system, and thus the memory cell array is divided into 1A and 1B. 2 is data writing,
It is a sense amplifier circuit as a latch means for reading. 3 is a row decoder for selecting a word line, 4
Is a column decoder for selecting a bit line, 5 is an address buffer, 6 is an I / O sense amplifier, 7 is a data input / output buffer, and 8 is a substrate potential control circuit.

FIG. 8 is a diagram showing the configuration of the memory cell array 1A, and FIG. 9 is a diagram showing the configuration of the memory cell array 1B. The memory cell array according to the present embodiment (FIGS. 8 and 9) is different from the conventional memory cell array (FIG. 21) in that the select gate on the source line side is not connected to the source line of the n-type diffusion layer. Both select gates at both ends are in contact with the bit line. That is, at the time of reading, the low resistance bit line serves as a source line, so that the reading speed becomes high. Moreover, since two bit lines are shared by four memory cell columns (four columns), the pitch of the bit lines is double that of the conventional one, and the bit lines can be easily processed.

In the memory cell array of this embodiment, two select MOs that connect one NAND cell column and a bit line are connected.
The threshold voltage of the S transistor is set to Vth1, Vth2 (Vth
Two types of 1> Vth2) are provided. High threshold voltage V
E-type select MOS transistor having th1 (eg 0.8V), low threshold voltage Vth2 (eg -2V)
The selection MOS transistor having the above is referred to as D-type. The voltage applied to the select gate is E-t for D-type transistors.
The voltage Vsgh (for example, 3
V) (Vsgh> Vt1, Vt2), and the voltage V at which the D-type transistor turns on but the E-type transistor turns off
sgl (for example, 0 V) (Vt1>Vsgl> Vt2).

As described above, by providing two types of threshold voltage of the selection MOS transistor and setting two types of voltage to be applied to the selection gate, among four NAND cell units sharing a contact at the time of writing or reading. Both ends of one NAND cell unit can be electrically connected to two bit lines, and the other memory cell units can be electrically disconnected.

The read and write methods will be specifically described below. <Read> Memory cell M in memory cell unit (3)
The data of C31, MC71, ... Is transferred to the bit lines BL1A, BL3A,
When reading to ..., first, the bit lines BL1A, BL3A,
Are precharged to the bit line read potential VA (for example, 1.8 V), and BL2A, BL4A, ... Are grounded to 0V.
After precharging, the bit lines BL1A, BL3A, ... Are floated.

Next, the control gate CG1 is 0V, and CG2-
CG8 is set to Vcc (for example, 3V). The selection gate SG3 is Vsgl, and the selection gates SG1, SG2, SG4.
To Vsgh. 0 for other select gates and control gates
Set to V. In this case, the bit lines BL0A, BL2A, BL4
Select MOS transistors ST11, ST1 connected to A, ...
2, ST21, ST22, ST23, ST31, ST32, ST4
1, ST42, ST51, ST52, ST61, ST62, ST7
1, ST72, ..., and bit lines BL1A, BL3A, BL5
Select MOS transistors ST14, ST2 connected to A, ...
4, ST34, ST44, ST54, ST64, ST74, ST8
4, ... turns on. On the other hand, via SG4, the bit line BL1
D-type selection MOS connected to A, BL3A, BL5A, ...
Transistors ST33, ST73, ... Turn on, but E-type
Select MOS transistors ST13, ST23, ST43, ST
53, ST63, ST83, ST93, ST103, ... Are turned off.

Therefore, if the data written in the memory cells MC31, MC71, ... Is "1", the precharged bit lines BL1A, BL3A, ... Are grounded bit lines BL2A ,.
The memory cell MC3 in the memory cell unit (3) is discharged by discharging to BL4A ,.
The data of 1, MC71, ... Is the bit lines BL1A, BL3A ,.
Read out. On the other hand, if the data written in the memory cell is "0", the bit lines BL1A, BL3A, ... Do not discharge and maintain the precharge potential.

On the other hand, the memory cells MC11, MC21, MC41, MC51, MC61, in the memory cell units (1) (2) (4),
Bit lines BL1A, BL for MC81, MC91, ...
E-type selection MOS transistors ST13, ST23, ST43, ST53, ST63, ST8 connected to 3A, BL5A, ...
Since 3, ST93, ... Are turned off, memory cells MC11, M
The data of C21, MC41, MC51, MC61, MC81, MC91, ... Is not read to the bit lines BL1A, BL3A, BL5A ,.

On the other hand, the data of the memory cells MC11, MC51, MC91, ... In the memory cell unit (1) are transferred to the bit line B.
When reading to L0A, BL2A, BL4A, BL6A, ..., Select gates SG2, SG3, SG4 are set to Vsgh, SG
Set 1 to Vsgl. When the data of the memory cells MC21, MC61, MC101, ... In the memory cell unit (2) are read to the bit lines BL0A, BL2A, BL4A, ..., The selection gates SG1, SG3, DG4 are set to Vsgh, SG.
Set 2 to Vsgl. The data of the memory cells MC41, MC81, ... Within the memory cell unit (4) are transferred to the bit line BL.
When reading to 1A, BL3A, ..., Select gate SG
1, SG2 and SG3 may be set to Vsgh, and SG4 may be set to Vsgl.

As described above, in the present embodiment, the source line (n-type diffusion layer) of the conventional memory cell array is eliminated, and half of the bit lines are grounded at the time of reading to perform the same role as the conventional source line. The data of the memory cell is read to the remaining half of the bit lines. By using a bit line formed of low resistance poly-Si, Al or the like instead of a source line formed of a conventional high resistance n-type diffusion layer, it is possible to solve the problem of reduction in read speed due to floating of the source line. .

The read operation will now be described in more detail with reference to the timing chart. FIG. 10 is a timing chart when reading the data written in the memory cells MC31, MC71, ... In the memory cell unit (1) of FIG.

Bit lines BL0A, BL2A, BL4A, BL6
, Are connected to the sense amplifier SA1 in FIG. 11, and the bit lines BL1A, BL3A, BL5A, ... Are connected to the sense amplifier SA2 in FIG. The sense amplifier uses the control signal φP
, ΦN, which are formed by CMOS flip-flops.

First, the precharge signals PRA1, PRA2,
PRB2 changes from Vss to Vcc (time t0), and bit line B
L1A, BL3A, BL5A, ... Are VA2 (eg 1.7V)
, The (dummy) bit lines BL1B, BL3B, BL5B, ... Are precharged to VB2 (for example, 1.5V) (time t
1). VA1 is 0V, and bit lines BL0A, BL2A, B
L4A, BL6A, ... Are grounded.

When the precharge is completed, PRA2 and PRB2 become Vss, and the bit lines BL1A, BL3A, BL5A, ... Are brought into a floating state. After that, a desired voltage is applied from the row decoder 3 to the selection gate and the control gate (time t2). Control gate CG1 is 0V, CG2 to CG8 are Vcc (for example, 3V), and SG1, SG2, SG4 are 3V.
(Vsgh) and SG3 become 0V (Vsgl). When the data written in the memory cells MC31, MC71, ... In the memory cell unit (3) is "0", the threshold voltage of the memory cell is positive, so the cell current does not flow and the bit line BL1A,
The potentials of BL3A, BL5A, ... Remain at 1.7V. When the data is "1", the cell current flows and the bit line BL
The potentials of 1A, BL3A, BL5A, ... Since the select gate SG3 is 0V, SG3
The E-type selection MOS transistor having the gate electrode as the gate electrode is turned off, and the data of the memory cell in the memory cell unit (1) (2) (4) is not transferred to the bit line. During this time, the (dummy) bit lines BL1B, BL3B, BL5B, ... Are kept at the precharge potential of 1.5V.

After that, at time t3, φP is 3V and φN is 0V.
V, the CMOS flip-flop FF is inactivated, and φE becomes 3V at time t4, so that C of SA2
The MOS flip-flop FF is equalized, and the nodes N1 and N2 become Vcc / 2 (1.5 V, for example). At time t5, SS2, SA, and SB become 3V, and after the bit line and the sense amplifier are connected, φN changes from 0V to 3V, φN
P changes from 3V to 0V, and bit lines BL1A, BL3A, B
The potential difference between L5A, ... And the bit lines BL1B, BL3B, BL5B, ... Is amplified (time t6). That is, the memory cell M
If "0" is written in C31, MC71, ..., SA
If the node N1 of 2 becomes 3V, the node N2 becomes 0V, and "1" is written in the memory cells MC31, MC71, ..., The node N1 becomes 0V and the node N2 becomes 3V. After that, when the column selection signal CSL changes from 0V to 3V, C
The data latched in the MOS flip-flop is I
It is output to O and / IO (time t7).

Through the read operation, the bit lines BL0A, B0
L2A, BL4A, BL6A, ... Are grounded to 0V. That is,
Every other bit line will be grounded. Therefore,
The distance between the read bit lines is twice as large as that when the bit lines are not grounded, and the noise due to the capacitive coupling between the bit lines is significantly reduced. Also, through the read operation, PRB1
To Vcc and VB1 to 0V, the bit line BL
0B, BL2B, BL4B, BL6B, ... May be grounded.
As a result, it is possible to reduce capacitive coupling noise between bit lines during amplification of the bit line potential.

FIG. 13 shows the memory cell unit (1) of FIG.
9 is a timing chart for reading data written in memory cells MC11, MC51, MC91, ... First, the precharge signals PRA1, PRA2, PRB1 change from Vss to Vcc (time t0), and the bit lines BL0A, B0
L2A, BL4A, ... Are precharged to VA1 (1.7 V, for example), and the (dummy) bit lines BL0B, BL2B, BL4B, ... Are precharged to VB1 (1.5 V, for example) (time t1). V
A2 is 0V, and bit lines BL1A, BL3A, BL5A, ...
Is grounded.

When the precharge is completed, PRA1 and PRB1 become Vss, and the bit lines BL0A, BL2A, BL4A, ... Become floating. After that, a desired voltage is applied from the row decoder 3 to the selection gate and the control gate (time t2). Control gate CG1 is 0V, CG2 to CG8 are Vcc (for example, 3V), SG2, SG3 and SG4 are 3V.
(Vsgh) and SG1 become 0V (Vsgl). When the data written in the memory cells MC11, MC51, MC91, ... Is “0”, the threshold voltage of the memory cell is positive, so that no cell current flows and the bit lines BL0A, BL2A, BL4A,
The potential of ... remains at 1.7V. When the data is "1", cell current flows and bit lines BL0A, BL2A, BL
The potential of 4A, ... falls to 1.5V or less. Further, since the selection gate SG1 is 0V, the E-type selection MOS transistor using SG1 as the gate electrode is turned off, and the data of the memory cell in the memory cell unit (2) (3) (4) is not transferred to the bit line. During this time, the (dummy) bit line BL
0B, BL2B, BL4B, ... Precharge potential 1.5V
Kept in.

After that, at time t3, φP is 3V and φN is 0.
V, the CMOS flip-flop FF is inactivated, and φE becomes 3V at time t4, so that C of SA1
The MOS flip-flop FF is equalized, and the nodes N1 and N2 become Vcc / 2 (1.5 V, for example). At time t5, SS1, SA, and SB become 3V, and after the bit line and the sense amplifier are connected, φN changes from 0V to 3V, φN
P changes from 3V to 0V, and bit lines BL0A, BL2A, B
The potential difference between L4A, ... And the bit lines BL0B, BL2B, BL4B, ... Is amplified (time t6). That is, if "0" is written in the memory cells MC11, MC51, MC91, ..., The node N1 of SA1 becomes 3V and the node N2 becomes 0V, and if "1" is written, the node N1 becomes 0.
V, the node N2 becomes 3V. After that, when the column selection signal CSL changes from 0V to 3V, the data latched by the CMOS flip-flop is output to IO and / IO (time t7).

Through the read operation, BL1A, BL3A, B
Since L5A, ... Are grounded to 0V, noise due to capacitive coupling between bit lines is reduced. Similarly, the data of the memory cells MC21, MC61, MC101, ... In the memory cell unit (2) are transferred to the bit lines BL0A, BL2A, BL4A, BL6A ,.
FIG. 14 is a timing chart for the case of reading the data. SG
By setting Vsgl to 2 and Vsgh to SG1, SG3 and SG4, the memory cell unit (2) can be selected and the memory cell units (1), (3) and (4) can be deselected.

Memory cell M in the memory cell unit (4)
The data of C41, MC81, ... is transferred to the bit lines BL1A, BL3A,
FIG. 15 is a timing chart for reading to ... S
If G4 is set to Vsgl and SG1, SG2, and SG3 are set to Vsgh, the memory cell unit (4) can be selected and the memory cell units (1) (2) (3) can be deselected.

The timing of the read operation is arbitrary. For example, the transfer gate connecting the bit line and the sense amplifier may be turned on at time t5 to transfer the potentials of the bit line and the dummy bit line to the nodes N1 and N2 of the sense amplifier, and then the transfer gate may be turned off.
In this case, since the bit line and the dummy bit line are separated from the sense amplifier, the load capacitance of the sense amplifier is reduced and the potentials of the nodes N1 and N2 are rapidly determined at the time of sensing and data latching.

In the above embodiment, for example, the memory cell MC
When reading 31, MC71, ... Bit lines BL1A, BL1
Precharge 3A, BL5A, ..., Bit lines BL2A, BL
4A, ... is grounded, and data of the memory cell is transferred to the bit line BL1.
Reading to A, BL3A, BL5A, ... Which of the bit lines connected to both ends of the memory cell unit is used to read data is arbitrary. For example, the memory cell MC
Bit lines BL2A, BL4 when reading 31, MC71, ...
Precharge A, ..., Bit lines BL1A, BL3A, BL5
The data of the memory cell is connected to the bit line BL2 by grounding A, ...
You may read to A, BL4A, .... <Write> The write operation of this embodiment will be described below.

A writing procedure for writing to the memory cells MC31, MC71, ... In the memory cell unit (3) of FIG. 8 will be described below. Select gates SG1 and SG2
Is set to 0V, and at least one of the selection MOS transistors connected in series using the selection gates SG1 and SG2 as gate electrodes is turned off. SG3, SG4, CG1
~ CG8 is Vcc, bit lines BL1A, BL3A, BL5A, ...
Is set to Vcc, and the channel of the page for writing is set to Vcc
Precharge to -Vth (being smaller than the bit line potential Vcc due to the threshold voltage drop in the selection MOS transistor). At this time, in order to transfer Vcc to the channel without dropping the threshold value, SG3 and SG4 are set to Vcc higher than Vcc.
cc + Vth or Vcc + 2Vth (Vth; threshold of E-type selection MOS transistor) may be used. Bit line BL0
A, BL2A, BL4A, ... May be set to Vcc or 0 V, and may be set to any voltage.

After that, when the selection gate SG3 is set to Vsgl (for example, 0 V), the D-type selection MOS transistor S
T33, ST73, ... Are turned on, but the E-type selection MOS transistor is turned off. Therefore, the channels of the memory cell units (1), (2), and (4) that are not written have the potential Vcc (-Vth) charged from the bit line. ) Makes it floating. The data to be written to the memory cells MC31, MC71, ... In the memory cell unit (3) is given from the bit lines BL1A, BL3A ,.

For example, when "0" is written in the memory cell MC31, if the bit line BL1A is set to 0V, D
The -type selection MOS transistor ST33 is turned on and the channel of the memory cell MC31 becomes 0V. Memory cell MC31
To write "1" to, set bit line BL1A to 3
When set to V, D-type selection MOS transistor ST33
Has a gate of 0V, a drain of 3V (Vcc), and a source of 2.2V (Vcc-Vth) or 3V (Vcc). D-type selection MOS so that ST33 turns off in this potential state
For example, the threshold value of the transistor is -1.6V or -2.
If set to V, D-type selection MOS transistor ST
33, ST73, ... Are turned off, and the channel of the memory cell MC31 for writing "1" becomes floating at Vcc (-Vth). Alternatively, the threshold value of the D-type selection MOS transistor may be set to, for example, -5V. In this case, D-t
Even if the ype selection MOS transistor ST33 is not turned off,
The source of the selection MOS transistor ST34 is Vcc or Vcc
ST34 with -Vth, drain Vcc, and gate Vcc
Is turned off, and the channel of the memory cell in which "1" is written is set to be floating.

Threshold value of D-type selection MOS transistor, threshold value of E-type selection MOS transistor, and
As described above, the potential applied to the select gates SG3 and SG4 may be set so that the channel of the memory cell to be written is 0V and the channel is floating when the channel is 0V and “1” is written. The threshold value and the select gate potential are highly arbitrary. Bit lines BL0A, BL2A, BL4A, ... May be set to Vcc,
It may be 0V.

Select gate SG3 is changed from Vcc to Vsgl (D-t
The control gates CG1 to CG8 are set to a voltage higher than the threshold voltage of the ype selection MOS transistor but lower than that of the E-type selection MOS transistor, for example, 0V.
From Vcc to the intermediate potential VM (about 10V). Then, the channels of the memory cell units (1) (2) (4) which are not written and the memory cells MC31, MC71, ... In which "1" is written are in a floating state, so that Vcc (- The voltage rises from Vth) to an intermediate potential (about 8V). The channel of the memory cells MC31, MC71, ... In which "0" is written is 0V because the bit line is 0V.

After the channel of the memory cell in which programming is not selected and "1" is programmed is boosted from Vcc (-Vth) to the intermediate potential, the control gate CG1 is boosted from the intermediate potential VM to the writing voltage Vpp (20V). Then, the memory cells in the memory cell units (1) (2) (4) that are not written and the memory cell unit (3) that is written "1"
Since the channel of the memory cell inside is an intermediate potential (about 8V) and the control gate CG1 is Vpp (about 20V), these memory cells are not written, but the channel of the memory cell for writing "0" is 0V, the control gate is Is Vpp (20
Since it is about V), electrons are injected from the substrate to the floating gate and "0" writing is performed.

Now, the write operation of this embodiment will be described in more detail with reference to a timing chart. FIG. 16 is a timing chart when writing to the memory cell MC31 (and the memory cell MC71, ...) In the memory cell unit (3).

Memory cell M in the memory cell unit (3)
The data to be written in C31, MC71, ... Is latched in the sense amplifier circuit (SA2 in FIG. 12). That is,
In the case of writing "0", the node N1 is 0V and the node N2 is 3V.
When writing V, "1", the node N1 is 3V, N2
Becomes 0V.

When the write operation is started, first at time t1, S
G3, SG4 as Vss, SG1, SG2, CG1 to CG8
To Vcc or Vcc + Vth or Vcc + 2Vth. In this embodiment, when writing to the memory cells MC31, MC71, ... In the memory cell unit (3), writing is not performed in the memory cells in the memory cell units (1) (2) (4). . In this example, the channels of the memory cell units (1) (2) (4) are charged from the bit lines BL0A, BL2A, BL4A, .... In this embodiment, the bit lines BL0A, BL2A, BL
4A, ... Are charged from VA1 of the sense amplifier SA1 of FIG. 11 to Vcc. As a result, the channel of the non-selected memory cell is V
It is charged to cc-Vth or Vcc. At this time, the channel of the memory cell for writing may also be charged to Vcc-Vth or Vcc. Thus memory cell unit (1)
(2) As a method of charging the channel of the memory cell of (4) to Vcc (-Vth), charging from BL0A, BL2A, BL4A, ... Or charging from BL1A, BL3A, BL5A may be performed. .

On the other hand, bit lines BL1A, BL3A, BL5A,
A potential of Vcc or Vss (0V) is applied to the ... Depending on the data latched in the sense amplifier circuit SA2. As a result, when "0" is written in the memory cell MC31 after charging the channel of the non-selected memory cell unit, the bit line BL1A is set to 0V and the channel of the memory cell MC31 is set to 0V. When writing "1" to the memory cell MC31, the bit line BL1A is set to Vcc (for example, 3V) and the memory cell MC
The 31 channels will be charged to Vcc (-Vth).

That is, the selection gates SG1 and SG2 are set to Vs.
s and SG3 are set to Vsgl (for example, 0V), and SG4 is set to Vcc or Vcc + Vth or Vcc + 2Vth. Select gate S
At least one of the selection MOS transistors connected in series with the gate electrodes G1 and G2 is turned off. Since the select MOS transistor using SG3 as the gate electrode in the memory cell unit (1) (2) (4) that does not write is E-type, it is turned off, and the memory cell unit (1) (2) (4) The cell channel becomes floating at Vcc (-Vth).

When "1" is written in the memory cells MC31, MC71, ..., Since the bit lines BL1A, BL3A, ... Are Vcc, the channels of these memory cells become floating.

When "0" is written in the memory cells MC31, MC71, ... Since the bit lines BL1A, BL3A, ... Are 0V, the channel of the memory cell is kept at 0V.
After the selection gate SG3 is set to Vsgl (for example, 0V), the control gates CG1 to CG8 are set to the intermediate potential VM (about 10V) from Vcc at time t2. Then, the channels of the memory cells not selected for writing and the memory cells MC31, MC71, ... For performing "1" writing are in a floating state, so that V is due to capacitive coupling between the control gate and the channel.
It rises from cc (-Vth) to an intermediate potential (about 8V).
The channel of the memory cells MC31, MC71, ... In which "0" is written is 0V because the bit line is 0V.

After the channel of the memory cell in which the write unselection and the "1" write are performed is boosted from Vcc (-Vth) to the intermediate potential, the control gate CG1 is boosted from the intermediate potential VM to the write voltage Vpp (20V) at time t3. To do. Then, the memory cells in the memory cell units (1) (2) (4) that are not written and the memory cell M that is written "1"
Since the channels of C31, MC71, ... Have an intermediate potential (about 10 V) and the control gate CG1 is Vpp (about 20 V), these memory cells are not written, but the channels of the memory cells MC31, MC71 ,. Is 0
Since V and the control gate are Vpp (about 20 V), electrons are injected from the substrate to the floating gate and "0" writing is performed.

After the writing is completed, the control gate, the selection gate, and the bit line are sequentially discharged, and the writing operation is completed. Memory cells MC11 and M in the memory cell unit (1)
When writing C51, MC91, ..., Similarly, the channels of the memory cells of the memory cell units (2) (3) (4) are set to Vcc.
(Or Vcc-Vth) after charging, select gate SG1 is set to Vsg
l, SG2 are set to Vsgh, SG3 and SG4 are set to Vss, and the bit lines BL0A, BL2A, BL4A, ... Are set to Vcc or Vss to transfer data to the memory cells MC11, MC51, MC91 ,.

Memory cell M in the memory cell unit (2)
When writing C21, MC61, MC101, ... Similarly, after the channels of the memory cells of the memory cell units (1) (3) (4) are charged to Vcc (or Vcc-Vth), the selection gate S
G2 is Vsgl, SG1 is Vsgh, SG3 and SG4 are Vss
And setting the bit lines BL0A, BL2A, BL4A, ... To Vcc or Vss, the memory cells MC21, MC61, M
The data may be transferred to C101, ....

Memory cell M in the memory cell unit (4)
When writing C41, MC81, ... Similarly, the channels of the memory cells of the memory cell units (1) (2) (3) are set to Vcc.
(Or Vcc-Vth), the selection gate SG4 is set to Vsg
, SG3 is set to Vsgh, SG1 and SG2 are set to Vss, and the bit lines BL1A, BL3A, ... Are set to Vcc or Vss.
Data may be transferred to the memory cells MC41, MC81, ....

After the writing is completed, a write verify operation is performed to check whether the writing is sufficiently performed (FIG. 17). In the verify read of the memory cell unit (3), the select gate SG3 is set to Vsgl, SG1, in order to select only the memory cell unit (3) as in the read.
SG2 and SG4 become Vsgh. In the verify read, the bit line is discharged from the precharge potential, the bit line is recharged by the write data, and the rewrite data is latched in the sense amplifier by sensing the bit line potential. For details of sense amplifier operation during verify operation and bit line recharging, refer to (T.
Tanaka, et al., IEEE J. Solid-State Circuit, vol29, p
p.1366-1373,1994).

In the above embodiment, writing is simultaneously performed in 1/4 of the memory cells in the column direction.
That is, of the four memory cell units, only one memory cell unit performs writing simultaneously.

According to this embodiment, it is possible to write to two memory cell units out of four memory cell units almost at the same time. For example, the selection gate SG
1 and SG3 are both Vsgl (for example, 0V), SG2 and SG
If 4 is set to Vsgh, the memory cell units (1) and (3) can be written almost simultaneously. In this case, the selection gate S
The E-type selection MOS transistor having the gate electrodes G1 and SG3 is turned off, and the D-type selection MOS transistor is turned on. The write data of the memory cells MC31, MC71, ... Of the memory cell unit (3) is the bit line BL.
Transferred from 1A, BL3A, .... In other words, when "0" is written, the bit line and the channel of the memory cell to be written become 0 V, and when "1" is written, the bit line is V
cc, and the channel becomes floating at Vcc (-Vth). Similarly, the write data of the memory cells MC11, MC51, MC91, ... Of the memory cell unit (1) are transferred from the bit lines BL0A, BL2A, BL4A ,.

Similarly, for example, SG2 and SG4 are set to Vsgl.
, SG1 and SG3 are set to Vsgh, it is possible to write to the memory cell units (2) and (4) almost at the same time.
In this case, the bit lines BL1A, BL3A, BL5A, ... To the memory cells of the memory cell unit (4), and the bit lines BL0A, BL2A, to the memory cells of the memory cell unit (2).
Data is transferred from BL4A, ....

After the write operation, verify read is performed to check whether the write has been sufficiently performed. In the verify read operation of the above embodiment, the data of one memory cell is read using two bit lines. That is, 4
Data of one memory cell unit of one memory cell unit is read out almost simultaneously. Therefore, in the case of writing two memory cell units almost at the same time, the verify read operation is performed twice for each write operation. In the method of writing two memory cell units almost at the same time, since the verify read is performed for each memory cell unit, the total time for writing the two memory cell units is about Tpr + 2Tvfy (T
pr: write pulse width, Tvfy: one verify read time). On the other hand, in the method of writing one memory cell unit almost at the same time, the total time for writing data for two memory cell units is about 2 (Tpr +
Tvfy), the writing operation is faster in the method of writing the data in the two memory cell units almost at the same time.

In the above embodiment, a sense amplifier is connected for each bit line, but a so-called shared sense amplifier system in which one sense amplifier is connected to two bit lines (FIG. 18)
You may The timing charts for writing and reading in this case are almost the same as those in the above embodiment.

According to the present invention, among the selection MOS transistors sharing one selection gate, it is possible to generate conductive MOS transistors and non-conductive MOS transistors, and prepare four such select gates. This makes it possible to easily realize a selected memory cell and a non-selected memory cell within a memory cell having the same selection gate.

Therefore, the threshold voltage of the selection MOS transistor and the voltage applied to the selection gate are arbitrary. One of the selection MOS transistors connected in series to one end side of the memory cell has two kinds of threshold voltages Vtd1 and Vtd2 (Vtd1> Vtd2), and the voltages applied to the selection gates are Vsghd (Vsghd> Vtd1) and Vsgld. (Vtd1>
Vsgld> Vtd2), and the other selection MOS transistors connected in series are Vte1 and Vte2 (Vte1> V).
te2), and the voltage applied to this select gate is Vsghe (Vsghe> Vte1), Vsgle
(Vte1>Vsgle> Vte2), one of the selection MOS transistors connected in series to the other end side of the memory cell has two threshold voltages of Vts1 and Vts2 (Vts1> Vts2). The voltage applied to the gate is Vsg
hs (Vsghs> Vts1), Vsgls (Vts1>Vsgls> Vts
2), and the other selection MOS transistor connected in series has two threshold voltages of Vtp1 and Vtp2 (Vtp1> Vtp2), and the voltage applied to this selection gate is Vsghp (Vsghp> Vtp1). , Vsglp (Vtp1> Vsg
It is sufficient if there are two types of lp> Vtp2).

As in the above embodiment, Vtd1 = Vte1 = V
ts1 = Vtp1, Vtd2 = Vte2 = Vts2 = Vtp2, Vsg
hd = Vsghe = Vsghs = Vsghp, Vsgld = Vsgle = Vsgls
= Vsglp does not have to be set, and the way of setting the threshold voltage and the select gate applied voltage is highly arbitrary. For example, one select MO connected in series on one end side of the memory cell
There are two types of threshold voltage of the S transistor, 2.5V and 0.5V, the threshold voltage of the other selection MOS transistor is 1V and -2V, and one selection MOS connected in series at the other end side of the memory cell. Set the threshold voltage of the transistor to -1
V and -3V, the other threshold is 0.8V and-
As the two types of 2.5 V, the voltage applied to one of the two selection gates connected in series on one end side of the memory cell is Vsgh =
3V, Vsgl = 1.5V, the voltage applied to the other is Vsgh
= 2V, Vsgl = -0.5V, the voltage applied to one of the series-connected select gates on the other end side of the memory cell is Vsgh =
0V, Vsgl = -2V, the voltage applied to the other is Vsgh =
4V and Vsgl = -1V may be used.

The threshold voltages of the four selection MOS transistors connected to one NAND string may be substantially the same. For example, four selection Ms connected to a NAND string
The threshold voltage of the OS transistor is 0.8 V, this NA
The ND column and the selection MOS transistor share the gate electrode and are connected in series at one end of another adjacent NAND cell 2
One of the selection MOS transistors has a threshold voltage of 0.8V and 2V, the other threshold voltage of 0.8V and -1V,
The threshold voltages of the two selection MOS transistors connected in series on the other end side of the memory cell are 0.8V and -1V, NAN
The voltage applied to one of the two selection gates connected in series to one end of the D cell is Vsgh = 3V, Vsgl = 1.4V, and the voltage applied to the other is Vsgh = 3V, Vsgl = 0V, NAN
The voltages applied to the two selection gates connected in series on the other end side of the D cell may be Vsgh = 3V and Vsgl = 0V.
Of course, the threshold value of the select gate may be a positive value or a negative value, and the select gate applied voltage may be a negative voltage.

If Vsgh is made larger than Vcc, selection M
Since the conductance of the OS transistor increases (that is, the resistance decreases) and the cell current flowing through the NAND cell string increases during reading, the bit line discharge time is shortened, and as a result, read / write verify read speeds up. To be done. Vsgh may be boosted from Vcc by a booster circuit in the chip, for example.

The larger one of the threshold voltages of the selection MOS transistors may be set to a voltage higher than the power supply voltage Vcc (for example, 3.5V). In this case, a selection MOS having a threshold voltage at the time of reading or verify reading
In order to turn on the transistor, for example, a booster circuit inside the chip may be used to apply, for example, 4V to the select gate.

A method of changing the threshold voltage is to change the gate oxide film thickness of the selection MOS transistor by selecting M
It is conceivable to change the concentration of the channel-doped impurities in the OS transistor. Alternatively, the threshold voltage may be made different depending on whether the selected MOS transistor is channel-doped with impurities or not. The threshold voltage can also be changed by changing the channel length of the selection MOS transistor. That is, a transistor having a short channel length has a small threshold voltage due to the short channel effect, and thus may be an I-type transistor or a D-type transistor. Further, as a method of changing the gate oxide film thickness and the impurity concentration of the channel, another manufacturing process such as channel doping of the peripheral circuit may be used without introducing a new manufacturing process. In either method, it suffices to make a difference in the threshold voltage of the selection MOS transistors, and if there is a difference in the threshold voltage, a predetermined threshold voltage can be obtained by substrate bias or the like. [Third Embodiment] The D-type selection MOS transistor of FIG. 8 may be of the I-type. That is, the threshold value of the transistor labeled D-type in FIG. 8 may be set to 0.5 V, for example. E-type threshold is 2V, I-typ
For example, if the threshold value of e is 0.5 V, E-type is also I
-type turns on 3V, E-type turns off, but I
-type may be set to 1.5V as an on-voltage. The read operation and the write operation are almost the same as those in the second embodiment.

In order to set the lower threshold voltage (I-type) of the threshold voltage of the selection MOS transistor to, for example, 0.5 V, a method of reducing the substrate concentration can be considered. In an I-type transistor with a low substrate concentration, when a drain voltage is applied without applying a gate voltage, a depletion layer between the drain and the substrate spreads, and as a result, a depletion layer between the drain and the substrate and a depletion layer between the source and the substrate are formed. There is a problem of connection and dullness (punch through). I-t
In order to increase the punch-through breakdown voltage of the ype selection MOS transistor, the channel length L of the I-type selection MOS transistor may be increased. [Fourth Embodiment] Further, when writing is performed by setting the threshold value of the D-type selection MOS transistor to about -8 V in FIG. A writing method (without floating the channel) can be performed. For example, when writing to the memory cell MC31 of FIG.
1, SG2 is 0V, SG3 is 0V, SG4 is VM10 (1
0V), CG1 is Vpp, CG2-CG8 is VM10,
When writing "1", BL1A is set to VM8 (about 8V),
In the case of writing "0", it may be set to 0V. Then, the channel of the memory cell MC31 in which "1" is written is charged from the bit line BL1A to the intermediate potential (about 8V).

On the other hand, regarding the memory cell units (1), (2), and (4) in which writing is not performed at this time, the bit line BL1A is set in the writing memory cell MC31 as described in the second embodiment.
Before biasing the write potential from Vcc (-Vt) to the memory cell channel of the memory cell unit (1) (2) (4).
h). During writing, SG3 of the non-selected memory cell units (1) (2) (4) is turned off, so that the channel of the memory cell becomes floating, and as a result, the second embodiment
As described above, when the control gate is boosted to VM8 or Vpp, the channel of the memory cell becomes the write non-selection potential (VM8) due to the coupling with the control gate.
Writing "0" is prevented.

[0083]

As described above in detail, according to the present invention, both the one end side and the other end side of the memory cell unit share a contact with another memory cell unit, respectively,
It is connected to the second common signal line. Therefore, by using a bit line formed of low resistance poly-Si, Al or the like instead of the source line formed of the conventional high resistance n-type diffusion layer, the problem of source line floating can be solved. Therefore, random access can be speeded up.

Further, by appropriately selecting E type, I type and D type as the selection MOS transistors for connecting one end side and the other end side of the memory cell unit to the common signal line, a plurality of memory cell columns can be formed. Bit lines can be shared, the pitch between bit lines in the column direction can be relaxed, and a high-density memory cell structure can be realized.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a sub array according to a first embodiment.

FIG. 2 is a block diagram showing a configuration of a memory cell array according to the first embodiment.

FIG. 3 is a circuit diagram showing a configuration of a memory cell unit according to the first embodiment.

FIG. 4 is a circuit diagram showing a configuration of a memory cell unit according to the first embodiment.

FIG. 5 is a circuit diagram showing a configuration of a memory cell section according to the first embodiment.

FIG. 6 is a circuit diagram showing a configuration of a memory cell section according to the first embodiment.

FIG. 7 is a NAND-type EEPROM according to the second embodiment.
The block diagram which shows the structure of M.

FIG. 8 is a circuit diagram showing a memory cell array according to a second embodiment.

FIG. 9 is a circuit diagram showing a memory cell array according to a second embodiment.

FIG. 10 is a timing chart for explaining a data read operation according to the second embodiment.

FIG. 11 is a circuit diagram showing a bit line control circuit according to a second embodiment.

FIG. 12 is a circuit diagram showing a bit line control circuit according to a second embodiment.

FIG. 13 is a timing chart for explaining a data read operation according to the second embodiment.

FIG. 14 is a timing chart for explaining a data read operation according to the second embodiment.

FIG. 15 is a timing chart for explaining a data read operation according to the second embodiment.

FIG. 16 is a timing chart for explaining a data write operation according to the second embodiment.

FIG. 17 is a timing chart for explaining a write verify read operation according to the second embodiment.

FIG. 18 is a circuit diagram showing another example of the bit line control circuit according to the second embodiment.

FIG. 19 is a plan view and an equivalent circuit diagram showing a cell configuration of a conventional NAND type EEPROM.

FIG. 20 is a sectional view taken along the line AA ′ and BB ′ of FIG.

FIG. 21 is an equivalent circuit diagram of a memory cell array of a conventional NAND type EEPROM.

[Explanation of symbols]

1 ... Memory cell array 2. Sense amplifier circuit 3 ... Row decoder 4 column decoder 5 ... Address buffer 6 ... I / O sense amplifier 7 ... Data input / output buffer 8 ... Substrate potential control circuit

─────────────────────────────────────────────────── ─── Continuation of front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H01L 21/8247 G11C 16/04 H01L 27/115 H01L 29/788 H01L 29/792

Claims (14)

(57) [Claims] 1. A non-volatile memory cell and a first select transistor.
The threshold value of the
And a second select transistor having
And the first to fourth memory cell units sharing the word line.
And a first connected to these memory cell units
To a nonvolatile semiconductor memory device having a memory cell array comprising a third bit line, wherein the first memory cell unit and said first bit line
A first bit line connected between the second bit line and
From the first to the first selection transistor, the first selection
A transistor, the memory cell, and the first selection transistor
The transistor and the second selection transistor are connected in series.
To the second bit line, and the second memory cell unit is connected to the first bit line.
A first bit line connected between the second bit line and
From the first to the first selection transistor, the first selection
A transistor, the memory cell, and the second selection transistor
The transistor and the first selection transistor are connected in series.
To the second bit line, and the third memory cell unit is connected to the second bit line.
A second bit line connected between the third bit line and
From the first to the first selection transistor, the first selection
A transistor, the memory cell, and the second selection transistor
The transistor and the first selection transistor are connected in series.
To the third bit line, and the fourth memory cell unit is connected to the second bit line.
A second bit line connected between the third bit line and
From the first to the first selection transistor, the first selection
A transistor, the memory cell, and the first selection transistor
The transistor and the second selection transistor are connected in series.
To the third bit line . 2. The threshold value of the first select transistor is
A positive n-type MOS transistor, the second selection
The selection transistor is an n-type MOS transistor with a negative threshold.
Nonvolatile according to claim 1, characterized in that it is a transistor.
Semiconductor memory device. 3. The threshold value of the first select transistor is
A positive n-type MOS transistor, the second selection
The select transistor has a threshold value of the first select transistor.
N-type MOS transistor positive below the threshold
The nonvolatile semi-transistor according to claim 1, characterized in that
Conductor storage device. 4. A memory cell portion composed of one or a plurality of non-volatile memory cells, and one end side of the memory cell portion.
And two selection transistors connected in series to
Two selection transistors connected in series to the other end of the resell unit
Static and the memory cell unit consists of the non-volatile semiconductor memory device having a memory cell array arranged in a matrix, the two memory cell units connected in parallel a plurality of parallel-connected units are configured, One side of any parallel connection unit shares the word line and select line, and the other side has a contour.
The two parallel connection units that do not share the same connection share a contact and are connected to the first common signal line, and the other end side
Are connected to a second common signal line by sharing a contact between two parallel connection units that share a word line and a select line and do not share a contact at one end side, and each memory cell 4 select transistors in the unit
Three of them have the same threshold, the other one is
Have different thresholds and connect to the same common signal line
Within the four memory cell units
Three of the four select transistors connected are the same
A non-volatile semiconductor memory device having a certain threshold value and the other one having a threshold value different from the other threshold values . 5. Four selection transistors in the same memory cell unit
Four memos connected to a transistor or the same common signal line
Four selection switches connected to the same selection line in the resell unit
Of the transistors, three are n-type MOs with a positive threshold.
S-transistor, the other one is n with a negative threshold
Claim characterized by being a type MOS transistor
Item 5. The nonvolatile semiconductor memory device according to item 4. 6. Four select transistors in the same memory cell unit
Four memos connected to a transistor or the same common signal line
Four selection switches connected to the same selection line in the resell unit
Of the transistors, three are n-type MOs with a positive threshold.
It is an S-transistor, and the other one has a threshold value of the other three.
N-type MOS transistor that is lower than
5. The non-volatile semiconductor memory according to claim 4, wherein
apparatus. 7. When reading a memory cell portion in the memory cell unit, a first common signal line connected to one end side of the memory cell unit is set to a read potential and the other end side of the memory cell unit is connected. Ground the 2 common signal line
The nonvolatile semiconductor memory device according to claim 4, wherein the keep potential. 8. When writing to a memory cell portion in the memory cell unit, a first common signal line connected to one end side of the memory cell unit is connected to write data "i" (i =
5. The nonvolatile semiconductor memory device according to claim 4 , wherein the i write potential is set according to 0, 1, ..., N; 9. Four memos connected to the same common signal line.
The re-cell unit is the first, second, third and fourth memory cells
And a unit, when reading the memory cell of the first memory cell unit, each select transistor of the first memory cell unit in a conductive state, at least one respective selected bets <br/> transistor of the second memory cell units one is the non-conducting state, at least one of the selection transistors of the third memory cell unit is non-conductive, each of the fourth memory cell unit
At least one of a non-conductive state of the selection transistor, when reading the memory cell of the second memory cell unit, each selection transistor of the second memory cell unit in a conductive state, the selection of the first memory cell unit At least one of the bets <br/> transistor is non-conductive, each of the at least one is non-conductive, the fourth memory cell units of each selection transistor of the third memory cell units
At least one of a non-conductive state of the selection transistor, when reading the memory cell portion of the third memory cell unit, each selection transistor of the third memory cell unit in a conductive state, the selection of the first memory cell unit At least one of the bets <br/> transistor is non-conductive, each of the at least one is non-conductive, the fourth memory cell units of each selection transistor of the second memory cell units
At least one of a non-conductive state of the selection transistor, when reading the memory cell portion of the fourth memory cell unit, each selection transistor of the fourth memory cell unit in a conductive state, the selection of the first memory cell unit At least one of the bets <br/> transistor is non-conductive, each of the at least one is non-conductive, the third memory cell units of each selection transistor of the second memory cell units
At least one of the selection transistors has a non-conducting state, the gate electrode of one of the selected selection transistors,
5. The nonvolatile semiconductor memory device according to claim 4, further comprising means for applying a read selection gate voltage. 10. Four memories connected to the same common signal line.
The memory cell unit is connected to the first, second, third and fourth memory cells.
When the memory cell portion of the first memory cell unit is written, the two selection transistors on one end side of the first memory cell unit are both turned on and the two selection transistors on the other end side are selected. /> At least one of the transistors is turned off, and the second
Of at least one of the two selection transistors <br/> other end side of the memory cell unit to a non-conducting state, and the non-conductive state at least one of the two select transistors at one end of the third memory cell units, the at least one of the two select transistors at one end of the fourth memory cell unit to a non-conductive state, when writing the memory cell of the second memory cell unit has two selection at one end of the second memory cell units < both of the transistors are made conductive, and at least one of the two selection transistors on the other end side is made non-conductive;
Of at least one of the two selection transistors <br/> other end side of the memory cell unit to a non-conducting state, and the non-conductive state at least one of the two select transistors at one end of the third memory cell units, the At least one of the two selection transistors on the one end side of the memory cell unit 4 of FIG. 4 is made non-conductive, and when the memory cell portion of the third memory cell unit is written, the two selection transistors on the other end side of the third memory cell unit are selected. Both transistors are made conductive, and at least one of the two selection transistors on one end side is made non-conductive, the first
Of at least one of the two selection transistors <br/> other end side of the memory cell unit to a non-conducting state, at least one of the two select transistors in the other end of the second memory cell unit to a non-conductive state , At least one of the two selection transistors on the other end side of the fourth memory cell unit is made non-conductive, and when writing the memory cell part of the fourth memory cell unit, the other end side of the fourth memory cell unit The two selection transistors are both turned on, and at least one of the two selection transistors on the one end side is turned off,
Of at least one of the two selection transistors <br/> other end side of the memory cell unit to a non-conducting state, at least one of the two select transistors in the other end of the second memory cell unit to a non-conductive state A means for applying a write selection gate voltage to any one of the selected selection transistors so that at least one of the two selection transistors on the other end side of the third memory cell unit is made non-conductive. The non-volatile semiconductor memory device according to claim 4 . Wherein said memory cell section, a nonvolatile semiconductor memory device according to claim 1 or 4 further characterized in that is composed of electrically rewritable nonvolatile memory cells. 12. The non-volatile memory cell includes a charge storage layer and a control gate stacked on a semiconductor layer, and a plurality of memory cells adjacent to each other are connected in series so as to share a source and a drain. 12. The non-volatile semiconductor memory device according to claim 11, which constitutes a memory cell section. 13. The non-volatile memory cell, wherein a charge storage layer and a control gate are stacked on a semiconductor layer, and one or a plurality of memory cells are connected in parallel so that all of them share a source and a drain. 12. The non-volatile semiconductor memory device according to claim 11, which constitutes a memory cell section. 14. By varying the impurity concentration of the channel, the non-volatile semiconductor memory device according to claim 1 or 4, wherein varying the threshold voltage of the selection transistor.