JP3532659B2 - Nonvolatile semiconductor memory device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device.

[0002]

2. Description of the Related Art In recent years, a NAND cell type EEPROM has been proposed as one of electrically rewritable non-volatile semiconductor devices (EEPROMs). This EEPROM
Is, for example, a plurality of memory cells having an n-channel FETMOS structure in which a floating gate and a control gate as a charge storage layer are stacked, connected in series such that their sources and drains are shared by adjacent ones. It is connected to the bit line as a unit.

38A and 38B are a plan view and an equivalent circuit diagram of one NAND cell portion of the memory cell array. FIGS. 39 (a) and 39 (b) respectively show A of FIG. 38 (a).
FIG. 6 is a cross-sectional view taken along line A-A 'and line BB'.

A memory cell array composed of a plurality of NAND cells is formed on a p-type silicon substrate (or p-type well) 11 surrounded by an element isolation oxide film 12. One N
Explaining by focusing on the AND cell, in this embodiment, 8
Memory cells M1 to M8 are connected in series to form one NA
It constitutes an ND cell. Each memory cell has a floating gate 14 on a substrate 11 via a tunnel insulating film 13.
(14 ₁ , 14 _{2 to} 14 ₈ ) are formed, and the control gate 16 (16 ₁ , 16 ₂ ) is formed thereon with the gate insulating film 15 interposed therebetween.
˜16 ₈ ) are formed and configured. The n-type diffusion layers 19 which are the sources and drains of these memory cells are connected in such a manner that adjacent ones are shared by each other, whereby a plurality of memory cells are connected in series.

First selection gates 14 ₉ and 16 ₉ and second selection gates 14 ₁₀ and 16 ₁₀ formed simultaneously with the floating gate and control gate of the memory cell are provided on the drain side and the source side of the NAND cell, respectively. It is provided. The substrate on which the elements are formed is covered with the CVD oxide film 17, and the bit line 18 is disposed on the CVD oxide film 17. The control gates 14 of the NAND cells are commonly arranged as control gates CG1 and CG2 to CG8. These control gate lines become word lines. The select gates 14 ₉ , 16 ₉ and 14 ₁₀ , 16 ₁₀ are also arranged continuously in the row direction as select gates SG1, SG2.

FIG. 40 shows an equivalent circuit of a memory cell array in which such NAND cells are arranged in a matrix. The source line is connected to a reference potential wiring such as Al or poly-Si via a contact at one location for every 64 bit lines, for example. This reference potential wiring is connected to the peripheral circuit. The control gate of the memory cell and the first and second selection gates are continuously arranged in the row direction. Usually, a set of memory cells connected to a control gate is called one page, and a set of pages sandwiched by a set of drain-side (first select gate) and source-side (second select gate) select gates is one NAND. It is called a block or simply one block.

The operation of the NAND cell type EEPROM is as follows. Data writing is performed in order from the memory cell farther from the bit line. A boosted write voltage Vpp (= about 20V) is applied to the control gate of the selected memory cell, and an intermediate potential (about 10V) is applied to the control gates of the other non-selected memory cells and the first select gate. Then, 0 V (“0” write) or an intermediate potential (“1” write) is applied to the bit line according to the data. At this time, the potential of the bit line is transmitted to the selected memory cell.
When the data is "0", a high voltage is applied between the floating gate of the selected memory cell and the substrate, and electrons are tunnel-injected from the substrate to the floating gate to shift the threshold voltage in the positive direction. When the data is "1", the threshold voltage does not change.

Data erasing is performed in block units at substantially the same time. That is, all the control gates and select gates of the block to be erased are set to 0V, and the boosted potential VppE (about 20V) is applied to the p-type well and the n-type substrate.
VppE is also applied to the control gate and select gate of the block that is not erased. As a result, in the memory cell of the block to be erased, electrons in the floating gate are emitted to the well, and the threshold voltage moves in the negative direction.

In the data read operation, the control gate of the selected memory cell is set to 0V and the control gates of the other memory cells are set to the power supply voltage Vcc (for example, 3V) to detect whether or not a current flows in the selected memory cell. It is done by doing. In the NAND cell type EEPROM, since a plurality of memory cells are connected in cascade, the cell current during reading is small. Further, since the control gate of the memory cell and the first and second selection gates are continuously arranged in the row direction, data for one page can be simultaneously read out to the bit line.

However, this type of device has the following problems.

(Problem 1) NAND cell type EEPROM
Then, the control gates of the memory cells selected at the time of data reading are 0V, and the control gates of the other memory cells are VV.
Whether or not the cell current Icell flows is detected as cc (for example, 3V). The magnitude of the cell current is not limited to the threshold voltage of the cell to be read, but the threshold values of all the remaining cells connected in series. It also depends on the voltage. Considering the case where eight memory cells are connected in series to form one NAND cell, Icell (Best) when Icell is the largest (when the resistance is the smallest) is calculated from the eight cells connected in series. This is a case where all the threshold voltages are negative (“1” state). When reading "1", if Icell is the smallest (if the resistance is the largest), Icell (Worst) indicates that the threshold voltage of all other cells connected in series to the cell to be read is positive ("0"). This is a case where the memory cell (for example, MC1 in FIG. 40) on the side of the first bit line contact is read as "1" in the "state".

The cell current flows from the bit line to the source line through the memory cell, but in the conventional memory cell array, the source line is shared by the NAND cells for one page to be read simultaneously (FIG. 40). When the memory cell farthest from the contact between the source line and the reference potential wiring (memory cell MC1 in FIG. 40) is read, the threshold voltage of the other seven cells connected in series to the memory cell MC1 is positive (that is, the cell current Is the minimum Icell (Worst)), and the resistance of the other NAND string sharing the source line is the minimum (that is, the maximum cell current Ic
Consider the case of ell (Best)). In this case, since the cell current flows from the NAND string having a small resistance in the initial reading and the resistance of the source line is large, the potential of the source line of the NAND cell to which the memory cell MC1 belongs is I × R (I: Flowing cell current, R: resistance of source line).

That is, a NAND including the memory cell MC1
Since the source of the memory cell in the column floats from the ground potential Vss, the source-drain voltage and the source-gate voltage of the memory cell decrease, and the floating source also causes a substrate bias effect, which causes the memory cell to lose its potential. Since the threshold value increases, the conductance of the memory cell in the NAND cell string including MC1 decreases. As described above, when the resistance of the source line is large, the source line floats from the ground potential, so that the cell current is further difficult to flow in the NAND string having a small cell current.

If the bit line capacitance is CB and the threshold voltage of the memory cell is negative (that is, "1" state), the bit line potential must be lowered from the precharge potential by .DELTA.VB in order to read. The maximum value of the bit line discharge time TRWL is determined when the cell current is the smallest, but when the source line does not float, TRWL = CB / Icell (Worst). Since the line floats, the TRWL becomes longer, and the random access time becomes longer. Further, in the conventional NAND cell type EEPROM, if only one source line / reference potential line contact is provided for every 16 lines in order to reduce the floating of the source line, there is a problem that the area of the memory cell increases.

The increase in the bit line discharge time due to the floating of the source line not only lengthens the read time but also causes the variation in the threshold value written in the memory cell.

FIG. 42 shows the bit line discharge time at the time of verify read after "0" is written in the memory cell MCC1 of FIG. 43 (the threshold value of the memory cell is changed from a negative value to a positive value). The threshold dependence of MCC1 is shown. The write and verify read operations will be described with reference to a known example (Japanese Patent Laid-Open No. 3-343363). In the verify read of the memory cell MCC1 of FIG. 43, the other memory cells MCC2, MCC3, MCC4, MCC5 ... Of the same page are “0” as shown in FIG.
A large cell current flows due to insufficient programming (that is, it has a negative threshold value instead of a positive threshold value), and as a result, the source line floats and the bit line discharge time becomes longer as shown in FIG.

As a result, in the verify read, if the bit line discharge time is TBL1 or more, "0" is written in the memory cell.
If written, the memory cell MCC1 of FIG.
Then, since the source line floats, it is determined that "0" is written when the threshold value of the memory cell is Vth1 or more in FIG. On the other hand, when the cell current is large and the source line does not float like the memory cell MCD1 in FIG. 44, the bit line discharge time is as shown in FIG. That is, when writing to the memory cell MCD1, it is determined that "0" has been written at the threshold value Vth1 or more in FIG.

As described above, in the memory cell MCC1 and the memory cell MCD1, the variation in the threshold voltage is Vthd1−
There is a problem that only Vth1 occurs. If the bit line discharge time can be shortened by eliminating the floating of the source line and the bit line discharge time of the memory cell MCC1 can be set as shown in, for example, FIG. Vthd1−Vth2) of 42.

The memory cell MCC1 of FIG. 43 is written by the first write pulse, and after the threshold value reaches Vth1 (FIG. 45), the memory cell MCC2 of FIG. 43 is written by the second and subsequent write pulses. , MC
It is assumed that C3, MCC4, MCC5 ... Are in the "0" state. Since the writing to the memory cell MCC1 is completed by the first writing pulse, the memory cell MCC1 is not written by the second and subsequent writing pulses, and the threshold value remains Vth1.

As a result, the memory cells MCC1, MCC
2, when the memory cell MCC1 is read after the writing of the pages of MCC3, ...
Since no cell current flows through CC3, MCC4, MCC5 ..., When reading the memory cell MCC1, the source line does not float, and the bit line discharge time is shortened by ΔT as shown in FIG. 45, and "1" is read. there is a possibility. That is,
Since the data of the memory cells MCC2, MCC3, MCC4, ... Of the same page of the memory cell MCC1 have changed by the second and subsequent write pulses after the writing of the memory cell MCC1, the data of the memory cell MCC1 which should have been written "0" is "1". There is a problem that it is read when it is ". This erroneous reading occurs because when reading a memory cell, the data of another memory cell via the source line affects the read current of the memory cell to be read.

(Problem 2) Conventional NAND cell type EEP
In the ROM, the contacts between the select gates on the drain side and the bit lines are arranged adjacent to each other as shown in FIG. Figure 41
(A) is a contact (hereinafter referred to as a bit line contact) for connecting the n-type diffusion layer of the conventional memory cell array and the source / gate / drain regions of the memory cell and the n-type diffusion layer and the bit line (Al or the like), that is, The element region is shown. 41A shows the element isolation region between the memory cells except the hatched portion. NAND in the Y direction of FIG.
The cells are arranged in series. In the X direction of FIG. 40, the n-type diffusion layer (source line) and the memory cell array-
The bit line contacts are arranged. L'is a distance between bit line contacts, L is an element isolation width between memory cells, and W is a channel width of a memory cell transistor.

In the conventional NAND cell array, even if the width of the element isolation region between memory cells is reduced, the bit line contacts are arranged adjacent to each other as shown in FIG. The pitch of the memory cells in the direction (X direction) cannot be reduced. That is, since the size in the X direction is determined by the bit line contact distance L ′,
The element isolation width L between the memory cell arrays is equal to that of the adjacent NAN.
There is a problem that the field inversion breakdown voltage between the D cell columns becomes larger than the minimum element isolation width L0 determined by the element isolation technique, etc., and as a result, the area of the memory cell array increases.

Further, as shown in FIG. 41 (b), the margin l between the contact and the element region must be reduced by reducing the pitch of the memory cell. However, if l is made small, there is a problem in that the contact is misaligned on the element isolation due to misalignment, and the bit line and the well or substrate in which the memory cell is formed are short-circuited.

[0024]

As described above, the conventional EE
In the PROM, when the resistance of the source line is large, the source line floats from the ground potential, so that the bit line discharge time becomes long and the random access time becomes long. Further, in order to reduce the floating of the source line, for example, if only one out of every 16 lines is provided between the source line and the reference potential line, there is a problem that the area of the memory cell increases.

Further, since the bit line contacts are arranged adjacent to each other, the pitch of the memory cells in the column direction cannot be reduced. Further, the alignment margin between the contact and the element region must be reduced by reducing the pitch of the memory cell. However, if this margin is reduced, the contact is misaligned due to misalignment and the bit line and the memory cell are formed. There is a problem that the well or the substrate to be short-circuited.

The present invention has been made in view of the above problems, and an object thereof is to reduce the resistance of the source line and reduce the floating of the source line without increasing the chip area. A non-volatile semiconductor memory device capable of speeding up random access is provided.

Another object of the present invention is to provide adjacent NAs.
An object of the present invention is to provide a non-volatile semiconductor memory device which can reduce the pitch of memory cells in the column direction by shifting the positions of the bit line contacts in the ND column and can realize a high density memory cell structure.

[0028]

In order to solve the above problems, the present invention employs the following configurations.

That is, according to the present invention, a memory cell portion composed of one or a plurality of non-volatile memory cells and zero, one or a plurality of selection MOS transistors for electrically connecting the memory cell portion to a common signal line. In a non-volatile semiconductor memory device having a memory cell array in which memory cell units composed of and are arranged in a matrix, (1) one end side of the memory cell unit is a plurality of memory cell units sharing a word line. The memory cell unit is connected to the first common signal line by sharing the contact, and the other end of the memory cell unit is connected to the second common signal line by sharing the contact among a plurality of memory cell units sharing the word line. It is characterized by being done.

(2) One end side of the memory cell unit is connected to the first common signal line by sharing a contact among a plurality of memory cell units sharing a word line,
The other end side of the memory cell unit shares a word line,
In addition, one or a plurality of memory cell units that do not share a contact with one end side of the memory cell unit are connected to the second common signal line sharing a contact.

(3) One end of the memory cell unit is connected to the first common signal line by sharing a contact among a plurality of memory cell units sharing a word line,
The other end side of the memory cell unit shares a word line,
In addition, one or a plurality of memory cell units that share a contact with one end of the memory cell unit are connected to the second common signal line sharing a contact.

(4) One end of the memory cell unit is connected to the first common signal line by sharing a contact among a plurality of memory cell units sharing a word line,
The other end of the memory cell unit has one or more memory cell units that share a word line and do not share a contact with one end of the memory cell unit, and a contact with one end of the memory cell unit. One or a plurality of shared memory cell units share a contact and are connected to the second common signal line.

The preferred embodiments of the present invention include the following in addition to those described in the dependent forms in the claims.

(1) The read non-selection potential is the ground potential.

(2) The write non-selection potential is the power supply voltage or the on-chip power supply voltage.

(3) The non-selection gate voltage is a negative voltage.

(4) The memory cell section is composed of electrically rewritable nonvolatile memory cells.

(5) In the non-volatile memory cell, a charge storage layer and a control gate are laminated and formed on a semiconductor layer, and a plurality of memory cells adjacent to each other are connected in series so as to share a source and a drain. thing.

(6) In the non-volatile memory cell, a charge storage layer and a control gate are laminated on a semiconductor layer, and one or a plurality of memory cells are all connected in parallel so as to share a source and a drain. thing.

(7) Make the impurity concentration of the channel the same,
Alternatively, the threshold voltages of the first to ninth selection MOS transistors are made the same or changed by changing them.

[0041]

According to the present invention, both the one end side and the other end side of the memory cell unit share contacts with other memory cell units and are connected to the first and second common signal lines, respectively. By using the bit line formed of low resistance Al or the like instead of the source line formed of the conventional high resistance n-type diffusion layer, the problem of floating of the source line can be solved. Therefore, the resistance of the source line can be reduced to reduce the floating of the source line, and as a result, random access can be speeded up.

Further, by appropriately selecting E type or I type as the selection MOS transistors for connecting the one end side and the other end side of the memory cell unit to the common signal line, the high speed operation can be achieved without increasing the chip area. The above memory cell array capable of random access can be realized.
Furthermore, by shifting the positions of the bit line contacts in the adjacent NAND strings, the pitch of the memory cells in the column direction can be reduced, and a high-density memory cell structure can be realized.

[0043]

Embodiments of the present invention will be described below with reference to the drawings.

(Embodiment 1) FIG. 1 shows the N according to this embodiment.
It is a block diagram showing a configuration of an AND cell type EEPROM. In the figure, reference numeral 1 denotes a memory cell array as a memory means, which is an open bit line system, and therefore the memory cell array is divided into 1A and 1B. Reference numeral 2 is a sense amplifier circuit as a latch means for writing and reading data. Reference numeral 3 is a row decoder for selecting a word line, 4 is a column decoder for selecting a bit line, 5 is an address buffer, 6 is an I / O sense amplifier, 7 is a data input / output buffer, and 8 is a substrate potential control circuit.

FIG. 2 is a diagram showing the array structure of the memory cell array 1A, and FIG. 3 is a diagram showing the array structure of the memory cell array 1B. In the memory cell array (FIGS. 2 and 3) according to this embodiment, the source side select gate (second select gate) is connected to the source line of the n-type diffusion layer as in the conventional memory cell array (FIG. 40). Instead, it is in contact with the bit line. Further, one bit line contact is shared by two NAND cell columns in the conventional memory cell, but is shared by four NAND cell columns in the memory cell array of the present embodiment, so that the entire memory cell array is shared. The number of bit line contacts does not increase from the conventional memory cell array.

A plurality of memory cell units (NAN
A sub-array composed of D cells) is a memory cell unit in which the selection MOS transistor STn1 on one end side is an I type and the selection MOS transistor STn2 on the other end side is an E type.
(1) and a memory cell unit (2) in which the selection MOS transistor STn1 on one end side is an E type and the selection MOS transistor STn2 on the other end side is an I type are arranged alternately in the word line direction. There is.

FIG. 4 shows a contact (bit line contact) for connecting the n-type diffusion layer of the memory cell of the present embodiment, the source / gate / drain regions of the memory cell, and the n-type diffusion layer and the bit line (Al, etc.). The element region is shown. As described above, in the conventional memory cell array, since the bit line contacts of the adjacent bit lines are arranged adjacent to each other as shown in FIG. 41, it is difficult to reduce the size in the column direction (X direction in FIG. 41). There is.

On the other hand, in the memory cell array of this embodiment, the bit line contacts of the adjacent bit lines are not arranged adjacent to each other as shown in FIG. The size of the region does not pose a problem in reducing the column direction (X direction) of the memory cell array, and the isolation width between the memory cells is determined by the field inversion breakdown voltage between adjacent NAND cell columns and the element isolation. The width can be reduced to the minimum element isolation region width L0 determined by the technology. Further, as in the conventional case, the number of selection MOS transistors is two per NAND string, so that the area does not increase due to the increase in the number of selection MOS transistors.

In the memory cell array of this embodiment, two selection MOSs connecting one NAND cell column and bit line are connected.
The threshold voltage of the transistor is Vth1, Vth2 (Vth1
> Vth2). High threshold voltage Vth
A selection MOS transistor having 1 (for example, 2V) is referred to as an E type, and a selection MOS transistor having a low threshold voltage Vth2 (for example, 0.5V) is referred to as an I type. The voltage applied to the select gate is a voltage Vsgh (for example, 3V) (Vsgh) at which both I-type and E-type transistors are turned on.
> Vt1, Vt2), and a voltage Vsgl (for example, 1.5 V) (Vt1>Vsgl> Vt2) that turns on the I-type transistor but turns off the E-type transistor.

As described above, two kinds of threshold voltages of the selection MOS transistor are provided and two kinds of voltages are applied to the selection gate, so that one of the adjacent NAND cell columns serves as a bit line at the time of writing or reading. Continuity,
The other can be non-conducting.

A specific reading and writing method will be described with reference to FIG.

<Read> When the data of the memory cells MC11, MC31, MC51 ... In the memory cell unit (1) is read to the bit lines BL1A, BL3A, BL5A ..., First, the bit lines BL1A, BL3A, BL5A ... The line read potential VA (for example, 1.8V) is precharged, and BL0A, BL2A, BL4A, BL6A ... Are grounded to 0V. After precharging, bit line BL1A,
BL3A, BL5A ... Are made floating.

Next, the control gate CG1 is 0V, and CG2-
CG8 is set to Vcc (for example, 3V). The selection gate SG1 is set to Vsgl and the selection gate SG2 is set to Vsgh.
The other select gates and control gates are set to 0V. In this case, the selection MOS transistors (ST02, ST12, ST22, ...) Connected to the bit lines BL0A, BL2A, BL4A ...
ST32, ST42, ST52 ...) are turned on. On the other hand, the I type selection MOS transistors ST11, ST31, ST51, ... Connected to the bit lines BL1A, BL3A, BL5A ...
21, ST41 ... turn off.

Therefore, the memory cells MC11, MC31, MC
If the data written in 51 ... Is "1", the precharged bit lines BL1A, BL3A, BL5A ... Are discharged to the grounded bit lines BL2A, BL4A, BL6A .. Memory cells MC11, MC31, MC51 in the unit (1) ...
Data is read out to the bit lines BL1A, BL3A, BL5A .... On the other hand, if the data written in the memory cell is "0", the bit lines BL1A, BL3A, BL5A
... does not discharge and maintains the precharge potential.

On the other hand, for the memory cells MC01, MC21, MC41 ... In the memory cell unit (2), the bit line B
Since the E type selection MOS transistors ST01, ST21, ST41 ... Connected to L1A, BL3A, BL5A ... Are turned off, the data of the memory cells MC01, MC21, MC41 ... Are not read to the bit lines BL1A, BL3A, BL5A.

Next, the data of the memory cells MC01, MC21, MC41 ... In the memory cell unit (2) are transferred to the bit line BL.
Consider the case of reading to 0A, BL2A, BL4A, BL6A .... First, bit lines BL0A, BL2A, BL4
A, BL6A ... Are precharged to the bit line read potential VA (for example, 1.8 V), and BL1A, BL3A, B are precharged.
Ground L5A ... to 0V. After precharging, the bit lines BL0A, BL2A, BL4A, BL6A ... Are made floating.

Next, the control gate CG1 is set to 0V, CG2
CG8 is set to Vcc (for example, 3V). Then, the selection gate SG1 is set to Vsgh and the selection gate SG2 is set to Vsgl.
The other select gates and control gates are set to 0V. In this case, the selection MOS transistors (ST01, ST11, ST21, ...) Connected to the bit lines BL1A, BL3A, BL5A ...
ST31, ST41, ST51 ...) are turned on. On the other hand, I type selection MOS transistors ST02, ST22, S connected to the bit lines BL0A, BL2A, BL4A, BL6A ...
T42 ... Turns on, but E type selection MOS transistors ST12, ST32, ST52 ... Turn off.

Therefore, if the data written in the memory cells MC01, MC21, MC41 ... In the memory cell unit (2) is "1", the precharged bit line BL0A,
BL2A, BL4A, BL6A ... are the grounded bit lines B
By discharging to L1A, BL3A, BL5A ... And dropping from the precharge potential, memory cells MC01, MC
21 and MC41 ... The data of bit lines BL0A, BL2A,
Read to BL4A ... On the other hand, if the data written in the memory cell is "0", the bit lines BL0A, BL
2A, BL4A ... Do not discharge and maintain the precharge potential.

On the other hand, regarding the memory cells MC11, MC31, MC51, ... In the memory cell unit (1), the bit line B
Since the E type selection MOS transistors ST12, ST32, ST52, ... Connected to L2A, BL4A, BL6A ... Are turned off, the data of the memory cells MC11, MC31, MC51 ... Are not read to the bit lines BL0A, BL2A, BL4A.

As described above, in the embodiment, the source line (n-type diffusion layer) of the conventional memory cell array is eliminated, and half of the bit lines are grounded at the time of reading to perform the same role as the conventional source line, and the rest. The data of the memory cell is read to half of the bit lines. By using the bit line formed of low resistance Al or the like instead of the source line formed of the conventional high resistance n-type diffusion layer, the problem of floating of the source line can be solved.

Now, the read operation will be described in more detail with reference to a timing chart.

FIG. 5 is a timing chart for reading the data written in the memory cells MC11, MC31, MC51 ... In the memory cell unit (1) of FIG.

Bit lines BL0A, BL2A, BL4A,
BL6A ... Are connected to the sense amplifier SA1 of FIG. 6, and the bit lines BL1A, BL3A, BL5A ... Are connected to the sense amplifier SA2 of FIG. The sense amplifier has a control signal φP,
It is formed of a CMOS flip-flop controlled by φN.

First, the precharge signals PRA1, PRA2,
PRB2 changes from Vss to Vcc (time t0), and bit line B
L1A, BL3A, BL5A ... Are VA2 (eg 1.7.
V), and the (dummy) bit lines BL1B, BL3B,
BL5B ... Are precharged to VB2 (for example, 1.5V) (time t1). VA1 is 0V and bit line BL0
A, BL2A, BL4A, BL6A ... Are grounded.

When the precharge is completed, PRA2 and PRB2 become Vss, and the bit lines BL1A, BL3A, BL5A ...
Becomes floating. After this, the row decoder 3
Then, a desired voltage is applied to the selection gate and the control gate (time t2). Control gate CG1 is 0V, CG2-CG
8 is Vcc (for example, 3V), SG2 is 3V (Vsgh), S
G1 becomes 1.5V (Vsgl).

Memory cell M in the memory cell unit (1)
The data written in C11, MC31, MC51 ... Is "0".
In this case, since the threshold voltage of the memory cell is positive, no cell current flows, and the potentials of the bit lines BL1A, BL3A, BL5A ... Remain at 1.7V. When the data is "1", cell current flows and bit lines BL1A, BL3A, B
The potential of L5A ... falls to 1.5V or less. Also, since the selection gate SG1 is 1.5V, it is an E type selection MOS.
The transistors ST01, ST21, ST41 are turned off, and the memory cells MC01, MC21,
The data of MC41 ... Is not transferred to the bit line. During this period, the (dummy) bit lines BL1B, BL3B, BL5B ... Are kept at the precharge potential of 1.5V.

After that, at time t3, φP is 3V and φN is 0V.
V, the CMOS flip-flop FF is inactivated, and φE becomes 3V at time t4, so that C of SA2
The MOS flip-flop FF is equalized and the nodes N1 and N2 become Vcc / 2 (for example, 1.5 V). At time t5, SS2, SA and SB become 3V, and after the bit line and the sense amplifier are connected, φN changes from 0V to 3V, φP
Changes from 3V to 0V and bit lines BL1A, BL3A, B
The potential difference between L5A ... And the bit lines BL1B, BL3B, BL5B ... Is amplified (time t6).

That is, the memory cells MC11, MC31, MC
If "0" is written in 51 ..., node N of SA2
1 becomes 3V, node N2 becomes 0V, and memory cell MC1
If "1" is written in 1, MC31, MC51 ...
The node N1 becomes 0V and the node N2 becomes 3V. afterwards,
When the column selection signal CSL changes from 0V to 3V, CMO
The data latched in the S flip-flop is IO,
/ IO (time t7).

Through the read operation, the bit lines BL0A,
BL2A, BL4A, BL6A ... Are grounded to 0V. That is, every other bit line is grounded. Therefore, the distance between the read bit lines is twice as large as that when the bit lines are not grounded, and the noise due to the capacitive coupling between the bit lines is significantly reduced (Japanese Patent Application No. 4-276393). Also, PRB1 is set to Vcc, VB1
The bit lines BL0B and BL2B
, BL4B, BL6B ... May be grounded. As a result, it is possible to reduce capacitive coupling noise between bit lines during amplification of the bit line potential.

FIG. 8 is a timing chart for reading data written in the memory cells MC01, MC21, MC41, MC61 ... In the memory cell unit (2) of FIG.

First, the precharge signals PRA1, PRA2,
PRB1 changes from Vss to Vcc (time t0), and bit line B
L0A, BL2A, BL4A ... Are VA1 (eg 1.7.
V), and the (dummy) bit lines BL0B, BL2B,
BL4B ... Are precharged to VB1 (for example, 1.5V) (time t1). VA2 is 0V and bit line BL1
A, BL3A, BL5A ... Are grounded.

When the precharge is completed, PRA1 and PRB1 become Vss, and the bit lines BL0A, BL2A, BL4A ...
Becomes floating. After this, the row decoder 3
Then, a desired voltage is applied to the selection gate and the control gate (time t2). Control gate CG1 is 0V, CG2-CG
8 is Vcc (for example, 3V), SG1 is 3V (Vsgh), S
G2 becomes 1.5V (Vsgl).

When the data written in the memory cells MC01, MC21, MC41 ... Is "0", the threshold voltage of the memory cell is positive, so that no cell current flows and the bit line BL0
The potentials of A, BL2A, BL4A ... Remain at 1.7V. When the data is "1", the cell current flows and the potentials of the bit lines BL0A, BL2A, BL4A ...
It becomes 1.5V or less. Further, the selection gate SG2 is 1.5
Since it is V, E type selection MOS transistor ST12, S
T32 and ST52 are turned off, and the data in the memory cells MC11, MC31, MC51 ... In the memory cell unit (1) are not transferred to the bit lines. During this period (dummy) bit line BL0
B, BL2B, BL4B ... are precharge potential 1.5V
Kept in.

Thereafter, at time t3, φP is 3V and φN is 0.
V, the CMOS flip-flop FF is inactivated, and φE becomes 3V at time t4, so that C of SA1
The MOS flip-flop FF is equalized and the nodes N1 and N2 become Vcc / 2 (for example, 1.5 V). At time t5, SS1, SA, SB become 3V, and after the bit line and the sense amplifier are connected, φN changes from 0V to 3V, φP
Changes from 3V to 0V and bit lines BL0A, BL2A, B
L4A ... And bit lines BL0B, BL2B, BL4B ...
The potential difference is amplified (time t6).

That is, the memory cells MC01, MC21, MC
If "0" is written in 41 ..., Node N of SA1
1 becomes 3V, node N2 becomes 0V, and memory cell MC0
If "1" is written in 1, MC21, MC41 ...
The node N1 becomes 0V and the node N2 becomes 3V. afterwards,
When the column selection signal CSL changes from 0V to 3V, CMO
The data latched in the S flip-flop is IO,
/ IO (time t7).

Through the read operation, BL1A, BL3A
, BL5A ... Are grounded to 0V, so that noise due to capacitive coupling between bit lines is reduced.

The timing of the read operation is arbitrary. For example, as shown in FIG. 9, at time t5, the transfer gate connecting the bit line and the sense amplifier is turned on to set the potentials of the bit line and the dummy bit line to the node N of the sense amplifier.
The transfer gate may be turned off after the transfer to 1, N2. In this case, since the bit line and the dummy bit line are separated from the sense amplifier, the load capacitance of the sense amplifier is reduced, and the nodes N1 and N1 are sensed during sensing and data latching.
The potential of N2 will be determined rapidly.

In the above embodiment, for example, the memory cell MC1
Bit line BL1A when reading 1, MC31, MC51 ...
, BL3A, BL5A ... Precharge, bit line B
L0A, BL2A, BL4A ... Are grounded, and the data of the memory cells are read to the bit lines BL1A, BL3A, BL5A. Which of the bit lines connected to both ends of the memory cell unit is used to read data is arbitrary. For example, when reading the memory cells MC11, MC31, MC51 ..., Bit lines BL2A, BL4A, BL6A.
Precharge, bit lines BL1A, BL3A, BL5
A ... is grounded and the data in the memory cell is transferred to the bit line BL2.
You may read in A, BL4A, BL6A ...

<Write> The write operation of this embodiment will be described below.

A writing procedure for writing to the memory cells MC11, MC31, MC51 ... In the memory cell unit (1) of FIG. 2 will be described below.

The selection gate SG2 is set to 0V, and all the selection MOS transistors having the selection gate SG2 as a gate electrode are turned off. SG1, CG1 to CG8 are set to Vcc, bit lines BL1A, BL3A, BL5A ... Are set to Vcc, and the channel of the page to be written is set to Vcc-Vth (select MO.
It becomes smaller than the bit line potential Vcc due to the threshold voltage drop in the S transistor. ) To precharge. The bit lines BL0A, BL2A, BL4A ... May be set to Vcc or 0V, and may be set to any voltage.

After that, when the selection gate SG1 is set to Vsgl (for example, 1.5 V), the I type selection MOS transistors ST11, ST31, ST51 ... Are turned on, but the E type selection MOS transistors ST01, ST21, ST41. , Memory cells MC01, MC21, M which are not written
The channel of C41 ... is the potential Vcc charged from the bit line.
Floating at -Vth. Memory cell unit
Data to be written in the memory cells MC11, MC31, MC51 ... In (1) are given from bit lines BL1A, BL3A, BL5A.

For example, when "0" is written in the memory cell MC11, if the bit line BL1A is set to 0V,
The I type selection MOS transistor ST11 is turned on and the channel of the memory cell MC11 becomes 0V. Memory cell MC
When "1" is written to 11, the bit line BL1A is set to 3V and the I type selection MOS transistor ST11
Turns off and the channel of the memory cell MC11 becomes floating at Vcc-Vth. Bit lines BL0A, BL2A, B
L4A ... May be set to Vcc or 0V, and may be set to any voltage.

After the selection gate SG1 is changed from Vcc to Vsgl (voltage higher than the threshold voltage of the I type selection MOS transistor, but lower than the E type selection MOS transistor, for example, 1.5V), the control gates CG1 to CG1.
G8 is changed from Vcc to the intermediate potential VM (about 10V). Then, the memory cells MC01, MC21, M which are not written
C41 ... and memory cells MC11, M for writing "1"
Since the channels of C31, MC51 ... Are in a floating state, Vcc is generated by capacitive coupling between the control gate and the channel.
It rises from -Vth to an intermediate potential (about 10V). "0"
The channels of the memory cells MC11, MC31, MC51, ... To be written are 0V because the bit line is 0V.

After the channel of the memory cell in which the write unselection and the "1" write are performed boosts from Vcc-Vth to the intermediate potential, the control gate CG1 is boosted from the intermediate potential VM to the write voltage Vpp (20V). Then, the memory cell MC01 in the memory cell unit (2) which is not written,
The channels of MC21, MC41 ... And the memory cells MC11, MC31, MC51.
Since the control gate CG1 is Vpp (about 20V), these memory cells are not written, but the channels of the memory cells MC11, MC31, MC51, etc. for writing "0" are 0V, and the control gate is Vpp (20V). Therefore, electrons are injected from the substrate to the floating gate, and "0" writing is performed.

Now, the write operation of this embodiment will be described in more detail with reference to a timing chart. 10 and 11 are timing charts when writing to the memory cell MC11 (and memory cells MC31, MC51 ...).

Memory cell M in the memory cell unit (1)
The data to be written in C11, MC31, MC51 ... Is latched in the sense amplifier circuit (SA2 in FIG. 7). That is,
In the case of writing "0", the node N1 is 0V and the node N2 is 3V.
When writing V, "1", the node N1 is 3V, N2
Becomes 0V.

When the write operation is started, first at time t1, S
G1 is set to Vss, SG2 and CG1 to CG8 are set to Vcc. In this embodiment, the memory cell MC in the memory cell unit (1)
When writing to 11, MC31, MC51 ..., Memory cells MC01, MC21, MC in the memory cell unit (2)
Do not write to 41 ... For that purpose, the channels of the memory cells MC01, MC21, MC41 ...
It is necessary to charge from A, BL2A, BL4A ....

In this embodiment, the bit lines BL0A, BL2
A, BL4A ... Are charged from VA1 to Vcc of the sense amplifier SA1 of FIG. As a result, the memory cells MC01, MC2
1, MC41 ... Channels are charged to Vcc-Vth. At this time, write memory cells MC11, MC31, MC
The channels of 51 ... Are also charged to Vcc-Vth. In this way, the channel of the memory cell of the memory cell unit (2) is set to Vcc.
To charge to (-Vth), use BL0A, BL2A
, BL4A ... can be charged, or BL1A, BL1
You may charge from 3A and BL5A.

On the other hand, bit lines BL1A, BL3A, BL
A potential of Vcc or Vss (0V) is applied to 5A ... In accordance with the data latched in the sense amplifier circuit SA2. As a result, for example, "0" is written in the memory cell MC11.
When writing is performed, the bit line BL1A is set to 0V and the channel of the memory cell MC11 is set to 0V. When "1" is written in the memory cell MC11, the bit line BL1A is set to Vcc (for example, 3V) to charge the channel of the memory cell MC11 to Vcc-Vth.

After charging the bit line, the selection gate SG1 is set to Vsg.
l (for example, 1.5 V) and SG2 are set to Vss (for example, 0 V). Selection MOS with selection gate SG2 as gate electrode
All transistors are turned off. Selected MO to which memory cells MC01, MC21, MC41, ... Which are not programmed are connected
Since the S transistors ST01, ST21, ST41 ... Are E type, they are turned off, and the channels of the memory cells MC01, MC21, MC41 ... Float at Vcc-Vth.

Memory cell MC11 for writing "1",
MC31, MC51 ... Select MOS transistors ST11, S
The drains on the memory cell side of T31, ST51 ... Are Vcc-Vth
(For example, assuming that the threshold voltage of the I-type transistor including the substrate bias effect is 0.8 V, 3-0.8 =
2.2 V), the source on the bit line contact side is Vcc (eg 3 V), and the select gate SG1 is Vsgl (eg 1.5 V).
V), select MOS transistors ST11, ST31,
ST51 ... turns off. As a result, like the write-unselected cells, the channels of the memory cells MC11, MC31, MC51 ... Float.

When "0" is written in the memory cells MC11, MC31, MC51 ..., The selection gate SG1 of the selection MOS transistors ST11, ST31, ST51 ... Is Vsg.
l (for example, 1.5V), and the source and drain are 0V, so that the selection MOS transistors ST11, ST31, ST51 ...
Is turned on, and the channel of the memory cell is kept at 0V.

Select gate SG1 is set to Vsgl (for example, 1.5
V), the control gates CG1 to CG8 are changed from Vcc to the intermediate potential VM (about 10 V) at time t2. Then, the memory cells MC01, MC21, MC41 ...
And memory cells MC11, MC31, which perform "1" writing,
Since the channels of MC51 ... Float, they rise from Vcc-Vth to an intermediate potential (about 10 V) due to capacitive coupling between the control gate and the channel. The channel of the memory cells MC11, MC31, MC51, ... In which "0" is written is 0V because the bit line is 0V.

After the channel of the memory cell in which programming is not selected and "1" is programmed is boosted from Vcc-Vth to the intermediate potential, the control gate CG1 is set to the intermediate potential VM at time t3.
To write voltage Vpp (20V). Then, the memory cells MC01, MC21, MC41 ...
And memory cells MC11, MC31, which perform "1" writing,
Since the channel of MC51 ... Is an intermediate potential (about 10V) and the control gate CG1 is Vpp (about 20V), these memory cells are not written, but the channels of the memory cells MC11, MC31, MC51 ... Since the control gate is Vpp (about 20 V), electrons are injected from the substrate into the floating gate to write "0".

After the writing is completed, the control gate, the selection gate, and the bit line are sequentially discharged to complete the writing operation.

After the writing is completed, a write verify operation is performed to check whether the writing has been sufficiently performed.

First, the precharge signals PRA1, PRA2,
PRB2 changes from Vss to Vcc (time t4), and bit line B
L1A, BL3A, BL5A ... Are VA2 (eg 1.7.
V) to (dummy) bit lines BL1B, BL3B, BL5
B ... Is precharged to VB2 (for example, 1.5 V) (time t5). VA1 is 0V, and bit line BL0A,
BL2A, BL4A, BL6A ... Are grounded.

When the precharge is completed, PRA2 and PRB2 become Vss, and the bit lines BL1A, BL3A, BL5A ...
Becomes floating. After this, the row decoder 3
Then, a desired voltage is applied to the selection gate and the control gate (time t6). Control gate CG1 is 0V, CG2-CG
8 is Vcc (for example, 3V), SG2 is 3V (Vsgh), S
G1 becomes 1.5V (Vsgl). Memory cell MC11,
When the data written in MC31, MC51 ... Is "0", the threshold voltage of the memory cell is positive, so that no cell current flows and the potentials of the bit lines BL1A, BL3A, BL5A ... remain at 1.7V. is there. When the data is "1", cell current flows and bit lines BL1A, BL3A, BL5A
The potential of ... Decreases to 1.5 V or less. Further, since the selection gate SG1 is 1.5 V, the E type selection MOS transistors ST01, ST21, ST41 are turned off, and the data of the memory cells MC01, MC21, MC41 ... Are not transferred to the bit line.

After bit line discharge, verify signal VRFY
A becomes 3V (time t7), and memory cells MC11 and MC
When the data written in 31, MC51 ... Is "1", the bit lines BL1A, BL3A, BL5A ... Are charged close to 3V. Here, the voltage level of the charging performed by the verify signal is the bit line BLjB (j = 1, 3,
5 ...) Precharge voltage of 1.5 V or more.

During this period (dummy) bit lines BL1B, BL
3B, BL5B ... Are kept at a precharge potential of 1.5V.

After that, at time t8, φP is 3 V and φN is 0.
V, the CMOS flip-flop FF is inactivated, and φE becomes 3V at time t9, so that the CMOS flip-flop FF of SA2 is equalized and the nodes N1 and N2 become Vcc / 2 (for example, 1.5V). . At time t10, SS2, SA, and SB become 3V, and after the bit line and the sense amplifier are connected, φN changes from 0V to 3V, φN
P changes from 3V to 0V and bit lines BL1A, BL3A,
BL5A ... And bit lines BL1B, BL3B, BL5B ...
Is amplified and the rewritten data is latched by the sense amplifier (time t11).

Bit lines BL0A, BL2A, BL4A, BL6A ... Are grounded to 0V through the verify read operation. That is, every other bit line is grounded.

As described above, in the present invention, since the source line is substituted with the low resistance bit line, the floating of the source line is significantly reduced, and as a result (problem 1), the random access time is reduced. Not only is shortened, but also variation in threshold value at the time of writing caused by a circuit factor is significantly reduced. Further, since the source line is not shared between the adjacent NAND cell columns, the data of the memory cells will not be erroneously read by the data of the adjacent memory cells as described in (Problem 1).

As described in the above embodiment, the channel of the memory cell is charged to Vcc-Vth at the beginning of writing. The way of charging is arbitrary. In the above embodiment, when writing to the memory cells MC11, MC31, MC51, ... First, the selection gate SG1 is Vss, SG2 is Vcc,
The bit lines BL0A, BL2A, BL4A ... Are set to Vcc to charge the memory cells MC01, MC21, MC31, MC41, MC51 ... From the bit lines BL0A, BL2A, BL4A. Besides this method, for example, the bit line BL0A,
BL1A, BL2A, BL3A ... are charged to Vcc and SG
1, SG2, CG1 to CG8 are set to Vcc, and Vcc is applied to the channels of the memory cells MC01, MC11, MC21, MC31 ...
You may charge with (-Vth).

Alternatively, the bit lines BL1A, BL3A, BL
5A ... Vcc, SG2 is Vss, SG1, CG1 to CG8
To Vcc, the bit lines BL1A and BL3A
, BL5A ... From memory cells MC01, MC11, MC2
1, MC31 ... Channels may be charged.

Further, both SG1 and SG2 may be set to Vsgl and the bit lines BL0A, BL2A, BL4A ... May be set to Vcc. In this case, the I type selection MOS transistor is turned on, but the E type selection MOS transistor is turned off. Therefore, the bit lines BL0A, BL2A, BL4A ...
From the memory cell unit 2 to the write non-select potential (V
The write potential (Vcc for writing "1", Vss for writing "0") can be transferred to the memory cell unit 1 from the bit lines BL1A, BL3A, BL5A ...

In the above embodiment, writing is simultaneously performed to the memory cells for 1/2 page. For example, when writing to the memory cells MC11, MC31, MC51 ... Of FIG. 2, the write data is transferred from the bit lines BL1A, BL3A, BL5A ... And the memory cells MC01, MC21, MC.
No writing is performed on 41 ..., and bit lines BL0A and BL2
A and BL4A are kept at constant potentials such as Vcc and 0V. on the other hand,
When writing to the memory cells MC01, MC21, MC41 ..., Write data is transferred from the bit lines BL0A, BL2A, BL4A.
1, MC51 ... Is not written, and bit line BL1A
, BL3A, BL5A are kept at constant potentials such as Vcc and 0V.

As described above, in the above embodiment, the memory cells for ½ page are written almost simultaneously, but according to the present invention, the memory cells for one page can be written almost simultaneously. For example, the selection gates SG1 and SG
Both should be set to Vsgl (eg 1.5V) (Fig. 1
2). Then, the E type selection MOS transistor having the selection gates SG1 and SG2 as gate electrodes is turned off, and the I type selection MOS transistor is turned on. The write data of the memory cells MC11, MC31, MC51 ... Is transferred from the bit lines BL1A, BL3A, BL5A. That is, in the case of "0" write, the bit line and the channel of the memory cell to be written become 0V, in the case of "1" write, the bit line becomes Vcc and the channel becomes Vcc-.
Floating at Vth. Similarly, the memory cell MC
The write data of 01, MC21, MC41 ... is the bit line B
Transferred from L0A, BL2A, BL4A ....

As described above, in the present embodiment, since the number of bit lines arranged in the column direction and the number of NAND cell columns in the column direction are almost the same, it is possible to give the data to be written in the memory cell to each bit line. Data for one page can be written almost simultaneously. After the write operation, verify read is performed to check whether the write has been sufficiently performed. In the verify read operation of the above embodiment, the data of one memory cell is read using two bit lines. That is, the data for 1/2 page is read out almost simultaneously.

Therefore, in the method of writing the data for one page almost at the same time, the verify read operation may be performed twice for each write operation. In the method of performing verify read twice for one write operation, 1
Total time to write page data is about Tpr
+ 2Tvfy (Tpr: write pulse width, Tvfy: one verify read time). On the other hand, in the method of writing the data for 1/2 page almost at the same time, the total write time for writing the data for 1 page is about 2 (T
pr + Tvfy), the writing operation is faster with the method of simultaneously writing data for one page.

According to the present invention, the selection MOS transistors of the two NAND strings sharing the selection gate with the bit line contact (for example, the selection MOS transistors ST12 and S12 of FIG. 2).
It suffices that there is a difference between the threshold voltages of T22, ST32 and ST42), and the method of setting the threshold voltage of the selection MOS transistor is arbitrary. In FIG. 2, the threshold voltages of the selection MOS transistors ST02 and ST03, ST12 and ST13, ST22 and ST23 are set to be almost the same, but for example, in FIG.
3, one of the selection MOS transistors is I
Type, the other selection MOS transistor may be of E type.

In the above embodiment, the sense amplifier is connected for each bit line, but one sense amplifier is connected to two bit lines, that is, a so-called shared sense amplifier system (FIG. 15).
You may The timing charts for writing and reading in this case are almost the same as those in the above-described embodiment (FIGS. 5, 10, 11 and the like).

Further, according to the present invention, it is possible to generate the conductive MOS transistor and the non-conductive MOS transistor of the selection MOS transistors sharing one selection gate, and prepare two such selection gates. This makes it possible to easily realize a selected memory cell and a non-selected memory cell within a memory cell having the same selection gate.

Therefore, the threshold voltage of the selection MOS transistor and the voltage applied to the selection gate are arbitrary. One end of the memory cell, the selection MOS transistor is V
It has two kinds of threshold voltages of td1 and Vtd2 (Vtd1> Vtd2), and the voltage applied to this selection gate is Vsghd (V
sghd> Vtd1) and Vsgld (Vtd1>Vsgld> Vtd2), and the selection MOS transistor on the other end side of the memory cell has two threshold voltages of Vts1 and Vts2 (Vts1> Vts2). The voltage applied to the selection gate is Vsghs (Vsghs> Vts1), Vsgls (Vts1>Vsgls>
Vts2), as in the above-mentioned embodiment.
td1 = Vts1, Vtd2 = Vts2, Vsghd = Vsghs, Vsg
It does not have to be ld = Vsgls.

For example, the selection MOS on one end side of the memory cell
The threshold voltage of the transistor is set to 2V and 0.5V, and the selection MOS transistor on the other end side of the memory cell is set to the threshold voltage of 2.5V and 1V. The voltage applied to the gate is Vsgh = 3
V, Vsgl = 1.5V, and the voltage applied to the select gate on the other end side of the memory cell may be Vsgh = 3V, Vsgl = 1.2V.

The threshold voltages of the two selection MOS transistors connected to one NAND string may be substantially the same. For example, two selections M connected to a NAND string
The threshold voltage of the OS transistor is 0.8 V, this NA
The threshold voltage of the selection MOS transistor on one end side of the adjacent NAND cell sharing the gate electrode of the selection MOS transistor with the ND column is 0.2 V, and the threshold voltage of the selection MOS transistor on the other end side of the memory cell is 1.4
The voltage applied to the select gate on one end side of the NAND cell is Vs
gh = 3V, Vsgl = 0.5V, and the voltage applied to the select gate on the other end side of the NAND cell is Vsgh = 3V, Vsgl =
It may be 1.2V.

If Vsgh is made larger than Vcc, selection M
Since the conductance of the OS transistor increases (that is, the resistance decreases), the cell current flowing through the NAND cell string increases at the time of reading, so that the bit line discharge time is shortened, and as a result, the verify read of read and write becomes faster. To be done. Vsgh may be boosted from Vcc by a booster circuit in the chip, for example.

It is desirable that the voltage Vsgh of the select gate, which makes all the select MOS transistors sharing one select gate conductive, be equal to or lower than the power supply voltage Vcc. If Vsgh is larger than Vcc, a booster circuit is required in the chip, which leads to an increase in chip area.

The larger value Vt1 of the threshold voltages of the selection MOS transistors may be set to a voltage higher than the power supply voltage Vcc (for example, 3.5V). In this case, in order to turn on the selection MOS transistor having the threshold voltage of Vt1 at the time of reading or verify reading, for example, 4V may be applied to the selection gate by using the booster circuit inside the chip.

As a method of changing the threshold voltage, the selection M is changed by changing the gate oxide film thickness of the selection MOS transistor.
It is conceivable to change the concentration of the channel-doped impurities in the OS transistor. Alternatively, the threshold voltage may be made different depending on whether the selective MOS transistor is channel-doped with impurities or not. The threshold voltage can also be changed by changing the channel length of the selection MOS transistor. That is, a transistor having a short channel length has a small threshold voltage due to the short channel effect, and thus may be an I-type transistor.

As a method of changing the gate oxide film thickness and the impurity concentration of the channel, another manufacturing process such as channel doping of the peripheral circuit may be used without introducing a new manufacturing process. In either method, the threshold voltage of the selection MOS transistor may be made different, and if there is a difference in threshold voltage, a predetermined threshold voltage can be obtained by substrate bias or the like.

In addition, the select gate on one end side of the write block (for example, the memory cells MC11, MC31, MC51 of FIG. 2).
When 0V is applied to SG2) when writing to ..., the selection MOS transistor using this selection gate as a gate electrode is of the I type and the threshold voltage Vt2 is about 0.1V (or a negative threshold). For voltage), select M
The OS transistor does not completely cut off, and the cell current flows. As a result, the channel of the memory cell in which programming is not selected or "1" is programmed is not boosted from Vcc-Vth to the intermediate potential VM, or even if boosted, the cell current flows and the potential drops from VM. In any case, since the channel of the memory cell not selected for writing or for writing "1" is lowered from VM, it is erroneously written to "0".

In order to improve the cut-off characteristic of the I-type transistor, the bit line (memory cells MC11, MC31,
When writing to MC51 ... BL0A, BL2A
, BL4A ...), for example, a voltage of about 0.5 V may be applied. If 0.5 V is applied to the source of the selection MOS transistor, the potential difference between the source and the substrate becomes −0.5 V, and the threshold voltage of the I type transistor increases due to the substrate bias effect. The cut-off characteristic when 0 V is applied to is improved.

In order to set the smaller threshold voltage (I type) of the threshold voltages of the selection MOS transistors to 0.5 V, for example, a method of reducing the substrate concentration can be considered. In an I-type transistor having a low substrate concentration, when a drain voltage is applied without applying a gate voltage, a depletion layer between the drain and the substrate spreads, resulting in a depletion layer between the drain and the substrate and a depletion layer between the source and the substrate. There is a problem that they are connected and dull (punch through).
In order to increase the punch-through breakdown voltage of the I type selection MOS transistor, the channel length L of the I type selection MOS transistor may be increased.

(Embodiment 2) The structure of a NAND cell type EEPROM according to this embodiment is the same as that of FIG. The memory cell array 11A of this embodiment is shown in FIG. 16, and the memory cell array 11B is shown in FIG. Similar to the first embodiment, two or more threshold voltages of the selection MOS transistor are provided. A memory cell array according to this embodiment (FIGS. 16 and 1)
In 7) as well, one bit line contact is shared by the four NAND cell columns, so that the number of bit line contacts in the entire memory cell array does not increase from the conventional memory cell array. The sense amplifier SA1 connected to the bit lines BL0A, BL2A, BL4A ... Is shown in FIG.
, BL3A, BL5A ... Sense amplifier SA
2 is FIG. 7.

FIG. 18 shows the n-type diffusion layer of the memory cell of this embodiment, the source / gate / drain regions of the memory cell, and
The contact (bit line contact) connecting the n-type diffusion layer and the bit line (Al or the like) is shown. As described above, in the conventional memory cell array, since the bit line contacts of the adjacent bit lines are arranged adjacent to each other as shown in FIG. 41, it is difficult to reduce the size in the column direction (X direction in FIG. 41). There is. On the other hand, in the memory cell array of this embodiment, the bit line contacts of the adjacent bit lines are not arranged adjacent to each other as shown in FIG. 18, so that the size of the element isolation region between the bit line contacts and the bit line contacts is large. Is the column direction (X direction) of the memory cell array
Does not become a problem when reducing the memory cell, and the element isolation width between memory cells should be reduced to the minimum element isolation region width L0 determined by the field inversion breakdown voltage between adjacent NAND cell columns and the element isolation technology. You can

<Read Operation> Now, the read operation will be described with reference to the timing chart.

FIG. 19 shows the memory cells MC11 and MC of FIG.
31 is a timing chart for reading the data written in 31, MC51 ....

First, the precharge signals PRA1, PRA2,
PRB2 changes from Vss to Vcc (time t0), and bit line B
L1A, BL3A, BL5A ... Are VA2 (eg 1.7.
V), and the (dummy) bit lines BL1B, BL3B,
BL5B ... Are precharged to VB2 (for example, 1.5V) (time t1). VA1 is 0V and bit line BL0
A, BL2A, BL4A, BL6A ... Are grounded.

When the precharge is completed, PRA2 and PRB2 become Vss, and the bit lines BL1A, BL3A, BL5A ...
Becomes floating. After this, the row decoder 3
Then, a desired voltage is applied to the selection gate and the control gate (time t2). Control gate CG1 is 0V, CG2-CG
8 is Vcc (for example, 3V), SG2 is 3V (Vsgh), S
G1 becomes 1.5V (Vsgl).

When the data written in the memory cells MC11, MC31, MC51 ... Is "0", the threshold voltage of the memory cell is positive, so that no cell current flows and the bit line BL1
The potentials of A, BL3A, BL5A ... Remain at 1.7V. When the data is "1", the cell current flows and the potentials of the bit lines BL1A, BL3A, BL5A ...
It becomes 1.5V or less. Further, the selection gate SG1 is 1.5
Since it is V, E type selection MOS transistors ST01, S
T21, ST41 ... Are turned off, and memory cells MC01, MC
The data of 21, MC41 ... Is not transferred to the bit line. During this period (dummy) bit lines BL1B, BL3B, BL5B ...
Is kept at a precharge potential of 1.5V. After that, at time t3, φP becomes 3V and φN becomes 0V, the CMOS flip-flop FF is inactivated, and at time t4 φE becomes 3V.
Becomes SA2 CMOS flip-flop F
F is equalized and the nodes N1 and N2 become Vcc / 2 (for example, 1.5V). SS2, SA, SB at time t5
Becomes 3V, and after the bit line and sense amplifier are connected, φN changes from 0V to 3V, φP changes from 3V to 0V,
Bit lines BL1A, BL3A, BL5A ... And bit line B
The potential difference between L1B, BL3B, BL5B ... Is amplified (time t6).

That is, the memory cells MC11, MC31, MC
If "0" is written in 51 ..., node N of SA2
1 becomes 3V, node N2 becomes 0V, and memory cell MC1
If "1" is written in 1, MC31, MC51 ...
The node N1 becomes 0V and the node N2 becomes 3V. afterwards,
When the column selection signal CSL changes from 0V to 3V, CMO
The data latched in the S flip-flop is IO,
/ IO (time t7).

Through the read operation, the bit lines BL0A,
BL2A, BL4A, BL6A ... Are grounded to 0V. Also, by setting PRB1 to Vcc and VB1 to 0V through the read operation, the bit lines BL0B, BL2B and BL
4B, BL6B ... May be grounded. As a result, it is possible to reduce capacitive coupling noise between bit lines during amplification of the bit line potential.

FIG. 20 shows the memory cells MC01 and MC of FIG.
21 and MC41 ... The data written in the bit line BL0B
, BL2B, BL4B, BL6B ...

<Write Operation> Now, the write operation of the present invention will be described with reference to a timing chart. 21, FIG.
2 is a memory cell MC11 (and memory cells MC31, MC51
() Is a timing diagram when writing ().

The data to be written in the memory cells MC11, MC31, MC51 ... Is latched in the sense amplifier circuit (SA2 in FIG. 7). In other words, when "0" is written, the node N1 is 0V, N2 is 3V, and when "1" is written, the node N1 is 3V and N2 is 0V.

When the write operation is started, first at time t1, S
G1 is set to Vss, SG2, CG1 to CG8 are set to Vcc. In this embodiment, when writing to the memory cells MC11, MC31, MC51 ...
Do not write to ... For that purpose, the memory cell M
The channels of C01, MC21, MC41 ... Are connected to the bit line BL0A.
, BL2A, BL4A ... Need to be charged. In this embodiment, the bit lines BL0A, BL2A, BL4A ... Are charged from VA1 to Vcc of the sense amplifier SA1 shown in FIG.
As a result, the channels of the memory cells MC01, MC21, MC41 ... Are charged to Vcc-Vth. At this time, the memory cell M
The channels of C11, MC31, MC51 ... Are also charged to Vcc-Vth.

Bit lines BL1A, BL3A, BL5A ...
Is given a potential of Vcc or Vss (0V) according to the data latched in the sense amplifier circuit SA2. Thus, for example, when "0" is written in the memory cell MC11, the bit line BL1A is set to 0V and the memory cell MC11
11 channels will be set to 0V. Memory cell MC
When "1" is written in 11, the bit line BL1A is set to Vcc (for example, 3V) to charge the channel of the memory cell MC11 to Vcc-Vth. Select gate SG2
Is 0V, and the selection MOS transistor having SG2 as a gate electrode is off.

After charging the bit line, the selection gate SG1 is set to Vsg.
l (for example, 1.5 V), and the selection gate SG2 is set to Vss. Memory cells MC01, MC21, M which are not programmed
Select MOS transistors ST01, ST connected to C41 ...
Since 21, ST41 ... are E type, they are turned off, and the memory cell MC
The channels 01, MC21, MC41, ... Float at Vcc-Vth.

Memory cell MC11 for writing "1",
MC31, MC51 ... Select MOS transistors ST11, S
The drains on the memory cell side of T31, ST51 ... Are Vcc-Vth
(For example, the threshold voltage of an I-type transistor is set to 0.
8V, 3-0.8 = 2.2V), the source on the bit line contact side is Vcc (for example, 3V), and the select gate S
Since G1 is Vsgl (for example, 1.5 V), the selection MOS transistors ST11, ST31, ST51 ... Are turned off. As a result, like the write-unselected cell, the memory cell MC1
Channels of 1, MC31, MC51 ... Become floating.

When "0" is written in the memory cells MC11, MC31, MC51 ..., The selection gate SG1 of the selection MOS transistors ST11, ST31, ST51 ... Is Vsg.
l (for example, 1.5V), and the source and drain are 0V, so that the selection MOS transistors ST11, ST31, ST51 ...
Is turned on, and the channel of the memory cell is kept at 0V.

The select gate SG1 is set to Vsgl (for example, 1.5
V), the control gates CG1 to CG8 are changed from Vcc to the intermediate potential VM (about 10 V) at time t2. Then, the memory cells MC01, MC21, MC41 which are not written
... and memory cells MC11 and MC for writing "1"
The channels of 31, MC51 ... are floating,
Vcc-V due to capacitive coupling between control gate and channel
It rises from th to an intermediate potential (about 10 V). The channel of the memory cells MC11, MC31, MC51, ... In which "0" is written is 0V because the bit line is 0V.

After the channel of the memory cell in which write unselection and "1" write are performed is boosted from Vcc-Vth to the intermediate potential, the control gate CG1 is set to the intermediate potential VM at time t3.
To write voltage Vpp (20V). Then, the memory cells MC01, MC21, MC41 ...
And memory cells MC11, MC31, which perform "1" writing,
Since the channels of MC51 ... Have an intermediate potential (about 10 V) and the control gate CG1 is Vpp (about 20 V), these memory cells are not written, but the channels of the memory cells MC11, MC31, MC51 ... Since the control gate is 0 V and Vpp (about 20 V), electrons are injected from the substrate to the floating gate and "0" writing is performed.

After the writing is completed, the control gate, the selection gate and the bit line are sequentially discharged to complete the writing operation.

After the writing is completed, a write verify operation is performed to check whether the writing is sufficiently performed.

First, the precharge signals PRA1, PRA2,
PRB2 changes from Vss to Vcc (time t4), and bit line B
L1A, BL3A, BL5A ... Are VA2 (eg 1.7.
V), and the (dummy) bit lines BL1B, BL3B,
BL5B ... Are precharged to VB2 (for example, 1.5V) (time t5). VA1 is 0V and bit line BL0
A, BL2A, BL4A, BL6A ... Are grounded.

When the precharge is completed, PRA2 and PRB2 become Vss, and the bit lines BL1A, BL3A, BL5A ...
Becomes floating. After this, the row decoder 3
Then, a desired voltage is applied to the selection gate and the control gate (time t6). Control gate CG1 is 0V, CG2-CG
8 is Vcc (for example, 3V), SG2 is 3V (Vsgh), S
G1 becomes 1.5V (Vsgl). Memory cell MC11,
When the data written in MC31, MC51 ... Is "0", the threshold voltage of the memory cell is positive, so that no cell current flows and the potentials of the bit lines BL1A, BL3A, BL5A ... remain at 1.7V. is there. When the data is "1", cell current flows and bit lines BL1A, BL3A, BL5A
The potential of ... Decreases to 1.5 V or less. Further, since the selection gate SG1 is 1.5 V, the E type selection MOS transistors ST01, ST21, ST41 are turned off, and the data of the memory cells MC01, MC21, MC41 ... Are not transferred to the bit line.

After bit line discharge, verify signal VRFY
A becomes 3V (time t7), and memory cells MC11 and MC
When the data written to 31, MC51 ... Is “1”, the bit lines BL1A, BL3A, BL5A ...
Charged nearby. Here, the voltage level of the charging performed by the verify signal is the bit line BLjB (j = 0, 1
It is sufficient if the precharge voltage of (1) to (127) is 1.5 V or higher.

During this period (dummy) bit lines BL1B, BL
3B, BL5B ... Are kept at a precharge potential of 1.5V.

After that, at time t8, φP is 3V and φN is 0V.
V, the CMOS flip-flop FF is inactivated, and φE becomes 3 V at time t9, so that C of SA2
The MOS flip-flop FF is equalized and the nodes N1 and N2 become Vcc / 2 (for example, 1.5 V). At time t10, SS2, SA, and SB become 3V, and after the bit line and the sense amplifier are connected, φN changes from 0V to 3V, φP
Changes from 3V to 0V and bit lines BL1A, BL3A, B
The potential difference between L5A ... And the bit lines BL1B, BL3B, BL5B ... Is amplified and the rewritten data is latched by the sense amplifier (time t11).

Through the read operation, the bit lines BL0A,
BL2A, BL4A, BL6A ... Are grounded to 0V. That is, every other bit line is grounded.

According to the present invention, if there is a difference in threshold voltage between the selection MOS transistors of the two NAND strings (for example, the selection MOS transistors ST02 and ST12, ST22 and ST32 in FIG. 16) sharing the bit line contact and the selection gate. Finally, the method of setting the threshold voltage of the selection MOS transistor has arbitrariness. In FIG. 16, select MOS transistors ST02 and ST03, ST12 and ST13, ST22 and ST23.
Although the threshold voltages are set to be substantially the same, one selection MOS transistor may be of the I type and the other selection MOS transistor may be of the E type as shown in FIGS. 23 and 24, for example.

In the above embodiment, the sense amplifier is connected for each bit line, but a so-called shared sense amplifier system (FIG. 15) in which one sense amplifier is connected to two bit lines may be used. The timing diagrams of writing and reading in this case are almost the same as those in the above-described embodiment (FIG. 19, FIGS. 21, 22 and the like). Further, as in the first embodiment, the data for one page can be written almost simultaneously.

(Embodiment 3) In the above-mentioned embodiment, it is utilized that among the selection MOS transistors sharing one selection gate, those of the conducting state and those of the non-conducting state can be generated. . Therefore, the smaller threshold voltage Vt2 of the selection MOS transistor may be a negative threshold voltage (for example, -1V). The memory cell array in this case is, for example, as shown in FIG. In FIG. 25, a selection MOS transistor having a negative threshold voltage is described as a D type. In the above embodiment, the E-type selection MOS transistor is turned off to the selection gate at the time of writing or reading, but the I-type selection MOS transistor is applied with a voltage Vsgl (for example, 1.5 V) for turning it on. Since the E type selection MOS transistor and the D type selection MOS transistor are used in this embodiment, Vsgl = 0V may be set, a positive voltage (for example, 0.5V) or a negative voltage (for example, -0.5V). ) Is okay.

Further, at the time of reading or writing, the select gate of an unselected block in which reading or writing is not performed (for example, memory cells MC11, MC31, M in FIG. 25).
When writing C51 ..., select gates SG3, SG
4, SG5, SG6 ...) is applied with 0V in the above embodiment, but a negative voltage (for example, -2V) may be applied so that the D type selection MOS transistor is turned off. When the D-type selection MOS transistor of the non-selected block is turned off, the bit line potential is not applied to the drain or channel of the memory cell via the selection MOS transistor during reading or writing, and the memory cell is not erased by mistake. The charge of the bit line does not leak to the non-selected block, and it does not take a long time to precharge the bit line during reading and writing.

(Embodiment 4) In the above embodiment, the selection MOS
There were two types of threshold voltage of the transistor.
Not limited to types. For example, if the selection MOS transistor is 3
It may have different threshold voltages. Fig. 26 shows Select MO
This is one of the embodiments in which the S transistor has three kinds of threshold voltages. When the threshold voltage of the E type transistor is Vth1, the threshold voltage of the I type transistor is Vth2, and the threshold voltage of the I'type transistor is Vth3, Vth1>Vth2> Vth3. There are also three types of voltage applied to the select gate, Vsgh
(Vsgh> Vth1), Vsgm (Vth1>Vsgm> Vth2
), Vsgl (Vth2>Vsgl> Vth3). By applying these three kinds of voltages to the select gate, both ends of one memory cell unit of the memory cell units (1), 2, 3 of FIG. 26 can be connected to the bit line.

Memory cells MC01, MC11, MC of FIG.
When reading the data written in 21, the control gate CG1 is applied with 0 V, and Vcc is applied to CG2 to CG8. Memory cell unit provided with memory cell MC01 (1)
When reading out, select gate SG1 is set to Vsgl, SG2
Is set to Vsgh, the memory cell unit among the selection MOS transistors having the selection gate SG1 as a gate electrode.
Select MOS transistor belonging to (1) (eg ST01)
Only conducts. All selection MOS transistors having the selection gate SG2 as a gate electrode are turned on. Therefore, through the memory cell unit (1), the bit lines BL2A-BL3A
Since a current path for connecting the memory cells is formed, the memory cell MC01
Can be read.

When the memory cell unit (2) in which the memory cell MC11 is arranged is read, the selection gate SG1
To Vsgm and SG2 to Vsgm, select gate SG1
It is only in the memory cell unit (2) that both the selection MOS transistor having the gate electrode as the gate electrode and the selection MOS transistor having the selection gate SG2 as the gate electrode are conductive. Therefore, a current path connecting between the bit lines BL3A and BL4A can be formed through the memory cell unit (2), so that the data written in the memory cell MC11 can be read.

When reading the memory cell unit 3 in which the memory cell MC21 is arranged, if the selection gate SG1 is set to Vsgh and SG2 is set to Vsgl, the memory cell of the selection MOS transistors having the selection gate SG2 as a gate electrode is selected. Only the selection MOS transistor (for example, ST22) belonging to the unit 3 becomes conductive. All the selection MOS transistors having the selection gate SG1 as a gate electrode are turned on. Therefore, through the memory cell unit 3, the bit lines BL3A-B
Since a current path connecting between L4A is formed, the memory cell MC21 can be read.

As described above, even if the threshold voltage of the selection MOS transistor is set to three or more, if the voltage applied to the selection gate is set to three or more, one of the three or more types of memory cell units is selected. Can be in a state. Thereby, as described in (Examples 1 to 3), not only the bit line contact margin can be increased, but also the wiring margin of the bit line itself can be increased. For example, in FIG.
In this embodiment, since two bit lines are arranged at a pitch of three memory cells, the number of bit lines becomes 2/3 of that of the conventional memory cell, and the wiring of bit lines becomes easy.

(Embodiment 5) In the above-mentioned embodiment, there are two selection MOS transistors for each NAND cell string in which memory cells are connected in series. For example, as shown in FIG.
One memory cell unit may be configured by providing three selection MOS transistors for each AND cell column. In the following, the memory cell unit (1) including the memory cell MC11 and the memory cell unit (2) including the memory cell MC21 in FIG. 27 will be described as an example.

One selection side of the NAND cell array has two selection MOs.
It is connected to a bit line (eg, bit line BL2A) via an S transistor (eg, ST13, ST14), and the other end side is connected to a bit line (eg, bit line BL1A) via one selection MOS transistor (eg, ST11). It
Two selection MOS transistors connected in series are of two types: E type (threshold voltage Vth1> 0) and D type (threshold voltage Vth2 <0). The selection MOS transistor (eg, ST13) of the memory cell unit (1) having the selection gate SG2 as a gate electrode is a D type, and the selection MOS transistor (eg, ST23) of the memory cell unit (2)
Is E type. The selection MOS transistor (eg, ST24) of the memory cell unit (2) having the selection gate SG3 as a gate electrode is a D type, the memory cell unit (1)
The selection MOS transistor (for example, ST14) is of E type.

The selection MOS on the other end side of the NAND cell
The transistors (for example, ST11 and ST21) are of E'type (threshold voltage Vth3). Vth3 is Vth1 or Vth
It may be equal to any one of 2 or different from Vth1 and Vth2. For example, Vth3 may be 0.7V.

The read operation and the write operation of this embodiment will be described below.

<Read Operation> Memory cell unit (1)
In order to read the data of the memory cells MC11, MC31, MC51 ... In the bit lines BL2A, BL4A, BL6A ..., First, the bit lines BL2A, BL4A, BL6A ... Are set to the bit line read potential VA (for example, 1.8V). Charge and ground BL1A, BL3A, BL5A ... to 0V. After precharging, bit lines BL2A, BL
Float 4A, BL6A ...

Next, the control gate CG1 is 0V, and CG2-
CG8 is set to Vcc (for example, 3V). Then, the selection gates SG1 and SG3 are set to Vcc, and the selection gate SG2 is set to Vss. The other select gates and control gates are set to 0V. In this case, the selection MOS transistors (ST01, ST11, ST21 ...,) having the selection gates SG1 and SG3 as gate electrodes
ST04, ST14, ST24 ...) are all turned on. The D-type selection MOS transistors (ST13, ST33, ST53 ...) Using the selection gate SG2 as a gate electrode are turned on, but E
Type selection MOS transistor (ST03, ST23, ST
43 ...) turns off.

Therefore, the memory cells MC11, MC31, MC
If the data written in 51 ... Is "1", the precharged bit lines BL2A, BL4A, BL6A ... Are discharged to the grounded bit lines BL1A, BL3A, BL5A .. 1)
The data of the memory cells MC11, MC31, MC51, ... Inside are read out to the bit lines BL2A, BL4A, BL6A. On the other hand, if the data written in the memory cell is "0", the bit lines BL2A, BL4A, BL6A ... Are not discharged and the precharge potential is maintained.

In the above embodiment, the bit lines BL2A, BL2
4A, BL6A ... are precharged and bit line BL1A
, BL3A, BL5A ... Are grounded, while bit lines BL2A, BL4A, BL6A ... are grounded and bit line B
L1A, BL3A, BL5A ... Are precharged and the data of the memory cells are transferred to the bit lines BL1A, BL3A, BL.
5A ... May be read.

On the other hand, for the memory cells MC01, MC21, MC41, ... In the memory cell unit (2), an E type selection MOS transistor ST03 having SG2 as a gate electrode,
Since ST23, ST43 ... Are turned off, the memory cell MC01,
The data of MC21, MC41 ... Is not read to the bit line.

Memory cell M in memory cell unit (2)
The data of C01, MC21, MC41 ...
When reading to BL2A, BL4A, BL6A ...
The selection gates SG1 and SG2 are set to Vcc, and the selection gate SG3 is set to Vss. Control gate CG1 is 0V, CG2 to CG8
To Vcc. In this case, the selection MOS transistors (ST01, S) using the selection gates SG1, SG2 as gate electrodes
T11, ST21, ..., ST03, ST13, ST23 ...) are all turned on. D-type selection MOS transistors (ST04, ST24, ST44) using the selection gate SG3 as a gate electrode
...) is turned on, but the E type selection MOS transistors (ST14, ST34, ST54 ...) Are turned off.

Therefore, since all the selection MOS transistors connecting the memory cells in the memory cell unit (2) to the bit lines are turned on, the data in the memory cells MC01, MC21, MC41 ... Read out on the line. In the memory cell unit (1), the selection MOS transistor having the selection gate SG3 as a gate electrode is turned off, so that data is not read out to the bit line.

<Write> A write procedure for writing to the memory cells MC11, MC31, MC51 ... In the memory cell unit (1) will be described below.

The selection gate SG1 is set to 0V, and all the selection MOS transistors having the selection gate SG1 as a gate electrode are turned off. SG2, SG3, CG1 to CG8 are Vcc, bit lines BL0A, BL1A, BL2A, BL3
A ... is set to Vcc and the channel of the memory cell of the block of the page to be written is precharged to Vcc-Vth (which becomes smaller than the bit line potential Vcc due to the threshold voltage drop in the selection MOS transistor).

After that, the selection gate SG2 is set to Vss (0V).
Then, the D type selection MOS transistors ST13, ST33, ST53 ... Using the selection gate SG2 as a gate electrode are turned on, but the E type selection MOS transistors ST03,
Since ST23, ST43, ... Are turned off, the channels of the memory cells MC01, MC21, MC41, ... Which are not written become floating at the potential Vcc-Vth charged from the bit line. At this time, the selection gate SG3 remains at Vcc.

Memory cell M in memory cell unit (1)
The data to be written in C11, MC31, MC51 ... Is the bit line B
L2A, BL4A, BL6A ... For example, when "0" is written in the memory cell MC11, SG3 is Vcc when the bit line BL2A is set to 0V, so the E type selection MOS transistor ST14 is turned on and the channel of the memory cell MC11 becomes 0V. When writing "1" to the memory cell MC11, the bit line BL2A is set to 3V.
Then, the E type selection MOS transistor ST14 is turned off and the channel of the memory cell MC11 becomes floating at Vcc-Vth. Bit lines BL1A, BL3A, BL5
A ... May be set to Vcc or 0 V, and may be set to any voltage.

After the selection gate SG2 is changed from Vcc to Vss, the control gates CG1 to CG8 are changed from Vcc to the intermediate potential VM.
(About 10V). Then, since the channels of the memory cells MC01, MC21, MC41, ... That are not written and the memory cells MC11, MC31, MC51 ,, that are written by "1" are in a floating state, capacitive coupling between the control gate and the channel causes an intermediate potential from Vcc-Vth. (About 10V). Memory cell MC for writing "0"
The channel of 11, MC31, MC51 ... Is 0V because the bit line is 0V.

After the channel of the memory cell in which the write unselection and the "1" write are performed is boosted from Vcc-Vth to the intermediate potential, the control gate CG1 is boosted from the intermediate potential VM to the write voltage Vpp (20V). Then, the memory cell MC01 in the memory cell unit (2) which is not written,
The channels of MC21, MC41 ... And the memory cells MC11, MC31, MC51.
Since the control gate CG1 is Vpp (about 20V), these memory cells are not written, but the channel of the memory cells MC11, MC31, MC51, etc. in which "0" is written is 0V, and the control gate is Vpp (about 20V). ), So
Electrons are injected from the substrate to the floating gate to write "0".

When writing to the memory cell unit (2), after precharging the channel of the memory cell unit (1) to Vcc-Vth, the select gate SG2 is set to Vcc, SG.
1, SG3 may be set to Vss. In this case, the bit line B
Write data to the memory cell unit (2) is transferred from L0A, BL2A, BL4A, BL6A .... Further, SG1 may be set to Vcc, SG2 and SG3 may be set to Vss, and pre-charge may be performed from the bit lines BL1A, BL3A, BL5A ... To the memory cell memory cell unit (1) in which writing is not performed.

In this embodiment, when Vss is applied to the selection gate at the time of reading and writing, among the selection MOS transistors having the selection gate as the gate electrode, the E type selection MOS transistor is turned off, but the D type selection MO transistor is turned off.
The S-transistor utilizes turning on. This D
The type selection MOS transistor may be of the I type (threshold voltage is positive). In this case, Vss is applied to the select gate
Instead of applying Vsgl, the E type is turned off but the I type selection MOS transistor is turned on.

(Embodiment 6) As shown in FIG. 28, the selection MOS transistors have four selection MOs per NAND cell column.
One memory cell unit may be configured by providing an S transistor. In the following, the memory cell unit (1) including the memory cell MC11 and the memory cell unit (2) including the memory cell MC21 in FIG. 28 will be described as an example.

One selection side of the NAND cell array has two selection MOs.
It is connected to a bit line (for example, bit line BL2A) through an S transistor (for example, ST13, ST14), and the other end side has two selection MOS transistors (for example, ST11 and ST1).
2) to the bit line (for example, bit line BL1A). Two selection MOS transistors connected in series are of two types: E type (threshold voltage Vth1> 0) and D type (threshold voltage Vth2 <0). Memory cell unit having select gates SG1 and SG3 as gate electrodes
Select MOS transistor of (1) (eg ST11, ST1
3) is D type, selection MOS of memory cell unit (2)
Transistors (eg ST21, ST23) are E type. Select MOS transistors (for example, ST
22 and ST24) are D type, and the selection MOS transistors (for example, ST12 and ST14) of the memory cell unit (1) are E type.

The read operation and the write operation of this embodiment will be described below.

<Read operation> Memory cell unit (1)
In order to read the data of the memory cells MC11, MC31, MC51 ... In the bit lines BL2A, BL4A, BL6A ..., First, the bit lines BL2A, BL4A, BL6A ... Are set to the bit line read potential VA (for example, 1.8V). Charge and ground BL1A, BL3A, BL5A ... to 0V. After precharging, bit lines BL2A, BL
Float 4A, BL6A ...

Next, the control gate CG1 is 0V, and CG2-
CG8 is set to Vcc (for example, 3V). The selection gates SG2 and SG4 are set to Vcc, and one or both of the selection gates SG1 and SG3 are set to Vss. The other select gates and control gates are set to 0V. In this case, the selection gates SG2, S
All selection MOS transistors having G4 as a gate electrode are turned on. D using the select gates SG1 and SG3 as gate electrodes
Type selection MOS transistor (ST11, ST13, ST
31, ST33 ...) turn on. Select gates SG1 and SG3
Among the E-type selection MOS transistors having the gate electrode as the gate electrode, the E-type selection MOS transistor whose selection gate is Vss is turned off.

Therefore, the memory cells MC11, MC31, MC
If the data written in 51 ... Is "1", the precharged bit lines BL2A, BL4A, BL6A ... Are discharged to the grounded bit lines BL1A, BL3A, BL5A and lowered from the precharge potential, and the memory cell unit (1 The data of the memory cells MC11, MC31, MC51 ... In () are read to the bit lines BL2A, BL4A, BL6A.
On the other hand, if the data written in the memory cell is "0", the bit lines BL2A, BL4A, BL6A ... Are not discharged and the precharge potential is maintained.

In the above embodiment, the bit lines BL2A, BL2
4A, BL6A ... are precharged and bit line BL1A
, BL3A, BL5A ... Are grounded, while bit lines BL2A, BL4A, BL6A ... are grounded and bit line B
L1A, BL3A, BL5A ... Are precharged and the data of the memory cells are transferred to the bit lines BL1A, BL3A, BL.
5A ... May be read.

On the other hand, the memory cells MC01, MC21, MC41, ... In the memory cell unit (2) have select gates SG1, S1.
Since either of the E type selection MOS transistors having G3 as a gate electrode (when one of SG1 and SG3 is set to Vss) or both (when both SG1 and SG3 are set to Vss) are turned off, the memory cell MC01, MC21, M
The data of C41 ... Is not read to the bit line.

<Write> A write procedure for writing to the memory cells MC11, MC31, MC51 ... In the memory cell unit (1) will be described below.

When the selection gates SG1 and SG2 are set to Vss, one of the selection MOS transistors having the selection gates SG1 and SG2 as gate electrodes, that is, the E type selection MOS
The transistor turns off. SG3, SG4, CG1-C
G8 is Vcc, bit lines BL0A, BL1A, BL2A,
BL3A is set to Vcc and the channel of the block to be written is precharged to Vcc-Vth (which becomes smaller than the bit line potential Vcc due to the threshold voltage drop in the selection MOS transistor).

After that, the selection gate SG3 is set to Vss (0V).
Then, the D type selection MOS transistors ST13, ST33, ST53, ... Using the selection gate SG3 as the gate electrode are turned on, but the E type selection MOS transistors ST03,
Since ST23, ST43, ... Are turned off, the channels of the memory cells MC01, MC21, MC41, ... Which are not written become floating at the potential Vcc-Vth charged from the bit line. At this time, the selection gate SG4 remains at Vcc.

Memory cell M in the memory cell unit (1)
The data to be written in C11, MC31, MC51 ... Is the bit line B
L2A, BL4A, BL6A ... For example, when "0" is written in the memory cell MC11, SG4 is Vcc when the bit line BL2A is set to 0V, so that the E type selection MOS transistor ST14 is turned on and the channel of the memory cell MC11 becomes 0V. To write "1" to the memory cell MC11, set the bit line BL1A to 3
When set to V, the E type selection MOS transistor ST14 is turned off and the channel of the memory cell MC11 becomes floating at Vcc-Vth. Bit lines BL1A, BL3A, BL
5A may be set to Vcc or 0V, and may be set to any voltage.

After the selection gate SG3 is changed from Vcc to Vss, the control gates CG1 to CG8 are changed from Vcc to the intermediate potential VM.
(About 10V). Then, since the channels of the memory cells MC01, MC21, MC41, ... That are not written and the memory cells MC11, MC31, MC51 ,, that are written by "1" are in a floating state, capacitive coupling between the control gate and the channel causes an intermediate potential from Vcc-Vth. (About 10V). Memory cell MC for writing "0"
The channel of 11, MC31, MC51, ... Is 0V because the bit line is 0V.

After the channel of the memory cell in which the write unselection and the "1" write are performed is boosted from Vcc-Vth to the intermediate potential, the control gate CG1 is boosted from the intermediate potential VM to the write voltage Vpp (20V). Then, the memory cell MC01 in the memory cell unit (2) which is not written,
The channels of MC, MC41 ... And memory cells MC11, MC31, MC51 ...
Since the control gate CG1 is Vpp (about 20V), these memory cells are not written, but the channels of the memory cells MC11, MC31, MC51, etc. for writing "0" are 0V, and the control gate is Vpp (20V). Therefore, electrons are injected from the substrate to the floating gate, and "0" writing is performed.

Furthermore, SG1 and SG4 are connected to Vcc, SG2 and
SG3 is set to Vss, and bit lines BL1A, BL3A, B
L5A may be set to Vcc. In this case, the bit line BL
From 1A, BL3A, BL5A ... Memory cell unit (2)
Write non-selection potential (Vcc), bit line BL2A,
The write potential (Vcc for "1" write, Vss for "0" write) can be transferred from BL4A, BL5A ... To the memory cell unit (1) substantially at the same time.

When writing to the memory cell unit (2), after precharging the channel of the memory cell unit (1) to Vcc-Vth, the select gate SG3 is set to Vcc, SG.
1, SG2, SG4 may be set to Vss. In this case, the write data to the memory cell unit (2) is transferred from the bit lines BL0A, BL2A, BL4A, BL6A .... Also, SG1 is Vcc, SG2, SG3, SG4 are Vcc
The write data to the memory cell unit (2) may be transferred from the bit lines BL1A, BL3A, BL5A ... With ss.

Further, when the memory cell unit (1) is written, the memory cell unit (2) may be written almost simultaneously. At this time, SG1, SG4 are Vcc, SG
2, when SG3 is set to Vss, the data to be written in the memory cell unit (1) is the bit lines BL2A, BL4A, BL6.
The data transferred from A ... And written in the memory cell unit (2) is transferred from the bit lines BL1A, BL3A, BL5A.

Even if the voltage of the select gate is set as follows, the memory cell units (1) and (2) can be written almost at the same time. When SG1 and SG4 are set to Vss and SG2 and SG3 are set to Vcc, the data to be written in the memory cell unit (2) is the bit lines BL0A, BL2A, BL4A and BL6A.
Data transferred from the memory cell unit (1) are transferred from the bit lines BL1A, BL3A, BL5A.

In this embodiment, when Vss is applied to the selection gate at the time of reading or writing, among the selection MOS transistors having the selection gate as the gate electrode, the E type selection MOS transistor is turned off, but the D type selection MO transistor is turned off.
The S-transistor utilizes turning on. This D
The type selection MOS transistor may be of the I type (threshold voltage is positive). In this case, Vss is applied to the select gate
Instead of applying Vsgl, the E type is turned off but the I type is turned on.

Another writing method of this embodiment will be described below.

Memory cell M in memory cell unit (1)
When writing C11, MC31, MC51 ..., Select gates SG1 and SG4 are set to intermediate potential VM and select gates SG2 and SG2.
SG3 is 0V, control gate CG1 is Vpp, CG2-CG
Set 8 to VM. E type selection MOS transistors ST12, ST using the selection gates SG2, SG3 as gate electrodes
32, ST52 ..., ST03, ST23, ST43 ... are turned off. Therefore, the memory cell unit (1) is connected to the bit line BL2
Conducted with A, BL4A, BL6A ..., Bit lines BL1A,
BL3A, BL5A ... Will become non-conductive. On the other hand, the memory cell unit (2) has bit lines BL0A, BL2A and BL4.
Bit lines BL1A, BL3A not electrically connected to A, BL6A ...
, BL5A ... It becomes conductive.

Therefore, the memory cells MC11, MC31, MC
The write data of 51 ... is the bit lines BL2A, BL4A,
You can give it from BL6A .... That is, when "0" is written, the bit line is set to 0V, and when "1" is written, the bit line is set to the intermediate potential VM. If the threshold voltage of the D type selection MOS transistor is, for example, −15 V,
The potential VM of the bit line in the case of writing "1" can be transferred to the channel of the memory cell.

On the other hand, when writing to the memory cells MC11, MC31, MC51 ... Of the memory cell unit (1), the memory cells MC01, MC21, MC41 ... Of the memory cell unit (2).
May or may not be written. Memory cells MC01, MC21, M of the memory cell unit (2)
When not writing to C41 ..., the bit line BL1
A, BL3A, BL5A ... May be set to VM, and when writing is performed, 0V is applied according to the write data.
It suffices to apply (when writing "0") or VM (when writing "1").

As described in (Example 1), the present invention takes advantage of the fact that it is possible to generate conductive MOS transistors and non-conductive MOS transistors of the selection MOS transistors sharing one selection gate. ing. Therefore, as described in (Example 1), the threshold voltage of the selection MOS transistor and the voltage applied to the selection gate have arbitrariness.

For example, the threshold voltage of the selection MOS transistor having the selection gate SG1 as the gate electrode is 0.7V.
And -0.3V, and the threshold voltage of the selection MOS transistor having SG2 as a gate electrode is -0.5V and -1.5V,
The threshold voltage of the selection MOS transistor having SG3 as its gate electrode is 1.5 V and 3.3 V, and the threshold voltage of the selection MOS transistor having SG4 as its gate electrode is 3.1.
It may be V and 3.6V. In this case, the voltage for turning on half and turning off the other half of the selection MOS transistors having the selection gate as a gate electrode at the time of reading and writing is, for example, 0V for SG1, -1V for SG2, SG.
3 may be 2V and SG4 may be 3.3V. The voltage for turning on all the selection MOS transistors using the selection gate as a gate electrode is, for example, 2.8 V for SG1 and SG2.
Is -0.2V, SG3 is 3.6V, and SG4 is 4V.

As described in the above (Embodiment 1) to (Embodiment 6), according to the present invention, the memory cell unit (1) and the memory cell unit (2) composed of the memory cell portion and the selection MOS transistor are the memory cells. One end side of the unit is shared as shown in FIG. 29 to form a sub-array. For example, as shown in FIG. 30, one end side of the memory cell units (1) and (2) share a contact and are connected to the bit line. Further, both ends of the memory cell units (1) and (2) may be shared to form a sub-array as shown in FIG. In this case, for example, as shown in FIG. 32, both ends of the memory cell unit share a contact and are connected to the bit line.

As means for selecting either the memory cell unit (1) or the memory cell unit (2) at the time of reading or writing, for example, select MOS transistors are provided at both ends of the memory cell portion as shown in FIG. By changing the threshold voltage of the selection MOS transistor sharing the gate electrode between the memory cell units (1) and (2), one of them may be made conductive and the other may be made non-conductive.
Further, as described in the above embodiment, three or four selection MOS transistors may be provided in the memory cell unit, and the threshold voltage of the selection MOS transistor may be set to three or more kinds. Does not have to be. An example of the memory cell unit is shown in FIGS.

In the embodiment, the memory cell portion is the source,
So-called NA in which the drain is shared by adjacent memory cells
I explained the ND cell (Fig. 37 (c)).
The present invention is not limited to D-type cells, and the present invention is effective as long as the memory cell portion is a non-volatile memory cell. Even if the memory cell portion is, for example, a NOR type EEPROM as shown in FIG. 37A, it is effective, and an AND type as shown in FIG.
Cell type EEPROM (H.Kume el.; IEDM Tech.Dig., D
ec.1992, pp.991-993), the present invention is effective, and so-called mask ROM is also effective.

(Embodiment 7) Next, an embodiment will be described.

In this embodiment, memory cells or memory cell units each composed of a memory cell and a selection transistor are arranged as shown in FIG. 46 to form a sub-array. That is, one end of the memory cell unit is connected to the common signal line by sharing contacts with the three memory cell units. The other end of the memory cell unit is also connected to the common signal line by sharing contacts with the three memory cell units as shown in FIG. Then, the sub-arrays are continuously arranged to form a memory cell array as shown in FIG.

As shown in FIGS. 48 and 49, the memory cell unit is composed of a memory cell portion composed of memory cells and a selection transistor. The memory cell units A, B, and C in FIGS. 48 and 49 correspond to one of the memory cell units (1, 2 ,, and 3) in FIGS. 46 and 47, respectively. Yes, for example, A; 1, B; 2, C; 3, or A; 2, B; 3,
C; may be 1). In FIG. 48, the threshold value Vt1 of the E type selection gate may be larger than the threshold value Vt2 of the I type selection gate, for example, Vt1 = 2V and Vt2 = 0.5V. In FIG. 49, the threshold value of the D type selection gate may be -0.8V, for example.

When selecting the memory cell of FIG. 48, there are two types of voltages applied to the select gates SG1, SG2, and S3 in the selected block, and the voltage Vsg for turning on both the E type and the I type.
h (eg Vcc, 3V), and I type turns on, but E
The type is a turn-off voltage Vsgl (for example, 1.5 V). For example, when selecting the memory cell unit A among the three memory cell units, SG1 and SG2 are set to Vsgh.
, SG3 is set to Vsgl, and when the memory cell unit B is selected, SG1 is set to Vsgl and SG2 and SG3 are set to Vsgh. Similarly, when selecting the memory cell unit C,
SG1 and SG3 may be set to Vsgh, and SG2 may be set to Vsgl.

When 0V is applied to the select gate in the non-selected block, all the select transistors in the non-selected block are turned off, so that the bit line does not leak through the non-selected block.

When the memory cell unit is as shown in FIG. 49, the method of selecting the memory cell unit is almost the same as that in the case of FIG. 48, but Vsgl applied in the selected block is selected.
May be 0V. As a result, the E type selection gate is turned off and the D type selection gate is turned on. In addition, it is desirable to turn off the select gate in the non-selected block in order to prevent bit line leakage. Therefore, in order to turn off the D-type select gate, a negative voltage (for example, -1V) is applied to the select gate in the non-selected block. May be applied.

There are various variations in the structure of the memory cell portion, and the examples shown in FIGS. 36 and 37 can be adopted. Further, the present invention is not limited to the EEPROM,
A so-called EPROM or mask ROM is also effective.

This embodiment will be described in detail below by taking a NAND cell type EEPROM as an example.

NAND cell type EEPR according to this embodiment
The configuration of the OM is the same as that shown in FIG.

FIG. 50 shows a memory cell array 1A, and FIG. 51 shows a memory cell array 1B. In the memory cell array (FIGS. 50 and 51) of this embodiment, the source side select gate (second select gate) is connected to the source line of the n-type diffusion layer as in the conventional memory cell array (FIG. 40). Instead, it is in contact with the bit line. That is, at the time of reading, the low resistance bit line plays the role of a source line, so that the reading speed becomes high. Further, since two bit lines are shared by three memory cell columns (three columns), the pitch of the bit lines is 1.5 times that of the conventional one, and the bit lines can be easily processed.

In the memory cell array of this embodiment, one N
The threshold voltages of the two selection MOS transistors connecting the AND cell column and the bit line are set to Vth1 and Vth2 (Vth1>
Vth2) is provided. High threshold voltage Vth1
Select MOS transistor with (for example, 2V) E-typ
e, a selection MOS transistor having a low threshold voltage Vth2 (for example, 0.5 V) is referred to as I-type. The voltage applied to the select gate is a voltage Vsgh (for example, 3V) (V that turns on both the I-type transistor and the E-type transistor).
sgh> Vt1, Vt2), and the voltage at which the I-type transistor turns on but the E-type transistor turns off Vsgl
(For example, 1.5 V) (Vt1>Vsgl> Vt2).

As described above, two kinds of threshold voltages of the selection MOS transistor are provided, and the voltage applied to the selection gate is set to two.
Depending on the type, when writing or reading,
One of the three NAND cell units sharing a contact can be electrically connected to the two bit lines at both ends, and the other memory cell units can be electrically disconnected.

The read and write methods will be specifically described below.

<Read> Memory cell unit of FIG.
When the data of the memory cells MC11, MC41, MC71 ... In (1) are read to the bit lines BL1A, BL3A, BL5A ... First, the bit lines BL1A, BL3A, BL5A.
Are precharged to the bit line read potential VA (for example, 1.8 V), and BL0A, BL2A, BL4A, BL6
Ground A ... to 0V. After precharge, bit line BL
Float 1A, BL3A, BL5A ....

Next, the control gate CG1 is 0V, and CG2-
CG8 is set to Vcc (for example, 3V). The selection gate SG1 is set to Vsgl and the selection gates SG2 and SG3 are set to Vsgh. The other select gates and control gates are set to 0V. In this case, the selection MOS transistors (ST12, ST13, ST) connected to the bit lines BL0A, BL2A, BL4A ...
22, ST23, ST32, ST33, ST42, ST43, ST5
2, ST53 ...) turns on. On the other hand, the bit line BL1A,
The I-type selection MOS transistors ST11, ST41, ST71, ... Connected to BL3A, BL5A.
-type selection MOS transistors ST21, ST31, ST5
1, ST61, ST81 ... are turned off.

Therefore, the memory cells MC11, MC41, MC
If the data written in 71 ... Is "1", the precharged bit lines BL1A, BL3A, BL5A ... Are discharged to the grounded bit lines BL0A, BL2A, BL4A .. Data of the memory cells MC11, MC41, MC71 ... In (1) are read to the bit lines BL1A, BL3A, BL5A. On the other hand, if the data written in the memory cell is "0", the bit lines BL1A, BL3A, BL5A ...
Does not discharge and maintains the precharge potential.

On the other hand, for the memory cells MC21, MC31, MC51, MC61 ... In the memory cell units (2) (3),
E connected to bit lines BL1A, BL3A, BL5A ...
-type selection MOS transistors ST21, ST31, ST5
Since 1, ST61 ... are turned off, memory cells MC21, MC3
The data of 1, MC51, MC61 ... is the bit lines BL1A, B
It is not read to L3A, BL5A ....

Memory cell M in the memory cell unit (2)
The data of C21, MC51, MC81 ...
When reading to BL4A, BL6A ..., Select gates SG1 and SG3 may be set to Vsgh and SG2 may be set to Vsgl. Memory cells MC31, MC61, in the memory cell unit (3)
Data of MC91 ... is transferred to bit lines BL2A, BL4A, BL
When reading to 6A ..., select gates SG1 and SG2 are set to V
sgh and SG3 should be set to Vsgl.

As described above, in the present embodiment, the source line (n-type diffusion layer) of the conventional memory cell array is eliminated, and half of the bit lines are grounded at the time of reading to perform the same role as the conventional source line. The data of the memory cell is read to the remaining half of the bit lines. By using a bit line formed of low resistance poly-Si, Al or the like instead of the source line formed of a conventional high resistance n-type diffusion layer, the problem of source line floating described in (Problem 1) is solved. Solvable.

Here, the read operation will be described in more detail with reference to the timing chart.

FIG. 52 shows the memory cell unit of FIG.
(1) is a timing chart for reading the data written in the memory cells MC11, MC41, MC71, ...

Bit lines BL0A, BL2A, BL4A,
BL6A ... Is connected to the sense amplifier SA1 shown in FIG.
The bit lines BL1A, BL3A, BL5A ... Are connected to the sense amplifier SA2 shown in FIG. The sense amplifier is formed of a CMOS flip-flop controlled by control signals φP and φN.

First, the precharge signals PRA1, PRA2,
PRB2 changes from Vss to Vcc (time t0), and bit line B
L1A, BL3A, BL5A ... Are VA2 (eg 1.7.
V) to (dummy) bit lines BL1B, BL3B, BL
.. are precharged to VB2 (for example, 1.5V) (time t1). VA1 is 0V and bit lines BL0A and B
L2A, BL4A, BL6A ... Are grounded.

When the precharge is completed, PRA2 and PRB2 become Vss, and the bit lines BL1A, BL3A, BL5A ...
Becomes floating. After this, the row decoder 3
Then, a desired voltage is applied to the selection gate and the control gate (time t2). Control gate CG1 is 0V, CG2-CG
8 is Vcc (for example 3V), SG2 and 3 are 3V (Vsg
h), SG1 becomes 1.5V (Vsgl).

Memory cell M in the memory cell unit (1)
The data written in C11, MC41, MC71 ... Is "0".
In this case, since the threshold voltage of the memory cell is positive, no cell current flows, and the potentials of the bit lines BL1A, BL3A, BL5A ... Remain at 1.7V. When the data is "1", cell current flows and bit lines BL1A, BL3A, B
The potential of L5A ... falls to 1.5V or less. Also,
Since the select gate SG1 is 1.5V, the E-type select MOS transistor using SG1 as the gate electrode is turned off, and the data of the memory cell in the memory cell unit (2) (3) is not transferred to the bit line. During this period, the (dummy) bit lines BL1B, BL3B, BL5B ... Are kept at the precharge potential of 1.5V.

After that, at time t3, φP is 3 V and φN is 0V.
V, the CMOS flip-flop FF is inactivated, and φE becomes 3V at time t4, so that C of SA2
The MOS flip-flop FF is equalized and the nodes N1 and N2 become Vcc / 2 (for example, 1.5V). At time t5, SS2, SA and SB become 3V, and after the bit line and the sense amplifier are connected, φN changes from 0V to 3V, φP
Changes from 3V to 0V and bit lines BL1A, BL3A, B
L5A ... And bit lines BL1B, BL3B, BL5B ...
The potential difference is amplified (time t6).

That is, the memory cells MC11, MC41, MC
If "0" is written in 71 ..., Node N of SA2
1 becomes 3V, node N2 becomes 0V, and memory cell MC1
If "1" is written in 1, MC31, MC51 ...
The node N1 becomes 0V and the node N2 becomes 3V. afterwards,
When the column selection signal CSL changes from 0V to 3V, CMO
The data latched in the S flip-flop is IO,
/ IO (time t7).

Through the read operation, the bit lines BL0A,
BL2A, BL4A, BL6A ... Are grounded to 0V. That is, every other bit line is grounded. Therefore, the distance between the read bit lines is twice as large as that when the bit lines are not grounded, and the noise caused by the capacitive coupling between the bit lines is significantly reduced (Japanese Patent Application No. 4-276393). Also, PRB1 is set to Vcc, VB1
The bit lines BL0B and BL2B
, BL4B, BL6B ... May be grounded. As a result, it is possible to reduce capacitive coupling noise between bit lines during amplification of the bit line potential.

FIG. 53 shows the memory cell unit of FIG.
It is a timing chart at the time of reading the data written in memory cell MC21, MC51, MC81 ... in (2).

First, the precharge signals PRA1, PRA2,
PRB1 changes from Vss to Vcc (time t0), and bit line B
L2A, BL4A ... Are precharged to VA1 (for example 1.7V) and (dummy) bit lines BL2B, BL4B ... are precharged to VB1 (for example 1.5V) (time t1). VA2 is 0V, and the bit lines BL1A, BL3A, BL5A ... Are grounded.

When the precharge is completed, PRA1 and PRB1 become Vss, and the bit lines BL2A, BL4A ... Are brought into a floating state. Thereafter, a desired voltage is applied from the row decoder 3 to the select gate and the control gate (time t2
). Control gate CG1 is 0V, CG2-CG8 is Vcc
(Eg 3V), SG1, 3 are 3V (Vsgh), SG2
Is 1.5 V (Vsgl).

When the data written in the memory cells MC21, MC51, MC81 ... Is "0", the threshold voltage of the memory cell is positive, so that the cell current does not flow and the bit line BL2A.
, BL4A ... The electric potential remains 1.7V. When the data is "1", cell current flows and bit line BL2A
, BL4A ... falls to 1.5 V or less.
Further, since the selection gate SG2 is 1.5V, the E-type selection MOS transistor using SG2 as a gate electrode is turned off, and the data of the memory cell in the memory cell unit (1) (3) is not transferred to the bit line. During this period (dummy) bit lines BL2B, BL4B ... Precharge potential 1.5V
Kept in.

After that, at time t3, φP is 3V and φN is 0V.
V, the CMOS flip-flop FF is inactivated, and φE becomes 3V at time t4, so that C of SA1
The MOS flip-flop FF is equalized and the nodes N1 and N2 become Vcc / 2 (for example, 1.5V). At time t5, SS1, SA, SB become 3V, and after the bit line and the sense amplifier are connected, φN changes from 0V to 3V, φP
Changes from 3V to 0V, and bit lines BL2A, BL4A ...
And the potential difference between the bit lines BL2B, BL4B ... Is amplified (time t6).

That is, the memory cells MC21, MC51, MC
If "0" is written in 81 ..., Node N of SA1
1 becomes 3V, node N2 becomes 0V, and if "1" is written, node N1 becomes 0V and node N2 becomes 3V. After that, when the column selection signal CSL changes from 0V to 3V, the data latched by the CMOS flip-flop is output to IO and / IO (time t7).

Through the read operation, BL1A and BL3A
, BL5A ... Are grounded to 0V, so that noise due to capacitive coupling between bit lines is reduced.

Similarly, the data of the memory cells MC31, MC61, MC91, ... In the memory cell unit (3) are transferred to the bit line B.
FIG. 54 shows the timing for reading to L2A, BL4A, BL6A .... If SG3 is set to Vsgl and SG1 and SG2 are set to Vsgh, the memory cell unit (3) can be selected and the memory cell units (1) and (2) can be deselected.

The timing of the read operation is arbitrary. For example, as shown in FIG. 55, at time t5, the transfer gate connecting the bit line and the sense amplifier is turned on to set the potentials of the bit line and the dummy bit line to the node N of the sense amplifier.
The transfer gate may be turned off after the transfer to 1, N2. In this case, since the bit line and the dummy bit line are separated from the sense amplifier, the load capacitance of the sense amplifier is reduced and the nodes N1 and N are latched during sensing and data latch.
The potential of 2 will be determined rapidly.

In the above embodiment, for example, the memory cells MC11,
When reading MC41, MC71, ... Bit lines BL1A,
BL3A, BL5A ... Precharge, bit line BL0
A, BL2A, BL4A ... Are grounded, and the data of the memory cells are read to the bit lines BL1A, BL3A, BL5A. Which of the bit lines connected to both ends of the memory cell unit is used to read data is arbitrary. For example, when the memory cells MC11, MC41, MC71 ... Are read, the bit lines BL0A, BL2A, BL4A ... Are precharged, the bit lines BL1A, BL3A, BL5A ... Are grounded, and the data of the memory cells are transferred to the bit lines BL0A, BL2.
You may read to A, BL4A ...

<Write> The write operation of this embodiment will be described below.

A writing procedure for writing to the memory cells MC11, MC41, MC71 ... In the memory cell unit (1) of FIG. 50 will be described below.

The selection gates SG2 and SG3 are set to 0V, and all the selection MOS transistors having the selection gate SG2 as a gate electrode are turned off. SG1, CG1 to CG8 are set to Vc
c, the bit lines BL1A, BL3A, BL5A ... Are set to Vcc, and the channel of the page to be written is set to Vcc-Vth (which is smaller than the bit line potential Vcc due to the threshold voltage drop in the selected MOS transistor). To charge. The bit lines BL0A, BL2A, BL4A ... May be set to Vcc or 0V, and may be set to any voltage.

After that, when the selection gate SG1 is set to Vsgl (for example, 1.5 V), the I-type selection MOS transistors ST11, ST41, ST71, ... Are turned on, but the E-type selection MOS transistors are turned off. The channels of the cells MC21, MC31, MC51, MC61 ... Float at the potential Vcc-Vth charged from the bit line.

Memory cell M in memory cell unit (1)
The data to be written in C11, MC41, MC71 ... Is given from the bit lines BL1A, BL3A, BL5A. For example,
When "0" is written in the memory cell MC11, if the bit line BL1A is set to 0V, the I-type selection MOS transistor ST11 turns on and the channel of the memory cell MC11 becomes 0V. When writing "1" to the memory cell MC11, if the bit line BL1A is set to 3V, I-typ
e The selection MOS transistor ST11 is turned off and the memory cell M
The channel of C11 becomes floating at Vcc-Vth.
The bit lines BL0A, BL2A, BL4A ... May be set to Vcc or 0V, and may be set to any voltage.

The selection gate SG1 is changed from Vcc to Vsgl (I-t
ype A voltage higher than the threshold voltage of the selection MOS transistor but lower than that of the E-type selection MOS transistor. Control gates CG1 to C
G8 is changed from Vcc to the intermediate potential VM (about 10V). Then, the memory cells MC21, MC31, M which are not written
Since the channels of C51, MC61 ... And the memory cells MC11, MC41, MC71 ... In which "1" is written are in a floating state, Vcc-Vth rises to an intermediate potential (about 8V) due to capacitive coupling between the control gate and the channel. ..
Memory cells MC11, MC41, MC for writing "0"
The channel of 71 ... Is 0V because the bit line is 0V.

After the channel of the memory cell in which the write unselection and the "1" write are performed is boosted from Vcc-Vth to the intermediate potential, the control gate CG1 is boosted from the intermediate potential VM to the write voltage Vpp (20V). Then, the channels of the memory cells in the memory cell units (2) and (3) that are not written and the channels of the memory cells in the memory cell unit (1) that perform "1" writing are at the intermediate potential (about 8 V), and the control gate CG1 is These memory cells are not written because it is (about 20V), but the channel of the memory cell for writing "0" is 0V and the control gate is Vpp (about 20V), so electrons are injected from the substrate to the floating gate and "0" is written. Writing is done.

Now, the write operation of this embodiment will be described in more detail with reference to a timing chart. FIG. 56 is a timing chart when writing to the memory cell MC11 (and memory cells MC41, MC71 ...) In the memory cell unit (1).

Memory cell M in memory cell unit (1)
The data to be written in C11, MC41, MC71 ... Is latched in the sense amplifier circuit (SA2 in FIG. 7). That is, in the case of writing "0", the node N1 has 0V and N2.
Is 3V, and when writing "1", the node N1 is 3V,
N2 becomes 0V.

Upon entering the write operation, first, at time t1, S
G1 is set to Vss, SG2, SG3, and CG1 to CG8 are set to Vcc. In this embodiment, when writing to the memory cells MC11, MC41, MC71 ... In the memory cell unit (1), the memory cells in the memory cell units (2) and (3) are not written. In this example, memory cells MC21, MC
31, MC51, MC61 ... Channels are connected to bit lines BL0A,
Charge from BL2A, BL4A ....

In this embodiment, bit lines BL0A and BL2
A, BL4A ... Are VA1 of the sense amplifier SA1 of FIG.
To Vcc. As a result, the channel of the non-selected memory cell is charged to Vcc-Vth. At this time, the channel of the memory cell for writing is also charged to Vcc-Vth.
As described above, the method of charging the channels of the memory cells of the memory cell units (2) and (3) to Vcc (-Vth) is BL
You may charge from 0A, BL2A, BL4A ...
You may charge from L1A, BL3A, BL5A.

On the other hand, bit lines BL1A, BL3A, BL
A potential of Vcc or Vss (0V) is applied to 5A ... In accordance with the data latched in the sense amplifier circuit SA2. As a result, for example, "0" is written in the memory cell MC11.
When writing is performed, the bit line BL1A is set to 0V and the channel of the memory cell MC11 is set to 0V. When "1" is written in the memory cell MC11, the bit line BL1A is set to Vcc (for example, 3V) to charge the channel of the memory cell MC11 to Vcc-Vth.

After charging the bit line, the selection gate SG1 is set to Vsg.
l (for example, 1.5 V), SG2, 3 to Vss (for example, 0
V). All selection MOS transistors having the selection gates SG2 and SG3 as gate electrodes are turned off. Since the selection MOS transistor using SG1 as the gate electrode in the memory cell unit (2) (3) which is not programmed is E-type, it is turned off, and the channel of the memory cell in the memory cell unit (2) (3) is Vcc- Floating at Vth.

Memory cell MC11 for writing "1",
MC41, MC71 ... Selection MOS transistors ST11, S
The drains on the memory cell side of T41, ST71 ... Are Vcc-Vth.
(For example, the threshold voltage of I-type transistor is 0.5
V is 3-0.5 = 2.5V), the source on the bit line contact side is Vcc (for example, 3V), and the selection gate SG
Since 1 is Vsgl (for example, 1.5 V), the selection MOS transistors ST11, ST41, ST71 ... Are turned off. As a result, the memory cells MC11,
The channels of MC41, MC71 ... Become floating.

When "0" is written in the memory cells MC11, MC41, MC71 ..., The selection gate SG1 of the selection MOS transistors ST11, ST41, ST71 ... Is Vsg.
l (for example, 1.5 V) and the source and drain are 0 V, so that the selection MOS transistors ST11, ST41, ST71 ...
Is turned on, and the channel of the memory cell is kept at 0V.

The select gate SG1 is set to Vsgl (for example, 1.5
V), the control gates CG1 to CG8 are changed from Vcc to the intermediate potential VM (about 10 V) at time t2. Then, since the channels of the memory cells not selected for writing and the memory cells MC11, MC41, MC71 ... In which "1" is written are in a floating state, capacitive coupling between the control gate and the channel causes an intermediate potential (about 8V) from Vcc-Vth. ) To rise. Memory cell MC for writing "0"
The channel of 11, MC41, MC71 ... Is 0V because the bit line is 0V.

After the channel of the memory cell in which the write unselection and the "1" write are performed is boosted from Vcc-Vth to the intermediate potential, the control gate CG1 is set to the intermediate potential VM at time t3.
To write voltage Vpp (20V). Then, the memory cells in the memory cell units (2) and (3) that are not written and the memory cells MC11 and M that are written "1"
Channels of C41, MC71 ... Have an intermediate potential (about 10V),
Since the control gate CG1 is Vpp (about 20 V), these memory cells are not written, but the channels of the memory cells MC11, MC41, MC71, ...
Since V and the control gate are Vpp (about 20 V), electrons are injected from the substrate to the floating gate and "0" writing is performed.

After the writing is completed, the control gate, the selection gate and the bit line are sequentially discharged to complete the writing operation.

Memory cell M in the memory cell unit (2)
When writing C21, MC51, MC81 ... Similarly, the channels of the memory cells of the memory cell units (1) and (3) are set to Vcc.
(Or Vcc-Vth), the select gate SG1 is set to Vs.
s, SG2 to Vsgl, SG3 to Vsgh, and bit line B
By setting L2A, BL4A, BL6A ... To Vcc or Vss, data may be transferred to the memory cells MC21, MC51, MC81.

Memory cell M in memory cell unit (3)
When writing C31, MC61, MC91, ... Similarly, the channels of the memory cells of the memory cell units (1) and (2) are set to Vcc.
(Or Vcc-Vth), the select gate SG1 is set to Vs.
s, SG3 to Vsgl, SG2 to Vsgh, and bit line B
By setting L2A, BL4A, BL6A ... To Vcc or Vss, data may be transferred to the memory cells MC31, MC61, MC91.

After the writing is completed, a write verify operation is performed to check whether the writing is sufficiently performed (FIG. 57). In the verify read of the memory cell unit (1), the select gate SG1 is set to Vsgl, SG2, in order to select only the memory cell unit (1) as in the read.
3 becomes Vsgh. In the verify read, after discharging the bit line from the precharge potential, the bit line is recharged by the write data, and then the rewrite data is latched in the sense amplifier by sensing the bit line potential. For details of the operation of the sense amplifier during the verify operation and recharging of the bit line, see, for example, the literature (T. Tanak
a, et al., IEEE J. Solid-State Circuit, vol29, pp. 1366
-1373,1994).

In the above-mentioned embodiment, writing is simultaneously performed to 1/3 of the memory cells in the column direction. That is, of the three memory cell units, only one memory cell unit performs writing simultaneously.

According to this embodiment, it is possible to write to two memory cell units out of three memory cell units almost at the same time. For example, the selection gate SG1,
SG2 is Vsgl (for example, 1.5V), SG3 is Vsg
You can set it to h. Then, select gates SG1 and SG2
The E-type selection MOS transistor having the gate electrode of is turned off, and the I-type selection MOS transistor is turned on. Memory cells MC11, M of the memory cell unit (1)
The write data of C41, MC71 ... is the bit line BL1A,
Transferred from BL3A, BL5A ....

That is, when "0" is written, the bit line and the channel of the memory cell to be written become 0V,
In the case of writing "1", the bit line becomes Vcc and the channel becomes floating at Vcc-Vth. Similarly, the memory cells MC21, MC51, M of the memory cell unit (2) are
The write data of C81 ... is the bit lines BL2A and BL4.
Transferred from A, BL6A ....

Similarly, SG1 and SG3 are Vsgl, and SG2 is Vsgl.
If sgh is set, writing can be performed in the memory cell units (1) and (3) almost at the same time. In this case, the bit lines BL1A and BL3 are connected to the memory cells of the memory cell unit (1).
Data is transferred from A, BL5A ... To the memory cells of the memory cell unit (3) through the bit lines BL2A, BL4A, BL6A.

After the write operation, verify read is performed to check whether the writing has been sufficiently performed. In the verify read operation of the above embodiment, the data of one memory cell is read using two bit lines. That is, 3
Data of one memory cell unit of one memory cell unit is read out almost simultaneously. Therefore, in the case of writing two memory cell units almost at the same time, the verify read operation is performed twice for each write operation.

In the method of writing two memory cell units almost at the same time, since the verify read is performed for each memory cell unit, the total time for writing two memory cell units is about Tpr + 2Tvfy (Tpr: write pulse width, Tvfy: 1 time). Verify read time). On the other hand, in the method of writing one memory cell unit almost at the same time, the total time for writing the data of two memory cell units is about 2 (Tpr + Tvfy), so 2
The writing operation is faster when the data in the memory cell unit is written simultaneously.

In the above embodiment, a sense amplifier is connected for each bit line, but a so-called shared sense amplifier system in which one sense amplifier is connected to two bit lines (see FIG.
It may be 5). The timing charts for writing and reading in this case are almost the same as those in the above embodiment. The memory cell units may be arranged in the memory cell array as shown in FIG. 58, for example.

According to the present invention, among the selection MOS transistors sharing one selection gate, it is possible to generate conductive MOS transistors and non-conductive MOS transistors, and prepare three such select gates. This makes it possible to easily realize a selected memory cell and a non-selected memory cell within a memory cell having the same selection gate.

Therefore, the threshold voltage of the selection MOS transistor and the voltage applied to the selection gate are arbitrary. The selection MOS transistor connected to one end of the memory cell has two threshold voltages of Vtd1 and Vtd2 (Vtd1> Vtd2), and the voltage applied to this selection gate is Vtd1.
sghd (Vsghd> Vtd1), Vsgld (Vtd1>Vsgld> V
td2), and one of the selection MOS transistors connected in series to the other end side of the memory cell is Vts1, V
It has two threshold voltages of ts2 (Vts1> Vts2), and the voltage applied to this selection gate is Vsghs (Vsghs>
Vts1) and Vsgls (Vts1>Vsgls> Vts2). The other selection MOS transistor connected in series has two threshold voltages of Vtp1 and Vtp2 (Vtp1> Vtp2) and is applied to this selection gate. The voltage to be applied is Vsghp
(Vsghp> Vtp1), Vsglp (Vtp1>Vsglp> Vtp2
).

As in the above embodiment, Vtd1 = Vts1 = Vtp
1, Vtd2 = Vts2 = Vtp2, Vsghd = Vsghs = Vsgh
It is not necessary that p, Vsgld = Vsgls = Vsglp, and there is great arbitrariness in how to set the threshold voltage and the select gate applied voltage. For example, the selection MO on one end side of the memory cell
The threshold voltage of the S transistor is set to two types, 2V and 0.5V, and the threshold voltage of one selection MOS transistor connected in series on the other end side of the memory cell is set to 2.5V and 1V, and the other is set to the other. There are two kinds of thresholds, 0.8V and 3.5V, the voltage applied to the select gate on one end side of the memory cell is Vsgh = 3V, Vsgl = 1.5V, and the other end of the memory cell is connected in series. The voltage applied to one side of the gate is V
sgh = 3V, Vsgl = 1.2V, and the voltage applied to the other may be Vsgh = 4V, Vsgl = 3V.

The threshold voltages of the three selection MOS transistors connected to one NAND string may be substantially the same. For example, three selection Ms connected to a certain NAND string
The threshold voltage of the OS transistor is 0.8 V, this NA
The threshold voltage of the select MOS transistor on one end side of the adjacent NAND cell sharing the gate electrode of the select MOS transistor with the ND column is 0.2 V, and the two select MOS transistors connected in series on the other end side of the memory cell are connected. The threshold voltages are 1.4V and 0.8V, the voltages applied to the select gates on one end side of the NAND cells are Vsgh = 3V, Vsgl = 0.
5V, the voltage applied to two select gates connected in series on the other end side of the NAND cell is Vsgh = 3V, Vsgl = 1.2
It may be V. Of course, the threshold value of the select gate may be a negative value, and the select gate applied voltage may be a negative voltage.

If Vsgh is made larger than Vcc, selection M
Since the conductance of the OS transistor increases (that is, the resistance decreases) and the cell current flowing through the NAND cell string increases during reading, the bit line discharge time is shortened, and as a result, read / write verify read speeds up. To be done. Vsgh may be boosted from Vcc by a booster circuit in the chip, for example.

The larger value of the threshold voltages of the selection MOS transistors may be set to a voltage higher than the power supply voltage Vcc (eg 3.5V). In this case, a selection MOS having a threshold voltage at the time of reading or verify reading
In order to turn on the transistor, for example, a booster circuit inside the chip may be used to apply, for example, 4V to the select gate.

The first method for changing the threshold voltage is
The various methods described in the embodiments can be accepted.

In the above embodiment, when writing to the memory cell unit (2) or the memory cell unit (3), SG1
0 V is applied to the selection MOS transistor. However, if the selection MOS transistor using this selection gate as the gate electrode is of I-type and the threshold voltage Vt2 is about 0.1 V (or a negative threshold voltage), this The selection MOS transistor is not completely cut off, and the cell current flows. As a result, the channel of the memory cell not selected for writing is not boosted from Vcc-Vth to the intermediate potential VM, or even if boosted, the cell current flows and the potential drops from VM. In any case, since the channel of the memory cell not selected for writing falls from VM, it is erroneously written to "0".

In order to improve the cut-off characteristic of the I-type transistor, the bit line to which write data is not given at the time of writing (BL1A when writing to the memory cell unit (2) or (3) in FIG. 50, BL3A,
For example, a voltage of about 0.5V may be applied to BL5A. If 0.5V is applied to the source of the selection MOS transistor, the potential difference between the source and the substrate becomes -0.5V, and the threshold voltage of the I-type transistor increases due to the substrate bias effect. The cut-off characteristic when 0 V is applied to is improved.

A method of reducing the substrate concentration is conceivable in order to set the lower threshold voltage (I-type) of the selection MOS transistors to 0.5 V, for example. In an I-type transistor with a low substrate concentration, when a drain voltage is applied without applying a gate voltage, a depletion layer between the drain and substrate expands, resulting in a drain-
There is a problem that the depletion layer between the substrate and the depletion layer between the source and the substrate are easily connected (punch through). I-typ
The channel length L of the I-type selection MOS transistor may be increased in order to increase the punch-through breakdown voltage of the selection MOS transistor of e.

(Embodiment 8) The threshold value of the selection MOS transistor may be as shown in FIG. The threshold of E-type is, for example, 2V, and the threshold of I-type is, for example, 0.5V.
The threshold values of V and D-type may be set to -2V. The method of reading and writing is almost the same as that of the seventh embodiment, except that the D-type selection MOS transistor is made conductive but E
The voltage Vsgl for turning off -type may be 0V. That is, when the memory cell unit (1) is selected for reading, SG1 is 1.5V, SG2 and SG3 are 3V, when memory cell unit (2) is selected, SG1 and SG3 are 3V, SG2 is 0V, When the memory cell unit (3) is selected, SG1 and SG2 may be set to 3V and SG3 may be set to 0V.

In writing, as in the first embodiment, SG1 is written in the case of writing in the memory cell unit (1).
Is 1.5V, SG2 and SG3 are 0V, SG1 and SG2 are 0V and SG when the memory cell unit (2) is written.
3 is 3V, SG1 and SG3 are 0V, and SG2 is 3V when the memory cell unit (3) is written. In addition, if the threshold value of the selection MOS transistor is set to about -8 V, when writing the memory cell units (2) and (3), the channel of the memory cell of the non-writing type such as the conventional NAND type EEPROM is changed. A writing method (not floating) can be performed.

For example, when writing to the memory cell MC51, SG1 and SG2 are set to 0V and SG3 is set to VM10 (10V).
), CG1 is Vpp, CG2-CG8 is VM10,
When writing "1", BL4A is set to VM8 (about 8V),
In the case of writing "0", it may be set to 0V. Then,
The channel of the memory cell in which "1" is written is charged from the bit line to the intermediate potential (about 8V). on the other hand,
Memory cell unit that does not write at this time (1) (3)
As for the above, as described in the seventh embodiment, the channel of the memory cell may be set to Vcc floating and the channel of the memory cell may be set to the write non-selection potential (VM8) by coupling with the control gate.

In addition, various modifications can be made without departing from the scope of the present invention.

[0289]

As described above, according to the present invention, both the one end side and the other end side of a memory cell unit share a contact with another memory cell unit, respectively.
Since it is connected to the second common signal line, it has a low resistance of Al.
By using the bit line formed by, for example, the source line formed of the conventional high resistance n-type diffusion layer, the problem of floating of the source line can be solved. Therefore, the resistance of the source line can be reduced to reduce the floating of the source line, and as a result, it is possible to realize a nonvolatile semiconductor memory device that can speed up random access.

Further, by appropriately selecting the E type and I type as the selection MOS transistors for connecting the one end side and the other end side of the memory cell unit to the common signal line, the high speed operation can be achieved without increasing the chip area. The memory cell array capable of random access can be realized.
Furthermore, the pitch of the memory cells in the column direction can be reduced by shifting the positions of the bit line contacts in the adjacent NAND strings. That is, the adjacent NAND
By shifting the position of the bit line contact in the column, the pitch of the memory cells in the column direction can be reduced,
It is possible to realize a nonvolatile semiconductor memory device having a high-density memory cell structure.

[Brief description of drawings]

FIG. 1 is a NAND cell type EEPR according to a first embodiment.
Block diagram showing the configuration of the OM

FIG. 2 is a diagram showing a configuration of a memory cell array of the first embodiment.

FIG. 3 is a diagram showing a configuration of a memory cell array of the first embodiment.

FIG. 4 is an n-type diffusion layer of the memory cell array of the first embodiment, source / gate / drain regions of the memory cell, and n.
Diagram showing contacts connecting type diffusion layer and bit line

FIG. 5 is a timing chart for explaining a data read operation of the first embodiment.

FIG. 6 is a circuit diagram of a sense amplifier circuit of the first embodiment.

FIG. 7 is a circuit diagram of a sense amplifier circuit according to the first embodiment.

FIG. 8 is a timing chart for explaining the data read operation of the first embodiment.

FIG. 9 is a timing chart for explaining the data read operation of the first embodiment.

FIG. 10 is a timing chart for explaining the data write operation of the first embodiment.

FIG. 11 is a timing chart for explaining the data write operation of the first embodiment.

FIG. 12 is a timing chart for explaining the data write operation of the first embodiment.

FIG. 13 is a diagram showing a configuration of a memory cell array of the first embodiment.

FIG. 14 is a diagram showing a configuration of a memory cell array of the first embodiment.

FIG. 15 is a circuit diagram of the sense amplifier circuit of the first embodiment.

FIG. 16 is a diagram showing a configuration of a memory cell array according to a second embodiment.

FIG. 17 is a diagram showing a configuration of a memory cell array according to a second embodiment.

FIG. 18 is an n-type diffusion layer of the memory cell array of the first embodiment, source / gate / drain regions of the memory cell, and
Diagram showing a contact connecting an n-type diffusion layer and a bit line

FIG. 19 is a timing chart for explaining a data read operation of the second embodiment.

FIG. 20 is a timing chart for explaining a data read operation of the second embodiment.

FIG. 21 is a timing chart for explaining the data write operation of the second embodiment.

FIG. 22 is a timing chart for explaining the data write operation of the second embodiment.

FIG. 23 is a diagram showing a configuration of a memory cell array according to a second embodiment.

FIG. 24 is a diagram showing a configuration of a memory cell array of a second embodiment.

FIG. 25 is a diagram showing a configuration of a memory cell array according to a third embodiment.

FIG. 26 is a diagram showing a configuration of a memory cell array of a fourth embodiment.

FIG. 27 is a diagram showing a configuration of a memory cell array of a fifth embodiment.

FIG. 28 is a diagram showing a configuration of a memory cell array of a sixth embodiment.

FIG. 29 is a diagram of a memory cell array for explaining the second aspect of the present invention.

FIG. 30 is a diagram of a memory cell array for explaining the second aspect of the present invention.

FIG. 31 is a diagram of a memory cell array for explaining claim 3 of the present invention.

FIG. 32 is a diagram of a memory cell array for explaining claim 3 of the present invention.

FIG. 33 is a diagram of a memory cell array for explaining the seventh aspect of the present invention.

FIG. 34 is a diagram showing an embodiment of a memory cell unit and a memory cell portion of the present invention.

FIG. 35 is a diagram showing an embodiment of a memory cell unit and a memory cell portion of the present invention.

FIG. 36 is a diagram showing an embodiment of a memory cell unit and a memory cell portion of the present invention.

FIG. 37 is a diagram showing an embodiment of a memory cell unit and a memory cell portion of the present invention.

FIG. 38 is a plan view and an equivalent circuit diagram showing a cell configuration of a conventional NAND type EEPROM.

39 is a cross-sectional view taken along the line A-A ′ and the line B-B ′ of FIG.

FIG. 40 is an equivalent circuit diagram of a memory cell array of a conventional NAND type EEPROM.

FIG. 41 is a diagram showing an n-type diffusion layer of a conventional NAND-type EEPROM memory cell array, source / gate / drain regions of the memory cell, and a contact connecting the n-type diffusion layer and a bit line.

FIG. 42 is a diagram for explaining a conventional problem, showing a relationship between a threshold value of a memory cell and a bit line discharge time.

FIG. 43 is a diagram showing a memory cell array configuration for explaining a conventional problem.

FIG. 44 is a diagram showing a memory cell array configuration for explaining a conventional problem.

FIG. 45 is a view for explaining a conventional problem and is a diagram showing a relationship between a threshold value of a memory cell and a bit line discharge time.

FIG. 46 is a diagram showing the configuration of a sub-array according to the seventh embodiment.

FIG. 47 is a diagram showing a configuration of a memory cell array according to a seventh embodiment.

FIG. 48 is a diagram showing the configuration of a memory cell unit of the seventh embodiment.

FIG. 49 is a diagram showing the configuration of a memory cell unit of the seventh embodiment.

FIG. 50 is a diagram showing the configuration of a memory cell portion of the seventh embodiment.

FIG. 51 is a diagram showing a configuration of a memory cell portion of the seventh embodiment.

FIG. 52 is a timing chart for explaining a data read operation of the seventh embodiment.

FIG. 53 is a timing chart for explaining a data read operation of the seventh embodiment.

FIG. 54 is a timing chart for explaining a data read operation of the seventh embodiment.

FIG. 55 is a timing chart for explaining the data read operation of the seventh embodiment.

FIG. 56 is a timing chart for explaining the data write operation of the seventh embodiment.

FIG. 57 is a timing chart for explaining the write verify read operation of the seventh embodiment.

FIG. 58 is a diagram showing another configuration example of the memory cell array according to the seventh embodiment.

FIG. 59 is a diagram showing a configuration of a memory cell array according to an eighth embodiment.

[Explanation of symbols]

1 ... Memory cell array 2. Sense amplifier circuit 3 ... Row decoder 4 column decoder 5 ... Address buffer 6 ... I / O sense amplifier 7 ... Data input / output buffer 8 ... Substrate potential control circuit

─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Koji Sakui 1 Komukai Toshiba Town, Komukai-shi, Kawasaki City, Kanagawa Prefecture Toshiba Research and Development Center (56) Reference JP-A-2-74069 (JP, A) JP-A-2-177199 (JP, A) JP-A-2-83971 (JP, A) JP-A-58-18959 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H01L 29/788-29/792 H01L 27/112-27/115 H01L 21/8247 G11C 16/00-16/34

Claims (31)

(57) [Claims] 1. A first and a second common signal line, a plurality of word lines, a memory cell array in which a plurality of memory cell units are arranged in a matrix, and each memory cell unit is at least one nonvolatile memory. A memory cell unit having cells, one end side of the memory cell unit is connected to the first common signal line, a plurality of memory cell units sharing the word line, the other end side of the memory cell unit, A nonvolatile semiconductor memory device, wherein a plurality of memory cell units sharing the word line are connected to the second common signal line. 2. A memory cell section comprising one or a plurality of non-volatile memory cells, and one or a plurality of selection MOS transistors for electrically connecting the memory cell section to a common signal line. In a nonvolatile semiconductor memory device having a memory cell array in which memory cell units are arranged in a matrix, a plurality of memory cell units sharing a word line are connected to a first common signal line on one end side of the memory cell unit. , The other end side of the memory cell unit shares a word line, and one or a plurality of memory cell units not connected to the one end side of the memory cell unit are connected to the second common signal line. A non-volatile semiconductor memory device characterized by the above. 3. A memory cell section comprising one or a plurality of non-volatile memory cells, and one or a plurality of selection MOS transistors for electrically connecting the memory cell section to a common signal line. In a non-volatile semiconductor memory device having a memory cell array in which memory cell units are arranged in a matrix, one end side of the memory cell unit has a plurality of memory cell units sharing a word line and serves as a first common signal line. The other end side of the memory cell unit shares a word line, and one or more memory cell units connected to one end side of the memory cell unit are connected to the second common signal line. A non-volatile semiconductor memory device characterized by: 4. A memory cell section composed of one or a plurality of non-volatile memory cells, and one or a plurality of selection MOS transistors for electrically connecting the memory cell section to a common signal line. In a nonvolatile semiconductor memory device having a memory cell array in which memory cell units are arranged in a matrix, a plurality of memory cell units sharing a word line are connected to a first common signal line on one end side of the memory cell unit. The one end side of the memory cell unit is connected to the other end side of the memory cell unit, the one or more memory cell units sharing a word line and not connected to the one end side of the memory cell unit. A non-volatile semiconductor memory device, characterized in that one or a plurality of memory cell units thus formed are connected to a second common signal line. 5. A non-volatile semiconductor memory device having a memory cell array in which memory cell units each including a memory cell portion composed of one or a plurality of non-volatile memory cells are arranged in a matrix. A plurality of memory cell units sharing a word line are connected to a first common signal line on one end side, and a plurality of memory cell units sharing a word line are connected to a second common signal line on the other end side. A nonvolatile semiconductor memory device characterized by being connected to a communication line. 6. When reading a memory cell portion in the memory cell unit, a first common signal line connected to one end side of the memory cell unit is set to a read potential, and a second common signal line connected to the other end side of the memory cell unit is connected. 6. The non-volatile semiconductor memory device according to claim 1, wherein the common signal line of is maintained at a read non-selection potential. 7. When writing into a memory cell portion in the memory cell unit, a first common signal line connected to one end side of the memory cell unit is written with "1" write potential or "0" according to write data. 6. The nonvolatile semiconductor memory device according to claim 1, wherein the second common signal line connected to the other end of the memory cell unit is kept at a write non-select potential. 8. When a read or write operation is performed on a memory cell portion in the memory cell unit, a select MOS transistor in a memory cell unit of a non-selected block in which read or write is not performed is turned off. 6. The non-volatile semiconductor memory device according to claim 2, wherein a non-selection gate voltage is applied to the selection gate of the non-selection block. 9. The memory cell unit, wherein the memory cell unit is composed of one or a plurality of non-volatile memory cells, and a first selection MOS transistor for electrically connecting the memory cell unit to a first common signal line. And a second selection MOS transistor having a threshold voltage different from that of the first selection MOS transistor for electrically connecting the memory cell section and the second common signal line.
~ The non-volatile semiconductor memory device according to claim 5. 10. A memory cell unit in which the memory cell unit is composed of one or a plurality of non-volatile memory cells, and a first selection MOS transistor for electrically connecting the memory cell unit to a first common signal line. , A second selection MOS transistor for electrically connecting the memory cell section and a second common signal line, and the first selection MOS transistor has a first threshold voltage V
a first memory cell unit having th1 and a second selection MOS transistor having a second threshold voltage Vth2; and a first selection MOS transistor having a third threshold voltage Vth.
a second memory cell unit having th3 and a second selection MOS transistor having a fourth threshold voltage Vth4, a gate electrode of the first selection MOS transistor and a gate electrode of the second selection MOS transistor, respectively. The sub-array is shared by the first and second select gates, and the first threshold voltage Vth1 is equal to the third threshold voltage Vt.
4. The non-volatile according to claim 1, wherein the second threshold voltage Vth2 is larger than h3 and smaller than the fourth threshold voltage Vth4. Semiconductor memory device. 11. When reading the memory cell portion of the first memory cell unit, the first memory cell unit of the first memory cell unit is read.
And the second selection MOS transistor is made conductive, and the first or second selection MOS of the second memory cell unit is set.
At least one of the transistors is in a non-conducting state, and at the time of reading the memory cell portion of the second memory cell unit, at least one of the first and second selection MOS transistors of the first memory cell unit is in a non-conducting state. First and second selections M of two memory cell units
First and second select MOs in the selected sub-array so as to make the OS transistor conductive.
11. The nonvolatile semiconductor memory device according to claim 10, further comprising means for applying a read selection gate voltage to the S transistor. 12. When writing data in the memory cell portion of the first memory cell unit, the first memory cell unit of the first memory cell unit is written.
Of the second selection MOS transistor is turned on, the second selection MOS transistor is turned off, the first selection MOS transistor of the second memory cell unit is turned off, and the second selection MOS transistor is turned on. When the memory cell portion of the second memory cell unit is written in the non-conducting state, the second selection MOS transistor of the second memory cell unit is set in the conducting state, and the first selection MOS transistor is set in the non-conducting state. The first selection MOS transistor of the first memory cell unit is turned off, and the selection MOS transistor of the first selection MOS transistor is turned on or off. Choice MO of 2
11. The non-volatile semiconductor memory device according to claim 10, further comprising means for applying a write selection gate voltage to the S transistor. 13. The memory cell unit, wherein the memory cell unit is composed of one or a plurality of non-volatile memory cells, and the memory cell unit is connected in series to electrically connect the memory cell unit to a first common signal line . 1 connected to the common signal line of 1
First connecting to the selection MOS transistor and the memory cell section
2 selection MOS transistors 2 selection MOS transistors
A first select MOS transistor and a second select MOS transistor that have different threshold voltages. 6. The non-volatile semiconductor memory device according to claim 1, 2, 3, or 5. 14. A memory cell unit, wherein the memory cell unit is composed of one or a plurality of non-volatile memory cells, and a memory cell unit connected in series for electrically connecting the memory cell unit to a first common signal line . 1 connected to the common signal line of 1
First connecting to the selection MOS transistor and the memory cell section
2 selection MOS transistors 2 selection MOS transistors
And register, is composed of a third selection MOS transistor connecting the memory cell portion and the second common signal line, the first selecting MOS transistor is a first threshold voltage V
a first memory cell unit having th1 and a second selection MOS transistor having a second threshold voltage Vth2;
The first selection MOS transistor has a third threshold voltage V
The second memory cell unit having th3 and the second selection MOS transistor having the fourth threshold voltage Vth4 has first to third gate electrodes of the first to third selection MOS transistors, respectively. constitute sub-arrays share a select gate, a first threshold voltage Vth1 is the third threshold voltage Vt
larger than h3 and the second threshold voltage Vth2 is equal to the fourth threshold voltage Vth2.
6. The nonvolatile semiconductor memory device according to claim 1, wherein the threshold voltage Vth4 is smaller than the threshold voltage Vth4. 15. A first threshold voltage Vth1 and a fourth threshold voltage Vth4 are equal to each other, and a second threshold voltage Vth2.
15. The nonvolatile semiconductor memory device according to claim 10, wherein the third threshold voltage Vth3 is equal to the third threshold voltage Vth3. 16. When reading the memory cell portion of the first memory cell unit, the first memory cell unit of the first memory cell unit is read.
When the third selection MOS transistor is rendered conductive, at least one of the first and second selection MOS transistors of the second memory cell unit is rendered non-conductive, and the memory cell portion of the second memory cell unit is read , At least one of the first and second selection MOS transistors of the first memory cell unit is made non-conductive, and the first to third selection M of the second memory cell unit
The first to third selection MOs in the selected sub-array so as to make the OS transistor conductive.
15. The nonvolatile semiconductor memory device according to claim 14, further comprising means for applying a read selection gate voltage to the S transistor. 17. When writing to the memory cell portion of the first memory cell unit, the first memory cell unit of the first memory cell unit is written.
And the second selection MOS transistor are both turned on, and the third selection MOS transistor is turned off,
At least one of the first selection MOS transistor and the second selection MOS transistor of the second memory cell unit is brought into a non-conduction state, and when the memory cell portion of the second memory cell unit is written, The first and second selection MOS transistors are both turned on, and the third selection M
The first to the second sub-arrays selected in the sub-array so that the OS transistor is turned off and at least one of the first selection MOS transistor and the second selection MOS transistor of the first memory cell unit is turned off. Third choice MO
15. The nonvolatile semiconductor memory device according to claim 14, further comprising means for applying a write selection gate voltage to the S transistor. 18. A memory cell unit, wherein the memory cell unit is composed of one or a plurality of non-volatile memory cells, and is connected in series to electrically connect the memory cell unit to a first common signal line . 1 connected to the common signal line of 1
First connecting to the selection MOS transistor and the memory cell section
2 selection MOS transistors 2 selection MOS transistors
A transistor and a second common signal line connected in series for electrically connecting the memory cell section to the second common signal line .
3 Select MOS transistor and memory cell
Two selection MOS transistors of the fourth selection MOS transistor
A first select MOS transistor and a second select MOS transistor have different threshold voltages, and a third select MOS transistor and a fourth select MOS transistor have different threshold voltages. Claims 1, 2, 3 or 5
The non-volatile semiconductor memory device described in 1. 19. A memory cell unit, wherein the memory cell unit is composed of one or a plurality of non-volatile memory cells, and is connected in series to electrically connect the memory cell unit to a first common signal line . 1 connected to the common signal line of 1
First connecting to the selection MOS transistor and the memory cell section
2 selection MOS transistors 2 selection MOS transistors
A transistor and a second common signal line connected in series for electrically connecting the memory cell section to the second common signal line .
3 Select MOS transistor and memory cell
Two selection MOS transistors of the fourth selection MOS transistor
A first transistor , a second transistor , a third transistor, and a fourth selective MOS transistor, which are sequentially connected to the first, second, third, and fourth threshold voltages Vth1 and Vth.
The first memory cell unit having 2, Vth3 and Vth4 and the first, second, third and fourth selection MOS transistors are arranged in order of fifth, sixth, seventh and eighth threshold voltages Vth5,
A second memory cell unit having Vth6, Vth7, and Vth8 shares a gate electrode of each of the first to fourth selection MOS transistors as a first to fourth selection gate to form a sub-array. the threshold voltage Vth1 is the fifth threshold voltage Vth5 of
Ri small, second threshold voltage Vth2 are larger than the threshold voltage Vth6 sixth, and third threshold voltage Vth3 is smaller than the seventh threshold voltage Vth7, 4
Threshold voltage Vth4 is higher than the eighth threshold voltage Vth8
The nonvolatile semiconductor memory device according to claim 1, wherein the nonvolatile semiconductor memory device is characterized by being hardened . 20. A first threshold voltage Vth1 and a sixth threshold voltage Vth6 are equal to each other, and a second threshold voltage Vth2.
And the fifth threshold voltage Vth5 are equal, the third threshold voltage Vth3 and the eighth threshold voltage Vth8 are equal,
Fourth threshold voltage Vth4 and seventh threshold voltage V
20. The nonvolatile semiconductor memory device according to claim 19, wherein th7 is equal. 21. The nonvolatile semiconductor memory according to claim 10, 14 or 20, wherein first memory cell units and second memory cell units are arranged alternately to form the sub-array. apparatus. 22. When reading the memory cell portion of the first memory cell unit, the first memory cell unit of the first memory cell unit is read.
To the fourth selection MOS transistor are rendered conductive, at least one of the first to fourth selection MOS transistors of the second memory cell unit is rendered non-conductive, and the memory cell portion of the second memory cell unit is read. Occasionally, at least one of the first to fourth selection MOS transistors of the first memory cell unit is turned off, and the first to fourth selection M of the second memory cell unit is turned off.
The first to fourth selection MOs in the selected sub-arrays are arranged so that the OS transistors become conductive.
20. The nonvolatile semiconductor memory device according to claim 19, further comprising means for applying a read selection gate voltage to the S transistor. 23. When writing to the memory cell portion of the first memory cell unit, the first memory cell unit of the first memory cell unit is written.
And the second selection MOS transistor are both turned on, and at least one of the third and fourth selection MOS transistors is turned off, and the first selection MOS transistor and the second selection MOS transistor of the second memory cell unit are turned on. At least one of the transistors is in a non-conducting state, the third and fourth selection MOS transistors are in a conducting state or a non-conducting state, and when the memory cell portion of the second memory cell unit is written, The first and second selection MOS transistors are both turned on, and the third and fourth selection MOS transistors are turned on.
Of at least one of the selection MOS transistors in the first selection MOS transistor of the first memory cell unit
At least one of the transistor and the second selection MOS transistor is made non-conductive, and the third and fourth selection MOS
The first to fourth selection MOs in the selected sub-arrays are set so as to make a transistor conductive or non-conductive.
20. The nonvolatile semiconductor memory device according to claim 19, further comprising means for applying a write selection gate voltage to the S transistor. 24. A memory cell unit, wherein the memory cell unit is composed of one or a plurality of non-volatile memory cells, and a serially connected first memory cell unit electrically connected to a first common signal line . 1 connected to the common signal line of 1
First connecting to the selection MOS transistor and the memory cell section
2 selection MOS transistors 2 selection MOS transistors
And register, is composed of a third selection MOS transistor connecting the memory cell portion and the second common signal line, among the threshold voltages of the first to third selection MOS transistor, at least one other The non-volatile semiconductor memory device according to claim 4, wherein the non-volatile semiconductor memory device is different from the threshold voltage. 25. A memory cell unit, wherein the memory cell unit is composed of one or a plurality of non-volatile memory cells, and a memory cell unit connected in series for electrically connecting the memory cell unit to a first common signal line . 1 connected to the common signal line of 1
First connecting to the selection MOS transistor and the memory cell section
2 selection MOS transistors 2 selection MOS transistors
And register, is composed of a third selection MOS transistor connecting the memory cell portion and the second common signal line, the first selecting MOS transistor is a first threshold voltage V
a first memory cell unit having th1 and a second selection MOS transistor having a second threshold voltage Vth2 and a third selection MOS transistor having a third threshold voltage Vth3; The selection MOS transistor has a fourth threshold voltage Vth4, the second selection MOS transistor has a fifth threshold voltage Vth5, and the third selection MOS
A second memory cell unit in which the transistor has a sixth threshold voltage Vth6, a first select MOS transistor has a seventh threshold voltage Vth7, and a second select MOS transistor has an eighth threshold voltage. The third memory cell unit having the value voltage Vth8 and the third selection MOS transistor having the ninth threshold voltage Vth9 is the gate electrode of the first selection MOS transistor and the gate of the second selection MOS transistor. The sub-array is formed by sharing the electrodes and the gate electrodes of the third selection MOS transistors as the first, second and third selection gates respectively, and the first threshold voltage Vth1 and the fourth threshold voltage Vth4 are formed.
, At least one of the seventh threshold voltage Vth7 is different from the others, and at least one of the second threshold voltage Vth2, the fifth threshold voltage Vth5, and the eighth threshold voltage Vth8 Is different from the others, at least one of the third threshold voltage Vth3, the sixth threshold voltage Vth6 and the ninth threshold voltage Vth9 is different from the others. Nonvolatile semiconductor memory device. 26. The first threshold voltage Vth1, the fifth threshold voltage Vth5, and the ninth threshold voltage Vth9 are equal to each other, and the second threshold voltage Vth2 and the third threshold voltage. Voltage V
26. The th3, the fourth threshold voltage Vth4, the sixth threshold voltage Vth6, the seventh threshold voltage Vth7, and the eighth threshold voltage Vth8 are equal to each other. Nonvolatile semiconductor memory device. 27. The nonvolatile memory according to claim 25, wherein the first memory cell unit, the second memory cell unit, and the third memory cell unit are alternately arranged to form the sub-array. Semiconductor memory device. 28. When reading the memory cell portion of the first memory cell unit, the first, second and third selection MOS transistors of the first memory cell unit are turned on, and the second memory cell unit of the second memory cell unit is turned on. At least one of the first, second or third selection MOS transistors is made non-conductive, and at least one of the first, second or third selection MOS transistors of the third memory cell unit is made non-conductive. , When reading the memory cell portion of the second memory cell unit, the first, second and third memory cells of the second memory cell unit are read.
Of the first memory cell unit is turned on, and at least one of the first, second, and third selection MOS transistors of the first memory cell unit is turned off, and the first, second, and third memory cell units are turned on. Or the third choice MO
At least one of the S transistors is in a non-conducting state, and when reading the memory cell portion of the third memory cell unit, the first, second and third memory cell units are read.
Of the first memory cell unit is turned on, and at least one of the first, second, or third selection MOS transistors of the first memory cell unit is turned off, and the first, second, or third memory cell unit is turned off. Or the third choice MO
And a means for applying a read selection gate voltage to the first, second and third selection MOS transistors in the selected sub-array so that at least one of the S transistors is rendered non-conductive. 26. The nonvolatile semiconductor memory device according to claim 25. 29. When writing to the memory cell section of the first memory cell unit, the first memory cell unit of the first memory cell unit is written.
And the second selection MOS transistor are both turned on, and the third selection MOS transistor is turned off,
First selection MOS of second and third memory cell units
At least one of the transistor and the second selection MOS transistor is made non-conductive, and when writing the memory cell portion of the second memory cell unit, both the first and second selection MOS transistors of the second memory cell unit are made conductive. State and the third selection M
The OS transistor is turned off, and at least one of the first selection MOS transistor and the second selection MOS transistor of the first and third memory cell units is turned off, and the memory cell section of the third memory cell unit is turned on. When writing, the third selection MOS transistor of the third memory cell unit is turned on, and the first and second selection MOS transistors are turned on.
At least one of the transistors is turned off,
And a write selection gate voltage is applied to the first, second and third selection MOS transistors in the selected sub-array so that the third selection MOS transistor of the second memory cell unit is made non-conductive. 26. The nonvolatile semiconductor memory device according to claim 25, further comprising means. 30. The memory cell unit according to claim 1, further comprising at least one selection MOS transistor for electrically connecting the memory cell unit to at least one of the first and second common signal lines. Nonvolatile semiconductor memory device. 31. When performing a read or write operation on a memory cell portion in the memory cell unit,
31. The non-selective gate voltage according to claim 30, wherein a non-selection gate voltage is applied to a selection gate of the non-selected block so that a selection MOS transistor in the memory cell unit of the non-selected block which is not read or written is turned off. Semiconductor memory device.