JP2004158193A - Non-volatile semiconductor memory - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an EEPROM which allows random access to be accelerated, as a result of the reduction in the floating of a source line by forming the source line into low resistance without increasing the chip area. <P>SOLUTION: This memory comprises a memory cell section constituted by one cell or a plurality of non-volatile memory cells, a signal line to perform data transfer with the memory cell section, and a selective transistor located between the signal line and the memory cell section. In write-protected operation, writing non-selective voltage is applied to the signal line, and by applying selective gate voltage higher than the writing non-selective voltage to a gate of the selective transistor, the writing non-selective voltage is transferred to a channel of the memory cell section. Writing gate voltage is then applied to a control gate of the memory cell, and write-protected channel voltage boosted by capacity coupling between the channel and the control gate of the memory cell is generated. <P>COPYRIGHT: (C)2004,JPO

Description

  The present invention relates to a nonvolatile semiconductor memory device.

  In recent years, a NAND cell type EEPROM has been proposed as one of electrically rewritable nonvolatile semiconductor devices (EEPROM). In this EEPROM, a plurality of memory cells having an n-channel FET MOS structure in which, for example, a floating gate and a control gate are stacked as a charge storage layer are connected in series by sharing their sources and drains with adjacent ones. Is connected to the bit line as one unit.

  FIGS. 38A and 38B are a plan view and an equivalent circuit diagram of one NAND cell part of the memory cell array. FIGS. 39A and 39B are cross-sectional views taken along AA ′ and BB ′ in FIG. 38A, respectively.

  A memory cell array including a plurality of NAND cells is formed on a p-type silicon substrate (or p-type well) 11 surrounded by an element isolation oxide film 12. Focusing on one NAND cell, in this embodiment, eight memory cells M1 to M8 are connected in series to form one NAND cell. In each of the memory cells, a floating gate 14 (141, 142 to 148) is formed on a substrate 11 via a tunnel insulating film 13, and a control gate 16 (161, 162 to 168) is formed thereon via a gate insulating film 15. Are formed and configured. The n-type diffusion layers 19, which are the source and the drain of these memory cells, are connected so as to be shared by adjacent ones, whereby a plurality of memory cells are connected in series.

  A first select gate 149, 169 and a second select gate 1410, 1610 formed simultaneously with the floating gate and the control gate of the memory cell are provided on the drain side and the source side of the NAND cell, respectively. The substrate on which the elements are formed is covered with a CVD oxide film 17, on which bit lines 18 are provided. The control gates 14 of the NAND cells are commonly arranged as control gates CG1, CG2 to CG8. These control gate lines become word lines. The selection gates 149, 169 and 1410, 1610 are also continuously provided in the row direction as selection gates SG1, SG2, respectively.

  FIG. 40 shows an equivalent circuit of a memory cell array in which such NAND cells are arranged in a matrix. The source line is connected to a reference potential wiring such as Al or poly Si via a contact, for example, at one place for every 64 bit lines. This reference potential wiring is connected to a peripheral circuit. The control gate and the first and second selection gates of the memory cell are continuously arranged in the row direction. Normally, a set of memory cells connected to the control gate is called one page, and a set of pages sandwiched between a set of select gates on the drain side (first select gate) and the source side (second select gate) is 1 NAND. It is called a block or simply one block.

  The operation of the NAND cell type EEPROM is as follows. Data writing is performed sequentially from the memory cell farthest from the bit line. A boosted write voltage Vpp (approximately 20 V) is applied to the control gate of the selected memory cell, and an intermediate potential (approximately 10 V) is applied to the control gate and the first select gate of the other unselected memory cells. 0V ("0" write) or an intermediate potential ("1" write) is applied to the bit line according to the data. At this time, the potential of the bit line is transmitted to the selected memory cell. When data is "0", a high voltage is applied between the floating gate of the selected memory cell and the substrate, electrons are tunnel-injected from the substrate to the floating gate, and the threshold voltage moves in the positive direction. When the data is "1", the threshold voltage does not change.

  Data erasure is performed almost simultaneously in block units. That is, all control gates and select gates of the block to be erased are set to 0 V, and a boosted potential VppE (about 20 V) is applied to the p-type well and the n-type substrate. VppE is also applied to the control gate and select gate of the block that is not erased. As a result, in the memory cell of the block to be erased, electrons of the floating gate are emitted to the well, and the threshold voltage moves in the negative direction.

  The data read operation is performed by setting the control gate of the selected memory cell to 0 V and setting the control gates of the other memory cells to the power supply voltage Vcc (for example, 3 V) to detect whether a current flows in the selected memory cell. Done. In the NAND cell type EEPROM, since a plurality of memory cells are connected in cascade, the cell current at the time of reading is small. Further, since the control gate and the first and second selection gates of the memory cell are continuously arranged in the row direction, data for one page is simultaneously read out to the bit line.

  However, this type of apparatus has the following problems.

(Issue 1)
In the NAND cell type EEPROM, the control gate of the memory cell selected at the time of data reading is set to 0 V, and the control gates of the other memory cells are set to Vcc (for example, 3 V) to detect whether or not the cell current Icell flows. The magnitude of the current depends not only on the threshold voltage of the cell to be read, but also on the threshold voltages of all the remaining cells connected in series. Considering the case where eight memory cells are connected in series to constitute one NAND cell, Icell (Best) when Icell is the largest (when the resistance is the smallest) is the number of eight cells connected in series. This is a case where the threshold voltages are all negative ("1" state). When reading "1", if Icell is the smallest (the resistance is the largest) and Icell (Worst) is, the threshold voltage of all other cells connected in series to the cell to be read is positive ("0"). This is a case where the memory cell (for example, MC1 in FIG. 40) on the first bit line contact side is read as "1" at the time of "state".

  The cell current flows from the bit line to the source line via the memory cell. In the conventional memory cell array, the source line is shared by one page of NAND cells to be read simultaneously (FIG. 40). When reading out the memory cell (memory cell MC1 in FIG. 40) farthest from the contact between the source line and the reference potential wiring, the threshold voltage of the other seven cells connected in series to the memory cell MC1 is positive (that is, the cell current). Is the minimum Icell (Worst)) and the resistance of the other NAND string sharing the source line is the minimum (that is, the cell current is the maximum Icell (Best)). In this case, a cell current flows from the NAND string having a small resistance at the initial stage of reading, and since the resistance of the source line is large, the potential of the source line of the NAND cell to which the memory cell MC1 belongs is I × R (I: Cell current, R: resistance of the source line).

  That is, since the source of the memory cell in the NAND string including the memory cell MC1 floats from the ground potential Vss, the source-drain voltage and the source-gate voltage of the memory cell decrease. Since the effect also occurs and the threshold value of the memory cell increases, the conductance of the memory cell in the NAND cell string including MC1 decreases. As described above, when the resistance of the source line is large, the source line floats from the ground potential, so that it becomes more difficult for the NAND string having a small cell current to flow.

  It is assumed that the bit line capacitance is CB, and the bit line potential needs to decrease by .DELTA.VB from the precharge potential in order to read when the threshold voltage of the memory cell is negative (that is, "1" state). Although the maximum value of the bit line discharge time TRWL is determined when the cell current is the smallest, TRWL = CB / Icell (Worst) when there is no floating of the source line. Since the line floats, TRWL becomes longer, and there is a problem that the random access time becomes longer. Further, in the conventional NAND cell type EEPROM, if only one out of 16 contacts between the source line and the reference potential wiring is provided in order to reduce the floating of the source line, the area of the memory cell increases.

  Increasing the bit line discharge time due to the floating of the source line not only increases the read time, but also causes variations in the threshold value written in the memory cell.

  FIG. 42 shows the bit line discharge time MCC1 for verify read after writing "0" (changing the threshold value of the memory cell from a negative value to a positive value) in the memory cell MCC1 of FIG. This indicates a threshold-dependent positive value. The write and verify read operations will be described with reference to a known example (Japanese Patent Application Laid-Open No. 3-343363). In the verify read of the memory cell MCC1 in FIG. 43, as shown in FIG. 43, other memory cells MCC2, MCC3, MCC4, MCC5... Of the same page are insufficiently written with "0" (that is, not a positive threshold but a negative one). (Has a threshold value), a large cell current flows, and as a result, the source line floats and the bit line discharge time becomes longer as shown in FIG.

  As a result, if the bit line discharge time is equal to or longer than TBL1 during the verify read, and if "0" is written to the memory cell, the source line floats in the memory cell MCC1 in FIG. It is determined that "0" has been written at Vth1 or higher in FIG. On the other hand, when the cell current is large and the source line does not float as in the memory cell MCD1 in FIG. 44, the bit line discharge time is as shown in FIG. That is, when writing to the memory cell MCD1, it is determined that "0" has been written at the threshold Vth1 or more in FIG.

  As described above, there is a problem that the variation in the threshold voltage between the memory cell MCC1 and the memory cell MCD1 is Vthd1−Vth1 in the circuit. If the bit line discharge time can be shortened by eliminating the floating of the source line, and the bit line discharge time of the memory cell MCC1 can be set to, for example, as shown in FIG. 42 Vthd1−Vth2).

  Also, after the memory cell MCC1 of FIG. 43 is written by the first write pulse and the threshold value becomes Vth1 (FIG. 45), the memory cells MCC2, MCC3, and MCC3 of FIG. It is assumed that MCC4, MCC5,. Since writing to the memory cell MCC1 is completed by the first write pulse, the memory cell MCC1 is not written by the second and subsequent write pulses, and the threshold value remains at Vth1.

  As a result, when reading the memory cell MCC1 after the page writing of the memory cells MCC1, MCC2, MCC3... Is completed, no cell current flows through the memory cells MCC2, MCC3, MCC4, MCC5. , The source line does not float, the bit line discharge time is shortened by ΔT as shown in FIG. 45, and “1” may be read. That is, since the data of the memory cells MCC2, MCC3, MCC4... Of the same page of the memory cell MCC1 has changed by the second and subsequent write pulses after the writing of the memory cell MCC1, the data of the memory cell MCC1 to which "0" has been written is changed. There is a problem that if it is "1", it is read. This erroneous read occurs because, when reading a memory cell, data of another memory cell via a source line affects a read current of the memory cell to be read.

(Issue 2)
In a conventional NAND cell type EEPROM, a contact between a drain-side select gate and a bit line is disposed adjacent to each other as shown in FIG. FIG. 41A shows an n-type diffusion layer of a conventional memory cell array and source / gate / drain regions of the memory cell, and a contact connecting the n-type diffusion layer and a bit line (such as Al) (hereinafter referred to as a bit line contact). That is, it shows the element region. The portions other than the hatched portions in FIG. 41A indicate the element isolation regions between the memory cells. NAND cells are arranged in series in the Y direction in FIG. In the X direction of FIG. 40, an n-type diffusion layer (source line) and a contact between the memory cell array and the bit line are arranged. L 'is the distance between bit line contacts, L is the element isolation width between memory cells, and W is the channel width of the memory cell transistor.

  In the conventional NAND cell array, even if the width of the element isolation region between memory cells is reduced, the bit line contacts are arranged adjacently as shown in FIG. Direction), the pitch of the memory cells cannot be reduced. That is, since the size in the X direction is determined by the distance L 'between the bit line contacts, the element isolation width L between the memory cell arrays is determined by the field inversion withstand voltage between adjacent NAND cell columns, the minimum element isolation determined by the element isolation technology, and the like. There is a problem that the width becomes larger than the width L0, and as a result, the area of the memory cell array increases.

  Further, as shown in FIG. 41B, the margin l between the contact and the element region must be reduced by reducing the pitch of the memory cells. However, when l is reduced, a contact is formed on the element isolation due to misalignment, and there is a problem that a well or a substrate in which a bit line and a memory cell are formed is short-circuited.

  As described above, in the conventional EEPROM, when the resistance of the source line is large, the source line floats from the ground potential, so that the bit line discharge time becomes longer and the random access time becomes longer. Furthermore, if only one of 16 contacts between the source line and the reference potential wiring is provided to reduce the floating of the source line, the area of the memory cell increases.

  Further, since the bit line contacts are arranged adjacent to each other, the pitch of the memory cells in the column direction cannot be reduced. Furthermore, the margin for matching between the contact and the element region must be reduced by reducing the pitch of the memory cell. However, if this margin is reduced, the contact is shifted on the element isolation due to misalignment, and the bit line and the memory cell are formed. There is a problem that the well or the substrate to be short-circuited.

  SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object to reduce the floating of source lines by reducing the resistance of the source lines without increasing the chip area, thereby reducing random access. It is an object of the present invention to provide a nonvolatile semiconductor memory device which can be operated at high speed.

  Another object of the present invention is to shift the position of the bit line contact between adjacent NAND strings, thereby reducing the pitch of memory cells in the column direction, and realizing a high-density memory cell structure. Another object of the present invention is to provide a nonvolatile semiconductor memory device.

In order to solve the above problems, the present invention employs the following configuration.
A memory cell unit including one or a plurality of nonvolatile memory cells; a (common) signal line for performing data transfer with the memory cell unit; and a signal line disposed between the signal line and the memory cell unit. And a selection transistor,
(1) In the case of a write-inhibiting operation, a write non-selection voltage is applied to the signal line, and a select gate voltage higher than the write non-selection voltage is applied to the gate of the select transistor. The write gate voltage is transferred to the channel of the memory cell section, and the write gate voltage is applied to the control gate of the memory cell to generate a write inhibit channel voltage boosted by capacitive coupling between the channel of the memory cell and its control gate. thing.
(2) In the case of a write inhibit operation, a write non-select voltage is applied to the signal line, and a select gate voltage higher than the write non-select voltage is applied to the gate of the select transistor and the control gate of the memory cell. The write non-selection voltage is transferred to the channel of the memory cell section, and the write gate voltage is applied to the control gate of the memory cell, and is boosted by capacitive coupling between the channel of the memory cell and the control gate. Generating a write-protected channel voltage.
(3) In the case of a write inhibit operation, a write non-selection voltage is applied to the common signal line, and a select gate voltage higher than the write non-selection voltage is applied to the gate of the select transistor. A voltage is transferred to a channel of the memory cell unit, a pass voltage is applied to a control gate of a non-selected memory cell, and a write voltage higher than the pass voltage is applied to a control gate of a selected memory cell. Generating a write-protected channel voltage boosted by capacitive coupling between the channels of the memory cells and the control gates thereof.
(4) In the case of a write inhibit operation, a write non-select voltage is applied to the signal line, and a select gate voltage higher than the write non-select voltage is applied to the gate of the select transistor and the control gate of the memory cell. The write non-selection voltage is transferred to the channel of the memory cell section, and a pass voltage is applied to the control gate of the non-selected memory cell, and a write voltage higher than the pass voltage is applied to the control gate of the selected memory cell. Generating a write-protected channel voltage which is applied and boosted by capacitive coupling between the channels of the plurality of memory cells and the control gates thereof.
(5) In the case of a write select operation, a write select voltage is applied to the signal line to be transferred to the channel of the memory cell section. In the case of a write inhibit operation, a write non-select voltage is applied to the signal line. The write non-selection voltage is transferred to the channel of the memory cell section by applying a select gate voltage higher than a write non-select voltage to the gate of the select transistor. A write voltage higher than the pass voltage is applied to the control gate of the memory cell, and a write voltage higher than the pass voltage is applied to the control gate of the selected memory cell, and the voltage is boosted by capacitive coupling between the channels of the plurality of memory cells and the control gates thereof. To generate a write-protected channel voltage.
(6) In the case of a write selection operation, a write selection voltage is applied to the signal line to be transferred to the channel of the memory cell section. In the case of a write inhibit operation, a write non-selection voltage is applied to the signal line. Applying a select gate voltage higher than the write non-select voltage to the select transistor and to the control gate of the memory cell to transfer the write non-select voltage to the channel of the memory cell portion; and A pass voltage is applied to a control gate of an unselected memory cell, a write voltage higher than the pass voltage is applied to a control gate of a selected memory cell, and a channel of the plurality of memory cells and a control gate of the channel are arranged. Generating a write-protected channel voltage boosted by capacitive coupling.
It is characterized by.

Here, preferred embodiments of the present invention include the following in addition to those described in the dependent claims.
(1) The read non-selection potential is the ground potential.
(2) The write non-selection potential is the power supply voltage or the power supply voltage in the chip.
(3) The non-selection gate voltage is a negative voltage.
(4) The memory cell section is composed of electrically rewritable nonvolatile memory cells.
(5) In the nonvolatile memory cell, a charge storage layer and a control gate are stacked on a semiconductor layer, and a plurality of memory cells are connected in series so that adjacent memory cells share a source and a drain.
(6) In the nonvolatile memory cell, a charge storage layer and a control gate are laminated on a semiconductor layer, and one or a plurality of memory cells are connected in parallel so that all of them share a source and a drain.
(7) To equalize or change the threshold voltage of the first to ninth select MOS transistors by equalizing or changing the impurity concentration of the channel.

  According to the present invention, both the one end side and the other end side of the memory cell unit are connected to the first and second common signal lines while sharing the contacts with the other memory cell units, respectively. By using a bit line formed of Al or the like instead of a conventional source line formed of a high-resistance n-type diffusion layer, the problem of floating of the source line can be solved. For this reason, the resistance of the source line is reduced to reduce the floating of the source line, and as a result, it is possible to speed up random access.

  In addition, by appropriately selecting the E type and the I type as the selection MOS transistors for connecting one end and the other end of the memory cell unit to the common signal line, high-speed random access can be performed without increasing the chip area. The possible memory cell array can be realized. Further, by shifting the position of the bit line contact between adjacent NAND strings, the pitch of the memory cells in the column direction can be reduced, and a high-density memory cell structure can be realized.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(Embodiment 1)
FIG. 1 is a block diagram showing a configuration of a NAND cell type EEPROM according to the present embodiment. In the figure, reference numeral 1 denotes a memory cell array as a memory means, which is an open bit line system, and the memory cell array is divided into 1A and 1B. Reference numeral 2 denotes a sense amplifier circuit as a latch unit for writing and reading data. 3 is a row decoder for selecting a word line, 4 is a column decoder for selecting a bit line, 5 is an address buffer, 6 is an I / O sense amplifier, 7 is a data input / output buffer, and 8 is a substrate potential control circuit.

  FIG. 2 is a diagram showing an array structure of the memory cell array 1A, and FIG. 3 is a diagram showing an array structure of the memory cell array 1B. In the memory cell array (FIGS. 2 and 3) according to the present embodiment, the source side select gate (second select gate) is connected to the source line of the n-type diffusion layer as in the conventional memory cell array (FIG. 40). Not in contact with the bit line. Further, one bit line contact is shared by two NAND cell columns in the conventional memory cell, but is shared by four NAND cell columns in the memory cell array of the present embodiment, so that the entire memory cell array is shared. Does not increase from the conventional memory cell array.

  The sub-array composed of a plurality of memory cell units (NAND cells) includes a memory cell unit (1) in which the select MOS transistor STn1 at one end is an I type and a select MOS transistor STn2 at the other end is an E type, And a memory cell unit (2) having the select MOS transistor STn1 of the E type and the select MOS transistor STn2 at the other end of the I type being alternately arranged in the word line direction.

  FIG. 4 shows the n-type diffusion layer of the memory cell according to the present embodiment, the source / gate / drain region of the memory cell, and a contact (bit line contact) connecting the n-type diffusion layer and a bit line (such as Al), that is, an element region. Is shown. As described above, in the conventional memory cell array, since the bit line contacts of adjacent bit lines are arranged adjacently as shown in FIG. 41, it is difficult to reduce the size in the column direction (X direction in FIG. 41). There is.

  On the other hand, in the memory cell array according to the present embodiment, the bit line contacts of the adjacent bit lines are not arranged adjacent to each other as shown in FIG. The size does not become a problem when the memory cell array is reduced in the column direction (X direction), and the element isolation width between memory cells is determined by the field inversion breakdown voltage between adjacent NAND cell columns, element isolation technology, and the like. Can be reduced to the minimum element isolation region width L0 determined by the above. Further, since the number of selection MOS transistors is two per NAND string as in the conventional case, there is no increase in area due to the increase in the number of selection MOS transistors.

  In the memory cell array of this embodiment, two types of threshold voltages Vth1 and Vth2 (Vth1> Vth2) are provided for two select MOS transistors that connect one NAND cell column and a bit line. A select MOS transistor having a high threshold voltage Vth1 (for example, 2 V) is referred to as an E type, and a select MOS transistor having a low threshold voltage Vth2 (for example, 0.5 V) is referred to as an I type. The voltage applied to the selection gate is a voltage Vsgh (for example, 3 V) at which both I-type and E-type transistors are turned on (Vsgh> Vt1, Vt2), and a voltage at which the I-type transistor turns on but the E-type transistor turns off. Vsgl (for example, 1.5 V) (Vt1> Vsgl> Vt2).

  As described above, by providing two types of threshold voltages of the selection MOS transistor and two types of voltages applied to the selection gate, one of the adjacent NAND cell columns is electrically connected to the bit line during writing or reading, and the other is performed. Can be made non-conductive.

  A specific reading and writing method will be described with reference to FIG.

<Read>
When the data of the memory cells MC11, MC31, MC51... In the memory cell unit (1) is read out to the bit lines BL1A, BL3A, BL5A..., First, the bit lines BL1A, BL3A, BL5A. 1.8V), and BL0A, BL2A, BL4A, BL6A ... are grounded to 0V. After the precharge, the bit lines BL1A, BL3A, BL5A,.

  Next, the control gate CG1 is set to 0V, and CG2 to CG8 are set to Vcc (for example, 3V). The selection gate SG1 is set to Vsgl, and the selection gate SG2 is set to Vsgh. Other select gates and control gates are set to 0V. In this case, the selection MOS transistors (ST02, ST12, ST22, ST32, ST42, ST52 ...) connected to the bit lines BL0A, BL2A, BL4A ... are turned on. On the other hand, the I-type selection MOS transistors ST11, ST31, ST51,... Connected to the bit lines BL1A, BL3A, BL5A... Turn on, but the E-type selection MOS transistors ST01, ST21, ST41.

  Therefore, if the data written in the memory cells MC11, MC31, MC51,... Is "1", the precharged bit lines BL1A, BL3A, BL5A, etc. are discharged to the grounded bit lines BL2A, BL4A, BL6A,. , The data of the memory cells MC11, MC31, MC51... In the memory cell unit (1) are read out to the bit lines BL1A, BL3A, BL5A. On the other hand, if the data written in the memory cell is "0", the bit lines BL1A, BL3A, BL5A... Do not discharge and maintain the precharge potential.

  On the other hand, for the memory cells MC01, MC21, MC41,... In the memory cell unit (2), the E-type selection MOS transistors ST01, ST21, ST41, ... connected to the bit lines BL1A, BL3A, BL5A,. The data of the memory cells MC01, MC21, MC41,... Is not read out to the bit lines BL1A, BL3A, BL5A,.

  Next, a case is considered where the data of the memory cells MC01, MC21, MC41,... In the memory cell unit (2) is read out to the bit lines BL0A, BL2A, BL4A, BL6A,. First, the bit lines BL0A, BL2A, BL4A, BL6A... Are precharged to a bit line read potential VA (for example, 1.8 V), and the BL1A, BL3A, BL5A. After the precharge, the bit lines BL0A, BL2A, BL4A, BL6A,.

  Next, the control gate CG1 is set to 0V, and CG2 to CG8 are set to Vcc (for example, 3V). Then, the selection gate SG1 is set to Vsgh, and the selection gate SG2 is set to Vsgl. Other select gates and control gates are set to 0V. In this case, the selection MOS transistors (ST01, ST11, ST21, ST31, ST41, ST51 ...) connected to the bit lines BL1A, BL3A, BL5A ... are turned on. On the other hand, the I-type selection MOS transistors ST02, ST22, ST42,... Connected to the bit lines BL0A, BL2A, BL4A, BL6A... Turn on, but the E-type selection MOS transistors ST12, ST32, ST52.

  Therefore, if the data written in the memory cells MC01, MC21, MC41... In the memory cell unit (2) is "1", the precharged bit lines BL0A, BL2A, BL4A, BL6A. By discharging to BL3A, BL5A,... And lowering from the precharge potential, data of the memory cells MC01, MC21, MC41,... Is read out to the bit lines BL0A, BL2A, BL4A,. On the other hand, if the data written in the memory cell is "0", the bit lines BL0A, BL2A, BL4A... Do not discharge and maintain the precharge potential.

  On the other hand, as for the memory cells MC11, MC31, MC51... In the memory cell unit (1), the E-type selection MOS transistors ST12, ST32, ST52. The data of MC11, MC31, MC51,... Is not read out to bit lines BL0A, BL2A, BL4A,.

  As described above, in the embodiment, the source line (n-type diffusion layer) of the conventional memory cell array is eliminated, and at the time of reading, half of the bit lines are grounded and play the same role as the conventional source line, and the other half are used. The data of the memory cell is read out to the bit line. By using a bit line formed of low-resistance Al or the like instead of a conventional source line formed of a high-resistance n-type diffusion layer, the problem of floating of the source line can be solved.

  Here, the read operation will be described in more detail with reference to a timing chart.

  FIG. 5 is a timing chart for reading data written in the memory cells MC11, MC31, MC51,... In the memory cell unit (1) of FIG.

  The bit lines BL0A, BL2A, BL4A, BL6A... Are connected to the sense amplifier SA1 in FIG. 6, and the bit lines BL1A, BL3A, BL5A. The sense amplifier is formed by a CMOS flip-flop controlled by control signals φP and φN.

  First, the precharge signals PRA1, PRA2, PRB2 change from Vss to Vcc (time t0), the bit lines BL1A, BL3A, BL5A... Change to VA2 (for example, 1.7V), and the (dummy) bit lines BL1B, BL3B, BL5B. Are precharged to VB2 (for example, 1.5 V) (time t1). VA1 is 0 V, and the bit lines BL0A, BL2A, BL4A, BL6A,... Are grounded.

  When the precharge ends, PRA2 and PRB2 become Vss, and the bit lines BL1A, BL3A, BL5A. Thereafter, a desired voltage is applied from the row decoder 3 to the selection gate and the control gate (time t2). The control gate CG1 is at 0V, CG2 to CG8 are at Vcc (for example, 3V), SG2 is at 3V (Vsgh), and SG1 is at 1.5V (Vsgl).

  If the data written in the memory cells MC11, MC31, MC51,... In the memory cell unit (1) is "0", the threshold voltage of the memory cell is positive and no cell current flows, and the bit lines BL1A, BL3A,. BL5A... Remain at 1.7V. When the data is "1", a cell current flows and the potentials of the bit lines BL1A, BL3A, BL5A... Decrease to 1.5 V or less. Since the selection gate SG1 is 1.5V, the E-type selection MOS transistors ST01, ST21, ST41 are turned off, and the data of the memory cells MC01, MC21, MC41... In the memory cell unit (2) are not transferred to the bit lines. During this time, the (dummy) bit lines BL1B, BL3B, BL5B... Are kept at a precharge potential of 1.5V.

  Thereafter, at time t3, .phi.P becomes 3 V and .phi.N becomes 0 V, the CMOS flip-flop FF is inactivated, and at time t4, .phi.E becomes 3 V, whereby the SA2 CMOS flip-flop FF is equalized and the nodes N1 and N2 become Vcc. / 2 (for example, 1.5 V). At time t5, SS2, SA, SB become 3V, and the bit line and the sense amplifier are connected. Then, φN becomes 0V to 3V, φP becomes 3V to 0V, and bit lines BL1A, BL3A, BL5A ... and bit lines BL1B, BL1B, The potential difference between BL3B, BL5B ... is amplified (time t6).

  That is, if "0" is written in the memory cells MC11, MC31, MC51,..., The node N1 of SA2 becomes 3 V, the node N2 becomes 0 V, and "1" is written in the memory cells MC11, MC31, MC51,. And the node N1 becomes 0V and the node N2 becomes 3V. Thereafter, when the column selection signal CSL changes from 0 V to 3 V, the data latched by the CMOS flip-flop is output to IO and / IO (time t7).

  Through the read operation, the bit lines BL0A, BL2A, BL4A, BL6A,... Are grounded to 0V. That is, every other bit line is grounded. Therefore, the distance between the read bit lines is twice as long as the case where the bit lines are not grounded, and the noise due to the capacitive coupling between the bit lines is significantly reduced (Japanese Patent Application No. 4-276393). The bit lines BL0B, BL2B, BL4B, BL6B... May be grounded by setting PRB1 to Vcc and VB1 to 0V through the read operation. As a result, it is possible to reduce inter-bit line capacitive coupling noise during bit line potential amplification.

  FIG. 8 is a timing chart for reading data written in the memory cells MC01, MC21, MC41, MC61,... In the memory cell unit (2) of FIG.

  First, the precharge signals PRA1, PRA2, PRB1 change from Vss to Vcc (time t0), the bit lines BL0A, BL2A, BL4A... Change to VA1 (for example, 1.7V), and the (dummy) bit lines BL0B, BL2B, BL4B. Are precharged to VB1 (for example, 1.5 V) (time t1). VA2 is 0V, and the bit lines BL1A, BL3A, BL5A... Are grounded.

  When the precharge is completed, PRA1 and PRB1 become Vss, and the bit lines BL0A, BL2A, BL4A. Thereafter, a desired voltage is applied from the row decoder 3 to the selection gate and the control gate (time t2). The control gate CG1 is at 0V, CG2 to CG8 are at Vcc (for example, 3V), SG1 is at 3V (Vsgh), and SG2 is at 1.5V (Vsgl).

  When the data written in the memory cells MC01, MC21, MC41,... Is "0", the cell current does not flow because the threshold voltage of the memory cell is positive, and the potential of the bit lines BL0A, BL2A, BL4A. It remains at 7V. When the data is "1", a cell current flows and the potentials of the bit lines BL0A, BL2A, BL4A... Decrease to 1.5V or less. Since the selection gate SG2 is 1.5 V, the E-type selection MOS transistors ST12, ST32, ST52 are turned off, and the data of the memory cells MC11, MC31, MC51... In the memory cell unit (1) are not transferred to the bit lines. . During this time, the (dummy) bit lines BL0B, BL2B, BL4B... Are kept at a precharge potential of 1.5V.

  Thereafter, at time t3, .phi.P becomes 3V and .phi.N becomes 0V, the CMOS flip-flop FF is inactivated, and at time t4, .phi.E becomes 3V, whereby the SA1 CMOS flip-flop FF is equalized, and the nodes N1 and N2 become Vcc. / 2 (for example, 1.5 V). At time t5, SS1, SA and SB become 3V and the bit lines are connected to the sense amplifier. Then, φN is changed from 0V to 3V, φP is changed from 3V to 0V, and bit lines BL0A, BL2A, BL4A... , BL2B, BL4B... Are amplified (time t6).

  That is, if "0" is written in the memory cells MC01, MC21, MC41,..., The node N1 of SA1 becomes 3V and the node N2 becomes 0V, and "1" is written in the memory cells MC01, MC21, MC41,. And the node N1 becomes 0V and the node N2 becomes 3V. Thereafter, when the column selection signal CSL changes from 0 V to 3 V, the data latched by the CMOS flip-flop is output to IO and / IO (time t7).

  .. Are grounded to 0 V throughout the read operation, so that noise due to capacitive coupling between bit lines is reduced.

  The timing of the read operation is arbitrary. For example, as shown in FIG. 9, at time t5, the transfer gate connecting the bit line and the sense amplifier is turned on to transfer the potentials of the bit line and the dummy bit line to the nodes N1 and N2 of the sense amplifier, and then the transfer gate is turned off. Is also good. In this case, since the bit line and the dummy bit line are disconnected from the sense amplifier, the load capacitance of the sense amplifier is reduced, and the potentials of the nodes N1 and N2 are quickly determined during sensing and data latch.

  In the above embodiment, for example, when reading out the memory cells MC11, MC31, MC51,..., The bit lines BL1A, BL3A, BL5A,... Are precharged, the bit lines BL0A, BL2A, BL4A. The data is read out to the lines BL1A, BL3A, BL5A. Which of the bit lines connected to both ends of the memory cell unit is used to read data is arbitrary. For example, when reading out the memory cells MC11, MC31, MC51..., The bit lines BL2A, BL4A, BL6A... Are precharged, the bit lines BL1A, BL3A, BL5A. , BL6A...

<Write>
The write operation of the present embodiment will be described below.

  A write procedure when writing to the memory cells MC11, MC31, MC51,... In the memory cell unit (1) of FIG. 2 will be described below.

  The selection gate SG2 is set to 0 V, and all the selection MOS transistors having the selection gate SG2 as a gate electrode are turned off. SG1 and CG1 to CG8 are set to Vcc, and the bit lines BL1A, BL3A, BL5A. Precharge). The bit lines BL0A, BL2A, BL4A,... May be set to Vcc or 0V, and may be set to an arbitrary voltage.

  Thereafter, when the selection gate SG1 is set to Vsgl (for example, 1.5 V), the I-type selection MOS transistors ST11, ST31, ST51... Are turned on, but the E-type selection MOS transistors ST01, ST21, ST41. The channels of the memory cells MC01, MC21, MC41,... Float at the potential Vcc-Vth charged from the bit line. Data to be written to the memory cells MC11, MC31, MC51,... In the memory cell unit (1) is given from bit lines BL1A, BL3A, BL5A,.

  For example, when writing "0" to the memory cell MC11, when the bit line BL1A is set to 0V, the I-type selection MOS transistor ST11 is turned on and the channel of the memory cell MC11 is set to 0V. When "1" is written to the memory cell MC11, when the bit line BL1A is set to 3 V, the I-type selection MOS transistor ST11 is turned off, and the channel of the memory cell MC11 becomes floating at Vcc-Vth. The bit lines BL0A, BL2A, BL4A,... May be set to Vcc or 0V, and may be set to an arbitrary voltage.

  After the selection gate SG1 is changed from Vcc to Vsgl (a voltage higher than the threshold voltage of the I-type selection MOS transistor but smaller than the E-type selection MOS transistor, for example, 1.5 V), the control gates CG1 to CG8 are changed from Vcc. It is set to the intermediate potential VM (about 10 V). Since the channels of the memory cells MC01, MC21, MC41,... To which no data is to be written and the memory cells MC11, MC31, MC51,. (About 10 V). The channels of the memory cells MC11, MC31, MC51,... To which "0" is written are at 0V because the bit lines are at 0V.

  After the channel of the memory cell in which writing is not selected and "1" is written rises from Vcc-Vth to the intermediate potential, the control gate CG1 is boosted from the intermediate potential VM to the write voltage Vpp (20 V). Then, the memory cells MC01, MC21, MC41... And the memory cells MC11, MC31, MC51... For writing "1" in the memory cell unit (2) where no writing is performed have an intermediate potential (about 10 V), (About 20 V), these memory cells are not written. However, since the channels of the memory cells MC11, MC31, MC51... For writing "0" are 0 V, and the control gate is Vpp (about 20 V), the floating gate Electrons are injected and "0" writing is performed.

  Here, the write operation of this embodiment will be described in more detail with reference to a timing chart. FIGS. 10 and 11 are timing charts when the memory cell MC11 (and the memory cells MC31, MC51,...) Is written.

  The data to be written into the memory cells MC11, MC31, MC51,... In the memory cell unit (1) is latched in the sense amplifier circuit (SA2 in FIG. 7). That is, in the case of "0" write, the node N1 is at 0V, N2 is 3V, and in the case of "1" write, the node N1 is at 3V and N2 is at 0V.

  At the time of writing operation, first, at time t1, SG1 is set to Vss, SG2 and CG1 to CG8 are set to Vcc. In this embodiment, when writing to the memory cells MC11, MC31, MC51,... In the memory cell unit (1), writing is performed to the memory cells MC01, MC21, MC41,. Absent. For this purpose, it is necessary to charge the channels of the memory cells MC01, MC21, MC41,... From the bit lines BL0A, BL2A, BL4A,.

  In this embodiment, the bit lines BL0A, BL2A, BL4A,... Are charged from VA1 to Vcc of the sense amplifier SA1 in FIG. As a result, the channels of the memory cells MC01, MC21, MC41 ... are charged to Vcc-Vth. At this time, the channels of the memory cells MC11, MC31, MC51... For writing are also charged to Vcc-Vth. As described above, the channel of the memory cell of the memory cell unit (2) may be charged to Vcc (-Vth) from BL0A, BL2A, BL4A... Or from BL1A, BL3A, BL5A. Good.

  On the other hand, a potential of Vcc or Vss (0 V) is applied to the bit lines BL1A, BL3A, BL5A,... According to the data latched in the sense amplifier circuit SA2. Thus, for example, when "0" is written to the memory cell MC11, the bit line BL1A is set to 0V and the channel of the memory cell MC11 is set to 0V. When "1" is written to the memory cell MC11, the bit line BL1A is set to Vcc (for example, 3 V), and the channel of the memory cell MC11 is charged to Vcc-Vth.

  After the bit line is charged, the selection gate SG1 is set to Vsgl (for example, 1.5 V), and SG2 is set to Vss (for example, 0 V). All the selection MOS transistors having the selection gate SG2 as a gate electrode are turned off. The selection MOS transistors ST01, ST21, ST41,... To which the memory cells MC01, MC21, MC41,.

  The drains of the select MOS transistors ST11, ST31, ST51,... Of the memory cells MC11, MC31, MC51... For writing "1" are Vcc-Vth (for example, a threshold voltage including the substrate bias effect of an I type transistor). Assuming that the voltage is 0.8V, 3-0.8 = 2.2V), the source on the bit line contact side is Vcc (for example, 3V), and the selection gate SG1 is Vsgl (for example, 1.5V). ST31, ST51 ... are turned off. As a result, the channels of the memory cells MC11, MC31, MC51,.

  When "0" is written to the memory cells MC11, MC31, MC51,..., The selection gate SG1 of the selection MOS transistors ST11, ST31, ST51,. The transistors ST11, ST31, ST51,... Are turned on, and the channel of the memory cell is maintained at 0V.

  After the selection gate SG1 is set to Vsgl (for example, 1.5 V), the control gates CG1 to CG8 are changed from Vcc to the intermediate potential VM (about 10 V) at time t2. Since the channels of the memory cells MC01, MC21, MC41,... To which no data is to be written and the memory cells MC11, MC31, MC51,. (About 10 V). The channels of the memory cells MC11, MC31, MC51,... To which "0" is written are at 0V because the bit lines are at 0V.

  After the channel of the memory cell performing the write non-selection and "1" write rises from Vcc-Vth to the intermediate potential, the control gate CG1 is boosted from the intermediate potential VM to the write voltage Vpp (20 V) at time t3. .. And the memory cells MC11, MC31, MC51... For writing "1" have an intermediate potential (about 10 V) and the control gate CG1 has Vpp (about 20 V). The cell is not written, but since the channels of the memory cells MC11, MC31, MC51... For writing "0" are 0 V and the control gate is Vpp (about 20 V), electrons are injected from the substrate into the floating gate to write "0". Is performed.

  After the writing is completed, the control gate, the selection gate, and the bit line are sequentially discharged, and the writing operation ends.

  After the end of the write, a write verify operation is performed to check whether the write has been performed sufficiently.

  First, the precharge signals PRA1, PRA2, PRB2 change from Vss to Vcc (time t4), the bit lines BL1A, BL3A, BL5A... Become VA2 (eg, 1.7V) and (dummy) bit lines BL1B, BL3B, BL5B. It is precharged to VB2 (for example, 1.5 V) (time t5). VA1 is 0 V, and the bit lines BL0A, BL2A, BL4A, BL6A,... Are grounded.

  When the precharge ends, PRA2 and PRB2 become Vss, and the bit lines BL1A, BL3A, BL5A. Thereafter, desired voltages are applied from the row decoder 3 to the selection gate and the control gate (time t6). The control gate CG1 is at 0V, CG2 to CG8 are at Vcc (for example, 3V), SG2 is at 3V (Vsgh), and SG1 is at 1.5V (Vsgl). When the data written in the memory cells MC11, MC31, MC51,... Is "0", the cell current does not flow because the threshold voltage of the memory cell is positive, and the potential of the bit lines BL1A, BL3A, BL5A. It remains at 7V. When the data is "1", a cell current flows and the potentials of the bit lines BL1A, BL3A, BL5A... Decrease to 1.5 V or less. Since the selection gate SG1 is 1.5V, the E-type selection MOS transistors ST01, ST21, ST41 are turned off, and the data of the memory cells MC01, MC21, MC41,... Is not transferred to the bit lines.

  After the bit line discharge, the verify signal VRFYA becomes 3V (time t7), and when the data written to the memory cells MC11, MC31, MC51,... Is "1", the bit lines BL1A, BL3A, BL5A. Charged. Here, the voltage level of the charging performed by the verify signal only needs to be 1.5 V or more of the precharge voltage of the bit line BLjB (j = 1, 3, 5,...).

  During this time, the (dummy) bit lines BL1B, BL3B, BL5B... Are kept at a precharge potential of 1.5V.

  Then, at time t8, .phi.P becomes 3 V and .phi.N becomes 0 V, and the CMOS flip-flop FF is inactivated. At time t9, .phi.E becomes 3 V, so that the SA2 CMOS flip-flop FF is equalized, and the nodes N1 and N2 become equal. Vcc / 2 (for example, 1.5 V). At time t10, SS2, SA, SB become 3V and the bit lines are connected to the sense amplifier. Then, .phi.N is changed from 0V to 3V, .phi.P is changed from 3V to 0V, and bit lines BL1A, BL3A, BL5A... The potential difference between BL3B, BL5B ... is amplified, and the sense amplifier latches the rewritten data (time t11).

  The bit lines BL0A, BL2A, BL4A, BL6A... Are grounded to 0 V through the verify read operation. That is, every other bit line is grounded.

  As described above, in the present invention, since the source line is replaced with a low-resistance bit line, the floating of the source line is significantly reduced, and as a result (problem 1), the random access time is shortened. In addition, the variation in the threshold value at the time of writing caused by circuit factors is significantly reduced. Further, since the source lines are not shared between the adjacent NAND cell columns, the data of the memory cells is not erroneously read by the data of the adjacent memory cells as described in (Problem 1).

  As described in the above embodiment, first, at the time of writing, the channel of the memory cell is charged with Vcc-Vth. The way of charging is arbitrary. In the above embodiment, when writing data to the memory cells MC11, MC31, MC51,..., First, the selection gate SG1 is set to Vss, SG2 is set to Vcc, and the bit lines BL0A, BL2A, BL4A are set to Vcc, and the bit lines BL0A, BL2A are set. , BL4A,..., The memory cells MC01, MC21, MC31, MC41, MC51,. In addition to this method, for example, the bit lines BL0A, BL1A, BL2A, BL3A... Are charged to Vcc and SG1, SG2, CG1 to CG8 are set to Vcc, so that the memory cells MC01 from the bit lines at both ends to which the NAND string is connected. , MC11, MC21, MC31... May be charged with Vcc (-Vth).

  Alternatively, by setting the bit lines BL1A, BL3A, BL5A... To Vcc, SG2 to Vss, and SG1, CG1 to CG8 to Vcc, the bit lines BL1A, BL3A, BL5A ... to the channels of the memory cells MC01, MC11, MC21, MC31. You may charge it.

  Further, both SG1 and SG2 may be set to Vsgl, and the bit lines BL0A, BL2A, BL4A... May be set to Vcc. In this case, the I-type selection MOS transistor is turned on, but the E-type selection MOS transistor is turned off. Therefore, the bit lines BL0A, BL2A, BL4A,. Write potentials (Vcc for "1" write, Vss for "0" write) can be transferred from BL3A, BL5A... To the memory cell unit 1 almost simultaneously.

  In the above embodiment, writing is performed simultaneously on the memory cells corresponding to １ ／ page. For example, when writing to the memory cells MC11, MC31, MC51... In FIG. 2, write data is transferred from the bit lines BL1A, BL3A, BL5A. , And the bit lines BL0A, BL2A, BL4A are kept at a constant potential such as Vcc, 0V. On the other hand, when writing to the memory cells MC01, MC21, MC41,..., The write data is transferred from the bit lines BL0A, BL2A, BL4A,. BL1A, BL3A and BL5A are kept at a constant potential such as Vcc and 0V.

  As described above, in the above embodiment, the writing is performed almost simultaneously on the memory cells of the ペ ー ジ page. However, according to the present invention, the writing can be performed almost simultaneously on the memory cells of the one page. For example, both the selection gates SG1 and SG2 may be set to Vsgl (for example, 1.5 V) (FIG. 12). Then, the E-type selection MOS transistor having the selection gates SG1 and SG2 as gate electrodes is turned off, and the I-type selection MOS transistor is turned on. The write data of the memory cells MC11, MC31, MC51,... Is transferred from the bit lines BL1A, BL3A, BL5A,. That is, in the case of "0" writing, the bit line and the channel of the memory cell to be written become 0 V, and in the case of "1" writing, the bit line becomes Vcc, and the channel floats at Vcc-Vth. Similarly, the write data of the memory cells MC01, MC21, MC41,... Is transferred from the bit lines BL0A, BL2A, BL4A,.

  As described above, in this embodiment, since the number of bit lines arranged in the column direction and the number of NAND cell columns in the column direction are substantially the same, by giving data to be written to the memory cells to each bit line, 1 Data for pages can be written almost simultaneously. After the write operation, a verify read is performed to check whether the write has been sufficiently performed. In the verify read operation of the above embodiment, data of one memory cell is read using two bit lines. That is, data for 1/2 page is read almost simultaneously.

  Therefore, in the method of writing data for one page almost simultaneously, the verify read operation may be performed twice for each write operation. In the method of performing the verify read twice for one write operation, the total time for writing data for one page is approximately Tpr + 2Tvfy (Tpr: write pulse width, Tvfy: one verify read time). On the other hand, in the method of writing data of ２ page almost at the same time, the total writing time for writing data of one page is about 2 (Tpr + Tvfy). Be fast.

  In the present invention, it is sufficient if there is a difference between the threshold voltages of the selection MOS transistors (for example, the selection MOS transistors ST12 and ST22 and ST32 and ST42 in FIG. 2) of the two NAND strings sharing the bit line contact and the selection gate. How to set the threshold voltage of the MOS transistor is arbitrary. In FIG. 2, the threshold voltages of the select MOS transistors ST02 and ST03, ST12 and ST13, and ST22 and ST23 are set to be substantially the same. For example, as shown in FIGS. The other select MOS transistor may be of the E type.

  In the above embodiment, a sense amplifier is connected for each bit line, but a so-called shared sense amplifier system (FIG. 15) in which one sense amplifier is connected to two bit lines may be used. The timing charts for writing and reading in this case are almost the same as those in the above-described embodiment (FIGS. 5, 10 and 11).

  According to the present invention, a conductive MOS transistor and a non-conductive MOS transistor can be generated among select MOS transistors sharing one select gate. By preparing two such select gates, This utilizes the fact that a selected memory cell and a non-selected memory cell can be easily realized in a memory cell having the same selection gate.

  Therefore, the threshold voltage of the selection MOS transistor and the voltage applied to the selection gate have arbitrary characteristics. One end of the memory cell, the selection MOS transistor has two threshold voltages Vtd1 and Vtd2 (Vtd1> Vtd2), and the voltages applied to the selection gate are Vsghd (Vsghd> Vtd1) and Vsgld (Vtd1> Vsgld> Vtd2), and the selection MOS transistor at the other end of the memory cell has two threshold voltages Vts1, Vts2 (Vts1> Vts2), and the voltage applied to the selection gate is Vsghs (Vsghs>). Vts1) and Vsgls (Vts1> Vsgls> Vts2) may be used, and Vtd1 = Vts1, Vtd2 = Vts2, Vsghd = Vsghs, and Vsgld = Vsgls as in the above embodiment.

  For example, the threshold voltage of the selection MOS transistor at one end of the memory cell is set to two types of 2 V and 0.5 V, and the threshold voltage of the selection MOS transistor at the other end of the memory cell is set to 2 V of 2.5 V and 1 V. As a type, the voltage applied to the selection gate at one end of the memory cell is Vsgh = 3V, Vsgl = 1.5V, and the voltage applied to the selection gate at the other end of the memory cell is Vsgh = 3V, Vsgl = 1.2V. Is also good.

  Also, the threshold voltages of the two select MOS transistors connected to one NAND string may be substantially the same. For example, the threshold voltage of two select MOS transistors connected to a certain NAND string is 0.8 V, and the select MOS transistor on one end side of an adjacent NAND cell shares the gate electrode of the select MOS transistor with the NAND string. The threshold voltage is 0.2 V, the threshold voltage of the select MOS transistor on the other end of the memory cell is 1.4, and the voltage applied to the select gate on one end of the NAND cell is Vsgh = 3 V, Vsgl = 0. The voltage applied to the selection gate at 5 V and the other end of the NAND cell may be Vsgh = 3 V and Vsgl = 1.2 V.

  If Vsgh is made larger than Vcc, it leads to an increase in the conductance of the selection MOS transistor (that is, a decrease in resistance), and the cell current flowing through the NAND cell array at the time of reading increases, so that the bit line discharge time becomes shorter. The result read and write verify read are speeded up. Vsgh may be boosted from Vcc by a booster circuit in the chip, for example.

  The selection MOS transistors sharing one selection gate are all turned on. The voltage Vsgh of the selection gate is desirably equal to or lower than the power supply voltage Vcc. When Vsgh is larger than Vcc, a booster circuit is required in the chip, which leads to an increase in chip area.

  The larger value Vt1 of the threshold voltage of the selection MOS transistor may also be set to a voltage higher than the power supply voltage Vcc (for example, 3.5 V). In this case, in order to turn on the selection MOS transistor having the threshold voltage of Vt1 at the time of reading or verify reading, for example, 4 V may be applied to the selection gate using, for example, a booster circuit inside the chip.

  As a method of changing the threshold voltage, changing the gate oxide film thickness of the selection MOS transistor, changing the concentration of the channel-doped impurity in the selection MOS transistor, and the like can be considered. Alternatively, the threshold voltage may be different depending on whether or not the select MOS transistor is channel-doped with impurities. The threshold voltage can also be changed by changing the channel length of the selection MOS transistor. That is, since the threshold voltage of a transistor having a short channel length is reduced due to the short channel effect, the transistor may be an I-type transistor.

  As a method of changing the gate oxide film thickness and the impurity concentration of the channel, another manufacturing process such as channel doping of a peripheral circuit may be used without introducing a new manufacturing process. In either method, the threshold voltage of the selection MOS transistor may be made different, and if the threshold voltage is made different, a predetermined threshold voltage can be obtained by a substrate bias or the like.

  When 0 V is applied to a select gate on one end side of the write block (for example, SG2 when writing is performed on the memory cells MC11, MC31, MC51,... In FIG. 2), a select MOS transistor using the select gate as a gate electrode is formed. When the threshold voltage Vt2 is about 0.1 V (or a negative threshold voltage) in the I type, the select MOS transistor does not completely cut off and a cell current flows. As a result, the channel of the memory cell in which writing is not selected or "1" is written is not boosted from Vcc-Vth to the intermediate potential VM, or even if the channel is boosted, the cell current flows and the potential drops from VM. In any case, since the channel of the memory cell in which writing is not selected or "1" is written falls from VM, "0" is erroneously written.

  In order to improve the cutoff characteristics of the I-type transistor, bit lines to which write data is not applied at the time of writing (BL0A, BL2A, BL4A... When writing to the memory cells MC11, MC31, MC51... In FIG. 2) A voltage of, for example, about 0.5 V may be applied to the above. When 0.5 V is applied to the source of the selection MOS transistor, the potential difference between the source and the substrate becomes -0.5 V, and the threshold voltage of the I-type transistor increases due to the substrate bias effect. Cutoff characteristics when 0 V is applied to the substrate.

  In order to set the smaller (I type) threshold voltage among the threshold voltages of the selection MOS transistors to, for example, 0.5 V, a method of reducing the substrate concentration is considered. In an I-type transistor having a low substrate concentration, when a drain voltage is applied without applying a gate voltage, a depletion layer between the drain and the substrate expands, and as a result, a depletion layer between the drain and the substrate and a depletion layer between the source and the substrate are reduced. However, there is a problem in that the connection and the dullness (punch through) occur. In order to increase the punch-through breakdown voltage of the I-type select MOS transistor, the channel length L of the I-type select MOS transistor may be increased.

(Embodiment 2)
The configuration of the NAND cell type EEPROM according to the present embodiment is the same as that of FIG. FIG. 16 shows the memory cell array 11A of this embodiment, and FIG. 17 shows the memory cell array 11B. As in the first embodiment, two or more threshold voltages of the selection MOS transistor are provided. Also in the memory cell array according to the present embodiment (FIGS. 16 and 17), since one bit line contact is shared by four NAND cell columns, the number of bit line contacts in the entire memory cell array is increased from the conventional memory cell array. do not do. The sense amplifier SA1 connected to the bit lines BL0A, BL2A, BL4A... Is shown in FIG. 6, and the sense amplifier SA2 connected to the bit lines BL1A, BL3A, BL5A.

  FIG. 18 shows the n-type diffusion layer of the memory cell according to the present embodiment, the source / gate / drain regions of the memory cell, and the contacts (bit line contacts) connecting the n-type diffusion layer to bit lines (such as Al). I have. As described above, in the conventional memory cell array, since the bit line contacts of adjacent bit lines are arranged adjacently as shown in FIG. 41, it is difficult to reduce the size in the column direction (X direction in FIG. 41). There is. On the other hand, in the memory cell array according to the present embodiment, the bit line contacts of the adjacent bit lines are not arranged adjacent to each other as shown in FIG. Does not cause a problem when the column direction (X direction) of the memory cell array is reduced, and the element isolation width between memory cells is determined by the field inversion breakdown voltage between adjacent NAND cell columns, element isolation technology, and the like. It can be reduced to the determined minimum element isolation region width L0.

<Read operation>
Here, the read operation will be described with reference to a timing chart.

  FIG. 19 is a timing chart for reading data written in the memory cells MC11, MC31, MC51,... In FIG.

  First, the precharge signals PRA1, PRA2, PRB2 change from Vss to Vcc (time t0), the bit lines BL1A, BL3A, BL5A... Change to VA2 (for example, 1.7V), and the (dummy) bit lines BL1B, BL3B, BL5B. Are precharged to VB2 (for example, 1.5 V) (time t1). VA1 is 0 V, and the bit lines BL0A, BL2A, BL4A, BL6A,... Are grounded.

  When the precharge ends, PRA2 and PRB2 become Vss, and the bit lines BL1A, BL3A, BL5A. Thereafter, a desired voltage is applied from the row decoder 3 to the selection gate and the control gate (time t2). The control gate CG1 is at 0V, CG2 to CG8 are at Vcc (for example, 3V), SG2 is at 3V (Vsgh), and SG1 is at 1.5V (Vsgl).

  When the data written in the memory cells MC11, MC31, MC51,... Is "0", the cell current does not flow because the threshold voltage of the memory cell is positive, and the potential of the bit lines BL1A, BL3A, BL5A. It remains at 7V. When the data is "1", a cell current flows and the potentials of the bit lines BL1A, BL3A, BL5A... Decrease to 1.5 V or less. Since the selection gate SG1 is 1.5 V, the E-type selection MOS transistors ST01, ST21, ST41,... Are turned off, and the data of the memory cells MC01, MC21, MC41,. During this time, the (dummy) bit lines BL1B, BL3B, BL5B... Are kept at a precharge potential of 1.5V. Thereafter, at time t3, .phi.P becomes 3 V and .phi.N becomes 0 V, the CMOS flip-flop FF is inactivated, and at time t4, .phi.E becomes 3 V, whereby the SA2 CMOS flip-flop FF is equalized and the nodes N1 and N2 become Vcc. / 2 (for example, 1.5 V). At time t5, after SS2, SA, SB become 3V and the bit line and the sense amplifier are connected, φN becomes 0V to 3V, φP becomes 3V to 0V, and bit lines BL1A, BL3A, BL5A ... and bit line BL1B , BL3B, BL5B... Are amplified (time t6).

  That is, if "0" is written in the memory cells MC11, MC31, MC51,..., The node N1 of SA2 becomes 3 V, the node N2 becomes 0 V, and "1" is written in the memory cells MC11, MC31, MC51,. And the node N1 becomes 0V and the node N2 becomes 3V. Thereafter, when the column selection signal CSL changes from 0 V to 3 V, the data latched by the CMOS flip-flop is output to IO and / IO (time t7).

  Through the read operation, the bit lines BL0A, BL2A, BL4A, BL6A,... Are grounded to 0V. The bit lines BL0B, BL2B, BL4B, BL6B... May be grounded by setting PRB1 to Vcc and VB1 to 0V through the read operation. As a result, it is possible to reduce inter-bit line capacitive coupling noise during bit line potential amplification.

  FIG. 20 is a timing chart when data written in the memory cells MC01, MC21, MC41... In FIG. 16 is read out to bit lines BL0B, BL2B, BL4B, BL6B.

<Write operation>
Here, the write operation of the present invention will be described with reference to a timing chart. FIGS. 21 and 22 are timing charts in the case where the memory cell MC11 (and the memory cells MC31, MC51,...) Is written.

  Data to be written into the memory cells MC11, MC31, MC51,... Is latched in the sense amplifier circuit (SA2 in FIG. 7). That is, in the case of "0" write, the node N1 is at 0V, N2 is 3V, and in the case of "1" write, the node N1 is at 3V and N2 is at 0V.

  When the write operation starts, SG1 is set to Vss and SG2, CG1 to CG8 are set to Vcc at time t1. In the present embodiment, when writing to the memory cells MC11, MC31, MC51,..., Writing is not performed to the memory cells MC01, MC21, MC41,. For this purpose, the channels of the memory cells MC01, MC21, MC41,... Need to be charged from the bit lines BL0A, BL2A, BL4A,. In this embodiment, the bit lines BL0A, BL2A, BL4A,... Are charged from VA1 to Vcc of the sense amplifier SA1 in FIG. As a result, the channels of the memory cells MC01, MC21, MC41 ... are charged to Vcc-Vth. At this time, the channels of the memory cells MC11, MC31, MC51 ... are also charged to Vcc-Vth.

  The bit lines BL1A, BL3A, BL5A,... Are supplied with a potential of Vcc or Vss (0 V) according to the data latched in the sense amplifier circuit SA2. Thus, for example, when "0" is written to the memory cell MC11, the bit line BL1A is set to 0V and the channel of the memory cell MC11 is set to 0V. When "1" is written to the memory cell MC11, the bit line BL1A is set to Vcc (for example, 3 V), and the channel of the memory cell MC11 is charged to Vcc-Vth. The selection gate SG2 is at 0 V, and the selection MOS transistor using SG2 as a gate electrode is off.

  After the bit line is charged, the selection gate SG1 is set to Vsgl (for example, 1.5 V) and the selection gate SG2 is set to Vss. Since the selection MOS transistors ST01, ST21, ST41,... To which the memory cells MC01, MC21, MC41.

  The drains on the memory cell side of the select MOS transistors ST11, ST31, ST51,... Of the memory cells MC11, MC31, MC51,... For writing "1" are Vcc-Vth (for example, the threshold voltage of the I-type transistor is 0.8 V). Then, since the source on the bit line contact side is Vcc (for example, 3 V) and the selection gate SG1 is Vsgl (for example, 1.5 V), the selection MOS transistors ST11, ST31, ST51,. I do. As a result, the channels of the memory cells MC11, MC31, MC51,.

  When "0" is written to the memory cells MC11, MC31, MC51,..., The selection gate SG1 of the selection MOS transistors ST11, ST31, ST51,. The transistors ST11, ST31, ST51,... Are turned on, and the channel of the memory cell is maintained at 0V.

  After the selection gate SG1 is set to Vsgl (for example, 1.5 V), the control gates CG1 to CG8 are changed from Vcc to the intermediate potential VM (about 10 V) at time t2. Since the channels of the memory cells MC01, MC21, MC41... To which no data is to be written and the memory cells MC11, MC31, MC51. It rises to the potential (about 10 V). The channels of the memory cells MC11, MC31, MC51,... To which "0" is written are at 0V because the bit lines are at 0V.

  After the channel of the memory cell performing the write non-selection and "1" write rises from Vcc-Vth to the intermediate potential, the control gate CG1 is boosted from the intermediate potential VM to the write voltage Vpp (20 V) at time t3. Then, the channels of the memory cells MC01, MC21, MC41... To which no data is to be written and the memory cells MC11, MC31, MC51. Although the memory cell is not written, since the channel of the memory cells MC11, MC31, MC51... For writing "0" is 0V and the control gate is Vpp (about 20V), electrons are injected from the substrate into the floating gate to "0". Writing is performed.

  After the writing is completed, the control gate, the selection gate, and the bit line are sequentially discharged, and the writing operation ends.

  After the end of the write, a write verify operation is performed to check whether the write has been performed sufficiently.

  First, the precharge signals PRA1, PRA2, PRB2 change from Vss to Vcc (time t4), the bit lines BL1A, BL3A, BL5A... Change to VA2 (eg, 1.7V), and (dummy) bit lines BL1B, BL3B, BL5B. Are precharged to VB2 (for example, 1.5 V) (time t5). VA1 is 0 V, and the bit lines BL0A, BL2A, BL4A, BL6A,... Are grounded.

  When the precharge ends, PRA2 and PRB2 become Vss, and the bit lines BL1A, BL3A, BL5A. Thereafter, desired voltages are applied from the row decoder 3 to the selection gate and the control gate (time t6). The control gate CG1 is at 0V, CG2 to CG8 are at Vcc (for example, 3V), SG2 is at 3V (Vsgh), and SG1 is at 1.5V (Vsgl). When the data written in the memory cells MC11, MC31, MC51,... Is "0", the cell current does not flow because the threshold voltage of the memory cell is positive, and the potential of the bit lines BL1A, BL3A, BL5A. It remains at 7V. When the data is "1", a cell current flows and the potentials of the bit lines BL1A, BL3A, BL5A... Decrease to 1.5 V or less. Since the selection gate SG1 is 1.5V, the E-type selection MOS transistors ST01, ST21, ST41 are turned off, and the data of the memory cells MC01, MC21, MC41,... Is not transferred to the bit lines.

  After the bit line discharge, the verify signal VRFYA becomes 3V (time t7), and when the data to be written into the memory cells MC11, MC31, MC51... Is "1", the bit lines BL1A, BL3A, BL5A. Is charged. Here, the voltage level of the charging performed by the verify signal may be 1.5 V or more of the precharge voltage of the bit line BLjB (j = 0, 1 to 127).

  During this time, the (dummy) bit lines BL1B, BL3B, BL5B... Are kept at a precharge potential of 1.5V.

  Thereafter, at time t8, .phi.P becomes 3 V and .phi.N becomes 0 V, and the CMOS flip-flop FF is inactivated. At time t9, .phi.E becomes 3 V, whereby the CMOS flip-flop FF of SA2 is equalized, and the nodes N1 and N2 become Vcc. / 2 (for example, 1.5 V). At time t10, SS2, SA, SB become 3V and the bit lines are connected to the sense amplifier. Then, .phi.N is changed from 0V to 3V, .phi.P is changed from 3V to 0V, and bit lines BL1A, BL3A, BL5A... The potential difference between BL3B, BL5B ... is amplified, and the rewritten data is latched by the sense amplifier (time t11).

  Through the read operation, the bit lines BL0A, BL2A, BL4A, BL6A,... Are grounded to 0V. That is, every other bit line is grounded.

  In the present invention, if there is a difference between the threshold voltages of the selection MOS transistors (for example, the selection MOS transistors ST02 and ST12 and ST22 and ST32 in FIG. 16) of the two NAND strings sharing the bit line contact and the selection gate, How to set the threshold voltage of the MOS transistor is arbitrary. In FIG. 16, the threshold voltages of the select MOS transistors ST02 and ST03, ST12 and ST13, and ST22 and ST23 are set to be substantially the same. For example, as shown in FIGS. The other select MOS transistor may be of the E type.

  In the above embodiment, a sense amplifier is connected for each bit line, but a so-called shared sense amplifier system (FIG. 15) in which one sense amplifier is connected to two bit lines may be used. The timing charts for writing and reading in this case are almost the same as those in the above embodiment (FIGS. 19, 21 and 22). Further, similarly to the first embodiment, data for one page can be written substantially simultaneously.

(Embodiment 3)
The above-described embodiment utilizes the fact that, of the select MOS transistors sharing one select gate, a conductive MOS transistor and a non-conductive MOS transistor can be generated. Therefore, the smaller threshold voltage Vt2 of the selection MOS transistor may be a negative threshold voltage (for example, -1 V). FIG. 25 shows a memory cell array in this case, for example. In FIG. 25, a select MOS transistor having a negative threshold voltage is described as a D type. In the above-described embodiment, at the time of writing or reading, the application of the voltage Vsgl (for example, 1.5 V) that turns on the E-type selection MOS transistor to the selection gate but turns on the I-type selection MOS transistor is used. In this embodiment, since the E-type selection MOS transistor and the D-type selection MOS transistor are used, Vsgl may be set to 0 V, may be set to a positive voltage (for example, 0.5 V), or may be set to a negative voltage (for example, -0). .5V).

  Further, at the time of reading or writing, the selection gates of the non-selected blocks (for example, when the memory cells MC11, MC31, MC51... Shown in FIG. 25 are written) are not connected to the selection gates SG3, SG4, SG5, SG6. Although 0 V is applied in the above embodiment, a negative voltage (for example, -2 V) may be applied so that the D-type selection MOS transistor is turned off. If the D-type selection MOS transistor in the unselected block is turned off, the bit line potential is applied to the drain or channel of the memory cell via the selection MOS transistor during reading or writing, and the memory cell is not erased erroneously. The electric charge of the bit line does not leak to the unselected block, so that it does not take a long time to precharge the bit line at the time of reading and writing.

(Embodiment 4)
In the above embodiment, two kinds of threshold voltages of the selection MOS transistor are provided, but the number is not limited to two. For example, the selection MOS transistor may have three types of threshold voltages. FIG. 26 shows an embodiment in which the selection MOS transistor has three types of threshold voltages. Assuming that the threshold voltage of the E-type transistor is Vth1, the threshold voltage of the I-type transistor is Vth2, and the threshold voltage of the I′-type transistor is Vth3, Vth1>Vth2> Vth3. In addition, three types of voltages to be applied to the selection gate may be set to Vsgh (Vsgh> Vth1), Vsgm (Vth1>Vsgm> Vth2), and Vsgl (Vth2>Vsgl> Vth3). By applying these three types of voltages to the select gate, both ends of one of the memory cell units (1), 2, and 3 in FIG. 26 can be connected to the bit line.

  When reading data written in the memory cells MC01, MC11, and MC21 in FIG. 26, 0 V is applied to the control gate CG1, and Vcc is applied to CG2 to CG8. When reading the memory cell unit (1) in which the memory cell MC01 is disposed, if the selection gate SG1 is set to Vsgl and SG2 is set to Vsgh, the memory cell unit among the selection MOS transistors having the selection gate SG1 as a gate electrode is selected. Only the selection MOS transistor (eg, ST01) belonging to (1) is turned on. All the selection MOS transistors having the selection gate SG2 as a gate electrode are turned on. Therefore, a current path connecting the bit lines BL2A and BL3A is formed through the memory cell unit (1), so that the memory cell MC01 can be read.

  When reading the memory cell unit (2) in which the memory cell MC11 is provided, if the selection gate SG1 is set to Vsgm and SG2 is set to Vsgm, the selection MOS transistor and the selection gate SG2 having the selection gate SG1 as a gate electrode are connected. It is only the memory cell unit (2) that both of the select MOS transistors serving as gate electrodes are turned on. Therefore, a current path connecting the bit lines BL3A and BL4A is formed through the memory cell unit (2), so that data written in the memory cell MC11 can be read.

  When reading the memory cell unit 3 in which the memory cell MC21 is disposed, if the selection gate SG1 is set to Vsgh and SG2 is set to Vsgl, the memory cell unit 3 of the selection MOS transistors having the selection gate SG2 as the gate electrode is read. Only the select MOS transistor to which it belongs (eg, ST22) conducts. All the selection MOS transistors having the selection gate SG1 as a gate electrode are turned on. Therefore, a current path connecting the bit lines BL3A and BL4A is formed through the memory cell unit 3, so that the memory cell MC21 can be read.

  As described above, even when the threshold voltage of the selection MOS transistor is three or more, if the voltage applied to the selection gate is three or more, one of the three or more memory cell units is set to the selected state. be able to. As a result, as described in the first to third embodiments, not only the bit line contact margin can be increased, but also the wiring margin of the bit line itself can be increased. For example, in the embodiment of FIG. 26, two bit lines are arranged at a pitch of three memory cells, so that the number of bit lines is 2/3 that of a conventional memory cell, and the bit line wiring is reduced. Become easy.

(Embodiment 5)
In the above embodiment, two selection MOS transistors are provided for one NAND cell row in which memory cells are connected in series. However, for example, as shown in FIG. 27, three selection MOS transistors are provided for one NAND cell row, and one memory cell is provided. A cell unit may be configured. In the following, description will be made by taking as an example a memory cell unit (1) including the memory cell MC11 and a memory cell unit (2) including the memory cell MC21 in FIG.

  One end of the NAND cell row is connected to a bit line (for example, bit line BL2A) via two select MOS transistors (for example, ST13 and ST14), and the other end is connected to a bit for one select MOS transistor (for example, ST11). Line (eg, bit line BL1A). The two selection MOS transistors connected in series are of an E type (threshold voltage Vth1> 0) and a D type (threshold voltage Vth2 <0). The selection MOS transistor (eg, ST13) of the memory cell unit (1) having the selection gate SG2 as a gate electrode is a D type, and the selection MOS transistor (eg, ST23) of the memory cell unit (2) is an E type. The selection MOS transistor (for example, ST24) of the memory cell unit (2) having the selection gate SG3 as a gate electrode is of the D type, and the selection MOS transistor (for example, ST14) of the memory cell unit (1) is of the E type.

  The selection MOS transistors (eg, ST11 and ST21) at the other end of the NAND cell are of the E 'type (threshold voltage Vth3). Vth3 may be equal to one of Vth1 and Vth2, or may be a value different from Vth1 and Vth2. For example, Vth3 may be set to 0.7V.

  Hereinafter, a read operation and a write operation of the present embodiment will be described.

<Read operation>
When the data of the memory cells MC11, MC31, MC51... In the memory cell unit (1) is read out to the bit lines BL2A, BL4A, BL6A..., First, the bit lines BL2A, BL4A, BL6A. 1.8 V), and BL1A, BL3A, BL5A ... are grounded to 0V. After precharging, the bit lines BL2A, BL4A, BL6A,.

  Next, the control gate CG1 is set to 0V, and CG2 to CG8 are set to Vcc (for example, 3V). The selection gates SG1 and SG3 are set to Vcc, and the selection gate SG2 is set to Vss. Other select gates and control gates are set to 0V. In this case, all the select MOS transistors (ST01, ST11, ST21..., ST04, ST14, ST24...) Using the select gates SG1 and SG3 as gate electrodes are turned on. The D-type selection MOS transistors (ST13, ST33, ST53,...) Having the selection gate SG2 as a gate electrode are turned on, while the E-type selection MOS transistors (ST03, ST23, ST43,...) Are turned off.

  Therefore, if the data written in the memory cells MC11, MC31, MC51,... Is "1", the precharged bit lines BL2A, BL4A, BL6A, etc. are discharged to the grounded bit lines BL1A, BL3A, BL5A,. , And the data of the memory cells MC11, MC31, MC51... In the memory cell unit (1) is read out to the bit lines BL2A, BL4A, BL6A. On the other hand, if the data written in the memory cell is "0", the bit lines BL2A, BL4A, BL6A... Do not discharge and maintain the precharge potential.

  In the above embodiment, the bit lines BL2A, BL4A, BL6A ... are precharged and the bit lines BL1A, BL3A, BL5A ... are grounded. Conversely, the bit lines BL2A, BL4A, BL6A ... are grounded, and the bit lines BL1A, BL6A ... BL3A, BL5A... May be precharged, and the data of the memory cells may be read out to the bit lines BL1A, BL3A, BL5A.

  On the other hand, for the memory cells MC01, MC21, MC41,... In the memory cell unit (2), the E-type selection MOS transistors ST03, ST23, ST43,. The data of MC41 is not read out to the bit line.

  When the data of the memory cells MC01, MC21, MC41,... In the memory cell unit (2) is read out to the bit lines BL0A, BL2A, BL4A, BL6A, etc., the selection gates SG1, SG2 are set to Vcc, and the selection gate SG3 is set to Vss. . The control gate CG1 is set to 0V, and CG2 to CG8 are set to Vcc. In this case, all the selection MOS transistors (ST01, ST11, ST21,..., ST03, ST13, ST23...) Having the selection gates SG1 and SG2 as gate electrodes are turned on. The D-type selection MOS transistors (ST04, ST24, ST44...) Having the selection gate SG3 as a gate electrode are turned on, while the E-type selection MOS transistors (ST14, ST34, ST54...) Are turned off.

  Therefore, the selection MOS transistors that connect the memory cells in the memory cell unit (2) and the bit lines are all turned on, so that the data in the memory cells MC01, MC21, MC41,... In the memory cell unit (2) is read out to the bit lines. It is. In the memory cell unit (1), since the selection MOS transistor having the selection gate SG3 as a gate electrode is turned off, no data is read to the bit line.

<Write>
The writing procedure when writing to the memory cells MC11, MC31, MC51,... In the memory cell unit (1) will be described below.

  The selection gate SG1 is set to 0 V, and all the selection MOS transistors using the selection gate SG1 as a gate electrode are turned off. SG2, SG3, and CG1 to CG8 are set to Vcc, and the bit lines BL0A, BL1A, BL2A, BL3A. For this reason, the potential becomes lower than the bit line potential Vcc.).

  Thereafter, when the selection gate SG2 is set to Vss (0 V), the D-type selection MOS transistors ST13, ST33, ST53,... Using the selection gate SG2 as the gate electrode are turned on, but the E-type selection MOS transistors ST03, ST23, ST43,. , The channels of the unwritten memory cells MC01, MC21, MC41,... Float at the potential Vcc-Vth charged from the bit line. At this time, the selection gate SG3 remains at Vcc.

  Data to be written into the memory cells MC11, MC31, MC51,... In the memory cell unit (1) is supplied from bit lines BL2A, BL4A, BL6A,. For example, when "0" is to be written to the memory cell MC11, when the bit line BL2A is set to 0V, SG3 is Vcc, so that the E-type selection MOS transistor ST14 is turned on and the channel of the memory cell MC11 becomes 0V. When "1" is written to the memory cell MC11, when the bit line BL2A is set to 3 V, the E-type selection MOS transistor ST14 is turned off, and the channel of the memory cell MC11 becomes floating at Vcc-Vth. The bit lines BL1A, BL3A, BL5A... May be set to Vcc or 0V, or may be set to an arbitrary voltage.

  After the selection gate SG2 is changed from Vcc to Vss, the control gates CG1 to CG8 are changed from Vcc to the intermediate potential VM (about 10 V). Since the channels of the memory cells MC01, MC21, MC41,... To which no data is to be written and the memory cells MC11, MC31, MC51,. (About 10 V). The channels of the memory cells MC11, MC31, MC51,... To which "0" is written are at 0V because the bit lines are at 0V.

  After the channel of the memory cell in which writing is not selected and "1" is written rises from Vcc-Vth to the intermediate potential, the control gate CG1 is boosted from the intermediate potential VM to the write voltage Vpp (20 V). Then, the memory cells MC01, MC21, MC41... And the memory cells MC11, MC31, MC51... For writing "1" in the memory cell unit (2) where no writing is performed have an intermediate potential (about 10 V), and the control gate CG1 has Vpp. (About 20 V), these memory cells are not written. However, since the channels of the memory cells MC11, MC31, MC51... For writing "0" are 0 V and the control gate is Vpp (about 20 V), electrons are transferred from the substrate to the floating gate. Is injected, and "0" writing is performed.

  When writing to the memory cell unit (2), the channel of the memory cell unit (1) may be precharged to Vcc-Vth, and then the select gate SG2 may be set to Vcc and SG1 and SG3 may be set to Vss. In this case, write data to the memory cell unit (2) is transferred from the bit lines BL0A, BL2A, BL4A, BL6A. Alternatively, SG1 may be set to Vcc, SG2 and SG3 may be set to Vss, and precharging may be performed from the bit lines BL1A, BL3A, BL5A.

  In the present embodiment, when Vss is applied to the selection gate at the time of reading and writing, among the selection MOS transistors having this selection gate as the gate electrode, the E type selection MOS transistor is turned off, but the D type selection MOS transistor is turned on. Use that thing. The D-type selection MOS transistor may be an I-type (threshold voltage is positive). In this case, instead of applying Vss to the selection gate, Vsgl which turns off the E type but turns on the I type selection MOS transistor may be applied.

(Embodiment 6)
As shown in FIG. 28, four selection MOS transistors may be provided for one NAND cell column to form one memory cell unit. Hereinafter, a description will be given of a memory cell unit (1) including the memory cell MC11 of FIG. 28 and a memory cell unit (2) including the memory cell MC21 as an example.

  One end of the NAND cell row is connected to a bit line (for example, bit line BL2A) via two selection MOS transistors (for example, ST13 and ST14), and the other end is also connected to two selection MOS transistors (for example, ST11 and ST12). Connected to a bit line (for example, bit line BL1A). The two selection MOS transistors connected in series are of the E type (threshold voltage Vth1> 0) and the D type (threshold voltage Vth2 <0). The selection MOS transistors (eg, ST11 and ST13) of the memory cell unit (1) having the selection gates SG1 and SG3 as gate electrodes are of the D type, and the selection MOS transistors (eg, ST21 and ST23) of the memory cell unit (2) are of the E type. is there. The selection MOS transistors (eg, ST22 and ST24) of the memory cell unit (2) having the selection gates SG2 and SG4 as gate electrodes are of the D type, and the selection MOS transistors (eg, ST12 and ST14) of the memory cell unit (1) are of the E type. is there.

  Hereinafter, a read operation and a write operation of the present embodiment will be described.

<Read operation>
When the data of the memory cells MC11, MC31, MC51... In the memory cell unit (1) is read out to the bit lines BL2A, BL4A, BL6A..., First, the bit lines BL2A, BL4A, BL6A. 1.8 V), and BL1A, BL3A, BL5A ... are grounded to 0V. After precharging, the bit lines BL2A, BL4A, BL6A,.

  Next, the control gate CG1 is set to 0V, and CG2 to CG8 are set to Vcc (for example, 3V). The selection gates SG2 and SG4 are set to Vcc, and one or both of the selection gates SG1 and SG3 are set to Vss. Other select gates and control gates are set to 0V. In this case, all the selection MOS transistors having the selection gates SG2 and SG4 as gate electrodes are turned on. D-type selection MOS transistors (ST11, ST13, ST31, ST33 ...) using the selection gates SG1 and SG3 as gate electrodes are turned on. Among the E-type selection MOS transistors having the selection gates SG1 and SG3 as gate electrodes, the E-type selection MOS transistor whose selection gate is Vss is turned off.

  Therefore, if the data written in the memory cells MC11, MC31, MC51,... Is "1", the precharged bit lines BL2A, BL4A, BL6A, etc. are discharged to the grounded bit lines BL1A, BL3A, BL5A and changed from the precharge potential. , And the data of the memory cells MC11, MC31, MC51... In the memory cell unit (1) is read out to the bit lines BL2A, BL4A, BL6A. On the other hand, if the data written in the memory cell is "0", the bit lines BL2A, BL4A, BL6A... Do not discharge and maintain the precharge potential.

  In the above embodiment, the bit lines BL2A, BL4A, BL6A ... are precharged and the bit lines BL1A, BL3A, BL5A ... are grounded. Conversely, the bit lines BL2A, BL4A, BL6A ... are grounded, and the bit lines BL1A, BL6A ... BL3A, BL5A... May be precharged, and the data of the memory cells may be read out to the bit lines BL1A, BL3A, BL5A.

  On the other hand, the memory cells MC01, MC21, MC41... In the memory cell unit (2) are either E-type selection MOS transistors having the selection gates SG1 and SG3 as gate electrodes (when one of SG1 and SG3 is set to Vss), Or both (when both SG1 and SG3 are set to Vss) are turned off, so that the data of the memory cells MC01, MC21, MC41,... Is not read out to the bit lines.

<Write>
The writing procedure when writing to the memory cells MC11, MC31, MC51,... In the memory cell unit (1) will be described below.

  When the selection gates SG1 and SG2 are set to Vss, one of the selection MOS transistors having the selection gates SG1 and SG2 as gate electrodes, that is, the E-type selection MOS transistor is turned off. SG3, SG4, CG1 to CG8 are set to Vcc, and the bit lines BL0A, BL1A, BL2A, BL3A... Are set to Vcc, and the channel of the block to be written is set to Vcc-Vth. (Less than the potential Vcc).

  Thereafter, when the selection gate SG3 is set to Vss (0 V), the D-type selection MOS transistors ST13, ST33, ST53,... Using the selection gate SG3 as a gate electrode are turned on, but the E-type selection MOS transistors ST03, ST23, ST43,. , The channels of the unwritten memory cells MC01, MC21, MC41,... Float at the potential Vcc-Vth charged from the bit line. At this time, the selection gate SG4 remains at Vcc.

  Data to be written into the memory cells MC11, MC31, MC51,... In the memory cell unit (1) is supplied from bit lines BL2A, BL4A, BL6A,. For example, when "0" is written to the memory cell MC11, when the bit line BL2A is set to 0V, SG4 is Vcc, so the E-type selection MOS transistor ST14 is turned on and the channel of the memory cell MC11 becomes 0V. When writing "1" to the memory cell MC11, when the bit line BL1A is set to 3 V, the E-type selection MOS transistor ST14 is turned off, and the channel of the memory cell MC11 becomes floating at Vcc-Vth. The bit lines BL1A, BL3A, BL5A... May be set to Vcc or 0V, or may be set to an arbitrary voltage.

  After the selection gate SG3 is changed from Vcc to Vss, the control gates CG1 to CG8 are changed from Vcc to the intermediate potential VM (about 10 V). Since the channels of the memory cells MC01, MC21, MC41,... To which no data is to be written and the memory cells MC11, MC31, MC51,. (About 10 V). The channels of the memory cells MC11, MC31, MC51,... To which "0" is written are at 0V because the bit lines are at 0V.

  After the channel of the memory cell in which writing is not selected and "1" is written rises from Vcc-Vth to the intermediate potential, the control gate CG1 is boosted from the intermediate potential VM to the write voltage Vpp (20 V). Then, the channels of the memory cells MC01, MC, MC41... And the memory cells MC11, MC31, MC51... For writing "1" in the non-written memory cell unit (2) have an intermediate potential (about 10 V), and the control gate CG1 Since Vpp (about 20 V), these memory cells are not written. However, since the channels of the memory cells MC11, MC31, MC51... For writing "0" are 0 V and the control gate is Vpp (about 20 V), the floating gate Is injected to write "0".

  Further, SG1 and SG4 may be set to Vcc, SG2 and SG3 may be set to Vss, and the bit lines BL1A, BL3A, BL5A. In this case, the write non-selection potential (Vcc) is written to the memory cell unit (2) from the bit lines BL1A, BL3A, BL5A..., And the write potential (writes "1") to the memory cell unit (1) from the bit lines BL2A, BL4A, BL5A. Then, Vcc, and if "0" is written, Vss) can be transferred almost simultaneously.

  When writing to the memory cell unit (2), after precharging the channel of the memory cell unit (1) to Vcc-Vth, the select gate SG3 may be set to Vcc, and SG1, SG2 and SG4 may be set to Vss. In this case, write data to the memory cell unit (2) is transferred from the bit lines BL0A, BL2A, BL4A, BL6A. Alternatively, the write data from the bit lines BL1A, BL3A, BL5A... To the memory cell unit (2) may be transferred by setting SG1 to Vcc and SG2, SG3, SG4 to Vss.

  When writing to the memory cell unit (1), writing may be performed to the memory cell unit (2) almost simultaneously. At this time, if SG1 and SG4 are set to Vcc and SG2 and SG3 are set to Vss, data to be written to the memory cell unit (1) is transferred from the bit lines BL2A, BL4A, BL6A. Are transferred from the lines BL1A, BL3A, BL5A.

  Even when the voltage of the selection gate is set as follows, it is possible to perform writing to the memory cell units (1) and (2) almost simultaneously. When SG1 and SG4 are set to Vss and SG2 and SG3 are set to Vcc, data to be written to the memory cell unit (2) is transferred from the bit lines BL0A, BL2A, BL4A, BL6A..., And data to be written to the memory cell unit (1) is a bit line. Are transferred from BL1A, BL3A, BL5A.

  In the present embodiment, when Vss is applied to the selection gate at the time of reading and writing, among the selection MOS transistors having this selection gate as the gate electrode, the E type selection MOS transistor is turned off, but the D type selection MOS transistor is turned on. Use that thing. The D-type selection MOS transistor may be an I-type (threshold voltage is positive). In this case, instead of applying Vss to the select gate, Vsgl which turns off the E type but turns on the I type may be applied.

  Another writing method according to the present embodiment will be described below.

  When writing the memory cells MC11, MC31, MC51... In the memory cell unit (1), the selection gates SG1 and SG4 are set to the intermediate potential VM, the selection gates SG2 and SG3 are set to 0 V, the control gate CG1 is set to Vpp, and CG2 to CG8 are set to VM. The E-type selection MOS transistors ST12, ST32, ST52,..., ST03, ST23, ST43,... Using the selection gates SG2, SG3 as gate electrodes are turned off. Therefore, the memory cell unit (1) becomes conductive with the bit lines BL2A, BL4A, BL6A... And becomes non-conductive with the bit lines BL1A, BL3A, BL5A. On the other hand, the memory cell unit (2) becomes nonconductive with the bit lines BL0A, BL2A, BL4A, BL6A,... And becomes conductive with the bit lines BL1A, BL3A, BL5A,.

  Therefore, the write data for the memory cells MC11, MC31, MC51,... May be supplied from the bit lines BL2A, BL4A, BL6A,. That is, the bit line is set to 0 V in the case of "0" writing, and to the intermediate potential VM in the case of "1" writing. If the threshold voltage of the D-type selection MOS transistor is, for example, −15 V, the potential VM of the bit line in the case of writing “1” can be transferred to the channel of the memory cell.

  On the other hand, when writing to the memory cells MC11, MC31, MC51,... Of the memory cell unit (1), writing to the memory cells MC01, MC21, MC41,. . When writing is not performed on the memory cells MC01, MC21, MC41,... Of the memory cell unit (2), the bit lines BL1A, BL3A, BL5A,. Accordingly, 0 V (in the case of “0” writing) or VM (in the case of “1” writing) may be applied.

  As described in (Embodiment 1), the present invention utilizes the fact that, of the select MOS transistors sharing one select gate, both a conductive MOS transistor and a non-conductive MOS transistor can be generated. . Therefore, as described in (Embodiment 1), the threshold voltage of the selection MOS transistor and the voltage applied to the selection gate are arbitrary.

  For example, the threshold voltage of a selection MOS transistor having the selection gate SG1 as a gate electrode is 0.7V and -0.3V, and the threshold voltage of a selection MOS transistor having SG2 as a gate electrode is -0.5V and -1. The threshold voltage of a selection MOS transistor having a gate electrode of 1.5V and SG3 is 1.5V and 3.3V, and the threshold voltage of a selection MOS transistor having a gate electrode of SG4 is 3.1V and 3.6V. Good. In this case, half of the selection MOS transistors having the selection gate as the gate electrode at the time of reading and writing are turned on, and the other half are turned off, for example, 0V for SG1, -1V for SG2, 2V for SG3, and 2V for SG3. Should be 3.3V. The voltage for turning on all the selection MOS transistors having the selection gate as the gate electrode may be, for example, 2.8V for SG1, -0.2V for SG2, 3.6V for SG3, and 4V for SG4.

  As described above (Embodiment 1) to (Embodiment 6), in the present invention, the memory cell unit (1) and the memory cell unit (2) each including the memory cell portion and the selection MOS transistor are composed of the memory cell unit. Are shared as shown in FIG. 29 to form a sub-array. For example, as shown in FIG. 30, one end of each of the memory cell units (1) and (2) shares a contact and is connected to a bit line. Alternatively, both ends of the memory cell units (1) and (2) may be shared as shown in FIG. 31 to form a sub-array. In this case, for example, as shown in FIG. 32, both ends of the memory cell unit share a contact and are connected to a bit line.

  As means for selecting either the memory cell unit (1) or the memory cell unit (2) at the time of reading or writing, for example, as shown in FIG. By changing the threshold voltage of the select MOS transistor sharing the same between the memory cell units (1) and (2), one may be made conductive and the other may be made non-conductive. Further, as described in the above embodiment, three or four selection MOS transistors may be provided in the memory cell unit, the threshold voltage of the selection MOS transistor may be three or more, or the selection MOS transistor may be provided at one end. The transistor need not be provided. An example of the memory cell unit is shown in FIGS.

  In the embodiment, the so-called NAND cell (FIG. 37C) in which the memory cell portion shares the source and the drain with the adjacent memory cell has been described. However, the present invention is not limited to the NAND cell, and the memory cell portion is non-volatile in the present invention. It is effective if the memory cell is a non-volatile memory. The memory cell section is effective even if it is, for example, a NOR type EEPROM as shown in FIG. 37A, or an AND cell type EEPROM (H. Kume el al .; IEDM) as shown in FIG. Tech.Dig., Dec.1992, pp.991-993), the present invention is effective, and so-called mask ROM is also effective.

(Embodiment 7)
Next, an embodiment will be described.

  In this embodiment, a memory cell or a memory cell unit including a memory cell and a selection transistor is arranged as shown in FIG. 46 to form a subarray. That is, one end of the memory cell unit is connected to the common signal line by sharing a contact among the three memory cell units. As shown in FIG. 46, the other end of the memory cell unit is connected to the common signal line by sharing the contacts among the three memory cell units. Then, the sub-arrays are continuously arranged to form a memory cell array as shown in FIG.

  As shown in FIGS. 48 and 49, the memory cell unit is constituted by a memory cell section constituted by memory cells and a selection transistor. The memory cell units A, B, and C in FIGS. 48 and 49 correspond to any of the memory cell units (1, 2, 3, 3) in FIGS. 46 and 47, respectively. (Eg, A; 1, B; 2, C; 3 or A; 2, B; 3, C; 1). In FIG. 48, it is sufficient that the threshold value Vt1 of the E type selection gate is larger than the threshold value Vt2 of the I type selection gate, for example, Vt1 = 2V and Vt2 = 0.5V. In FIG. 49, the threshold value of the D-type selection gate may be -0.8 V, for example.

  When selecting the memory cell shown in FIG. 48, there are two types of voltages applied to the selection gates SG1, SG2, and SG3 in the selected block, a voltage Vsgh (for example, Vcc, 3V) for turning on both the E type and the I type, and The voltage Vsgl (for example, 1.5 V) turns on the I type but turns off the E type. Of the three memory cell units, for example, when selecting the memory cell unit A, SG1 and SG2 are set to Vsgh, SG3 is set to Vsgl, and when selecting the memory cell unit B, SG1 is set to Vsgl and SG2 and 3 are set to Vsgh. do it. Similarly, when selecting the memory cell unit C, SG1 and SG3 may be set to Vsgh, and SG2 may be set to Vsgl.

  When 0 V is applied to the selection gate in the unselected block, all the selection transistors in the unselected block are turned off, so that the bit line does not leak through the unselected block.

  When the memory cell unit is as shown in FIG. 49, the method of selecting the memory cell unit is almost the same as that of FIG. 48, but Vsgl applied in the selected block may be 0V. As a result, the E type selection gate is turned off, and the D type selection gate is turned on. Further, in the unselected block, it is desirable to turn off the selection gate to prevent bit line leakage. Therefore, in order to turn off the D-type selection gate, a negative voltage (for example, -1 V) is applied to the selection gate in the unselected block. May be applied.

  There are various variations in the configuration of the memory cell portion, and the examples shown in FIGS. 36 and 37 can be employed. Further, the present invention is not limited to the EEPROM, but is also effective for a so-called EPROM or mask ROM.

  Hereinafter, the present embodiment will be described in detail by taking a NAND cell type EEPROM as an example.

  The configuration of the NAND cell type EEPROM according to the present embodiment is the same as that of FIG.

  FIG. 50 shows the memory cell array 1A, and FIG. 51 shows the memory cell array 1B. The memory cell array (FIGS. 50 and 51) according to the present embodiment has a source side select gate (second select gate) connected to a source line of an n-type diffusion layer as in a conventional memory cell array (FIG. 40). Not in contact with the bit line. That is, at the time of reading, a low-resistance bit line plays the role of a source line, so that reading is performed at high speed. Further, since two bit lines are shared for three memory cell columns (three columns), the pitch of the bit lines becomes 1.5 times that of the conventional one, and the processing of the bit lines becomes easy.

  In the memory cell array of the present embodiment, two kinds of threshold voltages of Vth1 and Vth2 (Vth1> Vth2) are provided for two select MOS transistors connecting one NAND cell column and a bit line. A select MOS transistor having a high threshold voltage Vth1 (for example, 2 V) is referred to as E-type, and a select MOS transistor having a low threshold voltage Vth2 (for example, 0.5 V) is referred to as I-type. The voltage applied to the selection gate is a voltage Vsgh (for example, 3 V) (Vsgh> Vt1, Vt2) that turns on both the I-type transistor and the E-type transistor, and the I-type transistor is turned on, but the E-type transistor is turned off. Vsgl (for example, 1.5 V) (Vt1> Vsgl> Vt2).

  As described above, two types of threshold voltages of the selection MOS transistors are provided, and two types of voltages are applied to the selection gate, so that one of the three NAND cell units sharing a contact at the time of writing or reading is used. Can be electrically connected to the two bit lines, and the other memory cell units can be electrically disconnected.

  Hereinafter, the reading and writing methods will be specifically described.

<Read>
When the data of the memory cells MC11, MC41, MC71... In the memory cell unit (1) in FIG. 50 are read to the bit lines BL1A, BL3A, BL5A..., The bit lines BL1A, BL3A, BL5A. Are precharged to VA (for example, 1.8 V), and BL0A, BL2A, BL4A, BL6A... Are grounded to 0V. After the precharge, the bit lines BL1A, BL3A, BL5A,.

  Next, the control gate CG1 is set to 0V, and CG2 to CG8 are set to Vcc (for example, 3V). The selection gate SG1 is set to Vsgl, and the selection gates SG2 and SG3 are set to Vsgh. Other select gates and control gates are set to 0V. In this case, the selection MOS transistors (ST12, ST13, ST22, ST23, ST32, ST33, ST42, ST43, ST52, ST53,...) Connected to the bit lines BL0A, BL2A, BL4A. On the other hand, the I-type selection MOS transistors ST11, ST41, ST71... Connected to the bit lines BL1A, BL3A, BL5A... Are turned on, but the E-type selection MOS transistors ST21, ST31, ST51, ST61, ST81.

  Therefore, if the data written in the memory cells MC11, MC41, MC71,... Is "1", the precharged bit lines BL1A, BL3A, BL5A, etc. are discharged to the grounded bit lines BL0A, BL2A, BL4A,. As a result, the data in the memory cells MC11, MC41, MC71... In the memory cell unit (1) is read out to the bit lines BL1A, BL3A, BL5A. On the other hand, if the data written in the memory cell is "0", the bit lines BL1A, BL3A, BL5A... Do not discharge and maintain the precharge potential.

  On the other hand, for the memory cells MC21, MC31, MC51, MC61, ... in the memory cell units (2), (3), E-type selection MOS transistors ST21, ST31, ST51 connected to the bit lines BL1A, BL3A, BL5A ... , ST61 ... are turned off, so that the data of the memory cells MC21, MC31, MC51, MC61 ... is not read to the bit lines BL1A, BL3A, BL5A ....

  When the data in the memory cells MC21, MC51, MC81,... In the memory cell unit (2) is read out to the bit lines BL2A, BL4A, BL6A,..., The selection gates SG1, 3 may be set to Vsgh, and SG2 may be set to Vsgl. When the data of the memory cells MC31, MC61, MC91,... In the memory cell unit (3) is read out to the bit lines BL2A, BL4A, BL6A, etc., the selection gates SG1, SG2 may be set to Vsgh, and SG3 may be set to Vsgl.

  As described above, in the present embodiment, the source line (n-type diffusion layer) of the conventional memory cell array is eliminated, and at the time of reading, half of the bit lines are grounded and play the same role as the conventional source line. Data is read from the memory cells to half of the bit lines. By using a bit line formed of low-resistance poly-Si or Al instead of a source line formed of a conventional high-resistance n-type diffusion layer, the problem of floating of the source line described in (Problem 1) can be solved. Solvable.

  Here, the read operation will be described in more detail with reference to a timing chart.

  FIG. 52 is a timing chart for reading data written in the memory cells MC11, MC41, MC71,... In the memory cell unit (1) of FIG.

  The bit lines BL0A, BL2A, BL4A, BL6A... Are connected to the sense amplifier SA1 in FIG. 6, and the bit lines BL1A, BL3A, BL5A. The sense amplifier is formed by a CMOS flip-flop controlled by control signals φP and φN.

  First, the precharge signals PRA1, PRA2, PRB2 change from Vss to Vcc (time t0), the bit lines BL1A, BL3A, BL5A... Change to VA2 (eg, 1.7V), and (dummy) bit lines BL1B, BL3B, BL5B. Is precharged to VB2 (for example, 1.5 V) (time t1). VA1 is 0 V, and the bit lines BL0A, BL2A, BL4A, BL6A,... Are grounded.

  When the precharge ends, PRA2 and PRB2 become Vss, and the bit lines BL1A, BL3A, BL5A. Thereafter, a desired voltage is applied from the row decoder 3 to the selection gate and the control gate (time t2). The control gate CG1 is at 0 V, CG2 to CG8 are at Vcc (for example, 3V), SG2 and 3 are at 3V (Vsgh), and SG1 is at 1.5V (Vsgl).

  If the data written in the memory cells MC11, MC41, MC71,... In the memory cell unit (1) is "0", the threshold voltage of the memory cell is positive and no cell current flows, and the bit lines BL1A, BL3A,. BL5A... Remain at 1.7V. When the data is "1", a cell current flows and the potentials of the bit lines BL1A, BL3A, BL5A... Decrease to 1.5 V or less. Further, since the selection gate SG1 is 1.5V, the E-type selection MOS transistor having the gate electrode SG1 is turned off, and the data of the memory cells in the memory cell units (2) and (3) are not transferred to the bit lines. During this time, the (dummy) bit lines BL1B, BL3B, BL5B... Are kept at a precharge potential of 1.5V.

  Thereafter, at time t3, .phi.P becomes 3 V and .phi.N becomes 0 V, the CMOS flip-flop FF is inactivated, and at time t4, .phi.E becomes 3 V, whereby the SA2 CMOS flip-flop FF is equalized, and the nodes N1 and N2 become Vcc. / 2 (for example, 1.5 V). At time t5, SS2, SA, SB become 3V and the bit lines and the sense amplifier are connected. Then, φN changes from 0V to 3V, φP changes from 3V to 0V, and bit lines BL1A, BL3A, BL5A... , BL3B, BL5B... Are amplified (time t6).

  That is, if "0" is written in the memory cells MC11, MC41, MC71,..., The node N1 of the SA2 becomes 3V, the node N2 becomes 0V, and "1" is written in the memory cells MC11, MC31, MC51,. And the node N1 becomes 0V and the node N2 becomes 3V. Thereafter, when the column selection signal CSL changes from 0 V to 3 V, the data latched by the CMOS flip-flop is output to IO and / IO (time t7).

  Through the read operation, the bit lines BL0A, BL2A, BL4A, BL6A,... Are grounded to 0V. That is, every other bit line is grounded. Accordingly, the distance between the read bit lines is twice as long as the case where the bit lines are not grounded, and the noise due to the capacitive coupling between the bit lines is significantly reduced (Japanese Patent Application No. 4-276393). The bit lines BL0B, BL2B, BL4B, BL6B... May be grounded by setting PRB1 to Vcc and VB1 to 0V through the read operation. As a result, it is possible to reduce inter-bit line capacitive coupling noise during bit line potential amplification.

  FIG. 53 is a timing chart for reading data written in the memory cells MC21, MC51, MC81,... In the memory cell unit (2) of FIG.

  First, the precharge signals PRA1, PRA2, PRB1 change from Vss to Vcc (time t0), the bit lines BL2A, BL4A,... Become VA1 (eg, 1.7V), and the (dummy) bit lines BL2B, BL4B,. 1.5 V) (time t1). VA2 is 0 V, and the bit lines BL1A, BL3A, BL5A,... Are grounded.

  When the precharge is completed, PRA1, PRB1 become Vss, and the bit lines BL2A, BL4A,. Thereafter, a desired voltage is applied from the row decoder 3 to the selection gate and the control gate (time t2). The control gate CG1 is at 0V, CG2 to CG8 are at Vcc (for example, 3V), SG1 and 3 are at 3V (Vsgh), and SG2 is at 1.5V (Vsgl).

  When the data written in the memory cells MC21, MC51, MC81,... Is "0", the cell current does not flow because the threshold voltage of the memory cell is positive, and the potentials of the bit lines BL2A, BL4A. It is. When the data is "1", a cell current flows and the potentials of the bit lines BL2A, BL4A... Decrease to 1.5 V or less. Further, since the selection gate SG2 is 1.5 V, the E-type selection MOS transistor having the gate electrode SG2 is turned off, and the data of the memory cells in the memory cell units (1) and (3) are not transferred to the bit lines. During this time, the (dummy) bit lines BL2B, BL4B,... Are kept at the precharge potential of 1.5V.

  Thereafter, at time t3, .phi.P becomes 3 V and .phi.N becomes 0 V, the CMOS flip-flop FF is inactivated, and at time t4, .phi.E becomes 3 V, so that the SA1 CMOS flip-flop FF is equalized and the nodes N1 and N2 become Vcc. / 2 (for example, 1.5 V). At time t5, SS1, SA and SB become 3V and the bit lines are connected to the sense amplifier. Then, φN is changed from 0V to 3V, φP is changed from 3V to 0V, and bit lines BL2A, BL4A ... and bit lines BL2B, BL4B are set. Are amplified (time t6).

  That is, if "0" is written in the memory cells MC21, MC51, MC81,..., The node N1 of SA1 becomes 3V and the node N2 becomes 0V, and if "1" is written, the node N1 becomes 0V. Node N2 becomes 3V. Thereafter, when the column selection signal CSL changes from 0 V to 3 V, the data latched by the CMOS flip-flop is output to IO and / IO (time t7).

  .. Are grounded to 0 V throughout the read operation, so that noise due to capacitive coupling between bit lines is reduced.

  Similarly, FIG. 54 shows the timing when the data of the memory cells MC31, MC61, MC91... In the memory cell unit (3) is read out to the bit lines BL2A, BL4A, BL6A. If SG3 is set to Vsgl and SG1 and SG2 are set to Vsgh, the memory cell unit (3) can be selected and the memory cell units (1) and (2) can be deselected.

  The timing of the read operation is arbitrary. For example, as shown in FIG. 55, at time t5, the transfer gate connecting the bit line and the sense amplifier is turned on to transfer the potentials of the bit line and the dummy bit line to the nodes N1 and N2 of the sense amplifier, and then the transfer gate is turned off. Is also good. In this case, since the bit line and the dummy bit line are disconnected from the sense amplifier, the load capacitance of the sense amplifier decreases, and the potentials of the nodes N1 and N2 are rapidly determined during sensing and data latching.

  In the above embodiment, for example, when reading out the memory cells MC11, MC41, MC71,..., The bit lines BL1A, BL3A, BL5A... Are precharged, the bit lines BL0A, BL2A, BL4A. The data is read out to BL1A, BL3A, BL5A... Which of the bit lines connected to both ends of the memory cell unit is used to read data is arbitrary. For example, when reading out the memory cells MC11, MC41, MC71,..., The bit lines BL0A, BL2A, BL4A... Are precharged, and the bit lines BL1A, BL3A, BL5A. ... may be read.

<Write>
The write operation of the present embodiment will be described below.

  The writing procedure when writing to the memory cells MC11, MC41, MC71,... In the memory cell unit (1) of FIG. 50 will be described below.

  The selection gates SG2 and SG3 are set to 0V, and all the selection MOS transistors using the selection gate SG2 as a gate electrode are turned off. SG1 and CG1 to CG8 are set to Vcc, and the bit lines BL1A, BL3A, BL5A. Precharge). The bit lines BL0A, BL2A, BL4A,... May be set to Vcc or 0V, and may be set to an arbitrary voltage.

  Thereafter, when the selection gate SG1 is set to Vsgl (for example, 1.5 V), the I-type selection MOS transistors ST11, ST41, ST71... Are turned on, but the E-type selection MOS transistors are turned off. The channels of MC31, MC51, MC61,... Float at the potential Vcc-Vth charged from the bit line.

  Data to be written into the memory cells MC11, MC41, MC71,... In the memory cell unit (1) is given from the bit lines BL1A, BL3A, BL5A,. For example, when writing "0" to the memory cell MC11, when the bit line BL1A is set to 0V, the I-type selection MOS transistor ST11 is turned on, and the channel of the memory cell MC11 is set to 0V. When "1" is written to the memory cell MC11, when the bit line BL1A is set to 3 V, the I-type selection MOS transistor ST11 is turned off, and the channel of the memory cell MC11 becomes floating at Vcc-Vth. The bit lines BL0A, BL2A, BL4A,... May be set to Vcc or 0V, and may be set to an arbitrary voltage.

  After the selection gate SG1 is changed from Vcc to Vsgl (a voltage higher than the threshold voltage of the I-type selection MOS transistor but lower than the E-type selection MOS transistor, for example, 1.5 V), the control gates CG1 to CG8 are turned on. From Vcc to the intermediate potential VM (about 10 V). Then, since the channels of the memory cells MC21, MC31, MC51, MC61,... To which no data is to be written and the memory cells MC11, MC41, MC71, etc. to which "1" is to be written are in a floating state, the capacitance coupling between the control gate and the channel causes Vcc-Vth. To an intermediate potential (about 8 V). The channels of the memory cells MC11, MC41, MC71,... To which "0" is written are at 0V because the bit lines are at 0V.

  After the channel of the memory cell in which writing is not selected and "1" is written rises from Vcc-Vth to the intermediate potential, the control gate CG1 is boosted from the intermediate potential VM to the write voltage Vpp (20 V). Then, the channels of the memory cells in the memory cell units (2) and (3) to which no data is to be written and the memory cells in the memory cell unit (1) to which "1" is to be written are set at the intermediate potential (about 8 V), and the control gate CG1 is set at Vpp. (About 20V), these memory cells are not written. However, since the channel of the memory cell for writing "0" is 0V and the control gate is Vpp (about 20V), electrons are injected from the substrate into the floating gate to "0". Writing is performed.

  Here, the write operation of this embodiment will be described in more detail with reference to a timing chart. FIG. 56 is a timing chart when the memory cell MC11 (and the memory cells MC41, MC71,...) In the memory cell unit (1) is written.

  The data to be written into the memory cells MC11, MC41, MC71,... In the memory cell unit (1) is latched by the sense amplifier circuit (SA2 in FIG. 7). That is, in the case of "0" write, the node N1 is at 0V, N2 is 3V, and in the case of "1" write, the node N1 is at 3V and N2 is at 0V.

  At the time of writing operation, SG1 is set to Vss and SG2, SG3, CG1 to CG8 are set to Vcc at time t1. In this embodiment, when writing to the memory cells MC11, MC41, MC71,... In the memory cell unit (1), writing is not performed to the memory cells in the memory cell units (2) and (3). In this example, the channels of the memory cells MC21, MC31, MC51, MC61,... Are charged from the bit lines BL0A, BL2A, BL4A,.

  In this embodiment, the bit lines BL0A, BL2A, BL4A... Are charged from VA1 to Vcc of the sense amplifier SA1 in FIG. As a result, the channel of the unselected memory cell is charged to Vcc-Vth. At this time, the channel of the memory cell to be written is also charged to Vcc-Vth. As described above, as a method of charging the channels of the memory cells of the memory cell units (2) and (3) to Vcc (-Vth), the channels may be charged from BL0A, BL2A, BL4A... Or from BL1A, BL3A and BL5A. You may charge it.

  On the other hand, a potential of Vcc or Vss (0 V) is applied to the bit lines BL1A, BL3A, BL5A,... According to the data latched in the sense amplifier circuit SA2. Thus, for example, when "0" is written to the memory cell MC11, the bit line BL1A is set to 0V and the channel of the memory cell MC11 is set to 0V. When "1" is written to the memory cell MC11, the bit line BL1A is set to Vcc (for example, 3 V), and the channel of the memory cell MC11 is charged to Vcc-Vth.

  After the bit line is charged, the selection gate SG1 is set to Vsgl (for example, 1.5 V), and SG2 and SG3 are set to Vss (for example, 0 V). The selection MOS transistors having the selection gates SG2 and SG3 as gate electrodes are all turned off. The selection MOS transistor having the gate electrode SG1 in the memory cell units (2) and (3) where writing is not performed is turned off because of the E-type, and the channel of the memory cell in the memory cell units (2) and (3) is Vcc−. Floating at Vth.

  The drains of the select MOS transistors ST11, ST41, ST71,... Of the memory cells MC11, MC41, MC71,... To which "1" is written are Vcc-Vth (for example, the threshold voltage of the I-type transistor is 0.5V. Then, since the source on the bit line contact side is Vcc (for example, 3 V) and the selection gate SG1 is Vsgl (for example, 1.5 V), the selection MOS transistors ST11, ST41, ST71,. I do. As a result, the channels of the memory cells MC11, MC41, MC71,.

  When writing "0" to the memory cells MC11, MC41, MC71,..., The selection gate SG1 of the selection MOS transistors ST11, ST41, ST71,. The transistors ST11, ST41, ST71,... Are turned on, and the channel of the memory cell is maintained at 0V.

  After the selection gate SG1 is set to Vsgl (for example, 1.5 V), the control gates CG1 to CG8 are changed from Vcc to the intermediate potential VM (about 10 V) at time t2. Then, since the channels of the memory cells not selected for writing and the memory cells MC11, MC41, MC71... For writing "1" are in a floating state, the intermediate potential (about 8 V) from Vcc-Vth due to the capacitive coupling between the control gate and the channel. ) To rise. The channels of the memory cells MC11, MC41, MC71,... To which "0" is written are at 0V because the bit lines are at 0V.

  After the channel of the memory cell performing the write non-selection and "1" write rises from Vcc-Vth to the intermediate potential, the control gate CG1 is boosted from the intermediate potential VM to the write voltage Vpp (20 V) at time t3. Then, the channels of the memory cells in the memory cell units (2) and (3) where no writing is performed and the memory cells MC11, MC41, MC71... For which "1" is to be written are at the intermediate potential (about 10 V), and the control gate CG1 is at Vpp (20 V Therefore, these memory cells are not written. However, since the channels of the memory cells MC11, MC41, MC71... For writing "0" are 0 V and the control gate is Vpp (about 20 V), electrons are injected from the substrate into the floating gate. "0" is written.

  After the writing is completed, the control gate, the selection gate, and the bit line are sequentially discharged, and the writing operation ends.

  When writing the memory cells MC21, MC51, MC81,... In the memory cell unit (2), the channels of the memory cells of the memory cell units (1) and (3) are similarly charged to Vcc (or Vcc-Vth). Data may be transferred to the memory cells MC21, MC51, MC81,... By setting the selection gate SG1 to Vss, SG2 to Vsgl, SG3 to Vsgh, and the bit lines BL2A, BL4A, BL6A.

  When writing the memory cells MC31, MC61, MC91... In the memory cell unit (3), similarly, after charging the channels of the memory cells of the memory cell units (1) and (2) to Vcc (or Vcc-Vth), The data may be transferred to the memory cells MC31, MC61, MC91,... By setting the selection gate SG1 to Vss, SG3 to Vsgl, SG2 to Vsgh, and the bit lines BL2A, BL4A, BL6A to Vcc or Vss.

  After the end of the write, a write verify operation for checking whether the write has been performed sufficiently is performed (FIG. 57). In the verify read operation of the memory cell unit (1), as in the read operation, the select gate SG1 is set to Vsgl and SG2 and SG3 are set to Vsgh in order to select only the memory cell unit (1). In the verify read, after the bit line is discharged from the precharge potential, the bit line is recharged by the write data, and then the rewrite data is latched by the sense amplifier by sensing the bit line potential. The details of the operation of the sense amplifier during the verify operation and the recharging of the bit line are described in, for example, a document (T. Tanaka, et al., IEEE J. Solid-State Circuit, vol. 29, pp. 1366-1373, 1994). ing.

  In the above embodiment, writing is performed simultaneously to one third of the number of memory cells in the column direction. That is, only one of the three memory cell units performs writing simultaneously.

  According to the present embodiment, writing can be performed almost simultaneously on two of the three memory cell units. For example, both the selection gates SG1 and SG2 may be set to Vsgl (for example, 1.5 V), and SG3 may be set to Vsgh. Then, the E-type selection MOS transistor using the selection gates SG1 and SG2 as gate electrodes is turned off, and the I-type selection MOS transistor is turned on. The write data of the memory cells MC11, MC41, MC71,... Of the memory cell unit (1) is transferred from the bit lines BL1A, BL3A, BL5A,.

  That is, in the case of "0" writing, the bit line and the channel of the memory cell to be written become 0 V, and in the case of "1" writing, the bit line becomes Vcc, and the channel floats at Vcc-Vth. Similarly, the write data of the memory cells MC21, MC51, MC81,... Of the memory cell unit (2) is transferred from the bit lines BL2A, BL4A, BL6A,.

  Similarly, if SG1 and SG2 are set to Vsgl and SG2 is set to Vsgh, writing can be performed almost simultaneously on the memory cell units (1) and (3). In this case, data is transferred to the memory cells of the memory cell unit (1) from the bit lines BL1A, BL3A, BL5A... And to the memory cells of the memory cell unit (3) from the bit lines BL2A, BL4A, BL6A.

  After the write operation, a verify read is performed to check whether the write has been performed sufficiently. In the verify read operation of the above embodiment, data of one memory cell is read using two bit lines. That is, data of one of the three memory cell units is read out almost simultaneously. Therefore, in the case where two memory cell units are written almost simultaneously, the verify read operation is performed twice for each write operation.

  In the method of writing two memory cell units almost simultaneously, the verify read is performed one memory cell unit at a time. Therefore, the total time for writing two memory cell units is approximately Tpr + 2Tvfy (Tpr: write pulse width, Tvfy: one verify read time). ). On the other hand, in the method of writing data in one memory cell unit almost simultaneously, the total time for writing data of two memory cell units is about 2 (Tpr + Tvfy), so the writing operation of the method of writing data in two memory cell units simultaneously is faster. It is.

  In the above embodiment, a sense amplifier is connected for each bit line, but a so-called shared sense amplifier system (FIG. 15) in which one sense amplifier is connected to two bit lines may be used. The write and read timing diagrams in this case are almost the same as those in the above embodiment. Further, the arrangement of the memory cell units in the memory cell array may be arranged as shown in FIG. 58, for example.

  According to the present invention, of the select MOS transistors sharing one select gate, a conductive MOS transistor and a non-conductive MOS transistor can be generated. By preparing three such select gates, This utilizes the fact that a selected memory cell and a non-selected memory cell can be easily realized in a memory cell having the same selection gate.

  Therefore, the threshold voltage of the selection MOS transistor and the voltage applied to the selection gate have arbitrary characteristics. The selection MOS transistor connected to one end of the memory cell has two threshold voltages Vtd1 and Vtd2 (Vtd1> Vtd2), and the voltages applied to the selection gate are Vsghd (Vsghd> Vtd1) and Vsgld (Vtd1>). Vsgld> Vtd2), and one of the selection MOS transistors connected in series to the other end of the memory cell has two threshold voltages Vts1 and Vts2 (Vts1> Vts2). Are two kinds of threshold voltages, Vsghs (Vsghs> Vts1) and Vsgls (Vts1> Vsgls> Vts2), and the other selection MOS transistors connected in series are two kinds of thresholds of Vtp1 and Vtp2 (Vtp1> Vtp2). The voltage applied to the select gate may be two types, Vsghp (Vsghp> Vtp1) and Vsglp (Vtp1> Vsglp> Vtp2).

  As in the above embodiment, Vtd1 = Vts1 = Vtp1, Vtd2 = Vts2 = Vtp2, Vsghd = Vsghs = Vsghp, Vsgld = Vsgls = Vsglp. Is highly arbitrary. For example, the threshold voltage of the select MOS transistor at one end of the memory cell is set to two types of 2 V and 0.5 V, and the threshold voltage of one select MOS transistor connected in series at the other end of the memory cell is set to 2. Assuming that two types of 5V and 1V and the other two types of thresholds are 0.8V and 3.5V, the voltages applied to the select gate at one end of the memory cell are Vsgh = 3V, Vsgl = 1.5V, and the memory cell Vsgh = 3V, Vsgl = 1.2V and Vsgh = 4V, Vsgl = 3V may be applied to one of the selection gates connected in series at the other end of the device.

  The threshold voltages of the three select MOS transistors connected to one NAND string may be substantially the same. For example, the threshold voltage of three select MOS transistors connected to a certain NAND string is 0.8 V, and the select MOS transistor on one end side of an adjacent NAND cell shares the gate electrode of the select MOS transistor with the NAND string. The threshold voltage is 0.2 V, the threshold voltages of two selection MOS transistors connected in series at the other end of the memory cell are 1.4 V and 0.8 V, and the voltage applied to the selection gate at one end of the NAND cell is Vsgh = 3V, Vsgl = 0.5V, and voltages applied to two select gates connected in series at the other end of the NAND cell may be set to Vsgh = 3V and Vsgl = 1.2V. Of course, the threshold value of the selection gate may be a negative value, and the voltage applied to the selection gate may be a negative voltage.

  If Vsgh is made larger than Vcc, it leads to an increase in the conductance of the selection MOS transistor (that is, a decrease in resistance), and the cell current flowing through the NAND cell array at the time of reading increases, so that the bit line discharge time becomes shorter. The result read and write verify read are speeded up. Vsgh may be boosted from Vcc by a booster circuit in the chip, for example.

  The larger one of the threshold voltages of the selection MOS transistors may be set to a voltage equal to or higher than the power supply voltage Vcc (for example, 3.5 V). In this case, in order to turn on the selection MOS transistor having the threshold voltage at the time of reading or verify reading, for example, 4 V may be applied to the selection gate using a booster circuit inside the chip.

  As a method of changing the threshold voltage, various methods described in the first embodiment can be used.

  In the above embodiment, when writing to the memory cell unit (2) or the memory cell unit (3), 0 V is applied to SG1, but the selection MOS transistor having this selection gate as the gate electrode is of the I-type. When the threshold voltage Vt2 is about 0.1 V (or a negative threshold voltage), this select MOS transistor does not completely cut off, and a cell current flows. As a result, the channel of the memory cell not selected for writing is not boosted from Vcc-Vth to the intermediate potential VM, or even if boosted, the cell current flows and the potential drops from VM. In any case, since the channel of the memory cell not selected for writing falls from VM, erroneous writing to "0" is performed.

  In order to improve the cut-off characteristic of the I-type transistor, it is necessary to write data to a bit line to which write data is not applied at the time of writing (BL1A, BL3A, BL5A when writing to the memory cell unit (2) or (3) in FIG. 50). ..) May be applied, for example, a voltage of about 0.5V. When 0.5 V is applied to the source of the selection MOS transistor, the potential difference between the source and the substrate becomes -0.5 V, and the threshold voltage of the I-type transistor increases due to the body bias effect. Cutoff characteristics when 0 V is applied to the substrate.

  In order to set the smaller (I-type) threshold voltage of the selection MOS transistors to, for example, 0.5 V, a method of reducing the substrate concentration is considered. In the case of an I-type transistor having a low substrate concentration, when a drain voltage is applied without applying a gate voltage, a depletion layer between the drain and the substrate expands, and as a result, a depletion layer between the drain and the substrate and a depletion layer between the source and the substrate increase. There is a problem of connection and dullness (punch through). In order to increase the punch-through breakdown voltage of the I-type select MOS transistor, the channel length L of the I-type select MOS transistor may be increased.

(Embodiment 8)
The threshold value of the selection MOS transistor may be as shown in FIG. The threshold value of the E-type may be 2 V, the threshold value of the I-type may be 0.5 V, and the threshold value of the D-type may be -2 V, for example. The method of reading and writing is almost the same as that of the seventh embodiment, but the voltage Vsgl for turning on the D-type selection MOS transistor but turning off the E-type may be 0 V. That is, when reading the memory cell unit (1), SG1 is 1.5V, SG2 and SG3 are 3V, and when selecting the memory cell unit (2), SG1 and SG3 are 3V, SG2 is 0V, When selecting the memory cell unit (3), SG1 and SG2 may be set to 3V and SG3 may be set to 0V.

  At the time of writing, similarly to the first embodiment, when writing to the memory cell unit (1), SG1 is 1.5V, when SG2 and SG3 are 0V, when writing to the memory cell unit (2), SG1 is used. , SG2 should be 0V, SG3 should be 3V, and when writing to the memory cell unit (3), SG1 and SG3 should be 0V and SG2 should be 3V. Further, if the threshold value of the selection MOS transistor is set to about -8V, when writing to the memory cell units (2) and (3), the channel of the memory cell not to be written is selected as in the conventional NAND type EEPROM. A writing method (not floating) can be performed.

  For example, when writing the memory cell MC51, SG1 and SG2 are set to 0V, SG3 is set to VM10 (about 10V), CG1 is set to Vpp, CG2 to CG8 are set to VM10, and when "1" is written, BL4A is set to VM8 (about 8V). In the case of writing "0", the voltage may be set to 0V. Then, the channel of the memory cell to which "1" is written is charged to an intermediate potential (about 8 V) from the bit line. On the other hand, as for the memory cell units (1) and (3) in which writing is not performed at this time, the channel of the memory cell is set to the Vcc floating state as described in the seventh embodiment, and the coupling with the control gate is performed. The channel of the memory cell may be set at the write non-selection potential (VM8).

  The present invention is not limited to the above embodiments, and various other modifications can be made in the implementation stage without departing from the spirit of the invention. Furthermore, the above embodiments include inventions at various stages, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent elements.

  Further, for example, even if some components are deleted from all the components shown in each embodiment, the problem described in the section of the problem to be solved by the invention can be solved, and the effects described in the effects of the invention can be solved. Is obtained, a configuration from which this configuration requirement is deleted can be extracted as an invention.

FIG. 1 is a block diagram showing a configuration of a NAND cell type EEPROM according to a first embodiment. FIG. 3 is a diagram illustrating a configuration of a memory cell array according to the first embodiment; FIG. 3 is a diagram illustrating a configuration of a memory cell array according to the first embodiment; FIG. 5 is a diagram showing an n-type diffusion layer of the memory cell array according to the first embodiment, source / gate / drain regions of the memory cell, and contacts for connecting the n-type diffusion layer to bit lines. FIG. 4 is a timing chart for explaining a data read operation according to the first embodiment; Circuit diagram of the sense amplifier circuit according to the first embodiment Circuit diagram of the sense amplifier circuit according to the first embodiment FIG. 4 is a timing chart for explaining a data read operation according to the first embodiment; FIG. 4 is a timing chart for explaining a data read operation according to the first embodiment; FIG. 6 is a timing chart for explaining a data write operation according to the first embodiment; FIG. 6 is a timing chart for explaining a data write operation according to the first embodiment; FIG. 6 is a timing chart for explaining a data write operation according to the first embodiment; FIG. 3 is a diagram illustrating a configuration of a memory cell array according to the first embodiment; FIG. 3 is a diagram illustrating a configuration of a memory cell array according to the first embodiment; Circuit diagram of the sense amplifier circuit according to the first embodiment The figure which shows the structure of the memory cell array of 2nd Embodiment. The figure which shows the structure of the memory cell array of 2nd Embodiment. FIG. 5 is a diagram showing an n-type diffusion layer of the memory cell array according to the first embodiment, source / gate / drain regions of the memory cell, and contacts for connecting the n-type diffusion layer to bit lines. FIG. 9 is a timing chart for explaining a data read operation according to the second embodiment. FIG. 9 is a timing chart for explaining a data read operation according to the second embodiment. FIG. 9 is a timing chart for explaining a data write operation according to the second embodiment. FIG. 9 is a timing chart for explaining a data write operation according to the second embodiment. The figure which shows the structure of the memory cell array of 2nd Embodiment. The figure which shows the structure of the memory cell array of 2nd Embodiment. The figure which shows the structure of the memory cell array of 3rd Embodiment. The figure which shows the structure of the memory cell array of 4th Embodiment The figure which shows the structure of the memory cell array of 5th Embodiment. The figure which shows the structure of the memory cell array of 6th Embodiment. FIG. 3 is a diagram of a memory cell array for explaining claim 2 of the present invention. FIG. 3 is a diagram of a memory cell array for explaining claim 2 of the present invention. FIG. 4 is a diagram of a memory cell array for explaining claim 3 of the present invention. FIG. 4 is a diagram of a memory cell array for explaining claim 3 of the present invention. FIG. 7 is a diagram of a memory cell array for explaining claim 7 of the present invention. FIG. 1 is a diagram showing one embodiment of a memory cell unit and a memory cell unit of the present invention. FIG. 1 is a diagram showing one embodiment of a memory cell unit and a memory cell unit of the present invention. FIG. 1 is a diagram showing one embodiment of a memory cell unit and a memory cell unit of the present invention. FIG. 1 is a diagram showing one embodiment of a memory cell unit and a memory cell unit of the present invention. Plan view and equivalent circuit diagram showing a cell configuration of a conventional NAND type EEPROM AA ′ and BB ′ cross-sectional view of FIG. Equivalent circuit diagram of a conventional NAND-type EEPROM memory cell array FIG. 3 is a diagram showing an n-type diffusion layer of a memory cell array of a conventional NAND-type EEPROM, source / gate / drain regions of the memory cell, and a contact connecting the n-type diffusion layer to a bit line; FIG. 6 is a diagram for explaining a conventional problem and showing a relationship between a threshold value of a memory cell and a bit line discharge time FIG. 3 is a diagram for explaining a conventional problem and showing a memory cell array configuration. FIG. 3 is a diagram for explaining a conventional problem and showing a memory cell array configuration. FIG. 6 is a diagram for explaining a conventional problem and showing a relationship between a threshold value of a memory cell and a bit line discharge time. The figure which shows the structure of the subarray concerning 7th Embodiment. The figure which shows the structure of the memory cell array concerning 7th Embodiment The figure which shows the structure of the memory cell unit of 7th Embodiment The figure which shows the structure of the memory cell unit of 7th Embodiment The figure which shows the structure of the memory cell part of 7th Embodiment The figure which shows the structure of the memory cell part of 7th Embodiment A timing chart for explaining a data read operation of the seventh embodiment A timing chart for explaining a data read operation of the seventh embodiment A timing chart for explaining a data read operation of the seventh embodiment A timing chart for explaining a data read operation of the seventh embodiment FIG. 17 is a timing chart for explaining a data write operation according to the seventh embodiment. FIG. 17 is a timing chart for explaining the write verify read operation of the seventh embodiment. FIG. 14 is a diagram showing another configuration example of the memory cell array according to the seventh embodiment. The figure which shows the structure of the memory cell array concerning 8th Embodiment

Explanation of reference numerals

Reference Signs List 1 memory cell array 2 sense amplifier circuit 3 row decoder 4 column decoder 5 address buffer 6 I / O sense amplifier 7 data input / output buffer 8 substrate potential control circuit

Claims (10)

A memory cell unit composed of one or more nonvolatile memory cells;
A signal line for performing data transfer with the memory cell portion,
A selection transistor disposed between the signal line and the memory cell unit,
In the case of a write inhibit operation, a write non-selection voltage is applied to the signal line, and a write non-selection voltage is applied to the gate of the selection transistor by applying a select gate voltage higher than the write non-selection voltage to the memory cell. And a write gate voltage is applied to a control gate of the memory cell to generate a write-inhibited channel voltage boosted by capacitive coupling between the channel of the memory cell and its control gate. Nonvolatile semiconductor memory device. A memory cell unit composed of one or more nonvolatile memory cells;
A signal line for performing data transfer with the memory cell portion,
A selection transistor disposed between the signal line and the memory cell unit,
In the case of a write inhibit operation, a write non-selection voltage is applied to the signal line, and a select gate voltage higher than the write non-selection voltage is applied to the gate of the select transistor and the control gate of the memory cell. A write non-selection voltage is transferred to the channel of the memory cell section, and a write gate voltage is applied to the control gate of the memory cell, and the write inhibit is boosted by capacitive coupling between the channel of the memory cell and its control gate. A nonvolatile semiconductor memory device for generating a channel voltage. A memory cell unit composed of a plurality of serially connected nonvolatile memory cells,
A common signal line for performing data transfer with the memory cell portion,
A selection transistor disposed between the common signal line and the memory cell unit,
In the case of the write inhibit operation, a write non-selection voltage is applied to the common signal line, and a write non-selection voltage is applied to the gate of the selection transistor by applying a select gate voltage higher than the write non-selection voltage. Transferred to the channel of the memory cell part,
Then, a pass voltage is applied to the control gate of the unselected memory cell, and a write voltage higher than the pass voltage is applied to the control gate of the selected memory cell, and the channels of the plurality of memory cells and the control gate therefor are applied. A non-volatile semiconductor memory device which generates a write-inhibited channel voltage boosted by capacitive coupling. A memory cell unit composed of a plurality of serially connected nonvolatile memory cells,
A common signal line for performing data transfer with the memory cell portion,
A selection transistor disposed between the common signal line and the memory cell unit,
In the case of a write inhibit operation, a write non-selection voltage is applied to the signal line, and a select gate voltage higher than the write non-selection voltage is applied to the gate of the select transistor and the control gate of the memory cell. A write non-selection voltage is transferred to a channel of the memory cell unit,
Then, a pass voltage is applied to the control gate of the unselected memory cell, and a write voltage higher than the pass voltage is applied to the control gate of the selected memory cell, and the channels of the plurality of memory cells and the control gate therefor are applied. A non-volatile semiconductor memory device which generates a write-inhibited channel voltage boosted by capacitive coupling. A memory cell unit composed of a plurality of serially connected nonvolatile memory cells,
A common signal line for performing data transfer with the memory cell portion,
A selection transistor disposed between the common signal line and the memory cell unit,
In the case of a write selection operation, a write selection voltage is transferred to the channel of the memory cell portion by being applied to the signal line,
In the case of the write inhibit operation, a write non-selection voltage is applied to the signal line, and a select gate voltage higher than the write non-selection voltage is applied to the gate of the select transistor. Transferred to the cell part channel,
Then, a pass voltage is applied to the control gate of the unselected memory cell, and a write voltage higher than the pass voltage is applied to the control gate of the selected memory cell, and the channels of the plurality of memory cells and the control gate therefor are applied. A non-volatile semiconductor memory device which generates a write-inhibited channel voltage boosted by capacitive coupling. A memory cell unit composed of a plurality of serially connected nonvolatile memory cells,
A common signal line for performing data transfer with the memory cell portion,
A selection transistor disposed between the common signal line and the memory cell unit,
In the case of a write selection operation, a write selection voltage is transferred to the channel of the memory cell portion by being applied to the signal line,
In the case of a write inhibit operation, a write non-selection voltage is applied to the signal line, and a select gate voltage higher than the write non-selection voltage is applied to the select transistor and the control gate of the memory cell. A non-selection voltage is transferred to a channel of the memory cell unit,
Then, a pass voltage is applied to the control gate of the unselected memory cell, and a write voltage higher than the pass voltage is applied to the control gate of the selected memory cell, and the channels of the plurality of memory cells and the control gate therefor are applied. A non-volatile semiconductor memory device which generates a write-inhibited channel voltage boosted by capacitive coupling. 7. The nonvolatile semiconductor memory device according to claim 1, wherein the write non-selection voltage is a power supply voltage or a power supply voltage in a chip that is stepped down or boosted from the power supply voltage. 8. Nonvolatile semiconductor memory device. 8. The non-volatile semiconductor storage device according to claim 1, wherein the select gate voltage is higher than a write non-select voltage by at least a threshold voltage of the memory cell or the select transistor. A nonvolatile semiconductor memory device characterized by the above-mentioned. 7. The nonvolatile semiconductor memory device according to claim 5, wherein the write selection voltage is lower than the write non-selection voltage. 7. The nonvolatile semiconductor memory device according to claim 5, wherein the write selection voltage is 0 V, and is a power supply voltage or an in-chip power supply voltage stepped down or boosted from the power supply voltage. Nonvolatile semiconductor memory device.

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