JPH0877781A - Nonvolatile semiconductor storage device - Google Patents

Abstract

PURPOSE: To enable high speed random reading without increasing an area by constituting a sub-array with two memory units in which magnitude relation of threshold values of selecting MOS transistors (STD), (STS), allowing a NAND cell to conduct to a bit line and a source line respectively, is different. CONSTITUTION: A NAND cell C00 connected in series to a memory cell unit 1 is conducted to a bit line the inverse of BLO and a source line through STD10 , STS10 . As for a memory cell unit 2, conduction is performed through STD00 , STS00 in the same way. A threshold value of the STD10 is larger than a threshold value of STS10 , a threshold value of the STS00 is larger than a threshold value of STD00 , a memory sub-array is constituted of plural memory units 1, 2 in which magnitude relation of threshold values is different, and a folded bit line system can be realized. Thereby, high speed random read can be performed without increasing a chip area.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device using electrically rewritable nonvolatile memory cells.

[0002]

2. Description of the Related Art In recent years, a non-volatile semiconductor memory device (EEPROM) capable of electrically rewriting and achieving high integration.
As one of the above, a NAND cell type EEPROM has been proposed. This NAND cell type EEPROM is an n-channel FET in which, for example, a floating gate as a charge storage layer and a control gate are stacked via an insulating film on the floating gate.
A plurality of memory cells of MOS structure are connected in series so that their sources and drains are shared by adjacent ones,
This is used as one unit and connected to the bit line.

The drain side of the NAND cell is connected to the bit line through a first selection MOS transistor having the first selection gate as a gate electrode, and the source side of the NAND cell has a second selection gate as a gate electrode. It is connected to the source line via the selection MOS transistor. The control gate of the memory cell and the first and second selection gates are continuously arranged in the row direction. Usually, a set of memory cells connected to a control gate is called one page, and a set of pages sandwiched by a set of drain-side and source-side select MOS transistors is called one NAND block or simply one block. The memory cell array is usually formed in a p-type well formed in an n-type semiconductor substrate.

The operation of the NAND cell type EEPROM is as follows. Data writing is performed in order from the memory cell farther from the bit line. A boosted write voltage Vpp (= about 20V) is applied to the control gate of the selected memory cell, and an intermediate potential (about 10V) is applied to the control gates of the other non-selected memory cells and the first select gate. Then, 0 V (“0” write) or an intermediate potential (“1” write) is applied to the bit line according to the data. At this time, the potential of the bit line is transmitted to the selected memory cell.
When the data is "0", a high voltage is applied between the floating gate of the selected memory cell and the substrate, electrons are tunnel-injected from the substrate to the floating gate, and the threshold value moves in the positive direction. When the data is "1", the threshold value does not change.

Data erasing is performed on all the memory cells in the NAND cell almost at the same time. That is, all control gates and select gates are set to 0V, and the boosted potential VppE (about 20V) is applied to the p-type well and the n-type substrate. As a result, in all the memory cells, electrons in the floating gate are emitted to the well, and the threshold value moves in the negative direction.

In the data read operation, the control gate of the selected memory cell is set to 0V, and the control gates of the other memory cells are set to the power supply voltage Vcc (eg, 3V) to detect whether or not a current flows in the selected memory cell. It is done by doing. In the NAND cell type EEPROM, since a plurality of memory cells are connected in cascade, the cell current during reading is small. Further, since the control gate of the memory cell and the first and second selection gates are continuously arranged in the row direction, data for one page can be simultaneously read out to the bit line.

(Problem 1) Conventional NAND cell type EEP
FIG. 30 shows a circuit example of the ROM sense amplifier. The bit line potential is detected by this sense amplifier as follows. First, when the address is set and the read mode is set, the bit line precharge control signal PREB changes to V
From cc to Vss, the bit line BLj and node N2 are charged to the power supply potential Vcc. Further, the node N2 is set to Vcc,
The node N1 is set to Vss to reset the sense amplifier SA. After selecting the word line, if the cell data is "0", the bit line potential is kept at Vcc, and if the cell data is "1", the bit line potential is discharged toward Vss. Then, after the potential of the bit line is determined, the potential of the bit line is transferred to the node N2.

Next, SENB changes from Vcc to Vss, SEN changes from Vss to Vcc, and the clocked inverter INV1 is activated. If the potential of the node N2 is higher than the circuit threshold of the clocked inverter INV1, the node N1 is kept at Vss, and if the potential of the node N2 is lower than the circuit threshold of the clocked inverter INV2, the node N1 is at Vcc. Then, the potential of the bit line BLj is detected. After that, clocked inverter IN
V2 is activated and the detected data is latched. When the column selection signal CSLj changes from Vss to Vcc, the latched data is output to I / O and I / O '.

In this method, cell data is detected depending on whether the potential of the bit line in the floating state is larger or smaller than the circuit threshold value of the clocked inverter as described above. Due to the capacitive coupling with the corresponding bit line, it changes depending on the state of the adjacent bit line. For example, "0" in the cell
When the data is written, the read current is not passed and the potential of the bit line BLj should keep the precharge potential Vcc. On the other hand, when "1" data is written in the cell connected to the adjacent bit line BLi and a read current is passed, the potential of the bit line BLi changes from Vcc to Vcc.
go down to ss. Then, the potential of the bit line BLj, which should maintain Vcc, is lowered by being dragged by the potential of the adjacent bit line BLi, which is lowered from Vcc to Vss.

Therefore, in order to correctly detect this bit line BLj as "0" data, the circuit threshold value of the clocked inverter INV1 takes into consideration the change of the bit line potential due to the capacitive coupling between the bit lines. And must be set lower. In order to read the bit line BLi as "1" data, the potential of the bit line BLi must be lowered from Vcc to the circuit threshold value of the clocked inverter INV1. Considering that the read current of the NAND cell is small. If the circuit threshold value of the clocked inverter INV1 is set low, the time required to detect the bit line becomes long.

In the sense amplifier using the clocked inverter as shown in FIG. 30, it takes a long time to detect the bit line potential, which will be exemplified below by using numerical values. If the capacitance between adjacent bit lines occupies 1/2 of the total capacitance of the bit lines, the bit line B that should keep Vcc
Lj is lowered to Vcc / 2 according to the adjacent bit line BLi. If the power supply voltage Vcc is, for example, 3V, B
Lj will be lowered to 1.5V. Therefore,
The circuit threshold value of the clocked inverter INV1 is set to 1.2V with a margin. The cell current is 1 μA when the read current of the NAND cell is the smallest, that is, when “1” is written in the selected cell and “0” is written in the non-selected cell. If the capacitance of the bit line is 3 pF, it takes 3 pF × (3-1.2) V / 1 μA = 5.4 μs to discharge the potential of the bit line BLi to the circuit threshold value.

As a method for solving the above problems, DRA
Using the folded bit line system used in M, the input to the sense amplifier is connected to the bit line pair BLj, /
It is conceivable that BLj is used and these are operated differentially to read at high speed. Taking as an example the case of reading a cell connected to the bit line BLj, the time for discharging the bit line will be estimated. If the potential of the bit line / BLj is kept at 1.5V and the potential of the bit line BLj is precharged to 1.7V, the information of the cell connected to the bit line BLj is "0".
If so, the bit line BLj should be kept at 1.7V, and if "1", the bit line should be discharged to 1.3V. If the cell current is 1 μA and the bit line capacitance is 3 pF, the time required to discharge the bit line is 3 pF × (1.7-1.3) / 1 μA = 1.2 μs, which is more than that of the conventional single-ended system. Also speeds up reading.

In the folded bit line system, the bit line / BLj must not be discharged when reading the cell connected to the bit line BLj, but the conventional NAND
In the cell type EEPROM, the control gates of the memory cells and the first and second selection gates are continuously arranged in the row direction, so that the cells connected to the adjacent bit lines BLj and / BLj are both "1". Is written, bit line B
Lj and / BLj are discharged at the same time.

As a method of not discharging the bit line / BLj when reading a cell connected to the bit line BLj, for example, the bit line BLj and the drain side select gate (or the source side select gate) of the bit line / BLj are set at different timings. It is possible to use the method. For example, in order to operate the selection gate on the drain side on the bit line BLj and the bit line / BLj at different timings, the control signal SGD1 for selecting the selection gate on the bit line BLj and the bit line / BLj are selected.
A control signal SGD2 for selecting j is required. Assuming that eight memory cells are connected in series between the bit line contact and the source line, 10 lines (8 control gates and 2 select gates) are provided in the row direction in one block in the conventional cell array. However, this method requires eleven wires (eight control gates and three select gates), which increases the area of the cell array and consequently the chip area.

(Problem 2) As described above, in the NAND cell type EEPROM, since the memory cells are connected in series, the cell current is small, it takes several μs to discharge the bit line, and about the random read is required. It takes 10 μs. The data is 1
Pages are simultaneously detected and latched by the sense amplifier. The page read can be read in about 100 ns because only the latch data is read. For example, page length is 2
When reading one page of data with 56 bytes,
It takes 10 + 0.1 × 255 to 35 μs for one random read and 255 page reads. Therefore, when reading the data over a plurality of pages, the page switching unit requires a random read operation of 10 μs.

As a method of eliminating the random read operation at the time of page switching and apparently reading data of a plurality of pages in a page read cycle, for example, a memory cell array and a sense amplifier are divided into two and random read and page read are simultaneously performed. There is. By performing a random read operation on the other side while performing a page read operation on one side of the memory cell array divided into two, a plurality of memory cell arrays can be maintained while maintaining the timing of page read without interposing the random read operation at the switching point of pages. Data can be read across pages.

In the conventional memory cell array, it is necessary to increase the peripheral circuits (row decoder etc.) for transmitting the voltage to the word line in order to shift the random read timing in the divided memory cell array to operate. In particular, in the EEPROM, since a high voltage of about 20 V is applied to the word line at the time of writing, the area of a transistor forming a peripheral circuit (row decoder etc.) for transmitting the voltage to the word line is large. Therefore, if this high-speed page read method is adopted in the conventional memory cell array, there is a problem in that the chip area increases due to the increase in the peripheral circuits (row decoder etc.) for transmitting the voltage to the word lines.

(Problem 3) As the degree of integration increases and the distance between bit lines decreases, the capacitance coupling between bit lines increases. As a result, the potential of the bit line, which should be kept in the "H;High" state during reading, is dragged by the adjacent bit line discharging to the "L;Low" state and falls from the "H" state. In order to reduce the noise caused by the capacitive coupling between bit lines, a method (bit line shield) of keeping every other bit line at a constant potential during reading has been proposed (Japanese Patent Laid-Open No. 4-276).
393). With the bit line shield, reading is performed for every other bit line, so data writing is also 1
Do this for every other bit line.

In the conventional open bit line system or single end system using a cell array, adjacent bit lines share a selection gate and a control gate. The lines also read the cell data and as a result discharge.
Therefore, when using the method of keeping every other bit line at the reference potential (bit line shield) in order to reduce noise due to capacitive coupling between bit lines, the reference potential must be 0V. As a result, when reading data written over multiple pages, for example, when reading data of memory cells connected to even-numbered bit lines and then reading data of memory cells connected to odd-numbered bit lines , The even-numbered bit lines read out first are all discharged to 0V, and the odd-numbered bit lines read out second are precharged from 0V.

That is, after the memory cell of the even-numbered bit line is read, the page is switched when the data of the odd-numbered bit line is read next, and after the memory cell of the odd-numbered bit line is read, When switching pages when reading data of even-numbered bit lines to
It is necessary to discharge all the bit lines read previously and precharge all the bit lines read next from 0V.
As described above, when the bit line shield is applied to the open bit line system and the single end system using the conventional cell array, there is a problem in that a precharge time is required for page switching and power consumption is large.

Next, a description will be given of a problem that occurs at the time of writing when the bit line shield is applied to the open bit line system or the single end system using the conventional memory cell array. When the bit line shield is applied as described above, writing is separately performed in the memory cells connected to the even-numbered bit lines and the memory cells connected to the odd-numbered bit lines. Therefore, for example, when writing to the memory cells connected to the even-numbered bit lines, writing is not performed to the memory cells connected to the odd-numbered bit lines, so that the intermediate potential (10 V is applied to the odd-numbered bit lines). Give a degree). That is, at the time of writing, at least half the bit lines must be charged to the intermediate potential.

In the write operation, first, write is performed, and then verify read is performed to check whether the write is sufficiently performed. Then, the additional writing is not performed on the sufficiently written cells, and the additional writing is performed only on the insufficiently written cells. In the conventional memory cell array, the odd-numbered bit lines are also discharged from the intermediate potential when the verify read is performed after the memory cells connected to the even-numbered bit lines are written. In writing, the odd-numbered bit lines must be charged / discharged to an intermediate potential in every write-verify read cycle, which causes a problem that the write time increases and the power consumption also increases.

As described in (Problem 1) above, the selection M
The problem (problem 3) can be solved by changing the select gate controlling the OS transistor by the adjacent bit line, but instead, 1 is set for each NAND string sandwiched between the source and the bit line.
An extra area for the selection MOS transistor is required,
As a result, there is a problem that the chip area increases.

[0024]

[Problems to be Solved by the Invention]

(Problem 1) As described above, the single-ended sense amplifier used in the conventional nonvolatile semiconductor memory device has a problem that the read time is slow. Further, when implementing a folded bit line system, which is used in so-called DRAM, which can be read at high speed, in a nonvolatile semiconductor memory device, the area of the cell array is increased in the conventional nonvolatile semiconductor memory device. There is a problem that the chip area increases.

(Problem 2) As described above, in the conventional non-volatile semiconductor memory device, when reading data over a plurality of pages, random read is required when switching the word lines, so that wasteful time is involved. However, there is a problem that it takes read time. to solve this problem,
A method has been proposed in which the memory cell array and the sense amplifier are divided into two, and random read and page read are performed at the same time. However, when this method is applied to a conventional nonvolatile semiconductor memory device, there is a problem that the chip area increases.

(Problem 3) In order to reduce the noise caused by the coupling capacitance between bit lines with respect to the conventional open bit line type or single end type memory cell array, every other bit line has a reference potential during reading. If a bit line shield that keeps the bit line is applied, writing and reading are performed for every other bit line, so that the non-selected bit line is set to the intermediate potential (10 V) every write-verify read cycle.
It is necessary to charge and discharge the battery. Further, when reading data over a plurality of pages, it is necessary to discharge the bit line shielded at the time of page switching and precharge the bit line to be selected next. Therefore, there is a problem that power consumption is large at the time of writing and reading, and writing and reading are slow for the precharge time.

The present invention has been made in consideration of the above circumstances, and an object of the present invention is to provide a nonvolatile memory having a memory cell array and a sense amplifier circuit capable of high-speed random read without increasing the chip area. To provide a conductive semiconductor memory device.

Another object of the present invention is to provide a non-volatile semiconductor device which can perform a page read operation at high speed without increasing the chip area, eliminating the dead time generated when switching the word lines. is there.

Still another object of the present invention is a problem that occurs when a bit line shield is applied to an open bit line system and a single end system using a conventional cell array, that is, data reading over a plurality of pages, An object of the present invention is to provide a semiconductor memory device capable of preventing an increase in power consumption, a read time, and a write time when writing data.

[0030]

In order to solve the above problems, the present invention employs the following configurations.

That is, according to the present invention (claim 1), in a nonvolatile semiconductor memory device, a non-volatile memory section composed of one or a plurality of non-volatile memory cells and a first non-volatile memory section are provided. A first selection MOS transistor which is electrically connected to the common signal line, and a second selection MOS transistor which electrically connects the nonvolatile memory section and the second common signal line and has a threshold value different from that of the first selection MOS transistor. And a memory cell unit having a memory cell array arranged in a matrix.

According to the present invention (claim 2), in a non-volatile semiconductor memory device, a non-volatile memory section composed of one or a plurality of non-volatile memory cells, and the non-volatile memory section is a bit line. A memory cell unit composed of a first selection MOS transistor which is made conductive, and a second selection MOS transistor which is made conductive between the nonvolatile memory section and the source line and has a threshold value different from that of the first selection MOS transistor. Has a memory cell array arranged in a matrix.

Further, the present invention (claim 3) includes a non-volatile memory portion composed of a plurality of non-volatile memory cells,
A memory cell unit including a first selection MOS transistor for electrically connecting the nonvolatile memory section to the bit line and a second selection MOS transistor for electrically connecting the nonvolatile memory section and the source line is arranged in a matrix. In a nonvolatile semiconductor memory device having a memory cell array, the first selection MOS transistor has a first threshold value Vth1 and the second selection MOS transistor has a second threshold value Vth1.
A first memory cell unit having a threshold Vth2 of
The first selection MOS transistor has a third threshold value Vth3.
And a second memory cell unit in which the second selection MOS transistor has a fourth threshold value Vth4, a gate electrode of the first selection MOS transistor, and a second selection M
The first and second gate electrodes of the OS transistor are respectively
Shared as select gates of
It is characterized in that the magnitude relation between the third and third threshold values Vth1 and Vth3 and the magnitude relation between the second and fourth threshold values Vth2 and Vth4 are opposite to each other.

Further, according to the present invention (claim 4), there is provided a non-volatile memory portion comprising a plurality of non-volatile memory cells,
A memory cell unit composed of a first selection MOS transistor for electrically connecting the nonvolatile memory section to a bit line and a second selection MOS transistor for electrically connecting the nonvolatile memory section and a source line is arranged in a matrix. In a non-volatile semiconductor memory device having an optimized memory cell array, a first selection MOS transistor has a first threshold value Vth1 and a second selection MOS transistor has a second threshold value Vth2. The cell unit and the first selection MOS transistor have a third threshold value V
a second memory cell unit having th3 and a second selection MOS transistor having a fourth threshold value Vth4, a gate electrode of the first selection MOS transistor and a gate electrode of the second selection MOS transistor, respectively. A sub-array is formed by sharing the first and second select gates,
The magnitude relationship between the first and third threshold values Vth1 and Vth3 is opposite to the magnitude relationship between the second and fourth threshold values Vth2 and Vth4, and the second threshold value and the The threshold values of 3 are different.

According to the present invention (claim 5), there is provided a non-volatile memory portion comprising a plurality of non-volatile memory cells,
A memory cell unit including a first selection MOS transistor for electrically connecting the nonvolatile memory section to the bit line and a second selection MOS transistor for electrically connecting the nonvolatile memory section and the source line is arranged in a matrix. In a nonvolatile semiconductor memory device having a memory cell array, the first selection MOS transistor has a first threshold value Vth1 and the second selection MOS transistor has a second threshold value Vth1.
A first memory cell unit having a threshold Vth2 of
The first selection MOS transistor has a third threshold value Vth3.
And a second memory cell unit in which the second selection MOS transistor has a fourth threshold value Vth4, a gate electrode of the first selection MOS transistor, and a second selection M
The first and second gate electrodes of the OS transistor are respectively
Shared as select gates of
And the third threshold values Vth1 and Vth3 are opposite in magnitude relationship with the second and fourth threshold values Vth2 and Vth4 are opposite in magnitude relationship, and the first and second memory cells in the sub-array are In the unit, the timing means for page-reading the data stored in the non-volatile memory unit in the other memory cell unit while randomly reading the data stored in the non-volatile memory unit in the other memory cell unit. It is characterized by having.

The preferred embodiments of the present invention are as follows.

(1) The first threshold value and the fourth threshold value are equal, and the second threshold value and the third threshold value are equal.

(2) The first memory cell units and the second memory cell units are arranged alternately to form a sub-array.

(3) When reading the non-volatile memory portion of the first memory cell unit, both the first and second selection MOS transistors of the first memory cell unit are made conductive, and the second memory cell unit is made conductive. One of the first and second selection MOS transistors is turned off,
When the non-volatile memory portion of the memory cell unit is read, one of the first and second selection MOS transistors of the first memory cell unit is brought into a non-conducting state, and the first and second selection memory transistors of the second memory cell unit are turned off. A means for applying a read selection gate voltage to the first and second selection MOS transistors in the selected sub-array is provided so that both the selection MOS transistors are made conductive.

(4) In (3), the data stored in the non-volatile memory part in one of the first memory cell unit and the second memory cell unit in the sub-array is stored in the bit line. When reading, the bit line connected to the other memory cell unit is kept at the non-selected read bit line potential.

(5) In (4), with the non-selected read bit line potential as the reference potential, the first bit line potential to which the first memory cell unit at the time of reading and the second memory cell unit are connected. A bit line voltage detection unit that differentially detects a potential difference between the second bit line potential and the second bit line potential to be connected.

(6) The non-volatile memory section is composed of a plurality of electrically rewritable non-volatile memory cells.

(7) A non-volatile memory cell is formed by stacking a charge storage layer and a control gate on a semiconductor layer, and a plurality of non-volatile memory cells adjacent to each other are connected in series to share a source and a drain. Be connected to form a non-volatile memory section.

(8) A non-volatile memory cell is formed by stacking a charge storage layer and a control gate on a semiconductor layer, and one or a plurality of non-volatile memory cells are all connected in parallel so that the source and drain are shared. To configure the non-volatile memory section.

(9) By controlling the impurity concentration of the channel of the non-volatile memory cell, the first, second, third and fourth
Select the threshold of.

(10) The first and second selection MOS transistors are constructed by stacking a charge storage layer and a selection gate on a semiconductor layer.

(11) First selection MOS transistor and second
The gate length of each selection MOS transistor is different.

(12) A verify operation for checking whether or not writing is sufficient in the nonvolatile memory section in one of the first memory cell unit and the second memory cell unit in the sub-array, To keep the bit line connected to the other memory cell unit at a constant potential during the operation, or through the write, write verify, rewrite, and write verify operations.

(13) The memory cell array is composed of a first sub memory cell array and a second sub memory cell array,
Each of these sub memory cell arrays has a first and second sub memory cell array.
Memory cell unit of the first sub-memory cell array, and applies the voltage applied to the gate of the first selection MOS transistor of the first sub-memory cell array to the second MOS of the second sub-memory cell array.
A voltage applied to the gate of the transistor and to the gate of the second MOS transistor of the first sub memory cell array is applied to the first MOS of the second sub memory cell array.
Apply to the gate of a transistor.

In addition, the present invention (claim 14) provides a non-volatile memory section composed of a plurality of non-volatile memory cells, and a first selection for electrically connecting the non-volatile memory section to the first common signal line. A second selection MO for electrically connecting the MOS transistor and the non-volatile memory unit to the second common signal line.
In a nonvolatile semiconductor memory device having a memory cell array in which memory cell units each composed of an S transistor are arranged in a matrix, a read or a read operation is performed for a memory cell connected to one or more bit lines in the memory cell array. It is characterized in that it has means for connecting and disconnecting between bit lines within a bit line group composed of a plurality of bit lines among the remaining bit lines in the memory cell array during writing.

Here, the following are preferred embodiments of the present invention.

(1) The means for connecting and disconnecting bit lines is
Must be a MOS transistor provided between bit lines.

(2) The bit line group is composed of bit line pairs connected to the same sense amplifier circuit.

(3) A plurality of bit lines are connected to the same sense amplifier circuit, and the sense amplifier circuit constitutes an open bit line type memory cell array arranged between the bit lines connected to the circuits. To do.

(4) In a memory cell array of the open bit line system, a shared sense amplifier system in which the first bit line pair and the second bit line pair share a sense amplifier is formed and connected to the first bit line pair. A means for connecting the bit lines forming the second bit line pair is provided when reading or writing the memory cell.

(5) The memory cell array is composed of one or a plurality of non-volatile memory cells, and a first selection MOS for electrically connecting the non-volatile memory section to the first common signal line. The transistor, the non-volatile memory unit and the second common signal line are electrically connected, and the first selection MO
A memory cell unit including an S transistor and a second selection MOS transistor having a different threshold value is arranged in a matrix.

(6) The first selection MOS transistor is the first
The first memory cell unit having the second threshold Vth1 and the second selection MOS transistor having the second threshold Vth2, and the first selection MOS transistor having the third threshold Vth3. The second selection MOS transistor is the fourth
And a second memory cell unit having a threshold value Vth4 of the sub-array by sharing the gate electrode of the first selection MOS transistor and the gate electrode of the second selection MOS transistor as the first and second selection gates, respectively. And the magnitude relationship between the first and third threshold values Vth1 and Vth3 and the magnitude relationship between the second and fourth threshold values Vth2 and Vth4 are opposite to each other.

(7) The first threshold value and the fourth threshold value are equal, and the second threshold value and the third threshold value are equal.

(8) The first memory cell units and the second memory cell units are alternately arranged to form a sub array.

(9) In (4), in the sub-array, the first
The memory cell unit of is connected to the first bit line pair,
The second memory cell unit is connected to the second bit line pair.

[0061]

According to the present invention, the selection MOS transistors sharing one selection gate can be made conductive and non-conductive, and by providing two such selection gates. It is possible to easily realize a selected memory cell and a non-selected memory cell in the memory cells having the same selection gate. Specifically, by changing the thresholds of the select gate on the source side and the select gate on the drain side, and changing the threshold of the select gate in the adjacent memory cell, for example, a memory connected to an even-numbered bit line. When reading the cell to the bit line, the memory cell connected to the odd-numbered bit line can be deselected. As a result, a folded bit line system can be realized without increasing the chip area, and high-speed random read is possible.

Further, according to the present invention, by randomly reading one of the first memory cell unit and the second memory cell unit while page-reading the other,
It is possible to perform the page read operation at high speed without increasing the chip area, eliminating the dead time generated when switching the word lines. Further, according to the present invention, the precharge associated with the bit line shield and the like can be omitted. Therefore, there is a problem that occurs when the bit line shield is applied to the open bit line system and the single end system using the conventional cell array, that is, Increased power consumption when reading and writing data across multiple pages,
It is possible to reduce the increase in reading and writing time.

[0063]

Embodiments of the present invention will be described below with reference to the drawings.

(Embodiment 1) An embodiment for solving (Problem 1) will be described below.

FIG. 1 shows N according to the first embodiment of the present invention.
FIG. 3 is a block diagram showing the overall configuration of an AND cell type EEPROM. In the figure, 1 is a memory cell array, 2 is a sense amplifier / latch circuit as a latch means for writing and reading data, 3 is a row decoder for selecting word lines, 4 is a column decoder for selecting bit lines, and 5 is An address buffer, 6 is an I / O sense amplifier, 7 is a data input / output buffer, and 8 is a substrate potential control circuit.

FIG. 2 is a diagram showing the structure of the memory cell array, in which BL and / BL are bit lines, WL is a word line, and S is a word line.
TD is a first selection MOS transistor connected to the drain side of the NAND cell, STS is a second selection MOS transistor connected to the source side of the NAND cell, SGD is a selection gate for driving the selection MOS transistor STD, and SGS is a selection MOS transistor. A select gate for driving the transistor STS, SA is a sense amplifier, and TG is a control signal for driving a gate for connecting the sense amplifier SA and the bit line BL.

The sense amplifier SA receives the adjacent bit line pair BLj, / BLj as shown in FIG. This is a folded bit line system used in DRAM. In order to realize the folded bit line system, it is necessary to prevent one bit line of a bit line pair from discharging while the other bit line does not discharge. Select MOS transistors sharing the same select gate (for example, STS00, STS10, STD in FIG. 2)
This is achieved by providing a difference between the threshold values of 00 and STD10) and applying different voltages to the select gate on the drain side and the select gate on the source side.

In FIG. 2, a high threshold value Vt1 (for example, 2
A selection MOS transistor having V) is described as E-type, and a selection MOS transistor having a low threshold Vt2 (for example, 0.5 V) (Vt1> Vt2) is described as I-type. The voltage applied to the gates (selection gates) of the two types of selection MOS transistors is the voltage Vsgh (for example, 3V) (Vsg) that turns on both the I-type transistor and the E-type transistor.
h> Vt1, Vt2), and the voltage Vsgl (for example 1.5V) (Vt1>Vsgl> Vt2) at which the I-type transistor turns on but the E-type transistor turns off.

Here, the memory cell is an electrically rewritable nonvolatile memory cell in which a floating gate (charge storage layer) and a control gate are laminated on a semiconductor substrate, and a plurality of NAND cells are connected in series. A cell (nonvolatile memory section) is configured. And I-typ to the NAND cell
The first memory cell unit is configured by connecting the STS of e and the STD of E-type, and the second memory cell unit is configured by connecting the STS of E-type and the STD of I-type to the NAND cell. , The first and second memory cell units are alternately arranged. A sub-array is composed of a plurality of first and second memory cell units sharing a word line.

A method of applying the voltage of the select gate will be specifically described with reference to FIG. For example, when reading data from the memory cell MC000, word lines WL00, WL08 ...
WL15 is set to 0V, and word lines WL01 to WL07 are set to Vcc (for example, 3V). Then, the source side select gate SGS0
Is set to Vsgh, and the drain side selection gate SGD0 is set to Vsgl. SGS1 and SGD1 are set to 0V. In this case, both the source side selection MOS transistors STS00 and STS10 are turned on. On the other hand, the selection MOS transistor STD00 on the drain side of the bit line BL0 turns on, but the selection MOS transistor STD on the drain side of the bit line / BL0.
Since 10 is turned off, if the data in the memory cell MC000 is "1", the bit line BL0 is discharged, but the bit line / BL0 is not discharged regardless of the data in the memory cell MC100.

On the other hand, when reading data from the memory cell MC100, the word lines WL00 and WL08 to WL15 are set to 0 V and the word lines WL01 to WL07 are set to Vcc, as in the case of reading the memory cell MC000. Source side selection gate S
GS0 is Vsgl and the drain side selection gate SGD0 is Vsgl
sgh SGS1 and SGD1 are set to 0V. In this case, the drain side selection MOS transistors STD00, S
TD10 turns on together. Since the selection MOS transistor STS10 on the source side is turned on, the bit line / BL0 is discharged if the data in the memory cell MC100 is "1", but the selection MOS transistor STS00 is turned off, so the bit line B
L0 does not discharge.

The present invention is a selection MOS transistor connected to the bit line pair BLj, / BLj, and has the same selection gate S.
Select MOS transistors controlled by GS and SGD (for example, STD00 and STD10, STS00 and ST in FIG. 2).
The threshold values of S10, STD01 and STD11, STS01 and STS11) may be made different, and the method of setting the threshold values is arbitrary. For example, as shown in FIG. 3, the selection MOS transistor STD00 of the bit line BLj is set to E-type, STS00.
May be I-type, the selection MOS transistor STD10 of the bit line / BLj may be I-type, and STS10 may be E-type.

Further, in FIG. 2, all the selection MOS transistors on the drain side of the cells connected to the bit line BLj are I-t.
With ype, the selection MOS transistor on the source side is E-type
However, for example, as shown in FIG. 4, two NAND blocks sharing a bit line contact are used to select the MO on the drain side.
One of the S transistors may be of I-type and the other may be of E-type. 2 to 4, the bit lines BLj alternately arranged are selected and read at the same time. For example, as shown in FIG. 5, the threshold value of the selection MOS transistor is set to select the bit line BL0. At this time, the bit line / BL1 may be selected.

In the present invention, not only in this (Embodiment 1) but also in all the embodiments up to the following (Embodiment 5), 1
Among the selection MOS transistors sharing the same selection gate, it is possible to generate conductive MOS transistors and non-conductive MOS transistors, and by preparing two such selection gates, the same selection gate can be provided. The fact that a memory cell in a selected state and a memory cell in a non-selected state can be easily realized in the memory cells included therein is utilized.

Therefore, the threshold voltage of the selection MOS transistor and the voltage applied to the selection gate are arbitrary. The drain side selection MOS transistors are Vtd1, Vtd2 (V
td1> Vtd2) and the voltage applied to the drain side select gate is Vsghd (Vsghd> Vtd1).
), Vsgld (Vtd1>Vsgld> Vtd2), and the source side selection MOS transistors are Vts1 and Vts.
2 (Vts1> Vts2), which has two threshold values, and the voltage applied to the source side select gate is Vsghs (Vsghs> V
ts1) and Vsgls (Vts1>Vsgls> Vts2), Vtd1 = Vts1, Vtd as in the above embodiment.
2 = Vts2, Vsghd = Vsghs, Vsgld = Vsgls are not required.

For example, the threshold values of the drain side selection MOS transistors are 2V and 0.5V, and the threshold values of the source side selection MOS transistors are 2.5V and 1V.
As the two types of V, the voltage applied to the drain side selection gate is Vsgh = 3V, Vsgl = 1.5V, and the voltage applied to the source side selection gate is Vsgh = 3V, Vsgl = 1.
It may be 2V.

If Vsgh is made larger than Vcc, selection M
Since the conductance of the OS transistor increases (that is, the resistance decreases) and the cell current flowing through the NAND cell string increases during reading, the bit line discharge time is shortened, and as a result, the verify read of read and write is accelerated. To be done. Vsgh may be boosted from Vcc by a booster circuit in the chip, for example.

The voltage V of the select gate for turning on all the select MOS transistors sharing one select gate
It is desirable that sgh be less than the power supply voltage Vcc. If Vsgh is larger than Vcc, a booster circuit is required in the chip, which leads to an increase in chip area.

The smaller threshold value Vt2 of the selection MOS transistor may be a negative threshold value (eg, -1V). At the time of writing, 0 V is applied to the bit line connected to the cell to be written, and an intermediate potential (about 10 V) is applied to the bit line connected to the cell not to be written. The source side select gate must be turned off to prevent current flow. Therefore, when Vt2 is set to a negative threshold value of about -1V, a negative voltage (for example, -1.5V) that turns off the selection gate having the negative threshold value is applied to the selection gate on the source side during writing. Good.

The larger value Vt1 of the threshold values of the select gate may be set to a voltage higher than the power supply voltage Vcc (for example, 3.5V). In this case, in order to turn on the selection MOS transistor having the threshold value of Vt1 at the time of reading or verify reading, for example, 4V may be applied to the selection gate by using the booster circuit inside the chip.

Now, referring to the timing chart of FIG. 8, the memory cell MC00 connected to the bit line BLj of FIG.
The operation for reading 0 will be described. The sense amplifier is formed of a CMOS flip-flop controlled by control signals SAN and SAP.

First, the control signal TG is Vcc (for example, 3V).
From Vss, the CMOS flip-flop FF and the bit lines BLj and / BLj are separated. Then, the precharge signals φpA and φpB change from Vss to Vcc (at time t
0), the bit line BLj is precharged to VA (for example, 1.7V), and the bit line / BLj is precharged to VB (for example, 1.5V) (time t1). When precharge is over, φpA,
φpB becomes Vss, and the bit lines BLj and / BLj are in a floating state. After that, a desired voltage is applied from the row decoder 3 to the control gate (word line) and the selection gate (time t2).

When reading the memory cell MC000 of FIG. 6, WL00 is 0 V, WL01 to WL07 are 3 V, and SGD0 is
Is 3V (Vsgh) and SGS0 is 1.5V (Vsgl). The data written in the memory cell MC000 is "0".
In this case, since the threshold value of the memory cell MC000 is positive, no cell current flows, and the potential of the bit line BLj remains 1.7V. When the data is "1", the cell current flows and the potential of the bit line BLj drops to 1.5 V or less. Further, since the selection gate SGS0 is 1.5V, the selection transistor STS10 is turned off, and the bit line / BLj is not discharged regardless of the data written in the memory cell MC100 and is kept at the precharge potential 1.5V. .

Thereafter, at time t3, SAP is 3V, SAN
Becomes 0V, the CMOS flip-flop FF is inactivated, and φE becomes 3V at time t4, so that CMO
When the S flip-flop FF is equalized, the node N
1, N2 becomes Vcc / 2 (for example, 1.5 V). Time t
After 5 TG becomes 3V and the bit line and the sense amplifier are connected (time t6), SAN becomes 0V to 3V and the potential difference between the bit lines BLj and / BLj is amplified. After that, at time t7, SAP changes from 3V to 0V and the data is latched.

That is, if "0" is written in the memory cell MC000, the node N1 is 3V and the node N2 is 0V.
It becomes V. If "1" is written in MC000, the node N1 becomes 0V and the node N2 becomes 3V. After that, when the column selection signal CSLj changes from 0V to 3V, CMO
The data latched in the S flip-flop is I /
It is output to O and I / O '(time t8).

Next, FIG. 10 shows a timing chart in the case of reading the memory cell MC100 connected to the bit line / BLj in FIG. In this case, the bit line BLj is 1.5
V and bit line / BLj are precharged to 1.7V (time t1). The voltage applied to the control gate (word line) from the row decoder 3 at the time of reading the cell data to the bit line is the same as that at the time of reading the memory cell MC000, but the voltage applied to the select gate is 1.5V for SGD0, SG
S0 is 3V (time t2).

When the data written in the memory cell MC100 is "0", the threshold value of the memory cell MC100 is positive, so that the cell current does not flow and the potential of the bit line / BLj remains 1.7V. When the data is "1", the cell current flows and the potential of the bit line / BLj drops to 1.5.
It becomes V or less. Further, since the selection gate SGD0 is 1.5V, the selection MOS transistor STD00 is turned off,
The bit line BLj is not discharged regardless of the data written in the memory cell MC000, and the precharge potential is 1.5V.
Kept in. After that, the data read to the bit line / BLj is sensed and latched by the sense amplifier as in the case of reading the memory cell MC000, and the I /
It is output to O and I / O '.

The timing of the read operation is arbitrary. For example, at time t5, as shown in FIG. 9, the transfer gate connecting the bit line and the sense amplifier is turned on to transfer the potentials of the bit lines BLj and / BLj to the nodes N1 and N2, and then the transfer gate may be turned off. . Therefore, since the load capacitance of the sense amplifier is reduced by disconnecting the bit line pair from the sense amplifier, the potentials of the nodes N1 and N2 are rapidly determined at the time of sensing and data latching.

In the timing charts of FIGS. 8 to 10, SAN is first changed from 0V to 3V to turn on the N-channel transistor of the CMOS flip-flop FF and then SAP is changed from 3V to 0V in the sense operation of the sense amplifier. Although the P-channel transistor of the flip-flop FF is turned on, SAP may be changed from 3V to 0V almost at the same time when SAN is changed from 0V to 3V.

When the data of the cell connected to the bit line BLj is sensed and latched by the sense amplifier, one of the potentials of the bit lines BLj and / BLj is 0V and the other is Vcc (for example, 3V). If φE is set to 3V after the cell data of the bit line BLj is output from the sense amplifier to I / O and I / O ', the bit lines BLj and / BLj are connected (equalized) without precharging.
Lj and / BLj become 1.5V. After that, for example, when reading the bit line / BLj, φPB is set to 3V and VB is set to 1.7V to set the bit line / BLj to 1.7.
Precharge to V. Bit line BL
By connecting the bit lines BLj and / BLj after sensing j, the precharge time for the next read can be shortened and the power consumption required for precharge can be reduced.

Further, as shown in FIG. 7, a circuit for verifying after writing to the sense amplifier may be added.

The method of precharging different potentials to the bit line pairs is performed by the potential VA from the peripheral circuit as shown in FIG.
, VB, a dummy cell may be provided as shown in FIG. 11, for example. In this case, the bit line BLj
, / BLj are precharged to the same potential VPR. The current flowing through the dummy cell is set smaller than the worst read current of the cell. This includes a dummy NAND connected in series
For example, the type cell may be a depletion type transistor, the channel length L may be increased, and the channel width W may be decreased.

When the threshold value of the dummy selection MOS transistor is set as shown in FIG. 11, when the data of the memory cell connected to the bit line BLj is read to the bit line BLj, the bit line / BLj is discharged through the dummy cell. , When reading the data of the memory cell connected to the bit line / BLj, the bit line BLj is discharged through the dummy cell.

The operation of this embodiment will be described by taking the case of reading the memory cell MC000 as an example. First, the precharge control signal PRE becomes 3V, and the bit lines BLj, / BL
j is precharged to the precharge potential VPR (for example, 1.7V). After that, the control gate line and the select gate of the memory cell are selected, and 0V is applied to the dummy word line DWL.
The dummy selection gates DSGS, DSGD are applied with a voltage substantially the same as the voltage applied to the selection gates SGS, SGD of the selection MOS transistors.

If "0" is written in the memory cell MC000, the bit line BLj is not discharged and the precharge potential of 1.7V is maintained. If "1" is written in MC000, the bit line BLj is discharged to 1.3V, for example.
When the bit line BLj written with "1" is discharged to 1.3V, the bit line / BLj may be discharged to 1.5V through the dummy cell. After that, the operation of differentially amplifying the potential of the bit line pair by the sense amplifier is the same as that of the embodiment of FIG.

As a method of precharging different potentials to the bit line pairs, the dummy cell may be composed of one transistor and one capacitor as shown in FIG. First, the bit line precharge control signal PRE becomes 3V, and the bit lines BLj and / BLj are precharged to the same potential VPR.
When the data of the memory cell MC000 is read to the bit line BLj after the control signal PRE becomes 0V and the bit line becomes floating, φPB becomes 3V and the capacitor C1 is charged. The bit line / BLj falls from the precharge potential VPR by the amount of the electric charge charged in the capacitor C1. This may be used as a reference potential when differentially amplifying the bit line pair.

Data in the memory cell MC100 is transferred to the bit line /
When reading to BLj, since .phi.PA becomes 3V, the capacitor C0 is charged and the bit line BLj falls from the precharge potential VPR. This bit line BLj may be used as the reference potential.

Further, in the embodiments of FIGS. 6 to 10, while discharging the bit line to which the memory cell to be read is connected, the other bit line of the bit line pair connected to the sense amplifier (for example, FIG. The bit line / BLj is read when the memory cell MC000 of No. 6 is read, and the bit line BLj is read when the memory cell MC100 is read. However, while the bit line (for example, the bit line BLj) is precharged to 1.7V and the data of the memory cell is read out thereafter, the precharge control signal φPB is kept at 3V, which serves as a reference (for example, the bit line BLj). Bit line / BLj) with reference potential of 1.5
It can also be fixed at V.

By keeping the bit line / BLj at the reference potential in this way, noise caused by capacitive coupling between adjacent bit lines at the time of discharging the bit line can be reduced. In the verify read after writing (described in detail in the fourth embodiment) as in the case of the above-mentioned reading, the bit line charges and discharges according to the data written in the cell, but the bit line / BLj that is not read is set to the reference potential. If this is maintained, noise due to capacitive coupling between bit lines can be reduced.

In order to reduce noise due to capacitive coupling between adjacent bit lines when sensing and latching the data of the memory cell read to the bit line, DR as shown in FIG.
The twisted bit line system proposed by AM may be used. A twisted bit line system as shown in FIG. 14 may be adopted.

The selection MOS transistor may be formed of a cell having a selection gate and a floating gate as shown in FIG. In the case of the present embodiment, the threshold value of the selection MOS transistor can be determined by injecting electrons into the floating gate of the selection MOS transistor before shipping the semiconductor memory device. The electrons may be injected into the floating gate of the drain side selection MOS transistor (eg, STD00 in FIG. 15) by tunneling from the substrate.

That is, the word lines WL00 to WL07 are at an intermediate potential (about 10 V) or 0 V, and the selection gate SGD0 is V.
pp (about 20V), select gate SGD0 is 0V, bit line BL0 is 0V, bit lines / BL0, BL1, / BL1
May be set to an intermediate potential (about 10 V). Further, in order to determine the threshold value of the selection MOS transistor on the source side, the selection gates SGD0, SGS0 and the word lines WL00 ...
All WL07 are set to "H" to turn on all the NAND cell strings, and Vpp or the intermediate potential and the bit line /
Hot electrons may be injected by applying 0 V to BL0, BL1, / BL1.

As described above, according to the present invention, by changing the threshold voltage of the selection MOS transistor and the voltage applied to the selection gate, the folded bit line system can be realized without increasing the chip area, and the high speed operation can be achieved. Random read is possible. As a method of changing the threshold value, it is possible to change the gate oxide film thickness of the selection MOS transistor or change the concentration of the channel-doped impurities in the selection MOS transistor. Or select MOS
The threshold may be different depending on whether the transistor is channel-doped with impurities or not. The threshold value can also be changed by changing the channel length of the selection MOS transistor. In other words, a transistor having a short channel length has a small threshold value due to the short channel effect, and thus may be an I-type transistor.

As a method of changing the gate oxide film thickness and the impurity concentration of the channel, another manufacturing process such as channel doping of the peripheral circuit may be used without introducing a new manufacturing process. In either method, the thresholds of the selection MOS transistors may be made different, and if there is a difference in the thresholds, a predetermined threshold can be obtained by a substrate bias or the like.

In the conventional NAND cell type EEPROM,
0V is applied to the source side select gate of the write block, but the source side select MOS transistor is I-typ.
When the threshold Vt2 at e is about 0.1 V (or a negative threshold), the source side select MOS transistor is not completely cut off, and the cell current is, for example, 0.1 μA.
Bit line that does not flow and is not written has an intermediate potential (about 10 V)
To discharge from.

For example, if the bit lines are charged to the intermediate potential without writing to the memory cells connected to the 200 bit lines, the total cell current is 200 × 0.1 μA =
20 μA will flow. In order to improve the cut-off characteristic of the I-type transistor, a voltage of about 0.5 V may be applied to the common source line during writing.
If 0.5V is applied to the source, the potential difference between the source and the substrate becomes -0.5V, and the threshold of the I-type transistor increases due to the substrate bias effect. Therefore, 0V is applied to the gate of the I-type transistor. The cutoff characteristic at the time of reading is improved, and the cell current at the time of reading can be reduced.

In order to set the lower threshold value (I-type) of the select gate threshold values to, for example, 0.5 V, a method of reducing the substrate concentration can be considered. In an I-type transistor with a low substrate concentration, when a drain voltage is applied without applying a gate voltage, a depletion layer between the drain and the substrate spreads, resulting in a depletion layer between the drain and the substrate and a depletion layer between the source and the substrate. There is a problem that they are connected and dull (punch through). To increase the punch-through withstand voltage of the I-type selection MOS transistor,
The channel length L of the selection MOS transistor may be increased.

In the above embodiment, the NAND cell type E is used.
Although the EPROM has been described, the present invention is effective as long as it is a nonvolatile semiconductor memory device in which the drain side of the memory cell is connected to the bit line via the select gate and the source side of the memory cell is connected to the source line via the select gate. .
For example, an AND cell type EEPROM as shown in FIG.
(H.Kume el al.; IEDM Tech.Dig., Dec.1992, pp.991-99
The present invention is also effective in 3), and is also effective in a NOR type EEPROM or a mask ROM having one memory cell between the drain side select gate and the source side select gate.

(Embodiment 2) An embodiment for solving (Problem 2) will be described below.

FIG. 17 is a block diagram showing the structure of a NAND cell type EEPROM according to this embodiment. Reference numeral 1 in the drawing denotes a memory cell array as a memory means, and the memory cell is divided into two 1A and 1B because of the open bit line system. The memory cell arrays 1A and 1B are each divided into at least two predetermined units.

In this embodiment, one page has 256 bits, and the memory cell arrays 1A and 1B have 128 bits each.
It is assumed that it is divided into A1, 1A2 and 1B1, 1B2. Reference numeral 2 is a sense amplifier circuit as a latch means for writing and reading data, which is divided into at least two for every predetermined unit like the memory cell arrays 1A and 1B. In FIG. 17, the sense amplifier is divided into 2A and 2B. 3 is a row decoder for selecting a word line,
Reference numeral 4 is a column decoder for selecting bit lines, 5 is an address buffer, 6 is an I / O sense amplifier, 7 is a data input / output buffer, and 8 is a substrate potential control circuit.

The memory cell array 1A1 is shown in FIGS.
19, 1A2 is shown in FIG. 20, and 1B2 is shown in FIG.
In FIGS. 18 to 21, the threshold value of the selection MOS transistor of the memory cell array has two kinds of values as in the above-mentioned (embodiment 1). It is assumed that the threshold value of the selection MOS transistor denoted by E-type is 2V and the threshold value of the selection MOS transistor denoted by I-type is 0.5V. Therefore, E-typ
When both the selection MOS transistor of e and the selection MOS transistor of I-type are turned on, Vcc is applied to the selection gate.
When, for example, 3V is applied and only the I-type is turned on, 1.5V is applied to the select gate.

When the data of the memory cell array 1A1 is read to the bit lines BL0A to BL127A, the drain side select gate SGD is 3V, and the source side select gate SGS.
Is 1.5V. On the other hand, when reading the data of the memory cell array 1A2 to the bit lines BL128A to BL255A, the drain side selection gate SGD is set to 1.5V and the source side selection gate SGS is set to 3V. If the data in the memory cell arrays 1A1 and 1A2 are read simultaneously, S
Both GS and SGD may be set to 3V.

The sense amplifier is a differential type sense amplifier like the folded bit line system of the first embodiment. A sense amplifier 2A (SA1) connected to the memory cell arrays 1A1 and 1B1 is shown in FIG. 22, and a sense amplifier 2B (SA2) connected to the memory cell arrays 1A2 and 1B2.
Is shown in FIG.

Here, the read operation of this embodiment will be described with reference to the timing charts of FIGS. 24 and 25, taking the case of reading the data written in two pages as an example. First,
On the first page, the sense amplifier 2A (SA1) and the sense amplifier 2B (SA2) operate simultaneously. Control signal TG
1, TG2 changes from 3V to 0V, and CMOS flip-flops FF1 and FF2 and bit lines BLjA and BLjB (j =
0, 1, ..., 255) are separated.

Next, the precharge signals φpA1, φpB1,
φpA2 and φpB2 change from 0V to 3V, and bit line BLjA
(J = 0,1, ..., 255) is, for example, 1.7V, and the bit line BLjB (j = 0,1, ..., 255) is, for example, 1.5V.
Precharged to V. ΦpA after precharge
1, φpB1, φpA2, φpB2 become 0V, and bit line B
LjA and BLjB (j = 0, 1, ..., 255) are in a floating state. After that, a desired voltage is applied from the row decoder 3 to the control gate and the selection gate.

In FIGS. 18 and 19, WL00 is 0 V and WL01 to W.
L07 becomes 3V, SGD0 becomes 3V, and SGS0 becomes 3V.
When the data written in the memory cell selected by the word line WL00 is "0", the threshold value of the memory cell is positive, so that no cell current flows and the potential of the bit line BLjA remains 1.7V. When the data is "1", the cell current flows and the potential of the bit line BLjA drops to 1.5V.
It becomes the following. Further, the bit line BLjB is not discharged and is kept at the precharge potential of 1.5V.

After that, SAP1 and SAP2 are 3V and SA
N1 and SAN2 are set to 0V, the CMOS flip-flops FF1 and FF2 are inactivated, and φE1 and φE2 are set to 3V.
2 is reset. Then, TG1 and TG2 become 3V, and after the bit line and the sense amplifier are connected, SAN1
, SAN2 goes from 3V to 0V and bit lines BLjA, B
The potential difference of LjB (j = 0, 1, ..., 255) is amplified. After that, SAP1 and SAN2 change from 0V to 3V, and the data is latched. Then, the column selection signal CSL
j (j = 0, 1, ..., 255) are selected one after another, and CM
The data latched in the OS flip-flop is I /
It is output to O and I / O '(page read).

After page-reading the first half data of the first page (column addresses 0 to 127), while page-reading the second half data of the first page, the first half data of the second page row address (bit line BLjA; j = 0,
1, ..., 127 ..., Random reading of data of memory cells connected to. This may be performed by detecting that the column address is 128, for example.

First, the precharge signals φpA1, φpB1,
φpA2 and φpB2 change from 0V to 3V, and bit line BLjA
(J = 0, 1, ..., 127) is set to 1.7V by the bit line BL
jB (j = 0, 1, ..., 127) is precharged to 1.5V. When precharge ends, φpA1, φpB1, φ
pA2 and φpB2 become 0V, and bit lines BLjA and BLjB
(J = 0, 1, ..., 127) is in a floating state. After that, a desired voltage is applied from the row decoder 3 to the control gate and the selection gate. WL01 is 0V, WL00,
WL02 to WL07 are 3V, SGD0 is 3V, and SGS0 is 1.5V.

When the data written in the memory cell selected by the word line WL01 is "0", the cell current does not flow because the memory cell threshold value is positive, and the bit line BL
The potential of jA (j = 0, 1, ..., 127) remains 1.7V. When the data is "1", a cell current flows and the potential of the bit line BLjA (j = 0, 1, ..., 127) decreases to 1.5 V or less. In addition, bit line BLjB (j =
0, 1, ..., 127) are not discharged, and the precharge potential of 1.5 V is maintained.

After that, SAP1 is 3V and SAN1 is 0V.
Then, the CMOS flip-flop FF1 is inactivated, and φE1 becomes 3V, so that the CMOS flip-flop FF1 is equalized. Then, TG1 becomes 3V, and after the bit line and the sense amplifier are connected, SAN
1 changes from 3V to 0V, and bit lines BLjA and BLjB (j =
The potential difference of 0, 1, ..., 127) is amplified. afterwards,
SAP1 and SAN2 change from 0V to 3V, and the data is latched in the sense amplifier 2A (SA1).

When the page read of the first page advances by 256 column addresses, the first page of the next second page has already been read.
The data for 28 column addresses is stored in the sense amplifier 2A (S
Since it is latched by A1), it is not necessary to perform the random read operation. While the page addresses of the second page column addresses 0 to 127 are read from the sense amplifier 2A (SA1), the second half column address 128 of the second page is read.
Perform a random read operation for .about.255. That is,
A desired voltage is applied from the row decoder 3 to the control gate and the selection gate. WL01 is 0V, WL00, WL02-WL
07 is 3V, SGD0 is 1.5V, and SGS0 is 3V.

When the data written in the memory cell selected by word line WL01 is "0", the cell current does not flow because the memory cell threshold value is positive and bit line BL
The potential of jA remains 1.7V. When the data is "1", cell current flows and bit line BLjA (j = 128,
, 129, ..., 255) decreases to 1.5 V or less.

The bit line BLjB (j = 128, 12
, ..., 255) are not discharged, and the precharge potential is 1.5.
Kept at V. And SAP2 is 3V and SAN2 is 0V.
The voltage becomes V, the CMOS flip-flop FF2 is inactivated, and φE2 becomes 3V, whereby the CMOS flip-flop FF2 is reset. And TG2 is 3V
After connecting the bit line and the sense amplifier, SA
N2 goes from 0V to 3V and bit lines BLjA, BLjB (j
= 128,129, ..., 255), the potential difference is amplified. After that, SAP2 changes from 3V to 0V, and the data is latched in the sense amplifier 2B (SA2).

When the page read of the second page advances by 128 column addresses, the data of 128 column addresses in the second half of the next second page has already been sensed by the sense amplifier 2.
Since it is latched by B (SA2), the data for 128 column addresses in the latter half of the second page can be serially read without performing the random read operation.

The present invention is not limited to the above embodiment. Although the memory cell is divided into two in the above embodiment, it may be divided into four, or may be divided into any number.

The timing charts of FIGS. 24 and 25 show only an example. In the timing charts of FIGS. 24 and 25, the sense amplifier 2A (SA1) and the sense amplifier 2B (SA2) simultaneously read the data of the first page, but as shown in the timing charts of FIGS. First, the memory cell corresponding to the column address in the first half of the first page is randomly read, and subsequently, while the data in the first half of the first page is page-read, the second half data of the first page is randomly read. Good.

Further, in FIGS. 24 and 25, the bit lines are precharged at the same time by the random read of the first half data of the second page and the random read of the second half data of the second page, but as shown in FIGS. Sense amplifier 2A
The timing of precharging the bit line may be changed depending on whether the random read is performed at (SA1) or the random read is performed at the sense amplifier 2B (SA2).

Further, the memory cell array may not be divided physically into one continuous unit. For example, as shown in FIGS. 28 and 29, the sense amplifier SA1
And the bit lines connected to the sense amplifier SA2 may be arranged alternately. Sense amplifier SA1
The bit line connected to the sense amplifier SA2 can be grounded to 0V during random reading of the bit line connected to the bit line. In this case, the distance between the bit lines connected to the sense amplifier SA1 is as shown in FIGS. Therefore, the noise due to capacitive coupling between bit lines can be reduced at the time of random read.

The present invention can be applied not only to the memory cell array having the open bit line arrangement. For example, a single end type memory cell arrangement as shown in FIG. 31 having an inverter type sense amplifier as shown in FIG. 30 may be used. FIG.
The memory cell array connected to the bit line BLj (j = 0, 1, ..., 255) at 1 is the bit line BLjA (j =
0, 1, ..., 255).

(Embodiment 3) An embodiment for solving (Problem 3) will be described below.

In the conventional memory cell array, reading,
When the word line which is the row decoder 3 is selected at the time of writing, all the memory cells arranged at the intersection of the selected word line and the bit line are selected. Therefore, it is not possible to select one of the memory cells connected to the adjacent bit lines and deselect the other.

As described in the above (Embodiment 1) and (Embodiment 2), according to the present invention, the source side select MOS transistor and the drain side select MO transistor of the NAND block are selected.
Selecting one of adjacent bit lines and deselecting the other bit line by changing the threshold value of the S transistor and further changing the voltage applied to the source side select gate and the drain side select gate. You can as a result,
By omitting the precharge to the bit line at the time of reading and writing, the precharge time can be shortened and the power consumption can be reduced.

Therefore, in the present embodiment (embodiment 3), an embodiment will be described in which the precharge time at the time of reading is shortened and the power consumption is reduced. An example of shortening the precharge time at the time of writing and reducing the power consumption will be described in the next embodiment (Embodiment 4).

FIG. 32 is a block diagram showing the structure of a NAND cell type EEPROM according to this embodiment. Reference numeral 1 in the drawing denotes a memory cell array as a memory means, which is divided into two parts 1A and 1B because it is an open bit line system. In this embodiment, one page has 256 bits. Reference numeral 2 is a sense amplifier circuit as a latch means for writing and reading data. 3 is a row decoder for selecting a word line, 4 is a column decoder for selecting a bit line, 5 is an address buffer, 6 is an I / O sense amplifier,
Reference numeral 7 is a data input / output buffer, and 8 is a substrate potential control circuit.

The memory cell array 1A is similar to FIG. 28, and the memory cell array 1B is similar to FIG. However, the sense amplifier SA1 connected to the bit lines BLjA, BLjB (j = 0, 1, ..., 127) of FIG. 28 arranged in the memory cell arrays 1A and 1B is not FIG. 22 but FIG. Similarly, the bit lines BLjA and BLjB (j = 128, 12) shown in FIG. 29 arranged in the memory cell arrays 1A and 1B.
9, ..., 255) is connected to the sense amplifier SA2 shown in FIG.
34, not 3. In the sense amplifiers SA1 and SA2 shown in FIGS. 33 and 34, a transistor is added to the sense amplifiers SA1 and SA2 shown in FIGS. 22 and 23 to equalize (make the same potential) between the bit lines BLjA and BLjB by the control signals φEQ1 and φEQ2. Has been done.

At the time of reading, every other bit line is kept at the reference potential in order to reduce noise caused by capacitive coupling between bit lines (bit line shield). In this case, the write operation is first performed, for example, on the bit line BLjA (j = 0, 1, ..., 1
27), and then write to the cell connected to the bit line BLjA (j = 128, 129, ..., 255). Here, the bit line B
The data (the data of the first page) written in LjA (j = 0, 1, ..., 127) is first read, and then the bit line BL
This embodiment will be described by taking as an example the case of reading the data (the data of the second page) written in jA (j = 128, 129, ..., 255).

Bit line BLjA (j = 0, 1, ..., 12)
When the data of 7) is read, the shielded bit line BLjA (j = 128, 129, ..., 255) is kept at the reference potential (for example, 1.5 V). In the conventional memory cell array, adjacent bit lines are selected and discharged at the same time, so that the shielded bit line can generate only 0V. The timing chart of FIG. 35 is divided into the case of reading the data of the first page to the bit line, the case of sensing the data read to the bit line by the sense amplifier, and the case of reading the data of the second page to the bit line. Will be explained.

<When Reading Data of First Page to Bit Line> In the memory cell array of FIG. 28, the memory cell selected by the word line WL00 and connected to the bit line BLjA (j = 0, 1, ..., 127) is read. In that case, first, bit line B
LjA (j = 0, 1, ..., 127) is set to 1.7V, and bit line BLjB (j = 128, 129, ..., 255) is set to 1.5V.
Bit lines BLjA, B that are precharged to V and shielded
LjB (j = 128, 129, ..., 255) is precharged to a reference potential (for example, 1.5 V).

After precharging the bit line, control gate WL
00 is 0V, WL01 to WL07 are 3V, select gate SGS0
Is 1.5V and SGD0 is 3V. In this case, the source side selection MOS transistor of the bit line BLjA (j = 0, 1, ..., 127) is turned on, but the bit line BLjA (j
= 128,129, ..., 255) Source side selection MO
The S transistor is turned off. Therefore, the bit line BLjA
(J = 0,1, ..., 127) is discharged if the data of the memory cell selected by the word line WL00 is "1", but bit line BLjA (j = 128, 129, ..., 25).
5) does not discharge.

Bit line BLjA (j = 0, 1, ..., 12)
7) is discharged, the potential of the bit line BLjA (j = 128, 129, ..., 255) drops from the reference potential due to capacitive coupling between bit lines, but the bit line BLjA (j = 0,
, ..., 127) are discharging, for example, VA2, V
B2 is the reference potential 1.5V, control signals φPA2 and φPB2 are 3V
The bit lines BLjA, BLjB (j = 1
28, 129, ..., 255) are continuously precharged to 1.5 V, the bit lines BLjA and BLjB to be shielded
(J = 128,129, ..., 255) can be maintained at the reference potential.

Bit line BLjA (j = 0, 1, ..., 12)
After the cell data is read in 7), the control signal φPA2,
φPB2 becomes 0V, and bit line BLjB (j = 0, 1,
, 127), and bit lines BLjA, BLjB (j = 12)
, 129, ..., 255) become floating.

At the time of reading cell data to the bit line, the shielded bit lines BLjA, BLjB (j = 12)
, 129, ..., 255) may be equalized by setting the control signal .phi.EQ2 to 3V, or the shielded bit lines BLjA and BLjB (j = 128,129, ..., 255).
255) may be independently precharged to the reference potential of 1.5 V without being connected (without equalization).

<When amplifying and sensing the data of the first page read to the bit line> Reflecting the data of the memory cell selected by the word line WL00, the bit line BL
After the potential of jA (j = 0, 1, ..., 127) is determined, the potential of the bit line is differentially sensed in the same manner as described in (Example 2). At that time, the shielded bit lines BLjA, BLjB (j = 128, 129, ..., 255)
Is a floating state, but the control signal φEQ2 is 3V
Are equalized by keeping the same potential (1.5
V). By sensing differentially,
If the cell data read to the bit line BLjA (j = 0, 1, ..., 127) is “0”, the bit line BLjA becomes 3V, and the bit line BLjB (j = 0, 1, ..., 127) becomes 0V.
become.

Therefore, as shown in FIG. 36 (a), the bit line BLjA (j = 128, 12) shielded by the sense.
, ..., 255) are connected to the bit lines BLjA (j = 0, 1,
, 127), the potential rises from the reference potential by δ. On the other hand, the shielded bit line BLjB
(J = 128,129, ..., 255) is the bit line BL
-δ due to capacitive coupling with jB (j = 0, 1, ..., 127)
Only the potential drops from the reference potential. However, the shielded bit lines BLjA, BLjB (j = 128, 129, ..., 2)
55) is equalized, the bit line capacitive coupling noise δ applied to the bit line BLjA and the bit line capacitive coupling noise −δ applied to the bit line BLjB cancel each other, and as a result, the shielded bit lines BLjA and BLjB (j = 12
, 129, ..., 255) are kept at the reference potential of 1.5V.

Bit line BLjA (j = 0, 1, ..., 12)
Similarly, when the data read in 7) is "1", as shown in FIG. 36B, the bit line BLjA (j = 0,
1, ..., 127), BLjB (j = 0, 1, ..., 127)
By connecting (equalizing) the spaces, the shielded bit line can maintain the reference potential.

<When Reading Data of Second Page> As described above, the bit lines BLjA (j = 0, 1, ...,
After reading the data of the memory cell connected to (127), the bit lines BLjA and BLjB (j = 128, 129,
..., 255) has already been precharged to 1.5V. In addition, the bit line BLjA (j =
0, 1, ..., 127) and bit line BLjB (j = 0,
1, ..., 127), one is at 0V and the other is at 3V after the sensing operation, so that next bit line BLjA (j = 12)
, 129, ..., 255), if φEQ1 is set to 3V (φE1 may be 3V), bit lines BLjA and BLjB (j = 0) that shield without precharging , 1, ..., 127) can be set to a reference potential of 1.5V.

Therefore, the bit line BLjA (j = 0, 1,
, 127), the data of the memory cell connected to the bit line BLjA (j = 128, 12) is read.
9, ..., 255), when reading the data of the memory cell connected to the memory cell, the second precharge is performed only by changing the read bit line BLjA (128, 129, ..., 255) from 1.5V to 1.7V. Good.

When reading is performed using the bit line shield as described above, the bit line to be shielded can be set to a reference potential other than 0 V by applying the memory cell array and the sense amplifier of the present invention. As a result, pre-charge can be shortened when reading data over a plurality of pages, the reading speed can be increased, and power consumption can be reduced.

Although the bit lines BLjA and BLjB are equalized by the control signals φEQ1 and φEQ2 in this embodiment, they may be equalized by the control signals φE1 and φE2. In FIGS. 33 and 34, the node connecting the sources and drains of the two transistors selected by the control signal φE1 (φE2) is fixed at Vcc / 2 potential (for example, 1.5 V). When reading the cell data to the bit line,
3 and FIG. 34 may be used as they are, but when sensing the bit line, the bit line to be shielded is floated, so the terminal connected to this node must be in the floating state.

In this embodiment, bit line BLjA (j = 0,
1, ..., 127) and then read the data of the memory cell connected to the bit line BLjA (j = 128,129,
, 255), the case where the data of the memory cell connected to the memory cell is read is taken as an example, but the read bit line has arbitrariness. Any bit line may be used as long as the bit line connected to the sense amplifier SA2 is read after the bit line connected to the sense amplifier SA1 is read. In addition, after reading the bit line connected to the sense amplifier SA2,
The bit line connected to the sense amplifier SA1 may be read.

The present invention is also effective in a so-called shared sense amplifier system in which a plurality of bit lines are shared by one sense amplifier. A memory cell array when this shared sense amplifier system is adopted is shown in FIGS. 37 and 38. FIG. 39 is a diagram showing a specific configuration of the sense amplifier SA3. After reading the data of the memory cell connected to the bit line BLjA (j = 0, 1, ..., 127) and selected by the word line WL00, the bit line BLjA (j = 128, 129 ,.
FIG. 40 is a timing chart in the case of reading the data of the memory cell selected by the word line WL00 connected to 255). The read operation is almost the same as that of the above-described embodiment having one sense amplifier for each bit line.

The present invention can be applied not only to the memory cell array having the open bit line arrangement. For example, a single end type memory cell arrangement as shown in FIG. 31 having an inverter type sense amplifier as shown in FIG. 30 may be used. Figure 31
The memory cell array connected to the bit line BLj with is shown in FIG.
A memory cell array connected to eight bit lines BLjA may be used.

Further, in this embodiment, after the cell data is read to the bit line, the two bit lines to be shielded are connected (equalized) when the potential of the read bit line is sensed. It was kept at the reference potential. When the potential of the bit line is sensed, the two shielded bit lines may not be equalized and may be left connected to the terminal for applying the reference potential. For example, when the bit line connected to the sense amplifier of FIG. 23 or 33 is shielded (maintained at the reference potential), φPA1 and φPB1 are set to 3V, TG1 and TG2 are set.
Is maintained at 0V, and VA1 and VB1 are maintained at the reference potential (for example, 1.5V).

(Example 4) Continuing from (Example 3),
An example for solving (Problem 3) will be described below.

NAND cell type EEPR according to this embodiment
A block diagram showing the configuration of the OM is FIG. 32 as in the case of the third embodiment. The memory cell array is similar to that of the third embodiment. That is, the memory cell array 1A is similar to FIG.
The memory cell array 1B is similar to that shown in FIG. However, in the memory cell arrays 1A and 1B, bit lines BLjA and BLjB
(J = 0, 1, ..., 127) connected to sense amplifier S
A1 may be either FIG. 22 or FIG. 33. Similarly, in the memory cell arrays 1A and 1B, bit lines BLjA and BLjB (j = 12
, 129, ..., 255) connected to the sense amplifier SA
2 may be either FIG. 23 or FIG. 34.

When a bit line shield method is used in which every other bit line is kept at the reference potential at the time of reading in order to reduce capacitive coupling between bit lines, the write operation is performed, for example, on the bit line as described in (Example 3). BLjA (j = 0, 1,
, 127) and then write to the cells connected to the bit line BLjA (j = 128, 129, ..., 255). In the write operation, first, write is performed, and then verify read is performed to check whether the write is sufficiently performed. Then, the additional writing is not performed on the sufficiently written cells, and the additional writing is performed only on the insufficiently written cells. Here, the bit lines BLjA (j = 0, 1, ..., 1) of the memory cell array 1A of FIG.
This embodiment will be described by taking as an example the case where the memory cell selected by the word line WL00 is connected to the memory cell 27).

FIG. 41 shows the write / write verify read operation except the data load operation of the write data from the data input / output buffer 7 to the sense amplifier 2. Prior to writing, all the control gates of the memory cell array are set to 0V, and the p-substrate (or p-type well and n-substrate) on which the memory cells are formed are collectively erased as a high voltage Vpp (about 20V). The write data is transferred from the data input / output buffer 7 to the input / output lines I / O and I / O.
After being latched by the CMOS flip-flop FF via O ′, first, the control signals φPA1, φPA2, φPB1, φPB2
Becomes 3V and all bit lines are reset.

After that, the bit line BLjA (j = 0, 1,
, 127) and the transfer gate control signals TGA1, VSW that connect the sense amplifier to the intermediate potential (about 10 V), the bit line BLjA (j = 0, 1, ..., 127) is set to "1" according to the data. Sometimes it becomes an intermediate potential, and when it is "0", it becomes 0V. Bit line BLjA (j = 128, 129,
.., 255) is not written, the terminal VA2 is charged to an intermediate potential. Then, when the word line WL00 is selected by the row decoder 3, WL00 is Vpp, W
L01 to WL07 and SGD0 become an intermediate potential, and SGS0 becomes 0V.

After the control gate and the select gate are reset to 0V after a fixed time (up to 20 μs), the transfer gate control signal TGA1 becomes 0V and the bit line BLjA
The sense amplifier is disconnected from (j = 0, 1, ..., 127). After that, the control signal φPA1 becomes 3V, and the bit lines BLjA (j = 0, 1, ..., 127) are reset to 0V. VSW also becomes 3V. During this time, the bit line BL
jA (j = 128, 129, ..., 255) remains precharged to the intermediate potential.

Next, the verify read operation is performed. First, φPA1 and φPB1 are set to 3V, and the bit line BLjA (j
= 0, 1, ..., 127) to 1.7V, and the bit line BLjB
(J = 0, 1, ..., 127) is charged to 1.5V, then φPA1 and φPB1 become 0V, and bit lines BLjA, B
LjB (j = 0, 1, ..., 127) is in a floating state. Next, for example, 0.5V is applied to the control gate WL00, the word lines WL01 to WL07 are 3V, and the selection gate SG
S0 is 1.5V and SGD0 is 3V. In normal read, if the threshold value of the memory cell is 0 V or more, it is read as "0", but in verify read, it is not read as "0" unless it is 0.5 V or more.

After the bit line discharge, the verify signal φAV becomes 3
V, and the bit line BLjA (j = 0, 1, ..., 127)
Is written to "1", the battery is charged to near 3V. Here, the voltage level of the precharge performed by the verify signal is the bit line BLjB (j = 0, 1, ...,
The precharge voltage of 127) may be 1.5 V or more. After that, the equalize signal φE becomes 3V, and the sense amplifier is reset. Then, the transfer gate control signals TGA1 and TGB1 become 3V, and the bit line BL
The data of jA (j = 0, 1, ..., 127) is read. The read data is latched in the sense amplifier,
It becomes the data for the next rewrite.

During verify read, bit line BLjA
(J = 128, 129, ..., 255) is not discharged and maintains an intermediate potential, so that bit line BLjA (j = 0, 1, ..., 1)
In the verify read of 27), it becomes a shield line to reduce bit line coupling capacitance noise.

Bit line BLjA (j = 0, 1, ..., 12)
When rewriting 7), the bit line BLjA (j = 12
, 129, ..., 255) are already precharged to the intermediate potential, there is no need to recharge them, and the charging time can be omitted. Further, since the booster circuit for charging the intermediate potential consumes a large amount of power when starting boosting, according to the present embodiment, the power consumption during writing can be reduced.

In this embodiment, at the time of verify read, the unselected bit lines BLjA (j = 128, 129, ..., 255) are continuously charged to the intermediate potential. For example, by setting φPA2 to 0V, the unselected bit lines BLjA are set to 0V. May be in a floating state at an intermediate potential.

This embodiment is also effective in a so-called shared sense amplifier system in which a plurality of bit lines are shared by one sense amplifier. 37 and 38 show memory cell arrays when the shared sense amplifier system is adopted. A block diagram showing the configuration of the NAND cell type EEPROM when the shared sense amplifier system is adopted is also FIG. 32 similarly to (Example 3). FIG. 39 shows the sense amplifier SA3 when the shared sense amplifier system is adopted. The timing diagram when the shared sense amplifier method is adopted is almost the same as that in FIG.

The present invention can be applied not only to the memory cell array having the open bit line arrangement. For example, a single end type memory cell arrangement as shown in FIG. 31 having an inverter type sense amplifier as shown in FIG. 30 may be used. Figure 31
The memory cell array connected to the bit line BLj with is shown in FIG.
A memory cell array connected to eight bit lines BLjA may be used.

The present invention can also be applied to the folded bit line system as shown in FIG. One of the two bit lines connected to the sense amplifier (for example, BL in FIG. 42)
0) while writing to the memory cell connected to
The other bit line BL1 has a transfer gate control signal T
G2 is set to 0V and an intermediate potential (about 10V) from the terminal VB
Just keep charging. Bit line B that has been written
Since the bit line BL1 is kept at the intermediate potential during the verify read of the memory cell connected to L0, the verify read of the memory cell connected to the bit line BL0 cannot be performed differentially.

However, for example, normal reading is differentially performed by the folded bit line method as described in (Embodiment 1), and at the time of verify reading, as described in the section of [Prior Art], single end is performed. Type, that is, one of the two inverters forming the flip-flop of the sense amplifier is made inactive, and the read data is determined by whether the potential of the bit line is larger than the circuit threshold value of the inverter as shown in FIG. It may be determined whether it is “0” or “1”.

(Embodiment 5) In this embodiment, in one block selected by the row decoder 3 at the time of verify-read for writing and at the time of normal reading, half of the memory cell units are connected to the selection MOS transistors on the drain side. When SGD0 is applied and SGS0 is applied to the source-side selection MOS transistor, SGS0 is applied to the drain-side selection MOS transistor in the other half of the memory cell units, and SGD0 is applied to the source-side selection MOS transistor. Is applied.

As a method of applying a voltage to the select gate, for example, as shown in FIG. 43, bit lines BL0 to BL127 are used.
A signal applied to the select gate of the memory cell connected to
A signal to be applied to the select gates of the memory cells connected to the bit lines BL128 to BL255 may be separately arranged. Also,
As shown in FIG. 44, the source side select gate and the drain side select gate may be interchanged in the middle of the memory cell array.

43 and 44, for example, when reading a memory cell selected by the word line WL00, the select gate SGS0 is 3V and the SGD0 is 1.5V.
Then, the memory cell connected to the bit line BLj (j; even number) is read. In this case, of the unselected bit lines BLj (j; odd number) that are not read, the unselected bit line B
For Lj (j = 1, 3, 5, ..., 125, 127), the selection MOS transistor on the source side is turned off, and the unselected bit line BLj (j = 129, 131, 133, ..., 253, 2).
In 55), the selection MOS transistor on the drain side is turned off. That is, half of the unselected bit lines are stopped by the drain-side selection MOS transistors being turned off, and the remaining half of the unselected bit lines are turned off by the source-side selection MOS transistors. Discharge is stopped.

On the other hand, in FIG. 43 and FIG. 44, the bit line BLj
When reading a memory cell connected to (j; odd number), the select gate SGS0 may be set to 1.5V and the SGD0 may be set to 3V. In this case, among the unselected bit lines BLj (j; even number) that are not read, the unselected bit lines BLj (j
= 0, 2, 4, ..., 124, 126), the selection MOS transistor on the drain side is turned off and the non-selected bit line BLj
(J = 128, 130, 132, ..., 252, 254)
The source-side selection MOS transistor is turned off. That is, half of the unselected bit lines are stopped by the drain-side selection MOS transistors being turned off, and the remaining half of the unselected bit lines are turned off by the source-side selection MOS transistors. Discharge is stopped.

In this way, at the time of reading, half of the unselected bit lines are selected MO on the drain side regardless of whether the odd-numbered bit lines or the even-numbered bit lines are read.
Discharge of the bit line is stopped by turning off the S transistor, and discharge of the bit line is stopped by turning off the select MOS transistors on the source side of the remaining half of the unselected bit lines. Therefore, even when reading the odd-numbered bit lines and the even-numbered bit lines,
The capacitances of the entire unselected bit lines are the same, and the bit lines BL
Also when reading j (j; odd number), the bit line BLj (j;
Even when reading (even number), the precharge time and the read time can be the same.

Although the case of reading has been described here, even in the case of verify reading after writing, the capacitance of the entire bit line is the same when reading the odd-numbered bit lines and when reading the even-numbered bit lines.

Although the folded bit line system is taken as an example in FIGS. 43 and 44, (Example 1) to
The open bit line system described in (Embodiment 4) or the single end system may be used. Also, a so-called shared sense amplifier system in which one sense amplifier shares a plurality of bit lines may be used.

(Sixth Embodiment) Next, another embodiment will be described. This embodiment is basically the same as the first embodiment, and the difference from the first embodiment is that the type of the selection MOS transistor is changed.

FIG. 45 is a diagram showing the structure of the memory cell array in this embodiment. The difference from FIG. 2 is that a part of the I-type selection MOS transistor is of D-type.

In FIG. 45, the high threshold value Vt1 (for example, 2
V-type selection MOS transistor is E-type, and has low threshold values Vt2, Vt3 (for example, 0.5V, -1V) (Vt1>
Select MOS transistor with Vt2> Vt3) is I-type
, D-type. The voltage applied to the select gate is the voltage Vsgh (for example, 3V) (Vsg) at which all I-type transistors, D-type and E-type transistors are turned on.
h> Vt1, Vt2, Vt3), and the voltage Vsg at which the I-type transistor turns on but the E-type transistor turns off.
l1 (for example, 1.5 V) (Vt1>Vsgl1> Vt2), and D
-type transistor turns on, but E-type transistor turns off Voltage Vsgl2 (for example, 0V) (Vt1> Vsgl2
> Vt3).

A method of applying the voltage of the select gate will be specifically described with reference to FIG. For example, memory cell MC000
When reading the data of, the word lines WL00, WL08
˜WL15 is set to 0V, and word lines WL01 to WL07 are set to Vcc (for example, 3V). Then, the source side select gate SGS
0 is Vsgh, the drain side selection gate SGD0 is Vsgl1
To SGS1 and SGD1 are set to 0V. in this case,
Source side selection MOS transistors STS00, STS10
Turn on together. On the other hand, the selection MOS transistor STD00 on the drain side of the bit line BL0 turns on, but the selection MOS transistor ST on the drain side of the bit line / BL0.
Since D10 is turned off, the bit line BL0 is discharged, but the bit line / BL0 is not discharged.

On the other hand, when reading the data from the memory cell MC100, the word lines WL00 and WL08 to WL15 are set to 0 V and the word lines WL01 to WL07 are set to Vcc, as in the case of reading the memory cell MC000. Source side selection gate S
GS0 is Vsgl2, select gate on the drain side SGD0 is Vsgl2
sgh SGS1 and SGD1 are set to 0V. In this case, the drain side selection MOS transistors STD00, S
TD10 turns on together. Since the selection MOS transistor STS10 on the source side is turned on, the bit line / BL0 is discharged, but since the selection MOS transistor STS00 is turned off, the bit line BL0 is not discharged.

The present invention is a selection MOS transistor connected to the bit line pair BLj, / BLj, and has the same selection gate S.
Select MOS transistors controlled by GS and SGD (for example, STD00 and STD10, STS00 and S in FIG. 45).
The thresholds of TS10, STD01 and STD11, STS01 and STS11) may be made different, and the method of setting the thresholds is arbitrary. In FIG. 45, all the selection MOS transistors on the drain side of the cells connected to the bit line BLj are I-t.
With ype, the selection MOS transistor on the source side is E-type
However, for example, two NAs sharing a bit line contact
In the ND block, one of the drain side selection MOS transistors may be I-type and the other may be E-type.

According to the present invention, among the selection MOS transistors which share one selection gate, it is possible to produce conductive MOS transistors and non-conductive MOS transistors, and prepare two such select gates. This makes it possible to easily realize a memory cell in a selected state and a memory cell in a non-selected state within a memory cell having the same selection gate.

As shown in FIG. 46, the selection MOS transistor connected to the drain side may be E-type or D-type, and the selection MOS transistor connected to the source side may be E-type or I-type. In this case, when the memory cell (eg MC000) in the memory cell unit 2 is selected, SGS0 is Vsgh (3V) and SGD0 is Vsgh.
Sgl2 (for example, 0V), SGD1, and SGS1 may be set to 0V. When selecting a memory cell in the memory cell unit 1 (eg MC100), SGS0 is Vsgl1 (eg 1.5V), SGD0 is Vsgh (eg 3V), S
It is sufficient to set GS1 and SGD1 to 0V.

If Vsgh is made larger than Vcc, selection M
Since the conductance of the OS transistor increases (that is, the resistance decreases), and the current flowing through the NAND cell string increases during reading, the bit line discharge time is shortened, and as a result, read and write verify read is speeded up. It Vsgh may be boosted from Vcc by a booster circuit in the chip, for example.

Also, an I-type selection MOS transistor and D
The thresholds of the -type selection MOS transistors may both be negative thresholds (for example, -1V and -2V).

The larger value Vt1 of the thresholds of the select gate may be set to a voltage higher than the power supply voltage Vcc (for example, 3.5V). In this case, in order to turn on the selection MOS transistor having the threshold value of Vt1 at the time of reading or verify reading, for example, 4V may be applied to the selection gate by using the booster circuit inside the chip.

Here, referring to the timing chart of FIG. 47, the memory cell MC connected to the bit line BL1 of FIG.
The operation for reading 000 will be described. The sense amplifier is formed of a CMOS flip-flop controlled by control signals SAN and SAP.

First, the control signals φA and φB become Vss, and the CMOS flip-flop FF and the bit lines BL0 and BL.
1 is disconnected. Then, precharge signals φpA and φ
pB changes from Vss to Vcc (time t0), and bit line BL1
Is VB (for example, 1.7V), the dummy bit line BL0 is V
Precharged to A (for example, 1.5 V) (time t1
). When the precharge is completed, φpA and φpB become Vss, and the bit lines BL0 and BL1 are brought into a floating state. Thereafter, a desired voltage is applied from the row decoder 3 to the control gate (word line) and the control gate (time t2).
).

When reading the memory cell MC000 of FIG. 48, WL00 is 0 V, WL01 to WL07 are 3 V, and SGD is
0 becomes 3V and SGS0 becomes 1.5V. Memory cell MC
When the data written in 000 is "0", the threshold value of the memory cell MC000 is positive, so that no cell current flows and the potential of the bit line BL1 remains 1.7V. When the data is "1", the cell current flows and the potential of the bit line BL1 drops to 1.5 V or less. In addition, the selection gate S
Since GS0 is 1.5V, select gate transistor ST
S10 is turned off, the bit line BL0 is not discharged regardless of the data written in the memory cell MC100, and is kept at the precharge potential of 1.5V.

Thereafter, at time t3, SAP is 3V, SAN
Becomes 0V, the CMOS flip-flop FF is inactivated, and φE becomes 3V at time t4, so that CMO
S flip-flop FF is equalized and node N1
, N2 becomes Vcc / 2 (for example, 1.5 V). Time t5
After φA and φB become 3V and the bit line and the sense amplifier are connected (time t6), SAN becomes 0V to 3V and the potential difference between the bit lines BL0 and BL1 is amplified. After that, at time t7, SAP changes from 3V to 0V and the data is latched. That is, if "0" is written in the memory cell MC000, the node N1 becomes 3V, node N2 becomes 0V, and if "1" is written in MC000,
The node N1 becomes 0V and the node N2 becomes 3V. afterwards,
When the column selection signal CSL1 changes from 0V to 3V, CM
The data latched in the OS flip-flop is I /
It is output to O and I / O '(time t8).

The read operation timing is arbitrary. For example, at time t5, the transfer gate connecting the bit line and the sense amplifier is turned on to turn on the bit lines BL1, B.
The transfer gate may be turned off after the potential of L2 is transferred to the nodes N1 and N2. Therefore, since the load capacitance of the sense amplifier is reduced by disconnecting the bit line pair from the sense amplifier, the potentials of the nodes N1 and N2 are rapidly determined at the time of sensing and data latching.

In the sense operation of the sense amplifier, SAN is first changed from 0V to 3V to turn on the N-channel transistor of the CMOS flip-flop FF, and then,
When SAP is changed from 3V to 0V and the P-channel transistor of the CMOS flip-flop FF is turned on.
SAP may be changed from 3V to 0V at the same time as AN is changed from 0V to 3V.

Further, in the above embodiment, while discharging the bit line to which the memory cell to be read is connected, the other dummy bit line of the bit line pair connected to the sense amplifier (for example, the memory cell of FIG. 48). The bit line BL0 is in the floating state when reading MC000, and the bit line BL1 is in the floating state when reading the memory cell MC100. However, even while the bit line BL1 is precharged and the data of the memory cell MC000 is read out thereafter,
By keeping the precharge control signal .phi.pA at 3V, the dummy bit line BL0 serving as the reference can be fixed at the reference potential of 1.5V.

By keeping the dummy bit line at the reference potential in this way, noise caused by capacitive coupling between adjacent bit lines at the time of discharging the bit line can be reduced. In addition, as in the case of the above-mentioned read, during the verify read after writing, the bit line charges and discharges according to the data written in the cell, but if the dummy bit line that is not read is kept at the reference potential, it will be caused by capacitive coupling between bit lines. The noise generated can be reduced.

<Write> The write operation of this embodiment, for example, the write procedure when writing to the memory cell MC000 of FIG. 48 will be described below.

Select gate SGD0, control gates WL01 ...
WL07 is the intermediate potential Vm (about 10V), WL00 is Vpp
(About 20V), and bit line BL0 from VA to Vm8
Charge to about 8V. "1" in memory cell MC000
When writing
When writing "0" to m8, set 0V to bit line BL1.
Apply to. Then, the memory cell MC that is not written
Memory cell MC for writing 100 and "1"
No electrons are injected into the floating gate of 000, and electrons are injected from the channel into the floating gate of the memory cell MC000 in which "0" is written.

After the writing is completed, the control gate, the selection gate and the bit line are sequentially discharged to complete the writing operation.

MC00 of the memory cell array as shown in FIG.
When writing to 0, select gate SGS0 is set to D
A voltage (for example, -3V) at which the -type selection MOS transistor STS10 is turned off may be applied.

After the writing is completed, a write verify operation is performed to check whether the writing is sufficient.

First, .phi.A and .phi.B are set to Vcc, the precharge signals .phi.pB and .phi.pA are set to Vcc, the bit line BL1 is set to 1.7 V, and the (dummy) bit line BL0 is set to 1.5 V, for example.
Will be precharged.

When precharging ends, φpA and φpB are Vss.
Then, the bit lines BL1 and BL0 are in a floating state. After that, a desired voltage is applied from the row decoder 3 to the selection gate and the control gate. The control gate WL00 becomes a verify voltage (for example, 0.5V), WL01 to WL07 become Vcc (for example, 3V), SGS0 becomes 1.5V, and SGD0 becomes 3V. When "0" is sufficiently written in the memory cell MC000, the threshold voltage of the memory cell is positive, so that no cell current flows and the potential of the bit line BL1 remains 1.7V. When "1" write or "0" write is insufficient, a cell current flows and the potential of the bit line BL1 drops,
It becomes 1.5V or less. During this period, the dummy bit line BL0 is
It may be floating or may be fixed at 1.5 V by setting φpA to Vcc. If the dummy bit line is kept at a constant voltage, the bit line capacitive coupling noise during bit line discharge can be significantly reduced.

After the bit line discharge, the verify signal φBV becomes 3
When the data becomes V and the data written in the memory cell MC000 is "1", the bit line BL1 is charged to near 3V. Here, the voltage level of the charging performed by the verify signal may be 1.5 V or more of the precharge voltage of the dummy bit line BL0.

After that, SAP becomes 3V and SAN becomes 0V, the CMOS flip-flop FF is inactivated, and φ
CMOS flip-flop F when E becomes 3V
F is equalized and the nodes N1 and N2 become Vcc / 2 (for example, 1.5 V). After that, φA and φB become 3V, the bit line and the sense amplifier are connected, SAN becomes 0V to 3V, SAP becomes 3V to 0V, the potential difference between the bit line BL1 and the dummy bit line BL0 is amplified, and The write data is latched in the sense amplifier.

As described above, according to this embodiment, the selection MOS
By changing the threshold voltage of the transistor and the voltage applied to the select gate, the folded bit line system can be realized without increasing the chip area, and high-speed random read is possible, as in the first embodiment. Become. As the method of changing the threshold value, various methods described in the first embodiment can be adopted.

[0207]

As described above, in the nonvolatile semiconductor memory device according to the present invention, the folded bit line system can be realized without increasing the chip area, and as a result, high speed random read can be performed. Further, according to the present invention, it is possible to perform the page read operation at high speed without increasing the chip area, eliminating the dead time generated when switching the word lines. Further, according to the present invention, there is a problem that occurs when the bit line shield is applied to the open bit line system and the single end system using the conventional cell array, that is, the increase in power consumption when reading and writing data over a plurality of pages, It is possible to reduce the increase in reading and writing time.

[Brief description of drawings]

FIG. 1 is a NAND cell type EEPR according to a first embodiment.
The figure which shows the whole structure of OM.

FIG. 2 is a diagram showing a configuration of a memory cell array in the first embodiment.

FIG. 3 is a diagram showing a configuration of a memory cell array in the first embodiment.

FIG. 4 is a diagram showing a configuration of a memory cell array in the first embodiment.

FIG. 5 is a diagram showing a configuration of a memory cell array in the first embodiment.

FIG. 6 is a diagram showing a configuration of a memory cell array and a sense amplifier circuit of the first embodiment.

FIG. 7 is a diagram showing a configuration of a memory cell array and a sense amplifier circuit of the first embodiment.

FIG. 8 is a timing chart for explaining a data read operation in the first embodiment.

FIG. 9 is a timing chart for explaining a data read operation in the first embodiment.

FIG. 10 is a timing chart for explaining a data read operation in the first embodiment.

FIG. 11 is a diagram showing a configuration of a memory cell array and a sense amplifier circuit of the first embodiment.

FIG. 12 is a diagram showing a configuration of a memory cell array and a sense amplifier circuit of the first embodiment.

FIG. 13 is a diagram showing a configuration of a twisted bit line system.

FIG. 14 is a diagram showing a configuration of a twisted bit line system.

FIG. 15 is a diagram showing a configuration of a memory cell array in which a selection MOS transistor has a selection gate and a floating gate.

FIG. 16 is a diagram showing a configuration of a memory cell array in the first embodiment.

FIG. 17 is a NAND cell type EEP according to the second embodiment.
The figure which shows the whole structure of ROM.

FIG. 18 is a diagram showing a configuration of a memory cell array in the second embodiment.

FIG. 19 is a diagram showing a configuration of a memory cell array in the second embodiment.

FIG. 20 is a diagram showing a configuration of a memory cell array in the second embodiment.

FIG. 21 is a diagram showing a configuration of a memory cell array in the second embodiment.

FIG. 22 is a diagram showing the configuration of a sense amplifier circuit in the second embodiment.

FIG. 23 is a diagram showing a configuration of a sense amplifier circuit according to a second embodiment.

FIG. 24 is a timing chart for explaining a data read operation in the second embodiment.

FIG. 25 is a timing chart for explaining a data read operation in the second embodiment.

FIG. 26 is a timing chart for explaining a data read operation in the second embodiment.

FIG. 27 is a timing chart for explaining a data read operation in the second embodiment.

FIG. 28 is a diagram showing a configuration of a memory cell array in the second embodiment.

FIG. 29 is a diagram showing a configuration of a memory cell array in the second embodiment.

FIG. 30 is a diagram showing a configuration of an inverter type sense amplifier circuit.

FIG. 31 is a diagram showing a configuration of a single-end type memory cell array and a sense amplifier.

FIG. 32 is a NAND cell type EEP according to the third embodiment.
The figure which shows the whole structure of ROM.

FIG. 33 is a diagram showing the configuration of a sense amplifier circuit in the third embodiment.

FIG. 34 is a diagram showing the configuration of a sense amplifier circuit in the third embodiment.

FIG. 35 is a timing chart for explaining a data read operation in the third embodiment.

FIG. 36 is a diagram showing the influence of noise on an adjacent bit line due to capacitive coupling between bit lines when the bit line potential is amplified.

FIG. 37 is a diagram showing a configuration of a shared sense amplifier type memory cell array.

FIG. 38 is a diagram showing a configuration of a shared sense amplifier type memory cell array.

FIG. 39 is a diagram showing a configuration of a shared sense amplifier type sense amplifier circuit.

FIG. 40 is a timing chart for explaining a data read operation according to the third embodiment.

FIG. 41 is a timing chart for explaining a data write operation in the fourth embodiment.

FIG. 42 is a diagram showing a configuration of a folded bit line system sense amplifier circuit in the fourth embodiment.

FIG. 43 is a diagram showing the configuration of a memory cell array in the fifth embodiment.

FIG. 44 is a diagram showing the configuration of a memory cell array in the fifth embodiment.

FIG. 45 is a diagram showing the configuration of a memory cell array in the sixth embodiment.

FIG. 46 is a diagram showing the configuration of a memory cell array in the sixth embodiment.

FIG. 47 is a timing chart for explaining a data read operation according to the sixth embodiment.

FIG. 48 is a diagram showing a configuration of a memory cell array and a sense amplifier circuit of a sixth embodiment.

[Explanation of symbols]

1, 1A, 1B, 1A1, 1A2, 1B1, 1B2 ... Memory cell array 2, 2A, 2B ... Sense amplifier / latch circuit 3, 3A, 3B ... Row decoder 4 ... Column decoder 5 ... Address buffer 6 ... I / O sense amplifier 7 ... Data input / output buffer 8 ... Substrate potential control circuit BL ... Bit line WL ... Word line STD ... First selection MOS transistor STS ... Second selection MOS transistor SGD ... First selection gate SGS ... Second selection gate

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI Technical indication H01L 21/8247 29/788 29/792 H01L 29/78 371

Claims (22)

[Claims] 1. A non-volatile memory section composed of one or a plurality of non-volatile memory cells, a first selection MOS transistor for electrically connecting the non-volatile memory section to a first common signal line, and the non-volatile section. Memory cell unit composed of a second selection MOS transistor, which electrically connects the first memory cell section and the second common signal line and has a threshold value different from that of the first selection MOS transistor, is arranged in a matrix. A nonvolatile semiconductor memory device having a memory cell array. 2. A non-volatile memory section composed of one or a plurality of non-volatile memory cells, a first selection MOS transistor for electrically connecting the non-volatile memory section to a bit line, and the non-volatile memory section. A memory cell array in which memory cell units each of which has a source line conductive and a second selection MOS transistor having a threshold value different from that of the first selection MOS transistor are arranged in a matrix. Nonvolatile semiconductor memory device. 3. A non-volatile memory section comprising one or a plurality of non-volatile memory cells, a first selection MOS transistor for electrically connecting the non-volatile memory section to a bit line, and the non-volatile memory section. Second to make the source line conductive
In the non-volatile semiconductor memory device having a memory cell array in which memory cell units each composed of the selection MOS transistor are arranged in a matrix, the first selection MOS transistor has a first threshold value Vth1.
And the second selection MOS transistor has a first memory cell unit having a second threshold Vth2, and the first selection MOS transistor has a third threshold Vth3,
The second selection MOS transistor has a fourth threshold value Vth4.
And a second memory cell unit having
The gate electrode of the S-transistor and the gate electrode of the second selection MOS transistor are shared as the first and second selection gates, respectively, to form a sub-array. 2. A non-volatile semiconductor memory device characterized in that the second and fourth threshold values Vth2 and Vth4 have a relationship opposite to the magnitude relationship. 4. A non-volatile memory section composed of one or a plurality of non-volatile memory cells, a first selection MOS transistor for electrically connecting the non-volatile memory section to a bit line, and the non-volatile memory section. Second to make the source line conductive
In the non-volatile semiconductor memory device having a memory cell array in which memory cell units each composed of the selection MOS transistor are arranged in a matrix, the first selection MOS transistor has a first threshold value Vth1.
And the second selection MOS transistor has a first memory cell unit having a second threshold Vth2, and the first selection MOS transistor has a third threshold Vth3,
The second selection MOS transistor has a fourth threshold value Vth4.
And a second memory cell unit having
The gate electrode of the S-transistor and the gate electrode of the second selection MOS transistor are shared as the first and second selection gates, respectively, to form a sub-array. Non-volatile semiconductor memory characterized in that the second and fourth threshold values Vth2 and Vth4 are opposite to each other in magnitude, and that the second threshold value and the third threshold value are different from each other. apparatus. 5. A non-volatile memory section composed of one or a plurality of non-volatile memory cells, a first selection MOS transistor for electrically connecting the non-volatile memory section to a bit line, and the non-volatile memory section. Second to make the source line conductive
In the non-volatile semiconductor memory device having a memory cell array in which memory cell units each composed of the selection MOS transistor are arranged in a matrix, the first selection MOS transistor has a first threshold value Vth1.
And the second selection MOS transistor has a first memory cell unit having a second threshold Vth2, and the first selection MOS transistor has a third threshold Vth3,
The second selection MOS transistor has a fourth threshold value Vth4.
And a second memory cell unit having
The gate electrode of the S-transistor and the gate electrode of the second selection MOS transistor are shared as the first and second selection gates, respectively, to form a sub-array.
Of the threshold values Vth1 and Vth3 and the magnitude relationship of the second and fourth threshold values Vth2 and Vth4 are opposite to each other. In the first and second memory cell units in the sub-array, , Randomly reading the data stored in the nonvolatile memory unit in one of the memory cell units,
A non-volatile semiconductor memory device comprising a timing means for page-reading the data stored in the non-volatile memory section in the other memory cell unit. 6. The method according to claim 3, wherein the first threshold value and the fourth threshold value are equal to each other and the second threshold value and the third threshold value are equal to each other. The nonvolatile semiconductor memory device described. 7. The non-volatile semiconductor according to claim 3, wherein the first memory cell unit and the second memory cell unit are alternately arranged to form the sub-array. Storage device. 8. When reading the non-volatile memory portion of the first memory cell unit, both the first and second selection MOS transistors of the first memory cell unit are turned on, and the second memory cell unit is turned on. One of the first and second selection MOS transistors is made non-conductive, and when the non-volatile memory portion of the second memory cell unit is read, the first and second selection MOS transistors of the first memory cell unit are read. One of them is made non-conductive,
First and second selection MOS of second memory cell unit
A first and a second select MO in the selected sub-array so as to render both transistors conductive.
6. The nonvolatile semiconductor memory device according to claim 3, further comprising means for applying a read selection gate voltage to the S transistor. 9. When reading data stored in the non-volatile memory unit in one of the first memory cell unit and the second memory cell unit in the sub-array to a bit line. 9. The non-volatile semiconductor memory device according to claim 8, wherein the bit line connected to the other memory cell unit is kept at a non-selected read bit line potential. 10. A non-selected read bit line potential is used as a reference potential, and a first bit line potential to which the first memory cell unit at the time of reading is connected and a second bit line potential to which the second memory cell unit is connected. 10. The non-volatile semiconductor memory device according to claim 9, further comprising bit line voltage detection means for differentially detecting a potential difference between the bit line potential and the bit line potential. 11. The non-volatile memory unit comprises a plurality of electrically rewritable non-volatile memory cells in which a charge storage layer and a control gate are stacked on a semiconductor layer, and adjacent ones have a source and a drain. 6. The nonvolatile semiconductor memory device according to claim 1, wherein the nonvolatile semiconductor memory devices are connected in series in a shared manner. 12. A verify operation for checking whether or not writing is sufficient in the nonvolatile memory portion in one of the first memory cell unit and the second memory cell unit in the sub-array, 6. The non-volatile memory according to claim 3, wherein the bit line connected to the other memory cell unit is kept at a constant potential during the operation or through the write, write verify, rewrite, and write verify operations. Semiconductor memory device. 13. The memory cell array comprises a first sub-memory cell array and a second sub-memory cell array, and each of these sub-memory cell arrays comprises a first and a second memory cell unit. The voltage applied to the gate of the first selection MOS transistor of the cell array is applied to the gate of the second MOS transistor of the second sub memory cell array,
6. The voltage applied to the gate of the second MOS transistor of the first sub-memory cell array is applied to the gate of the first MOS transistor of the second sub-memory cell array. The non-volatile semiconductor memory device described in 1. 14. A non-volatile memory section composed of one or a plurality of non-volatile memory cells, a first selection MOS transistor for electrically connecting the non-volatile memory section to a first common signal line, and the non-volatile section. Non-volatile semiconductor memory device having a memory cell array in which memory cell units each composed of a non-volatile memory section and a second selection MOS transistor that conducts a second common signal line are arranged in a matrix. Within a bit line group composed of a plurality of bit lines among the remaining bit lines in the memory cell array while reading or writing to a memory cell connected to one or a plurality of bit lines of so,
A semiconductor memory device having means for connecting and disconnecting bit lines. 15. The means for connecting / disconnecting between the bit lines is a MOS transistor provided between the bit lines, and the bit line group is composed of bit line pairs connected to the same sense amplifier circuit. 15. The semiconductor memory device according to claim 14, which is characterized in that. 16. An open bit line type memory cell array in which a plurality of bit lines are connected to the same sense amplifier circuit, and the sense amplifier circuit is arranged between bit lines connected to the circuit. 16. The semiconductor memory device according to claim 15, which is configured. 17. A shared sense amplifier system in which a first bit line pair and a second bit line pair share a sense amplifier in the open bit line system memory cell array,
17. When the memory cell connected to the bit line pair is read or written, there is provided means for connecting between the bit lines forming the second bit line pair.
The semiconductor memory device described. 18. The non-volatile memory section, wherein the memory cell array is composed of one or a plurality of non-volatile memory cells, and a first selection MOS for electrically connecting the non-volatile memory section to a first common signal line. A second selection M for electrically connecting the transistor, the non-volatile memory unit and the second common signal line, and having a threshold different from that of the first selection MOS transistor.
15. The non-volatile semiconductor memory device according to claim 14, wherein memory cell units composed of OS transistors are arranged in a matrix. 19. A first memory cell unit in which a first selection MOS transistor has a first threshold value Vth1 and a second selection MOS transistor has a second threshold value Vth2, and a first selection cell. A second memory cell unit in which the MOS transistor has a third threshold value Vth3 and the second selection MOS transistor has a fourth threshold value Vth4;
The gate electrode of the first selection MOS transistor and the gate electrode of the second selection MOS transistor are shared as the first and second selection gates to form a sub-array, and the first and third threshold values Vth1 and Vth3 are formed. 15. The non-volatile semiconductor memory device according to claim 14, wherein the magnitude relationship between the above and the second and fourth threshold values Vth2 and Vth4 is opposite. 20. The non-volatile semiconductor according to claim 19, wherein the first threshold value is equal to the fourth threshold value and the second threshold value is equal to the third threshold value. Storage device. 21. The non-volatile semiconductor memory device according to claim 14, wherein the first memory cell unit and the second memory cell unit are alternately arranged to form the sub-array. 22. In the sub-array, a first memory cell unit is connected to a first bit line pair and a second memory cell unit is connected to a second bit line pair. Item 19. The nonvolatile semiconductor memory device according to item 18.