JP3225024B2 - Nonvolatile semiconductor memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an electrically rewritable nonvolatile semiconductor memory device (EEPROM),
In particular, the present invention relates to an EEPROM that performs multi-value storage in which more than one bit of information is stored in one memory cell.

[0002]

2. Description of the Related Art As one type of EEPROM, a NAND cell type EEPROM capable of high integration is known. This is because a plurality of memory cells are connected in series in such a manner that their sources and drains are shared by adjacent ones, and
It is connected to a bit line as a unit. The memory cell usually has an FETMOS structure in which a floating gate (charge storage layer) and a control gate are stacked. The memory cell array is integrally formed in a p-type well formed on a p-type substrate or an n-type substrate. The drain side of the NAND cell is connected to a bit line via a selection gate, and the source side is also connected to a common source line via a selection gate. The control gates of the memory cells are arranged continuously in the row direction to form word lines.

The operation of this NAND cell type EEPROM is as follows. Data writing is performed sequentially from the memory cell located farthest from the bit line. The high voltage Vpp (= about 20 V) is applied to the control gate of the selected memory cell, and the intermediate voltage Vppm (= 1) is applied to the control gate and the selection gate of the memory cell on the bit line side from the high voltage Vpp.
0V) and apply 0V to the bit line according to the data.
Alternatively, an intermediate voltage Vm (= about 8 V) is applied.

When 0 V is applied to the bit line, the potential is transferred to the drain of the selected memory cell, and electrons are injected into the charge stack. As a result, the threshold value of the selected memory cell shifts in the positive direction. This state is, for example, “1”. When Vm is applied to the bit line, electron injection does not occur effectively, so that the threshold does not change,
Stay negative. This state is "0" in the erase state. Data writing is performed simultaneously on the memory cells sharing the control gate.

[0005] Data erasure is performed simultaneously on all memory cells in the NAND cell. That is, all control gates are set to 0V, and the p-type well is set to 20V. At this time, the selection gate, bit line and source line are also set to 20V. As a result, in all the memory cells, electrons in the charge storage layer are emitted to the p-type well, and the threshold value shifts in the negative direction.

For data reading, the control gate of the selected memory cell is set to 0 V, and the control gates and selection gates of the other memory cells are set to the power supply potential Vcc (for example, 5 V).
This is performed by detecting whether or not a current flows in the selected memory cell.

[0007] Due to the restrictions on the read operation, the threshold value after writing "1" must be controlled between 0 V and Vcc. Therefore, write verification is performed,
"1" Only memory cells with insufficient writing are detected and "1"
Rewrite data is set so that rewrite is performed only on a memory cell with insufficient write (bit-by-bit verify). A memory cell with insufficient writing of “1” is detected by setting the selected control gate to, for example, 0.5 V (verify voltage) and reading (verify read). That is, if the threshold value of the memory cell is not 0.5 V or more with a margin with respect to 0 V, a current flows in the selected memory cell, and it is detected that "1" is insufficiently written.

Since a current naturally flows in a memory cell set to the "0" write state, a circuit called a verify circuit for compensating a current flowing through the memory cell is provided so that the memory cell is not mistaken for "1" write shortage.
This verify circuit executes write verify at high speed.

By performing data writing while repeating the write operation and the write verify, the write time is optimized for each memory cell, and the threshold value after "1" write is controlled between 0 V and Vcc. .

In this NAND cell type EEPROM, for example, it is assumed that the state after writing is set to three states of "0", "1", and "2". The "0" write state has a negative threshold value, and the "1" write state has a threshold value of, for example, 0V.
(1/2) Vcc, the threshold value is "1/2" when "2" is written.
Vcc to Vcc. In the conventional verify read, a verify voltage is applied to the control gate to determine whether or not the threshold voltage of the memory cell is equal to or higher than the verify voltage by determining whether a current flows in the memory cell.
In order to judge whether or not the "2" write state has been reached, the verify voltage must be set to 0 V and (1/2) Vcc, respectively, to perform two checks, and there is a problem that it takes time to perform the verify read. .

[0011]

As described above, the conventional N
In the AND cell type EEPROM, when multi-value information is stored in a memory cell and a bit-by-bit verification is performed by a conventional verification circuit, there is a problem that it takes time to perform a verify read.

The present invention has been made in view of the above circumstances, and an object of the present invention is to read multi-valued information without changing a verify read voltage.
EEPRO that can reduce verify read time
M.

[0013]

(Constitution) A nonvolatile semiconductor memory device of multi-value (n-value) storage according to the present invention is controlled so that a bit line potential at the time of a read operation indicates a threshold value of a memory cell. Is done. This means, for example, that a common source line
V, 2 V is applied to the selected control gate, and the potential of the common source line is transferred to the bit line. When the bit line potential reaches the threshold value of the memory cell, the current flowing through the memory cell stops, and the bit line potential becomes a value obtained by subtracting the threshold value of the memory cell from the control gate voltage 2V. If the bit line potential is 3V, the threshold value of the memory cell is -1V.
The non-selected control gate and select gate are set to, for example, 6 V so that the bit line potential is not determined by the threshold value of the unselected memory cell or the select transistor.

The erase state is set to "0", and the multi-valued levels are set to "0", "1",.
Assuming that “i”,... “N−1”, the verify reading is simultaneously performed for all data “i” to determine whether or not writing is sufficient. The potential is set.
Also, as in the case of writing data "0", the current of the memory cell is compensated if it is already detected that writing is sufficient, and the current of the memory cell is not compensated if it is detected that writing is insufficient. A circuit is provided.

A first register for storing whether or not the writing is sufficient as data and a second register for storing any one of the multilevel levels to be written, "1",..., "N-1". The first register also has a function of a sense amplifier for detecting whether or not writing is sufficient. Furthermore, if there is a memory cell that has not reached the desired write state, a bit line write voltage output circuit that outputs a bit line voltage at the time of writing according to the desired write state so that rewriting is performed only on that memory cell. It is characterized by having.

That is, according to the present invention, in a multi-valued nonvolatile semiconductor memory device, a plurality of memory cells which can be electrically rewritten and have n storage states (n ≧ 3) are arranged in a matrix. The arranged memory cell array, a plurality of bit lines connected to the memory cell array, a plurality of word lines connected to the memory cell array, and a write pulse applied to each memory cell during data writing. The control data is stored, and a reference signal determined by the stored control data is compared with a signal indicating the storage state of the memory cell output via the bit line. A plurality of data circuits for detecting whether the state has reached a desired state.

Here, preferred embodiments of the present invention include the following. (1) A data input buffer is provided, and control data stored in the data circuit is initially set to initial control data sent from the data input / output buffer. (2) The data circuit controls the voltage of the write pulse applied to the corresponding memory cell according to the stored control data. (3) Data writing must be continued until all memory cells have been written.

(4) The data circuit has an i-th (i = 2,...,
In the case where the control data of n) is stored, when it is detected that the corresponding memory cell has reached the i-th storage state, the stored i-th control data is changed to the first control data, and the j-th control data is changed. (J = 2,..., N), when it is detected that the corresponding memory cell has not reached the j-th storage state, the stored j-th control data is held; When the first control data is stored, the first control data is held.

(5) A control data detection circuit for detecting control data stored in a plurality of data circuits, wherein the control data detection circuit determines whether the control data stored in all the data circuits is the first control data Detect whether or not. (6) The data writing is continued until the control data detection circuit detects that the control data stored in all the data circuits is the first control data.

(7) The data circuit detects the storage state of the corresponding memory cell during data writing only when storing control data other than the first control data. (8) A data input buffer is provided, and the data circuit includes n first, second, and second data indicating the storage state to be stored in each memory cell sent from all data input buffers.
.., A write pulse is applied to initially store any one of the n-th control data and to promote writing only to the memory cells that have not reached the storage state indicated by the control data to be initially stored. As described above, when the i-th (i = 2,..., N) control data is initially stored, the control data stored is detected when the corresponding memory cell has reached the i-th storage state. Change to the first control data, and if the first control data is stored, hold the first control data.

(9) A control data detection circuit for detecting control data stored in a plurality of data circuits is provided. The control data detection circuit determines whether the control data stored in all the data circuits is the first control data. Detect whether or not. (10) The data writing is continued until the control data detection circuit detects that the control data stored in all the data circuits is the first control data. (11) The data circuit detects the storage state of the corresponding memory cell during data writing only when control data other than the first control data is stored.

(Operation) In the present invention, after performing the multi-level data writing, it is simultaneously detected whether or not the writing state of each memory cell has reached the desired multi-level level state. If there is a memory cell that does not reach a desired multi-value level, a bit line voltage at the time of writing is output according to a desired writing state so that rewriting is performed only on that memory cell. This write operation and verify read are repeated, and when it is confirmed that all the memory cells have reached the desired write state, the data write ends.

As described above, according to the present invention, one write time is shortened, and the write operation is repeated little by little while checking the progress of the write state, whereby the data write is finally completed. Decreasing the threshold value of the memory cell can be performed at high speed.

[0024]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a memory cell array 1 of a NAND cell type EEPROM according to a first embodiment of the present invention. The memory cell array 1 is formed on a p-well or p-substrate, and has eight memory cells M1 to M8 between a select transistor S1 connected to a bit line BL and a select transistor S2 connected to a common source line Vs. One NAND cell is connected in series. Each select transistor S (S1, S2) has a select gate SG (SG1, S2).
G2). Each memory cell has a stacked floating gate (charge storage layer) and a control gate CG (CG1 to CG).
8) to store information by the amount of charge stored in the floating gate. The amount of the stored charge can be read as the threshold value of the memory cell.

In the present invention, this threshold value is read out as shown in FIG. Here, the memory cell M2 having the control gate CG2 is selected. As shown in FIG. 2A, a voltage is applied to each part, and the bit line BL is made floating. When the bit line BL is reset to 0 V in advance, the bit line BL is charged through the NAND cell by the common source line Vs. The selection gate and control gate voltages are controlled such that the potential of the charged bit line BL is determined by the threshold value of the selected memory cell M2.

In this example, the selection gates SG1 and SG2, the control gates CG1 and CG3 to 8 are set to 6V, the selected control gate CG2 is set to 2V, and the common source line Vs is set to 6V.
The voltage waveform of each part is shown in FIG. As a result, a threshold value of 2 V or less can be read, and if the threshold value of an unselected memory cell is controlled to 2.5 V or less,
A threshold of 1.5 V or more can be read. If the potential of the bit line BL is 0 V, the threshold value is 2 V or more, and if the bit line potential is 3.5 V, the threshold value is -1.5 V or less. Select gates SG1, SG2, non-select control gate C
If the voltages of G1 and CG3 to 8 are made sufficiently high, the threshold value up to -4V can be read.

FIG. 3 shows the relationship between the threshold voltage of the memory cell and the bit line output voltage in this case. When calculated from the threshold value when the back bias is 0 V, the result is as shown by the solid line. However, actually, the bit line voltage becomes the back bias, and the bit line output voltage becomes lower as indicated by the one-dot chain line.
Hereinafter, for the sake of simplicity, the expression “threshold” is based on the consideration of the back bias, unless otherwise specified.

After the electrons are emitted from the floating gate of the memory cell by the erase operation, the electrons are injected into the floating gate by the write operation according to the write data. FIG.
Shows the relationship between the write time and the bit line output voltage at the time of reading when the bit line output voltage at the time of reading is not limited by the threshold value of the unselected memory cell. For example, when the voltage of the common source line at the time of reading is 3 V,
The bit line output voltage does not change unless electrons are injected into the floating gate and the threshold value becomes -1 V or more. Even when the voltage of the common source line is 6 V, if the threshold value of the unselected memory cell is a positive value, the bit line output voltage at the time of reading is limited.

When one memory cell has two states (data "0" and "1"), for example, as shown in FIG. 5, a state in which the bit line output voltage at the time of reading becomes 3 to 4 V (threshold). The value (about -2 V to -1 V) may be data "0" (erased state), and the state in which the bit line output voltage is 1 to 2 V (threshold value about 0 to 1 V) may be data "1".

When one memory cell has three states (data "0", "1", "2"), for example, FIG.
As shown in FIG.
4.5V state (about -2.5V to -1.
5V) with data "0" (erased state) and a state where the bit line output voltage is 1.5 to 2.5 V (about -0.5 by threshold).
V to 0.5 V) as data “1” and bit line output voltage as 0
To 0.5V (about 1.5V to 2.5V at threshold)
V) may be data “2”.

FIG. 7 shows a memory cell array 1 of a NOR cell type EEPROM according to a second embodiment of the present invention. The memory cell array 1 is formed on a p-well or a p-substrate, and one memory cell M is arranged between a bit line BL and a common source line Vs. Each memory cell has a stacked floating gate and a word line WL.

The threshold value of the memory cell is read out as shown in FIG. As shown in FIG. 8A, a voltage is applied to each part, and the bit line BL is made floating.
When the bit line BL is reset to 0 V in advance, the bit line BL is charged through the memory cells by the common source line Vs. The potential of the charged bit line BL is determined by the threshold value of the selected memory cell M.

In this example, the word line WL is set to 6V and the common source line Vs is set to 6V. The voltage waveform of each part is shown in FIG.
This is shown in (b). Thereby, a threshold value of 0 to 6 V can be read. The potential of the bit line BL is 0 V
If the bit line potential is 6 V, the threshold is 0 V or less. In this case, the relationship between the threshold value of the memory cell and the bit line output voltage is as shown in FIG. When calculated from the threshold value when the back bias is 0 V, the result is as shown by the solid line. However, as in FIG. 3, the bit line voltage becomes the back bias and the bit line output voltage is lower as shown by the dashed line. Become.

After electrons are injected into the floating gate of the memory cell by the erase operation, the electrons are emitted from the floating gate by the write operation according to the write data. FIG.
Shows the relationship between the writing time and the bit line output voltage at the time of reading. For example, when the voltage of the common source line at the time of reading is 3V, if electrons are emitted from the floating gate and the threshold value becomes 3V or less, the bit line output voltage does not change. Even when the voltage of the common source line is 6 V, the bit line output voltage at the time of reading does not change if the threshold value becomes 0 V or less.

When one memory cell has two states (data "0" and "1"), for example, as shown in FIG. 11, a state in which the bit line output voltage at the time of reading becomes 1-2 V (threshold). A value of about 4N to 5V) may be set to data "0" (erase state), and a state where the bit line output voltage becomes 3 to 4V (about 2V to 3V by threshold) may be set to data "1".

When one memory cell has three states (data "0", "1", "2"), for example, FIG.
As shown in FIG.
When the voltage becomes 0.5 V (about 5.5 V or more as a threshold value), the data "0" (erase state),
2.5V state (about 3.5V to 4.5 at threshold)
V) is "1", and the bit line output voltage is 3.5-4.
The state where the voltage becomes 5 V (about 1.5 V to 2.5 V as a threshold value) may be used as data “2”.

FIG. 13 shows a configuration of a ternary storage type EEPROM according to the first and second embodiments of the present invention. For the memory cell array 1 ((a) (b)), a bit line control circuit 2 for controlling a bit line at the time of reading / writing and a word line driving circuit 6 for controlling a word line potential are provided. . The bit line control circuit 2 is selected by the column decoder 3. Bit line control circuit 2
Performs exchange of read data / write data with the input / output data conversion circuit 4 via a data input / output line (IO line). The input / output data conversion circuit 4 converts the read multi-value information of the memory cell into binary information for output to the outside, and converts the binary information of the write data input from outside into the multi-value information of the memory cell. Convert. The input / output data conversion circuit 4 is connected to a data input / output buffer 5 for controlling data input / output with the outside.

FIG. 14 shows the NAN according to the first embodiment.
1 shows a specific configuration of a memory cell array 1 and a bit line control circuit 2 of a D-cell type EEPROM. One end of the NAND type cell is connected to the bit line BL, and the other end is connected to the common source line Vs. The selection gates SG1 and SG2 and the control gates CG1 to CG8 are shared by a plurality of NAND cells,
The memory cells M sharing one control gate constitute a page. The memory cell stores data at the threshold value Vt, and stores "0", "1", and "2" data as shown in FIG. One memory cell has three states, and two memory cells can have nine combinations.
Of these, eight combinations are used to store 3-bit data in two memory cells.

In this embodiment, a set of two adjacent memory cells sharing a control gate stores 3-bit data. The memory cell array 1 ((a) (b)) is formed on a dedicated p-well.

An n-channel MOS transistor (n-ch T
r.) Qn8-10 and p-channel MOS transistor (p-
ch Tr.) Qn3-5, n-ch Tr.Qn11-13 and p-ch T
r.Qn6 to 8 to flip flop FF1,2 respectively
And latch the write / read data. It also operates as a sense amplifier. The flip-flop FF1 latches “whether“ 0 ”write,“ 1 ”or“ 2 ”write” as write data information, and checks whether the memory cell holds “0” information. , "1" or "2" is latched as read data information. The flip-flop FF2 latches “whether“ 1 ”write or“ 2 ”write” as write data information, and checks whether the memory cell holds “2” information.
"Whether the information of" 0 "or" 1 "is held" is latched as read data information.

The n-ch Tr. Qn1 has a precharge signal φpa
Becomes "H", the voltage Va is transferred to the bit line BLa. When the precharge signal φpb becomes “H”, the n-ch Tr. Qn20 transfers the voltage Vb to the bit line BLb.
The n-ch Trs Qn4 to Qn7 and the p-ch Trs Qp1 to Qp2 selectively transfer the voltages VBHa, VBMa and VBLa to the bit line BLa according to the data latched in the flip-flops FF1 and FF2. I do. n-ch Tr.Qn14 ~ 17,
p-ch Tr. 9 to 10 are flip-flop FF1, FF
2, the voltage VBHb,
VBMb and VBLb are selectively transferred to bit line BLb. The n-ch Tr. Qn2 connects the flip-flop FF1 to the bit line BLa when the signal φa1 becomes “H”.
The n-ch Tr. Qn3 connects the flip-flop FF2 to the bit line BLa when the signal φa2 becomes “H”. n-ch
Tr. Qn19 connects the flip-flop FF1 to the bit line BLb when the signal φb1 becomes “H”. n-ch T
r.Qn18 is flip-flopped when the signal φb2 becomes “H”.
The flop FF2 is connected to the bit line BLb.

Next, the EEPROM constructed as described above will be described.
Will be described with reference to FIGS. 15 shows the timing of the read operation, FIG. 16 shows the timing of the write operation, and FIG. 17 shows the timing of the verify read operation. In each case, the case where the control gate CG2a is selected is shown as an example.

The read operation is executed in two basic cycles. In the first read cycle, first, when the voltage Vb is 3
The bit line BLb which becomes V and becomes a dummy bit line is precharged. Also, the precharge signal φpa is “L”
And the selected bit line BLa is floated,
The common source line Vsa becomes 6V. Subsequently, the selection gates SG1a and 2a and the control gates CG1a and 3a to 8a
V. The control gate CG2a selected at the same time is 2
V. Only when data “0” is written in the selected memory cell, the voltage of the bit line BLa is 3 V
That is all.

Thereafter, flip-flop activating signal φ
n1 and φp1 become "L" and "H", respectively, and the flip-flop FF1 is reset. When the signals φa1 and φb1 become “H”, the flip-flop FF1 and the bit line B
La and BLb are connected, the signals φn1 and φp1 become “H” and “L”, respectively, and the bit line potential is sensed. “0” data or “1” is supplied to the flip-flop FF1.
Or, information of “2” data is latched.

The second read cycle is the same as the first read cycle, except that the voltage of the dummy bit line BLb is 1V instead of 3V.
And that the signals φa2, φb2, φn2, φp2 are output instead of the signals φa1, φb1, φn1, φp1. Therefore, in the second read cycle, the information of “whether“ 2 ”data,“ 1 ”or“ 0 ”data” is latched in the flip-flop FF2.

The data written in the memory cells is read by the two read cycles described above.

Prior to data writing, the data in the memory cell is erased, and the threshold value Vt of the memory cell becomes -1.5.
V or less. Erase is performed on the p-well and the common source line V
sa, the selection gates SG1a and 2a are set to 20V, and the control gates CG1a to 8a are set to 0V.

In the write operation, first, the precharge signal φpa becomes “L”, and the bit line BLa is floated. Select gate SG1a is Vcc, control gate C
G1a to 8a are set to Vcc. The selection gate SG2a is at 0 V during the write operation. At the same time, the signal VRFYa becomes “H” and PBa becomes “L”. In the case of writing “0”, since the data is latched in the flip-flop FF1 so that the node N1 becomes “L”, the bit line B
La is charged to Vcc by the voltage VBHa. “1”
Alternatively, in the case of “2” write, the bit line BLa is at 0V.

Subsequently, the selection gate SG1a, the control gates CG1a to CG8a are set to 10V, and the voltages VBHa and Vrw are set to 8
V and the voltage VBMa become 1V. In the case of writing “1”, since the data is latched in the flip-flop FF2 so that the node N3 becomes “L”, the bit line B
1 V is applied to La by the voltage VBMa. “2”
In the case of writing, the bit line BLa becomes 0V, and in the case of "0" writing, it becomes 8V. Thereafter, the selected control gate CG2a is set to 20V.

In the case of "1" or "2" writing, electrons are injected into the charge storage layer of the memory cell due to the potential difference between the bit line BLa and the control gate CG2a, and the threshold value of the memory cell rises. In the case of “1” write, the amount of charge to be injected into the charge storage layer of the memory cell must be smaller than in the case of “2” write.
a is set to 1V and the potential difference between the control gate CG2a and the control gate CG2a is set to 19V.
To relax. When writing “0”, the bit line voltage 8
The threshold voltage of the memory cell is not effectively changed by V.

At the end of the write operation, first, the selection gate SG1a and the control gates CG1a to 8a are set to 0V,
The voltage 8V of the bit line BLa at the time of writing "0" is reset to 0V with a delay. This is because if this order is reversed, the state of the "2" write operation is temporarily created, and incorrect data is written when "0" is written.

After the write operation, the verify read is performed in order to confirm the write state of the memory cell and to perform additional write only on the memory cell with insufficient write.

The verify read is similar to the first read cycle. The difference is that first flip flop F
The data of F1 is inverted, the voltage Vb becomes Vcc, and the signals VRFYa and VRFYb are output. At this time, the voltages VBLb and VBMb are 2.5 V and 0.5 V, respectively.
It is to become. The voltage of the dummy bit line BLb is determined by the voltages Vb, VBLb, VBMb and the data of the flip-flops FF1, FF2. The signal VRFYa,
VRFYb is the signal φn1, after the selection gates SG1a, 2a and the control gates CG1a-8a are reset to 0V.
It is output before φp1 becomes “L” and “H”, respectively. In other words, after the potential of the bit line BLa is determined by the threshold value of the memory cell, the flip-flop FF1
Before it is reset.

The operation of inverting the data of the flip-flop FF1 will be described. First, the voltage Vb becomes 2.5 V, and the bit line BLb serving as a dummy bit line is precharged. Further, the precharge signals φpa and φpb become “L”, and the bit lines BLa and BLb are floated.
Subsequently, the signal PBa becomes “L” and the bit line BLa is charged to 2.5 V or more only when the node N1 is “L”. Thereafter, flip-flop activation signals φn1, φn1,
φp1 becomes “L” and “H”, respectively, and the flip-flop FF1 is reset. When the signals φa1 and φb1 become “H”, the flip-flop FF1 and the bit line B
La and BLb are connected, and signals φn1 and φp1 become “H” and “L”, respectively, and the bit line potential is sensed.
By this operation, the data of the flip-flop FF1 is inverted.

Next, the data (data1) latched in the flip-flop FF1, the data (data2) latched in the flip-flop FF2, and the data after the data inversion operation determined by the threshold value of the selected memory cell. The voltage of the bit line BL will be described. The data1 controls “whether“ 0 ”write,“ 1 ”or“ 2 ”write”, and in the case of “0” write, the node N1 becomes “H”, “1” or “2” write after data inversion operation. In this case, the node N1 is at "L" after the data inversion operation. dat
a2 controls “whether“ 1 ”write or“ 2 ”write”. In the case of “1” write, the node N3 is “L”,
In the case of "2" write, the node N3 is "H".

In the verify read operation after writing "0" data, the signal VRF is applied regardless of the state of the memory cell.
When Ya becomes “H”, the voltage VBLa or VB of 0 V is set.
The bit line BL becomes “L” by Ma. Therefore, the bit line BLa is sensed by the flip-flop FF1 so that the node N1 becomes "L", and the rewritten data latched is "0".

In the verify read operation after writing the "1" data, the signal VRFYb becomes "H" and the dummy bit line BLb is set to 2.5V. Therefore, when the memory cell has not reached the “1” write state, the bit line BLa is set to 2.5 V or higher, and the bit line BLa is set to “H” by the flip-flop FF1 so that the node N1 becomes “H”.
Is sensed and the rewritten data latched is
It is "1". When the memory cell has reached the "1" write state, the bit line BLa is sensed and latched so that the voltage of the bit line BLa is 2.5 V or less and the node N1 is set to "L" by the flip-flop FF1. The write data is “0”.

In the verify read operation after "2" data write, the signal VRFYb becomes "H" and the dummy bit line BLb is set to 0.5V. Therefore, when the memory cell has not reached the “2” write state, the bit line BLa is set to 0.5 V or higher, and the bit line BLa is set to “H” by the flip-flop FF1 so that the node N1 becomes “H”.
Is sensed and the rewritten data latched is
It is “2”. When the memory cell has reached the "2" write state, the bit line BLa is sensed and latched so that the node N1 is set to "L" by the flip-flop FF1 at a voltage of 0.5 V or less. The write data is “0”.

By this verify read operation, rewrite data is set as shown in the following (Table 1) from the write data and the write state of the memory cell.

[0061]

[Table 1]

As can be seen from this (Table 1), "1" writing is performed again only on the memory cells for which "1" writing is insufficient even though it should be in the "1" writing state.
The "2" writing is performed again only on the memory cells for which the "2" writing is insufficient even though the "2" writing state should be established.

Data writing is performed by repeatedly performing the write operation and the verify read operation.

The following (Table 2) shows the potential of each part of the memory cell array at the time of erasing, writing, reading and verify reading.

[0065]

[Table 2]

FIG. 18 shows the NOR in the second embodiment.
1 shows a specific configuration of a memory cell array 1 and a bit line control circuit 2 of a cell type EEPROM. One end of the NOR type cell is connected to the bit line BL and the other end is connected to the common source line V.
s. The word line WL is shared by a plurality of NOR type cells, and is a memory cell M that shares one word line.
Constitutes a page. The memory cell stores data at the threshold value Vt, and stores "0", "1",
"2" data is stored. One memory cell has three states, and two memory cells can have nine combinations. Of these, eight combinations are used to store 3-bit data in two memory cells. In this embodiment, data of 3 bits is stored in a set of two adjacent memory cells sharing a word line. The memory cell array 1 ((a) (b)) is formed on a p substrate.

The n-ch Tr.Qn26-28 and the p-ch Tr.Qn1
5-17, n-ch Tr.Qn29-31 and p-ch Tr.Qn18
Flip-flops FF3 and Flip-flop FF4 are respectively constituted by .about.20, and write / read data is latched. It also operates as a sense amplifier. Flip flop F
F3 is “write“ 0 ”or“ 1 ”or“ 2 ”
"Whether to write" is latched as write data information, and whether the memory cell holds the information "0"
"Whether the information of" 1 "or" 2 "is held" is latched as read data information. Flip flop F
F4 latches “whether“ 1 ”write or“ 2 ”write” as write data information, and whether the memory cell holds “2” information, “0” or “1”. "Does information hold?" Is latched as read data information.

The n-ch Tr. Qn21 receives a precharge signal φ.
When pa becomes "H", the voltage Va is transferred to the bit line BLa. The n-ch Tr. Qn36 transfers the voltage Vb to the bit line BLb when the precharge signal φpb becomes “H”.
The n-ch Tr. Qn24, 25 and the p-ch Tr. 11 to 14 selectively transfer the voltages VBHa, VBMa, 0V to the bit line BLa according to the data latched in the flip-flops FF3, FF4. I do. n-ch Tr.Qn32,33,
p-ch Trs 21 to 24 are flip-flops FF3, F
According to the data latched in F4, the voltage VBH
b, VBMb and 0V are selectively transferred to the bit line BLb. The n-ch Tr. Qn22 connects the flip-flop FF3 to the bit line BLa when the signal φa1 becomes “H”. The n-ch Tr. Qn23 connects the flip-flop FF4 to the bit line BLa when the signal φa2 becomes “H”. The n-ch Tr. Qn35 connects the flip-flop FF3 to the bit line BLb when the signal φb1 becomes “H”. The n-ch Tr. Qn34 connects the flip-flop FF4 to the bit line BLb when the signal φb2 becomes “H”.

Next, the EEPROM constructed as described above will be described.
Will be described with reference to FIGS. 19 shows the timing of the read operation, FIG. 20 shows the timing of the write operation, and FIG. 21 shows the timing of the verify read operation. In each case, the case where the word line WLa is selected is shown as an example.

The read operation is executed in two basic cycles. In the first read cycle, first, the voltage Vb is set to 1
The bit line BLb which becomes V and becomes a dummy bit line is precharged. Also, the precharge signal φpa is “L”
And the selected bit line BLa is floated,
The common source line Vsa becomes 6V. Then, the word line W
La is set to 6V. Only when data “0” is written in the selected memory cell, the voltage of the bit line BLa becomes 0.5 V or less.

Thereafter, flip-flop activating signal φ
n1 and φp1 become “L” and “H”, respectively, and the flip-flop FF3 is reset. The signals φa1 and φb1 become “H” and the flip-flop FF3 and the bit line B
La and BLb are connected, the signals φn1 and φp1 become “H” and “L”, respectively, and the bit line potential is sensed, and “0” data or “1” is supplied to the flip-flop FF3.
Or, information of “2” data is latched.

The second read cycle is the same as the first read cycle, and the voltage of the dummy bit line BLb is 3V instead of 1V.
And that the signals φa2, φb2, φn2, φp2 are output instead of the signals φa1, φb1, φn1, φp1. Therefore, in the second read cycle, the information of “whether“ 2 ”data,“ 1 ”or“ 0 ”data” is latched in the flip-flop FF4.

The data written in the memory cell is read by the two read cycles described above.

Prior to data writing, the data in the memory cell is erased, and the threshold value Vt of the memory cell is 5.5 V
That is all. The operation is performed by setting the word line WLa to 20V and the bit line BLa to 0V.

In the write operation, first, the precharge signal φpa becomes “L”, and the bit line BLa is floated. Subsequently, the signal VRFYBa becomes “L” and Pa becomes “H”. In the case of "0" writing, the bit line BLa is set to 0 V because data is latched in the flip-flop FF3 so that the node N5 becomes "H". In the case of “1” or “2” writing, the bit line BL
a is set to Vcc by the voltage VBHa or VBMa.

Subsequently, the voltages VBHa and Vrw become 8V, and the voltage VBMa becomes 7V. In the case of "1" writing, since the data is latched in the flip-flop FF4 so that the node N7 becomes "H", 7V is applied to the bit line BLa by the voltage VBMa. In the case of "2" write, the bit line BLa becomes 8V, and in the case of "0" write, it becomes 0V. Thereafter, the selected word line WLa is set to -12V.

In the case of "1" or "2" writing, electrons are emitted from the charge storage layer of the memory cell due to the potential difference between the bit line BLa and the word line WLa, and the threshold value of the memory cell decreases. In the case of “1” write, the amount of charge to be released from the charge storage layer of the memory cell must be reduced as compared with “2” write, so that the bit line BL
By setting a to 7 V, the potential difference from the word line WLa is reduced to 19 V. At the time of writing “0”, the threshold value of the memory cell is not effectively changed by the bit line voltage 0V.

After the write operation, the verify read is performed in order to confirm the write state of the memory cell and perform additional write only to the memory cell with insufficient write.

The verify read is similar to the first read cycle. The difference is that first flip flop F
The data of F3 is inverted, the voltage Vb is 0 V, and the signals VRFYBa and VRFYBb are output. At this time, the voltages VBHb and VBMb are 1.5 V and 3.5 V, respectively.
V. The voltage of the dummy bit line BLb is determined by the voltages Vb, VBHb, VBMb and the data of the flip-flops FF3, FF4. Signal VRFYB
a and VRFYBb are output before the signals φn1 and φp1 become “L” and “H”, respectively, after the word line WLa is reset to 0V. In other words, after the potential of the bit line BLa is determined by the threshold value of the memory cell, but before the flip-flop FF3 is reset.

First, the operation of inverting the data of the flip-flop FF1 will be described. First, the voltages Va and Vb become Vcc and 2.5 V, respectively, and the bit lines BLa and BLb are precharged. In addition, precharge signals φpa, φpb
Becomes "L", and the bit lines BLa and BLb are floated. Subsequently, when the signal Pa becomes “H” and the node N3 is “H”, the bit line BLa
It is discharged below. Thereafter, the flip-flop activation signals φn1 and φp1 become “L” and “H”, respectively, and the flip-flop FF3 is reset. Signal φa1,
φb1 becomes “H”, the flip-flop FF3 is connected to the bit lines BLa and BLb, and the signals φn1 and φp1 become “H” and “L”, respectively, and the bit line potential is sensed. By this operation, the data of the flip-flop FF3 is inverted.

Next, the data (data1) latched in the flip-flop FF3, the data (data2) latched in the flip-flop FF4, and the data after the data inversion operation determined by the threshold value of the selected memory cell. The voltage of the bit line BL will be described. The data1 controls “whether“ 0 ”write,“ 1 ”or“ 2 ”write”. In the case of “0” write, the node N5 outputs “L”, “1” or “2” write after the data inversion operation. In this case, the node N5 is at "H" after the data inversion operation. data
2 controls “whether“ 1 ”write or“ 2 ”write”. In the case of “1” write, the node N7 is “H”,
In the case of "2" write, the node N7 is "L".

In the verify read operation after writing "0" data, the signal VRF is applied regardless of the state of the memory cell.
When YBa becomes “L”, the voltage VBHa or VBMa
As a result, the bit line BLa becomes "H". Therefore, the bit line BLa is sensed by the flip-flop FF3 so that the node N5 becomes "H", and the rewritten data latched is "0".

In the verify read operation after writing the “1” data, the signal VRFYBb becomes “L” and the dummy bit line BLb is set to 1.5V. Therefore, when the memory cell has not reached the “1” write state, the bit line BLa is set to 1.5 V or less and the flip-flop FF3
Bit line BL such that node N5 attains "L".
a is sensed and latched rewrite data is:
It is "1". When the memory cell has reached the "1" write state, the bit line BLa is sensed and latched by the flip-flop FF3 so that the node N5 becomes "H" at 1.5V or higher. The write data is “0”.

In the verify read operation after writing the "2" data, the signal VRFYBb becomes "L" and the dummy bit line BLb is set to 3.5V. Therefore, when the memory cell has not reached the “2” write state, the bit line BLa is set to 3.5 V or less and the flip-flop FF3
Bit line BL such that node N5 attains "L".
a is sensed and latched rewrite data is:
It is “2”. When the memory cell has reached the "2" write state, the bit line BLa is sensed and latched so that the node N5 is set to "H" by the flip-flop FF3 at 3.5 V or more and the flip-flop FF3. The write data is “0”.

By this verify read operation, rewrite data is set as shown in Table 1 from the write data and the write state of the memory cell. (Table 1)
As can be seen from the figure, "1" writing is performed again only on the memory cell where "1" writing is insufficient even though it should be in "1" writing state. "2" write is performed again only on the memory cell for which write is insufficient.

Data writing is performed by repeatedly performing the write operation and the verify read operation.

The following (Table 3) shows the potential of each part of the memory cell array at the time of erasing, writing, reading and verify reading.

[0088]

[Table 3]

FIG. 22 shows the flip-flops FF1 and FF2 shown in FIG. 14 or the flip-flops FF1 and FF2 shown in FIG.
This is a circuit for controlling data input / output between the flops FF3, 4 and the input / output data conversion circuit 4 shown in FIG.
The column decoder 3 is constituted by the inverter I1 and the NAND circuit G1, and when the column activation signal CENB becomes "H", the decoder output selected by the address signal becomes "H", and the nodes A, B, C, and D respectively become IOA
1, IOB1, IOA2, and IOB2. Nodes A, B, C, and D are nodes N1, N2,
18, nodes N6, 5, 8, and 7 in FIG. Read / write data and IOA1, IOB1, IOA2, IOB when bit line BLa is selected
The relationship of 2 is as follows (Table 4).

[0090]

[Table 4]

[0091]

As described above, according to the present invention, it is possible to set three or more write states in one memory cell while suppressing an increase in circuit area, and furthermore, to set each write state in each memory cell. To obtain an EEPROM in which a write time until a state is changed is independently optimized by performing write verify control, and a threshold distribution of a finally written memory cell can be quickly reduced to a small range. Can be.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a NAND cell array according to a first embodiment.

FIG. 2 is a diagram showing a read operation of a NAND cell according to the first embodiment;

FIG. 3 is a diagram showing a relationship between a threshold value of a memory cell and a bit line output voltage at the time of reading in the first embodiment;

FIG. 4 is a diagram showing a relationship between a writing time and a bit line output voltage at the time of reading in the first embodiment.

FIG. 5 is a diagram showing a relationship between bit line output voltage and data at the time of reading when binary data is stored in one memory cell according to the first embodiment.

FIG. 6 is a diagram showing a relationship between bit line output voltage and data at the time of reading when one memory cell stores three values in the first embodiment.

FIG. 7 is a diagram showing a configuration of a NOR cell array according to a second embodiment.

FIG. 8 is a diagram showing a read operation of a NOR cell according to the second embodiment.

FIG. 9 is a diagram showing a relationship between a threshold value of a memory cell and a bit line output voltage at the time of reading in the second embodiment.

FIG. 10 is a diagram showing a relationship between a writing time and a bit line output voltage at the time of reading in the second embodiment.

FIG. 11 is a diagram showing a relationship between a bit line output voltage and data at the time of reading when binary data is stored in one memory cell in the second embodiment.

FIG. 12 is a diagram showing a relationship between bit line output voltage and data at the time of reading when one memory cell stores ternary data according to the second embodiment;

FIG. 13 is a block diagram showing a configuration of an EEPROM according to the first and second embodiments.

FIG. 14 is a diagram showing a configuration of a memory cell array and a bit line control circuit according to the first embodiment.

FIG. 15 is a timing chart showing a read operation in the first embodiment.

FIG. 16 is a timing chart showing a write operation in the first embodiment.

FIG. 17 is a timing chart showing a verify read operation according to the first embodiment;

FIG. 18 is a diagram illustrating a configuration of a memory cell array and a bit line control circuit according to the second embodiment.

FIG. 19 is a timing chart showing a read operation in the second embodiment.

FIG. 20 is a timing chart showing a write operation in the second embodiment.

FIG. 21 is a timing chart showing a verify read operation in the second embodiment.

FIG. 22 is a diagram showing a configuration of a column decoder according to the first and second embodiments.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 memory cell array 2 bit line control circuit 3 column decoder 4 input / output data conversion circuit 5 data input / output buffer 6 word line drive circuit

Continuation of front page (56) References JP-A-59-121696 (JP, A) JP-A-5-282883 (JP, A) JP-A-5-259413 (JP, A) JP-A-59-63095 (JP, A) , A) JP-A-2-40198 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G11C 16/00-16/34

Claims (14)

(57) [Claims] 1. A memory cell array in which a plurality of memory cells which can be electrically rewritten and have n storage states (n ≧ 3) are arranged in a matrix, and are connected to the memory cell array. A plurality of bit lines; a plurality of word lines connected to the memory cell array; and a control provided for each of the bit lines, for controlling a write pulse applied to each memory cell during data writing. Memorize and memorize the data
Applied to the corresponding memory cell according to the control data
The voltage of the write pulse is controlled, and a reference signal determined by the stored control data is compared with a signal indicating the storage state of the memory cell output via the bit line. A nonvolatile semiconductor memory device, comprising: a plurality of data circuits for detecting whether a storage state of a cell has reached a desired state. 2. A memory cell array in which a plurality of memory cells which can be electrically rewritten and have n storage states (n ≧ 3) are arranged in a matrix, and are connected to the memory cell array. A plurality of bit lines; a plurality of word lines connected to the memory cell array; and a control provided for each of the bit lines, for controlling a write pulse applied to each memory cell during data writing. The memory stores data, compares a reference signal determined by the stored control data with a signal indicating the storage state of the memory cell output via the bit line, and stores the storage state of each memory cell during data writing. And a plurality of data circuits for detecting whether or not the data has reached a desired state , wherein the data circuit includes an i-th (i = 2,..., N) control data.
When a memory cell is stored, the corresponding memory cell is
I-th control stored when it is detected that the storage state has been reached
The data is changed to the first control data, and j-th (j = 2,
.., N) are stored.
Memory cells have Do the Most detected reaches a storage state of the j
Hold the j-th control data stored therein, and execute the first control
If data is stored, the first control data is stored.
A nonvolatile semiconductor memory device characterized by having. Wherein a data input buffer, according to claim wherein the control data stored in the data circuit is initially set to an initial control data transmitted from the data input buffer, it is characterized by 1 Or the nonvolatile semiconductor memory device according to 2. 4. A data writing, the all memory cells is continued until they are written, the non-volatile semiconductor memory device according to claim 1 or 2, wherein the. 5. A control data detecting circuit for detecting control data stored in the plurality of data circuits, wherein the control data detecting circuit is configured to transmit control data stored in all data circuits to a first control data. 3. The nonvolatile semiconductor memory device according to claim 2 , wherein whether or not the non-volatile semiconductor memory device is detected is determined. 6. The data writing is continued until the control data detection circuit detects that the control data stored in all the data circuits is the first control data.
3. The nonvolatile semiconductor memory device according to claim 2 , wherein: Wherein said data circuit only when storing the control data other than the first control data, claim to detect the storage state of the corresponding memory cells in the data write, be characterized by 2 14. The nonvolatile semiconductor memory device according to claim 1. 8. A data input buffer, wherein the data circuit includes n first, second,..., And n data indicating storage states to be stored in respective memory cells sent from all data input buffers. n is initially stored, and a write pulse is applied so as to promote writing only to memory cells that have not reached the storage state indicated by the initially stored control data. In the case where the i-th (i = 2,..., N) control data is initially stored, when the corresponding memory cell is detected to have reached the i-th storage state, the stored control data is stored in the first storage cell. 3. The non-volatile semiconductor memory device according to claim 1, wherein the control data is changed to control data, and when the first control data is stored, the first control data is held. 9. A control data detecting circuit for detecting control data stored in the plurality of data circuits, wherein the control data detecting circuit is configured to transmit control data stored in all data circuits to a first control data. 9. The non-volatile semiconductor memory device according to claim 8 , wherein whether or not the non-volatile semiconductor memory device is detected is determined. 10. Data writing, according to claim wherein the control data detecting circuit is the control data stored in all the data circuit continues until it detects that a first control data, characterized in that 9 14. The nonvolatile semiconductor memory device according to claim 1. Wherein said data circuit only when storing the control data other than the first control data, according to claim 8 for detecting the storage state of the corresponding memory cells in the data write, be characterized by 14. The nonvolatile semiconductor memory device according to claim 1. 12. A transformer having a charge storage layer and a control gate.
One end is connected to the bit line and the other end
Is connected to the source line, and the gate electrode is connected to the word line.
Electrically rewritable nonvolatile memory cell, and the bit line is previously set in a floating state,
A positive voltage is applied to the source line, and the bit line is
A control circuit for charging through the nonvolatile memory cell, the first and
The ternary data composed of the second binary storage circuit is
A data storage circuit that can be stored , wherein the first binary storage circuit is connected to the bit line.
And detects whether the voltage is equal to or higher than a predetermined level.
The state of the volatile memory cell, and the detection is performed by the second
Binary data stored in the binary storage circuit
Controlled by the nonvolatile semiconductor memory.
Storage device. 13. The data storage circuit according to claim 1 , wherein
The nonvolatile memory cell has a plurality of pressure detection levels.
Detecting which of three or more states it is in
13. The nonvolatile semiconductor memory device according to claim 12, wherein: 14. The data storage circuit according to claim 1 , wherein:
Has a plurality of pressure detection levels, and the detection level is the second level.
Of the nonvolatile memory,
Detects whether the moricell is in more than two states
13. The non-volatile semiconductor according to claim 12, wherein
Storage device.