JP4970402B2 - Semiconductor memory device - Google Patents

Description

  The present invention relates to a semiconductor memory device, and more particularly, to an electrically rewritable and erasable semiconductor memory device.

  As one of electrically rewritable and erasable nonvolatile semiconductor memory devices, one having a MISFET structure in which a charge storage layer and a control gate are stacked on a semiconductor substrate is known.

  In the floating gate nonvolatile semiconductor memory device, as shown in FIGS. 25A, 25B, and 25C, the erase operation is as follows.

  First, a negative charge is charged in the floating gate 106 shown in FIG. Next, an operation of extracting negative charges from the floating gate 106 to the semiconductor substrate 101 shown in FIG. In this process, a positive charge is charged in the floating gate 106 shown in FIG. Here, a source / drain diffusion layer 102 is provided on the surface of the semiconductor substrate 101, and a floating gate 106 is provided on the semiconductor substrate 101 via a tunnel insulating film 103. A control gate 104 is provided on the floating gate 106 via an interpoly insulating film 105.

  Next, in the MONOS (metal-silicon oxide film-silicon nitride film-silicon oxide film-semiconductor: Metal-Oxide-Nitride-Oxide-Semiconductor) type nonvolatile semiconductor memory device, FIGS. As shown in F), the erase operation is as follows.

  First, as shown in FIG. 25D, a positive charge is taken into the charge storage layer 110 from the semiconductor substrate 101 as shown in FIG. 25E from a state in which the charge storage layer 110 is charged with a negative charge. Operation is performed. By injecting positive charges into the charge storage layer in this manner, the charge storage layer 110 is brought into a state where positive charges are taken in as shown in FIG. This operation is called positive charge direct tunneling. In this case, if the thickness of the tunnel insulating film 111 between the charge storage layer and the semiconductor substrate increases, it becomes difficult for positive charges to enter the charge storage layer. However, as a data retention characteristic, the tunnel insulating film is preferably thick.

  Here, a source / drain diffusion layer 102 is provided on the surface of the semiconductor substrate 101, and a charge storage layer 110 is provided on the semiconductor substrate 101 via a tunnel insulating film 111. A control gate 104 is provided on the charge storage layer 110 via a block insulating film 105.

  Usually, the threshold value of the memory cell transistor is changed according to the amount of charge stored in the charge storage layer, and the written state and the erased state are stored. The data storage state in the conventional nonvolatile memory will be described with reference to FIG. A state where the charge amount of the charge storage layer is 0 is called a neutral state, and the threshold value of the memory cell transistor at that time is defined as a neutral threshold value Vthi. A state where positive charges are stored in the charge storage layer is referred to as an erase state, and a state where negative charges are stored is referred to as a write state. Such a state is common to NAND type, AND type, and NOR type memories.

  In FIG. 26A, the horizontal axis indicates the number of memory cells, and the vertical axis indicates a threshold value. In the erased state, all distributions exist at a threshold value smaller than Vthi. In the write state, all distributions exist at a threshold value greater than Vthi.

  As shown in FIG. 26B, in the writing operation, for example, a high voltage (for example, 10 to 25 V) is applied to the control gate 104 in a state where the semiconductor substrate 101 is set to 0 V, and the charge accumulation layer 110 is transferred from the semiconductor substrate 101. This is done by injecting a negative charge. Alternatively, the drain potential is positively biased with respect to the source potential to generate hot electrons accelerated by the channel, and the control gate 104 is positively biased with respect to the source potential to inject the hot electrons into the charge storage layer. Is done.

  As shown in FIG. 26C, in the erasing operation, for example, a high voltage (for example, 10 to 25 V) is applied to the semiconductor substrate 101 in a state where the control gate 104 is set to 0 V, and the charge accumulation layer 110 is applied to the semiconductor substrate 101. This is done by releasing negative charges. Alternatively, the drain potential is negatively biased with respect to the source potential to generate hot holes accelerated in the channel, and the control gate 104 is negatively biased with respect to the source potential to inject the hot holes into the charge storage layer 110. It is done by doing.

  Next, a data storage state and a data read operation of a NAND type EEPROM which is a typical nonvolatile memory will be described with reference to FIGS. In general, in a NAND type EEPROM, a state in which the threshold value of the memory cell is higher than 0 V is set as a write state, and a state where the threshold value is low is set as an erase state. In FIG. 27, the horizontal axis indicates the number of memory cells, and the vertical axis indicates the threshold value. In the erased state, all distributions exist at negative threshold values smaller than Vthi and the threshold value Vthsg of the selection transistor, and the state shown in FIG. In the writing state, all distributions exist at threshold values larger than Vthi and smaller than Vread, and are in the state shown in FIG.

  As shown in FIG. 28, in the read operation of the NAND type EEPROM, the bit line BL is precharged and then floated, the voltage of the control gate of the memory cell M2 selected for reading is set to the read voltage 0V, and the other memory cells The voltage of the control gates M0, M1, M3 to M31 is set to the unselected read voltage Vread, the gate voltages of the select transistors S1 and S2 are set to the power supply voltage Vcc, the source line Source is set to 0 V, and a current is supplied to the memory cell M2 selected for reading. This is done by detecting whether or not it flows through the bit line BL.

  That is, if the threshold value Vth of the memory cell M2 selected for reading is in a writing state, the memory cell is turned off, so that the bit line BL maintains the precharge potential.

  On the other hand, if the threshold value Vth of the memory cell M2 selected for reading is negative, the memory cell is turned on, so that the potential of the bit line BL decreases by ΔV from the precharge potential. Data in the memory cell is read by detecting this potential change with a sense amplifier.

  As shown in FIG. 29A, in the non-selected memory cell, after the data is stored, the charge is gradually discharged and decreased in the left memory cell, and the charge amount finally converges to 0. To do. Here, in both the positive charge and the negative charge, the amount of decrease in the charge amount increases as the charge amount increases in the initial state. In general, the write operation of the semiconductor memory device is performed using a case where the slope of change in charge is small and the amount of charge is small.

  In the conventional EEPROM, as shown in FIG. 26, the negative charge accumulation state and the positive charge accumulation state are stored in correspondence with the writing state and the erasing state, respectively. In particular, in the NAND type EEPROM, as shown in FIG. 27, data is stored in such a manner that the threshold value of the memory cell is in a positive state and a negative state in correspondence with a write state and an erase state, respectively.

  The conventional semiconductor device as described above has the following problems.

  In the read operation of the NAND type EEPROM, the non-selected memory cell needs to be turned on regardless of its storage state, and therefore, a voltage Vread higher than the write threshold voltage is applied to the control gate. As shown in FIG. 29B, when a non-selected memory cell immediately after erasing indicated by a solid line is in an erasing state, that is, a negative threshold state, the threshold is set by Vread stress by repeating the reading operation. Rising, the data is destroyed, and the threshold is positive as shown by the dashed line in the figure. This is called lead disturb.

  That is, as shown in FIGS. 29A and 29B, read-unselected cells are always exposed to Vread stress, and therefore the threshold value gradually increases.

  Here, when the retention charge of the memory cell is positive, the data retention characteristic is particularly deteriorated under any of the following conditions.

  This problem becomes more serious with the miniaturization of memory cells, which will be described below. With the miniaturization of the nonvolatile memory, there is an increasing demand for a decrease in write / erase voltage.

  This is because the area of the peripheral circuit for handling the write and erase voltages has a great influence on the entire semiconductor chip. If the write / erase voltage remains high, the area of the peripheral circuit is not reduced. If the cell is miniaturized, the area of the peripheral circuit is relatively increased. In this way, the area of the peripheral circuit limits the area of the entire semiconductor chip.

In order to realize this in a floating gate type memory cell, it is effective to improve the coupling ratio and reduce the thickness of the tunnel oxide film. Here, the voltage applied between the control gate and the channel at the time of writing and erasing is Vpp, the electric field applied to the tunnel oxide film is Eox, the tunnel oxide film thickness is d, the capacitance between the semiconductor substrate and the floating gate is C1, and the floating gate The capacitance between the control gates is C2, and the coupling ratio γ is a value obtained by dividing C2 by the sum of C1 and C2. Approximately, when Vth is equal to Vthi, the following formula 1 is established.

  Therefore, in order to lower the program voltage Vpp while maintaining Eox (while maintaining the write / erase speed), it is necessary to reduce the tunnel oxide film thickness d or increase the coupling ratio γ.

When the electric field applied to the tunnel oxide film of the non-selected memory cell at the time of the read operation is E′ox, the relationship of the following formula 2 is established when considering the case where Vth is approximately equal to Vthi.

  Therefore, if the coupling ratio γ is increased in order to lower the voltage applied to the control gate and the channel to Vpp and the tunnel oxide film thickness d is reduced, E′ox increases, and the read disturb characteristic is deteriorated.

  That is, the read disturb is caused by the leak of the tunnel oxide film, and the leak current increases when the E'ox, that is, the oxide film electric field increases.

  Further, there is a non-volatile memory using an insulating film such as a silicon nitride film as a charge storage layer, which is generally characterized by a low write / erase voltage Vpp (see, for example, Patent Document 1). However, it is known that in such a memory cell, as described in FIG. 4 of Patent Document 1, threshold fluctuations occur even at a low control gate voltage of 2.5 V or less.

  In addition, it has been pointed out by Minami et al. That holes accumulated in the erased state deteriorate reliability in repeated rewrite operations of cells using SiN as a charge storage layer (see, for example, Non-Patent Document 1). In the case of MONOS, when the charge storage layer is thinned and the stress is applied for a long time, the characteristic deterioration is remarkable.

Furthermore, it has been pointed out by Minami et al. That deterioration of data retention characteristics due to repetitive rewriting in a cell using SiN as a charge storage layer is deteriorated only by repetitive rewriting only in the hole accumulation state and not in the electron accumulation state (for example, non-deletion). Patent Document 2).
JP-A-11-330277 IEEE TRANSACTIONS ON ELECTRON DEVICES.Vol. 40, No. 11, pp.2011-2017 November 1993, Shin-ichi Minami and Yoshiaki Kamigaki "A Novel MONOS Nonvolatile memory Device Ensuring 10-Year Data Retentionafter 107 Erase / Write Cycles" IEEE TRANSACTIONS ON ELECTRON DEVICES.Vol. 38, No. 11, pp. 2519-2526 November 1991, Shin-ichi Minami and Yoshiaki Kamigaki `` New Scaling Guidelines for MNOS Nonvolatile Memory Devices

  An object of the present invention is to provide a highly integrated semiconductor memory device with improved read disturb characteristics.

The first aspect of the present invention includes an information storage unit that has at least one control terminal, is electrically erasable, and stores data of discrete n values (n is an integer of 2 or more), A plurality of memory elements connected in series between at least two current terminals, all the discrete first to nth threshold voltages in which the n-valued data is determined in order from the lowest threshold, It is higher than the lower one of the voltages applied to the current terminals at the time of data reading, and is arranged to share the current terminal with the memory element, and is electrically connected to the control terminals of the plurality of memory elements. has a separate control terminal, if the threshold voltage of the control terminal and the conducting state and a cutoff state is switched between the current terminals, a lower threshold voltage than the threshold voltage of the erased state of said plurality of memory elements A semiconductor memory device characterized by comprising a selection element to be.

A second aspect of the present invention includes an information storage unit that has at least one control terminal, is electrically erasable, and stores data of discrete n values (n is an integer of 2 or more), A plurality of memory elements connected in series between at least two current terminals are arranged, and a selection element is arranged by sharing the current terminal with the memory element, and is electrically separated from a control terminal of the memory element Discrete nth to nth data determined in ascending order of the threshold value with the voltage of the control terminal at which the conduction state and the cutoff state between the current terminals are switched as a threshold value. made to correspond to the threshold voltage, the threshold voltage in the data storage state corresponding to an erase state, and the higher memory elements than the threshold voltage of the selected element, the threshold voltage of the selected element The semiconductor memory device characterized by both and a lower memory element also.

  According to the present invention, it is possible to provide a highly integrated semiconductor memory device with improved read disturb characteristics.

  Next, embodiments of the present invention will be described with reference to the drawings. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, the drawings are schematic, and the relationship between the thickness and the planar dimensions, the ratio of the thickness of each layer, and the like are different from the actual ones. Accordingly, specific thicknesses and dimensions should be determined in consideration of the following description. Moreover, the part from which the relationship and ratio of a mutual dimension differ also in between drawings is contained.

  (First Embodiment) A read operation when this embodiment is applied to a NAND type EEPROM will be described with reference to FIG. Here, the memory cell unit includes 16 memory cell transistors M0 to M15 between a first selection transistor S1 having one end connected to the bit line BL and a second selection transistor S2 having one end connected to the source line Source. It is configured to be connected in series.

  The bit line BL is precharged and then floated, the voltage of the control gate of the memory cell transistor M2 selected for reading is set to the reading voltage Vref, and the voltages of the control gates of the other memory cells M0, M1, M3 to M15 are not selected. The bit line BL detects whether or not a current flows through the memory cell M2 selected for reading by setting the read voltage Vread, the gate voltage of the first selection transistor S1 and the second selection transistor S2 to the power supply voltage Vcc, and the source line Source to 0V. Is done.

  That is, if the threshold value Vth of the selected memory cell M2 is larger than the read voltage Vref, the selected memory cell M2 is turned off and the bit line BL maintains the precharge potential.

  On the other hand, if the threshold value Vth of the selected memory cell M2 is smaller than the read voltage Vref, the selected memory cell M2 is turned on, so that the potential of the bit line BL is lowered from the precharge potential by the voltage drop ΔV in the memory cell unit. To do. By detecting this potential change with a sense amplifier (not shown) in a data circuit (not shown) connected to the bit line, the data of the selected memory cell M2 is read.

  Here, the read voltage Vref is an intermediate voltage between the write state threshold and the erase state threshold, the non-select read voltage Vread is higher than the write state threshold, and the power supply voltage Vcc is higher than the select transistor threshold. .

  FIG. 1B shows the data storage state in this embodiment, with the horizontal axis representing the number of memory cell transistors and the vertical axis representing the threshold value. What is characteristic of this embodiment is that both the write state and the erase state of the memory cell have a positive threshold value.

  Here, the threshold values of the writing state and the erasing state have a distribution as shown in FIG. The threshold value of the erased state has a distribution that is larger than 0V and smaller than the read voltage Vref. The threshold value of the writing state has a distribution larger than the read voltage Vref and smaller than the non-selective read voltage Vread.

  In some cases, a data storage state as shown in FIG. The threshold value in the erased state has both positive and negative values across 0 V, and has a distribution smaller than the read voltage Vref. The threshold value of the writing state has a distribution larger than the read voltage Vref and smaller than the non-selective read voltage Vread.

  As shown in FIG. 27A, there is a problem that the threshold value of the non-selected cell rises due to the stress caused by the non-selected read voltage Vread due to repeated reading. Therefore, the threshold value for data storage and various voltage settings are taken into consideration. It is necessary to do it.

  FIG. 2A shows a distribution in which the horizontal axis represents the number of memory cell transistors and the vertical axis represents the threshold value in the threshold setting method considering read disturb.

  Let Vthw (min) be the lowest threshold value among the memory cells in the written state, and let ΔV be a distribution width of the write threshold value (ΔV is generally about 0.4 V, for example).

  In order to obtain a sufficient cell current for speeding up the read operation, the non-select read voltage Vread needs to be a voltage sufficient to turn on even a memory cell having the highest threshold.

  That is, since the cell current increases as the gate voltage increases, the gate voltage needs to be sufficiently high in order to earn the cell current.

This margin is V1. Generally, a voltage of about 1V is desirable as V1. At this time, the relationship of Equation 3 holds.

When the constant α is the sum of ΔV and V1, the following equations 4 and 5 that are equal to each other hold.

  Further, the highest threshold value among the memory cells in the erased state is Vthe (max). The erasing threshold indicated by the broken line gradually rises due to the repeated reading operation, and Vthe (max) becomes Vthe '(max) after a non-selection reading voltage Vread stress for a certain time, resulting in a distribution state indicated by the solid line. Here, Vthe '(max) increases as the unselected read voltage Vread stress time increases.

  The non-selected read voltage Vread stress time is determined by the reliability guarantee specifications of the nonvolatile memory, and is, for example, the product of the read time and the number of calls for guaranteeing the operation for 10 years.

Even after the non-selected read voltage Vread stress determined in this way, the threshold distribution in the written state and the erased state must be separated, and if the margin for separation is β, the relationship of Equation 6 needs to be satisfied. There is.

  Here, β is determined by the operation margin of the sense amplifier, but is generally about 0.4V.

  The inventor investigated the relationship between the erase threshold, the non-selected read voltage, and the non-selected read voltage stress time in the nonvolatile memory. In FIG. 2B, the horizontal axis is the read stress time, the vertical axis is the erase threshold voltage, and the erase threshold is expressed as a function of the read stress time.

  As a result, it has been found that the erase threshold Vthe 'after a sufficiently long read stress is determined only by the non-select read voltage Vread, regardless of the initial erase threshold Vthe.

  Regardless of the erase threshold when the read stress is 0 seconds (erase threshold in the initial state), the threshold after applying the stress for a long time converges to a constant value. When erasing is deep, the threshold fluctuation at the initial stage of stress is large due to the self electric field, and catches up when erasing is shallow.

In other words, the erase threshold after a certain read stress time (this time is determined by the reliability specification) is a function of the non-selected read voltage Vread, and Equation 7 is established.

  Here, F (x) depends on the read disturb characteristic of the memory cell transistor, but the inventor has found that it can be approximated by a quadratic function.

  FIG. 3 plots the above equation 5 on the graph as (1) and equation 7 as (2). The horizontal axis of the graph is the unselected read voltage Vread, and the vertical axis is the memory cell threshold Vth.

  In this graph, it is necessary to set the threshold values for writing and erasing so as to satisfy the relational expression (6). The erasing threshold Vthe ′ after a sufficiently long read stress may be set to be larger than the initial erasing threshold Vthe, and the difference between Vthe ′ and Vthe is not too large to reduce the erasing time and erasing voltage. It is desirable.

  By the way, Equation 6, that is, the erase threshold value Vthe '(max) after a certain time, depends on the read disturb characteristic of the memory cell. In the graph of FIG. 3, two types are plotted, when the threshold fluctuation due to read disturb is large (2) and when the threshold variation is small (3). When the threshold fluctuation due to read disturb is large (2), the erase threshold Vthe ′ (max) after a certain time becomes high. Therefore, the threshold value for writing / erasing is also higher than when the threshold fluctuation is small (3). It is desirable from the viewpoint of reliability.

  For miniaturized memory cells, techniques such as a MONOS type memory cell that increases the coupling ratio γ, reduces the tunnel oxide film thickness d, or traps charges in the insulating film are advantageous. In addition, when these techniques are used, threshold fluctuation due to read disturb increases. Furthermore, in the MONOS type memory cell, when erasing by direct tunneling of positive charges from the entire channel surface, if the tunnel oxide film is thinned in order to shorten the erasing time, the threshold fluctuation due to read disturb increases. By applying the mode, it is possible to suppress the decrease in the write / erase window due to the threshold fluctuation.

  In this embodiment, by making the threshold setting of the memory cell positive in both the write / erase state, it is possible to prevent data destruction of erase data in repeated read operations.

  Another effect of this embodiment is related to the erase verify operation. The erase verify operation is an operation for confirming that the threshold value of the memory cell erased after erasure is equal to or less than a desired threshold value (hereinafter referred to as Vverify). In the conventional NAND type EEPROM, the erase threshold value is 0 V or less, so the margin. Therefore, Vverify must be smaller than 0V. In the erase verify operation, Vverify is applied to the control gate electrode to confirm that the memory cell transistor is turned on at this time.

  Here, when Vverify is negative, an extra data control line driver for applying a negative voltage to the control gate is required, and the peripheral circuit area increases. If a negative voltage is not applied to the gate, it is necessary to increase the source voltage during the erase verify operation. In this case as well, an extra circuit for applying a positive voltage to the source line is required, and the peripheral circuit is also used. The area increases.

  Here, in this embodiment, since the erase threshold value is positive, Vverify is also positive. During the erase verify operation, the source line may be 0 V which is the reference potential as in the normal read operation, and the control gate electrode is also positive. Therefore, the peripheral circuit portion does not need an extra circuit for the erase verify operation, so that the circuit can be simplified and the area can be reduced.

  4 to 7 show an equivalent circuit diagram, a plan view, and a cross-sectional view of a memory cell when the present embodiment is applied to a NAND type EEPROM.

  In FIG. 4A, nonvolatile memory cells M0 to M15 made of MOS transistors having charge storage electrodes are connected in series, and one end is connected to the data transfer line BL via the selection transistor S1. The other end is connected to the common source line SL via the selection transistor S2. The control electrodes of the memory cells M0 to M15 are connected to data selection lines WL0 to WL15. A common well potential Well is applied to each of the memory cells M0 to M15.

  Further, in order to select one memory cell block from the plurality of memory cell blocks along the data transfer lines WL0 to WL15 and connect it to the data transfer line, the control electrode of the selection transistor S1 is connected to the block selection line SSL. .

  Further, the control electrode of the selection transistor S2 is connected to the block selection line GSL, and a so-called NAND type memory cell block 1 is formed.

  FIG. 4B shows a structure in which three memory cell blocks 1 shown in FIG. 4A are arranged in parallel. In particular, in FIG. 4B, only the structure below the control gate electrode is shown for easy understanding of the cell structure. Here, the block selection lines SSL and GSL of the selection gate are formed to be connected to adjacent cells in the horizontal direction of the drawing by a conductor in the same layer as the charge storage layer of the control wirings WL0 to WL15 of the memory cell element. Here, the memory cell block 1 may have at least one block selection line SSL, GSL, and is preferably formed in the same direction as the data selection lines WL0 to WL15 for high density.

  In FIG. 4B, three data transfer lines BL are arranged in the vertical direction of the drawing in the direction perpendicular to the data selection lines WL0 to WL15. A bit line contact 2 is disposed in the vicinity of the block selection line SSL of each data transfer line BL. Further, a source line contact 3 is disposed in the vicinity of the block selection line GSL of each data transfer line BL. By forming the data selection lines in this way, the line / space pattern of the control gate becomes regular, and the processing becomes easy.

Although FIG. 4A shows an example in which 16 memory cell transistors are connected to the memory cell block 1, that is, the power cell number of 2 is the number of memory cells connected to the data transfer line and the data selection line. May be any number, and 32 or 2 ⁿ (n is a positive integer) is desirable for address decoding.

  Data is stored, for example, by applying a high voltage of, for example, 10 to 25 V between the control gate and the semiconductor substrate, the charge moves through the tunnel insulating film, and the amount of charge in the insulating film or floating gate serving as the charge storage layer This is done by changing By changing the amount of charge in the charge storage layer, the threshold voltage of the memory cell transistor changes. By detecting this, data can be read out.

  FIG. 5A shows a cross section on the “AB” line which is the column direction in FIG. FIG. 5B shows a cross section on the “CD” line which is the row direction in FIG.

  FIG. 5A is a cross-sectional view when a MONOS memory cell transistor using an insulating film such as a silicon nitride film as a charge storage layer is used.

  An N-type well 5 is formed on the P-type semiconductor substrate 4. A P-type well 6 is formed on the N-type well 5. Each transistor is formed on the same P-type well 6.

Here, the P-type well 6 is formed, for example, with a boron impurity concentration between 10 ¹⁴ cm ⁻³ and 10 ¹⁹ cm ⁻³ . On this P-type well 6, for example, a charge storage layer 8 made of, for example, SiN or SiON is 3 nm through a tunnel gate insulating film 7 made of a silicon oxide film or an oxynitride film having a thickness of 1 to 10 nm. To a thickness of 50 nm.

  On top of this, for example, a stack structure of polysilicon, WSi (tungsten silicide) and polysilicon, NiSi, MoSi, TiSi, and the like via a block insulating film 9 made of a silicon oxide film having a thickness of 2 nm to 10 nm, for example. The control gate 10 having a stack structure of CoSi and polysilicon, a stack structure of metal and polysilicon, or a single layer structure of metal, polysilicon, WSi, NiSi, MoSi, TiSi, CoSi, etc. has a thickness of 10 nm to 500 nm. Is formed.

  A gate cap insulating film 11 is formed on the control gate 10. A side surface of the laminated structure of the gate cap insulating film 11, the control gate 10, the block insulating film 9, the charge storage layer 8, and the tunnel insulating film 7 is made of, for example, a silicon nitride film or a silicon oxide film having a thickness of 5 nm to 200 nm. A gate sidewall insulating film 12 is formed, and a memory cell gate 13 is formed therefrom.

  The control gate 10 is formed up to the block boundary in the horizontal direction of the paper so as to be connected by the adjacent memory cell blocks in FIG. 4B, and the data selection lines WL0 to WL15 and the selection gate control lines SSL and GSL are connected to each other. Forming.

  Note that it is desirable that the P-type well 6 can be applied with voltage independently from the P-type semiconductor substrate 4 by the N-type well 5 in order to reduce the booster circuit load during erasing and to reduce power consumption.

A source / drain N type diffusion layer 14 is formed on both sides of the memory cell gate 13 with a gate sidewall insulating film 12 interposed therebetween. The source / drain N-type diffusion layer 14, the charge storage layer 8, and the control gate 10 form a MONOS type nonvolatile EEPROM cell. The gate length of the charge storage layer is 0.5 μm or less and 0.01 μm or more. To do. The source / drain N-type diffusion layer 14 is formed of, for example, phosphorus, arsenic, and antimony at a depth of 10 nm to 500 nm so that the surface concentration is 10 ¹⁷ cm ⁻³ to 10 ²¹ cm ⁻³ .

  Further, these source / drain N-type diffusion layers 14 are connected in series between the memory cells to realize NAND connection. In FIG. 5A, the gate electrode 15 is connected to a block selection line corresponding to the selection gate control line GSL, and the gate electrode 16 is connected to a block selection line corresponding to the selection gate control line SSL. The gate electrodes 15 and 16 are formed in the same layer as the control electrode 10 of the memory cell gate 13 of the memory cell transistor of the MONOS type EEPROM.

  These gate electrodes 15 and 16 are opposed to the P-type well 6 via a gate insulating film 17 made of, for example, a silicon oxide film or an oxynitride film having a thickness of 3 to 15 nm to form a MOS transistor.

  Here, the gate length of the gate electrodes 15 and 16 is longer than the gate length of the memory cell gate 13, for example, by forming it as 1 μm or less and 0.02 μm or more, the ON / OFF ratio at the time of block selection and non-selection is increased. Can be ensured, and erroneous writing and erroneous reading can be prevented.

  The N-type diffusion layer 18 serving as a source or drain electrode formed on one side of the gate electrode 16 is connected to a data transfer line 19 and a contact 20 made of, for example, tungsten, tungsten silicide, titanium, titanium nitride, or aluminum. Connected.

  Here, the data transfer line 19 (BL) is formed up to the memory cell block boundary in the vertical direction of FIG. 4B so as to be connected by adjacent memory cell blocks.

  On the other hand, the source / drain N type diffusion layer 21 formed on one side of the gate electrode 15 is connected to the source line 23 (SL) via the contact 22.

  The source line 23 (SL) is formed up to the block boundary in the left-right direction of FIG. 4B so as to be connected by adjacent memory cell blocks. These contacts 20 and 22 are, for example, filled with N-type or P-type doped polysilicon, tungsten, tungsten silicide, Al, TiN, Ti, or the like to form a conductor region.

Further, the space between the source line 23, the data transfer line 19 and the P-type well 6 is filled with an interlayer film 24 made of, for example, SiO ₂ or SiN.

Further, an insulating film protective layer 25 made of, for example, SiO ₂ , SiN, or polyimide is formed on the upper portion of the data transfer line 19. An upper wiring made of W, Al or Cu is formed.

  The cross section shown in FIG. 5B shows a state in which each gate electrode 13 is isolated and insulated in the element isolation region 26. A data transfer line 19 is formed directly above each memory cell gate 13 via an interlayer film 24.

  In this embodiment, since the MONOS type cell is used, the writing voltage and the erasing voltage can be lowered as compared with the floating gate type EEPROM cell, and even if the element isolation interval is narrowed and the gate insulating film thickness is reduced. The breakdown voltage can be maintained.

  Therefore, the area of the circuit to which the high voltage is applied can be reduced, and the chip area can be further reduced. Furthermore, compared to the floating gate type memory cell, the thickness of the charge storage layer 8 can be reduced to 20 nm or less, the aspect during gate formation can be further reduced, the processing shape of the gate electrode can be improved, and the gate of the interlayer film 24 can be improved. In addition, the embedding can be improved, and the breakdown voltage can be further improved.

  Further, the process for forming the floating gate electrode and the slit creation process are unnecessary, and the process steps can be further shortened. In addition, since the charge storage layer 8 is an insulator and charges are trapped in each charge trap, it is possible to impart a strong resistance to radiation that is difficult to escape. Furthermore, even if the sidewall insulating film 12 of the charge storage layer 8 is thinned, good retention characteristics can be maintained without any charges trapped in the charge storage layer 8 being lost.

  The NAND memory can be highly integrated, and the NOR memory can perform a random access operation. Further, the AND memory can be highly integrated. In addition, the MONOS type memory can operate at a low voltage. On the other hand, the floating gate type memory has better data retention characteristics than the MONOS type memory. This embodiment is effective particularly in a NAND MONOS type memory in order to improve read disturb in the sense of improving the weak point.

  (First Modification of First Embodiment) FIG. 6A is an equivalent circuit diagram of a memory cell block 27 using MONOS type cells. This is different from the equivalent circuit diagram in the first embodiment shown in FIG. 1A only in that the selection transistors S1 and S2 are not MONOS transistors but MOS transistors, and the others are the same. The top view is as shown in FIG. 5B, the cross section on the “AB” line is shown in FIG. 6B, but the cross section on the “CD” line is the same as the structure shown in FIG. 5B. is there.

  FIG. 6B shows a cross-sectional view when the selection transistor has the same MONOS structure as the memory cell. In this case, the manufacturing process is reduced because the process for making the selection transistor and the memory cell transistor can be omitted, and the distance between the selection transistor and the memory cell is reduced because it is not necessary to have a margin for making the selection transistor. The device area can be reduced. If it is made separately, lithography is required for that purpose, and it is necessary to take a margin for misalignment of the mask. However, if it is not made separately, it is not necessary to take the allowance for alignment, so that the miniaturization is advanced accordingly.

  (Second Modification of First Embodiment) This modification is a case where a floating gate type memory structure using a conductor such as polysilicon doped with impurities as a charge storage layer is used.

  An equivalent circuit of this modification is as shown in FIG. 1A or FIG. 6A, and a top view thereof is as shown in FIG. 4B. A cross section on the “AB” line in FIG. 4B is shown in FIG. 7A, and a cross section on the “CD” line is shown in FIG. 7B.

As shown in FIG. 7A, an N-type well 5 is formed on a P-type semiconductor substrate 4 and, for example, a boron impurity concentration of 10 ¹⁴ cm ⁻³ to 10 ¹⁹ cm ⁻³ is formed thereon. For example, phosphorus or arsenic is added from 10 ¹⁸ cm ⁻³ to the P-type well 6 through a tunnel gate insulating film 30 formed of, for example, a silicon oxide film or oxynitride film having a thickness of 3 to 15 nm. A charge storage layer 31 made of added polysilicon is formed with a thickness of 10 nm to 500 nm between 10 ²¹ cm ⁻³ .

  These are formed in a self-aligned manner with the P-type well 6 on a region where the element isolation insulating film 26 made of, for example, a silicon oxide film is not formed as shown in FIG. 7B. This is because, for example, the tunnel gate insulating film 30 and the charge storage layer 31 are deposited on the entire surface of the P-type well 6 and then patterned to reach the P-type well 6. It can be formed by etching to a depth of 2 mm and embedding an insulating film.

  As described above, since the tunnel gate insulating film 30 and the charge storage layer 31 can be entirely formed on a flat surface without a step, it is possible to perform film formation with improved uniformity and uniform characteristics. Thus, it is preferable to employ a process in which the gate electrode is formed before the element isolation region. Here, when the tunnel gate insulating film 30 and the charge storage layer 31 are formed after the element isolation region is formed, it is difficult to form it uniformly because of the step of the element isolation region.

On this, for example, phosphorus, arsenic, for example, via a silicon oxide film or oxynitride film having a thickness of 5 nm to 30 nm, or an interpoly insulating film 32 made of silicon oxide film / silicon nitride film / silicon oxide film. , Or polysilicon doped with 10 ¹⁷ to 10 ²¹ cm ⁻³ of boron, or a stack structure of WSi (tungsten silicide) and polysilicon, a stack structure of NiSi, MoSi, TiSi, CoSi and polysilicon, a metal and A control gate 33 having a stack structure with polysilicon or a single layer structure of metal, polysilicon, WSi, NiSi, MoSi, TiSi, CoSi or the like is formed with a thickness of 10 nm to 500 nm.

  The control gate 33 is formed up to the block boundary in the horizontal direction in FIG. 4B so as to be connected by adjacent memory cell blocks in FIG. 4A, and forms data selection lines WL0 to WL15. ing. Note that it is desirable that the P-type well 6 can be applied with a voltage independently of the P-type semiconductor substrate 4 by the N-type well 5 in order to reduce the load on the booster circuit at the time of erasing and to suppress power consumption. . A gate cap insulating film 34 is formed on the control gate 33.

  The side surfaces of the gate cap insulating film 34, the control gate 33, the interpoly insulating film 32, the charge storage layer 31, and the tunnel gate insulating film 30 are gate sidewall insulating made of a silicon nitride film or a silicon oxide film having a thickness of 5 nm to 200 nm, for example. Covered with film 35, these form memory cell gates 36.

  As shown in FIG. 7A, source / drain N-type diffusion layers 37 are formed on both sides of these memory cell gates 36 with a gate sidewall insulating film 35 interposed therebetween. The source / drain N-type diffusion layer 37 and the memory cell gate 36 form a floating gate type EEPROM cell in which the amount of charge stored in the charge storage layer 31 is an information amount. 5 μm or less and 0.01 μm or more.

The source / drain N-type diffusion layer 37 is formed of, for example, phosphorus, arsenic, and antimony at a depth of 10 nm to 500 nm so that the surface concentration is 10 ¹⁷ to 10 ²¹ cm ⁻³ . Further, these source / drain N-type diffusion layers 37 are shared by adjacent memory cells to realize NAND connection.

  7A, the gate electrode 38 is connected to the selection gate control line SSL in FIG. 4B, and the gate electrode 39 is connected to the selection gate control line GSL. These gate electrodes are formed in the same layer as the memory cell gate 36 of the floating gate type EEPROM.

  The gate lengths of the gate electrodes 38 and 39 are longer than the gate length of the memory cell gate 36. For example, by forming the gate electrodes 38 and 39 at 1 μm or less and 0.02 μm or more, a large on / off ratio can be ensured when the block is selected and when it is not selected Incorrect writing and erroneous reading can be prevented.

  The source / drain N type diffusion layer 18 formed on one side of the gate electrode 38 is connected to a data transfer line 19 made of, for example, tungsten, tungsten silicide, titanium, titanium nitride, or aluminum via a contact 20. ing. Here, the data transfer line 19 is formed up to the block boundary in the vertical direction of the paper in FIG. 4B so as to be connected by adjacent memory cell blocks.

  On the other hand, the source / drain N type diffusion layer 21 formed on one side of the gate electrode 39 is connected to the source line 23 via a contact 22. The source line 23 is formed up to the block boundary in the left-right direction in FIG. 4B so as to be connected by adjacent memory cell blocks.

The contacts 20 and 22 are, for example, filled with polysilicon or tungsten doped with N-type or P-type, tungsten silicide, Al, TiN, Ti, or the like to form a conductor region. Further, the space between the data transfer line 19 and the P-type well 6 is filled with an interlayer film 24 made of, for example, SiO ₂ or SiN.

Further, an insulating film protective layer 25 made of, for example, SiO ₂ , SiN, or polyimide is formed on the data transfer line 19. An upper wiring made of, for example, W, Al, or Cu is formed thereon, although not shown in the drawing.

  In this modification, the write / erase threshold is both positive for the data storage state of the memory cell. Alternatively, the threshold values of all memory cells in the written state and the threshold values of some memory cells in the erased state are positive. Therefore, it is possible to improve the decrease in the threshold window due to the read disturb in which the erased memory cell rises by the repeated read operation. Further, since the erase threshold is positive, it is not necessary to handle a negative voltage during the erase verify operation, and the peripheral circuit can be simplified.

  (Second Embodiment) FIGS. 8 and 9 show a data storage state in the second embodiment of the present invention. As shown in FIG. 8, what is characteristic of this embodiment is that negative charge (electrons) is stored in the charge storage layer in both cases of writing and erasing of the memory cell. In other words, the threshold value in either the writing or erasing state is higher than the neutral threshold value (threshold value of the memory cell when there is no charge in the charge storage layer) Vthi.

  In FIG. 8A, the horizontal axis represents the number of memory cells, and the vertical axis represents the threshold value. In the written state, all memory cell distributions have threshold values larger than Vref. In the erased state, the distribution of memory cells is smaller than Vref and within a range larger than Vthi.

  FIG. 8B shows the charge state of the memory cell gate in the written state. A source / drain diffusion layer 51 is provided in the semiconductor substrate 50, a charge storage layer 52 is provided on the semiconductor substrate 50 sandwiched between the source / drain diffusion layers 51, and a control gate 53 is provided on the charge storage layer 52. Is provided. Here, a state in which a large number of negative charges are accumulated in the charge accumulation layer 52 is shown.

  FIG. 8C shows the charge state of the memory cell gate in the erased state. The state in which the amount of negative charges stored in the charge storage layer 52 is smaller than that in the writing state is shown.

  Further, as shown in FIG. 9, the characteristic feature of the alternative example of this embodiment is that negative charges (electrons) are accumulated in the charge storage layer of all memory cells in the written state and in a part of the erased state. Yes. That is, the threshold distribution in the erased state crosses the neutral threshold Vthi. That is, the neutral threshold value exists in the range of the erase threshold distribution.

  In FIG. 9A, the horizontal axis represents the number of memory cells and the vertical axis represents the threshold value. In the written state, all memory cell distributions have threshold values larger than Vref. In the erased state, the distribution of the memory cells is smaller than Vref and extends in both the large state and the small state across Vthi.

  FIG. 9B shows the charge state of the memory cell gate in the written state. Here, a state in which a large number of negative charges are accumulated in the charge accumulation layer 52 is shown.

  FIG. 9C shows a case where the threshold value is higher than Vthi in the charge state of the memory cell gate in the erased state. The state in which the amount of negative charges stored in the charge storage layer 52 is smaller than that in the writing state is shown.

  FIG. 9D shows a case where the threshold value is lower than Vthi in the charge state of the memory cell gate in the erased state. Here, a state where a small number of positive charges are stored in the charge storage layer 52 is shown.

  Here, the erasing operation is performed, for example, by applying a high voltage, for example, 10 to 25 V to the semiconductor substrate with the control gate at 0 V, and discharging negative charges from the charge storage layer to the substrate. Alternatively, the drain potential is negatively biased with respect to the source potential to generate hot holes accelerated in the channel, and the gate electrode is negatively biased with respect to the source potential to inject the hot holes into the charge storage layer. Done in

  For example, the writing operation is performed by injecting a negative charge from the semiconductor substrate to the charge storage layer by applying a high voltage, for example, 10 to 25 V to the control gate with the semiconductor substrate at 0V. Alternatively, the drain potential is positively biased with respect to the source potential to generate hot electrons accelerated in the channel, and the gate electrode is positively biased with respect to the source potential to inject the hot electrons into the charge storage layer. Done in

  Next, FIG. 10A shows a data read operation in the case where this embodiment is applied to a NAND-type EEPROM. The configuration of the memory cell block 1 is the same as the configuration shown in FIG. 4A, and the potential application state is different.

  First, the bit line BL is precharged and then brought into a floating state. Next, the voltage of the control gate of the memory cell M2 selected for reading is set to the reading voltage Vref. The control gate voltages of the memory cells M0, M1, M3 to M15 other than the memory cell M2 are set to the unselected read voltage Vread, the gate voltages of the two select transistors S1 and S2 are set to the read voltage Vref, and the source line Source is set to 0V. The bit line BL detects whether or not a current flows through the memory cell M2 selected for reading.

  That is, if the threshold value Vth of the selected memory cell M2 is larger than Vref, the selected memory cell M2 is turned off, so that the bit line BL maintains the precharge potential.

  On the other hand, if the threshold value Vth of the selected memory cell M2 is a read state smaller than Vref, the memory cell is turned on, so that the potential of the bit line BL decreases by ΔV from the precharge potential. Data in the memory cell is read by detecting this potential change with a sense amplifier.

  Here, Vref is an intermediate voltage between the write state threshold and the erase state threshold, Vread is a voltage higher than the write state threshold, and Vcc is a voltage higher than the threshold of the selection transistor.

  Next, a data read operation when applied to an AND-type EEPROM will be described with reference to FIG.

  In the AND type EEPROM, a plurality of memory cell transistors M0 are connected in parallel between the other end of the selection transistor S1 having one end connected to the bit line BL and the other end of the selection transistor S2 having one end connected to the source line Source. To M15 are connected to form a memory cell block 55.

  First, the bit line BL is precharged and then brought into a floating state. Next, the voltage of the control gate of the memory cell M2 selected for reading is set to the reading voltage Vref. The voltage of the control gate of the memory cells other than the memory cell M2 selected for reading is set to the non-selected reading voltage Vread.

  Next, the gate voltage of the selection transistor S1 is set to the power supply voltage Vcc, the source line Source is set to 0 V, and the bit line BL detects whether or not a current flows through the memory cell M2 selected for reading.

  That is, if the threshold value Vth of the selected memory cell M2 is larger than Vref, the selected memory cell M2 is turned off and the bit line BL maintains the precharge potential.

  On the other hand, if the threshold value Vth of the selected memory cell M2 is a read state smaller than Vref, the selected memory cell M2 is turned on, so that the potential of the bit line BL is lowered by ΔV from the precharge potential.

  By detecting this potential change with a sense amplifier (not shown) in a data circuit (not shown), data in the memory cell is read out. Here, Vref indicates a voltage intermediate between the write state threshold and the erase state threshold, Vread is a voltage lower than the erase state threshold, and Vcc is a voltage higher than the threshold of the selection transistor.

  Next, a data read operation when applied to a NOR type EEPROM will be described with reference to FIG. In the NOR type EEPROM, one end of the selected memory cell transistor M2 is connected to the other end of the memory cell transistor M1 whose one end is connected to the first bit line BL1, and the other end is connected to the first bit line BL1. . Similarly, one end of the memory cell transistor M3 is connected to the other end of the selected memory cell transistor M1. Thus, the memory cell block 56 is configured by the memory cell transistors M1 to M3.

  A second bit line BL2 is provided in parallel with the first bit line BL1, and a plurality of memory cell transistors M4 to M6 are connected like the first bit line BL1. First, the selected bit line BL1 is set in a floating state after being set in a precharged state. Next, the voltage of the control gate of the memory cell M2 selected to be read is set to the read voltage Vref, the voltage of the control gate of the memory cells other than the memory cell M2 selected to be read is set to the unselected read voltage Vread, and the source A data read operation is performed by detecting whether or not a current flows through the memory cell M2 selected for reading with the selected bit line BL1 with the line voltage set to Vsl.

  That is, if the threshold value Vth of the selected memory cell M2 is in a write state larger than Vref, the selected memory cell M2 is turned off, so that the selected bit line BL maintains the precharge potential.

  On the other hand, if the threshold value Vth of the selected memory cell M2 is a read state smaller than Vref, the selected memory cell M2 is turned on, so that the potential of the bit line BL is lowered by ΔV from the precharge potential.

  By detecting this potential change with a sense amplifier (not shown) in a data circuit (not shown), data in the memory cell is read out. Here, Vref indicates an intermediate voltage between the threshold value in the write state and the threshold value in the erase state, Vread is a voltage lower than the threshold value in the erase state, and Vsl is normally 0V.

  Note that in the equivalent circuit diagrams shown in FIGS. 10A and 10B, the selection transistor has a structure different from that of the memory cell. However, similarly to the memory cell, a nonvolatile memory structure having a charge storage layer may be used. . As the structure of the memory cell, a floating gate type memory cell, a MONOS type memory cell, or the like can be applied.

  The effect of this embodiment will be described with reference to FIG. FIG. 11 shows the data retention characteristics of the nonvolatile memory cell. In FIG. 11A, the horizontal axis represents data retention time, and the vertical axis represents threshold value Vth. FIG. 11A shows data of a semiconductor memory device having a structure of a charge storage layer 59 provided above a pair of source / drain diffusion layers 58 provided in a semiconductor substrate 57 and a control gate 60 provided thereon. Represents retention characteristics.

  In FIG. 11A, the solid line indicated by (1) corresponds to the state as shown in FIG. That is, this corresponds to a state where a lot of negative charges are accumulated in the charge accumulation layer 59.

  In FIG. 11A, the solid line indicated by (2) corresponds to the state shown in FIG. That is, this corresponds to a state where a small amount of negative charge is accumulated in the charge accumulation layer 59.

  In FIG. 11A, the solid line indicated by (3) corresponds to the state shown in FIG. That is, this corresponds to a state where a large amount of positive charge is accumulated in the charge accumulation layer 59.

  In FIG. 11A, the broken line indicated by (4) corresponds to the state shown in FIG. 11D before repeated rewriting.

  Here, the charge accumulated in the charge storage layer leaks over a long time, and finally converges to zero charge, that is, the neutral threshold value Vthi. The inventor has found that the charge retention characteristics of negative carriers (electrons) and positive carriers (holes) are different in the charge storage layer of the nonvolatile memory.

  This is particularly noticeable in data retention after repeated writing and erasing, and the result is that the charge retention characteristics of holes are inferior to those of electrons. This characteristic shows that in FIG. 11A, negative carriers are accumulated (1), (2) the solid line state is not changed so much as the retention time elapses. The state of the solid line (3) is represented by the fact that it rapidly approaches Vthi as the holding time elapses.

  For this reason, the method of accumulating electrons at the time of writing and accumulating holes at the time of erasing as has been conventionally performed has a problem that the lifetime of the device is determined by the threshold fluctuation of the hole accumulation state inferior in charge retention.

  On the other hand, in this embodiment, since negative charges are accumulated even in the erased state, data retention characteristics can be improved.

  Next, the effect when this embodiment is applied to a MONOS type memory cell will be described with reference to FIG. Here, a case where the tunnel oxide film is 4 nm or less and direct tunneling of holes on the entire surface of the channel is used for erasing will be described. If the thickness of the tunnel oxide film is about 5 nm to 6 nm, the erase operation is performed using hot holes. The insulating film thickness can be measured using a TEM (Transmission Electron Microscope) or the like.

  FIG. 12A shows erase characteristics in the MONOS type memory cell. In FIG. 12A, the horizontal axis is the erase time, and the vertical axis is the threshold value Vth. Here, the characteristics are shown for the absolute values of the four types of erase voltages. Here, Vera1 has a larger absolute value than Vera2, Vera2 has a larger absolute value than Vera3, and Vera3 has a larger absolute value than Vera4.

  The saturation erase depth (the amount of fluctuation of the erase threshold) is determined by the balance between the positive charge injection from the semiconductor substrate and the negative charge injection from the gate electrode, but the saturation erase depth becomes shallower as the erase voltage is higher. For this reason, in order to erase deeply, it is necessary to set the erasing voltage low, and the erasing time becomes long. Therefore, it is desirable to reduce the erase depth in order to shorten the erase time. In this embodiment, since the negative charge is accumulated in the charge storage layer even in the erased state, the electric field in the block oxide film is not strengthened by the positive charge in the charge storage layer. No charge is injected.

  Therefore, by changing the absolute value of the erase voltage from Vera2 to Vera1 and changing the erase threshold value from Vthe2 to Vthe1 and setting it higher than the neutral threshold value, the erase time is changed from Tera2 to Tera1 and shortening is realized.

  The erase characteristic mechanism after the erase time Tera2 when this erase voltage is Vera1 is shown in FIG.

  As shown in FIG. 12B, erasing of the MONOS type memory cell is performed by injecting positive charges from the semiconductor substrate Sub to the charge storage layer (silicon nitride film SiN) as indicated by a right-pointing arrow. At this time, the gate electrode gate is negatively biased when viewed from the semiconductor substrate Sub.

When positive charges (holes) are accumulated in the charge storage layer SiN during the erase operation, the electric field in the tunnel oxide film (Tunnel SiO ₂ ) is relaxed by the self electric field created by the holes, and the charge storage layer SiN is removed from the semiconductor substrate Sub. The amount of holes injected into the substrate decreases.

On the other hand, the electric field in the block oxide film BlockSiO ₂ between the charge storage layer SiN and the gate electrode gate is strengthened, and unnecessary negative charges are injected from the gate electrode gate to the charge storage layer SiN as indicated by the left-pointing arrow. The

  FIG. 13A shows experimental data by the inventors on the dependency of the data retention characteristics on the charge storage layer SiN film thickness in the MONOS type memory cell. The inventor obtained the result that the data retention characteristic in the positive charge accumulation state depends on the SiN film thickness, and the deterioration of the data retention characteristic is remarkable especially in the region where the SiN film thickness is 15 nm or less, especially 12 nm or less. Here, the positive charge accumulation state corresponds to a state in which a slightly larger positive charge is accumulated in the charge accumulation layer 59 on the semiconductor substrate 57 as shown in FIG.

  On the other hand, the data retention characteristics in the negative charge accumulation state did not depend on the SiN film thickness, and no deterioration of the data retention characteristics was observed even when the SiN film was thinned. Here, the negative charge accumulation state corresponds to a state in which a large amount of negative charge is accumulated in the charge accumulation layer 59 on the semiconductor substrate 57 as shown in FIG.

  In this embodiment, since a negative charge accumulation state is used for both writing and erasing, even if the SiN film is thinned for the purpose of lowering the writing and erasing voltage, there is no deterioration in data retention characteristics, which is advantageous for lowering the voltage. It is. This is particularly effective when the physical film thickness of the SiN film is 15 nm or less, particularly 12 nm or less, and the write / erase voltage can be reduced to 20 V or less.

  Further, in the present embodiment, since positive charges are not accumulated in the erased state, reliability deterioration due to repeated rewriting can be avoided.

  Therefore, from these points, it can be said that the effect of this example is particularly great in the MONOS type cell using the SiN film as the charge storage layer.

  Here, in the first embodiment, this embodiment can be realized by performing an operation of accumulating negative charges.

  4 to 7 described in the first embodiment can be applied as they are to the equivalent circuit diagram, the top view, and the cross-sectional view when the present embodiment is applied to a NAND type EEPROM.

  (First Modification of Second Embodiment) This modification will be described with reference to FIGS. 14, 15, and 16 when applied to a NOR type EEPROM instead of a NAND type EEPROM. FIG. 14A shows an equivalent circuit diagram of a NOR type EEPROM. In the NOR type EEPROM, one end of the memory cell transistor M1 is connected to the other end of the memory cell transistor M0 having one end connected to the first bit line BL1, and the other end is connected to the first bit line BL1. Similarly, one end of the memory cell transistor M2 is connected to the other end of the memory cell transistor M1.

  In the NOR memory cell, a memory cell block is formed by one transistor. Each transistor is formed on the same well. The control electrode of each memory cell is connected to data selection lines WL0 to WL2.

  A second bit line BL2 is provided in parallel with the first bit line BL1, and a plurality of memory cell transistors M0 'to M2' are connected like the first bit line BL1.

  A top view of this NOR type EEPROM is shown in FIG. In particular, in FIG. 14B, only the structure below the gate electrode is shown for easy understanding of the cell structure. In FIG. 14B, three bit lines BLi (i is a natural number) are arranged in the vertical direction in the figure, and two common source lines SL are arranged orthogonal to them. Further, the word lines WL0 to WL2 are arranged in parallel to the common source line SL. A bit line contact 61 is provided on each bit line BLi at a portion not intersecting with the word lines WL0 to WL2.

Next, FIG. 15 shows a cross-sectional view in the case of a floating gate on the “AB” line of FIG. 14B in a NOR type EEPROM. Similar to FIG. 7A, an N-type well 5 is formed on a P-type semiconductor substrate 4, a P-type well 6 is formed thereon, and a silicon oxide having a thickness of 3 to 15 nm is formed thereon. Through the tunnel gate insulating film 30 formed of a film or an oxynitride film, for example, a charge storage layer 31 made of polysilicon doped with phosphorus or arsenic at 10 ¹⁸ to 10 ²¹ cm ⁻³ has a thickness of 10 nm to 500 nm. Is formed.

  These are formed in a self-aligned manner with the P-type well 6 on a region where the element isolation insulating film 26 made of, for example, a silicon oxide film is not formed as shown in FIG. 7B. On top of this, WSi (tungsten silicide) and a silicon oxide film or oxynitride film having a thickness of 5 nm to 30 nm, or an interpoly insulating film 32 made of silicon oxide film / silicon nitride film / silicon oxide film are formed. A control gate 33 having a stack structure of polysilicon, a stack structure of CoSi and polysilicon, a stack structure of metal and polysilicon, or a single layer structure of metal, polysilicon, WSi, NiSi, MoSi, TiSi, CoSi, etc. It is formed with a thickness of 10 nm to 500 nm.

  A gate cap insulating film 34 is formed on the control gate 33.

  Side surfaces of the gate cap insulating film 34, the control gate 33, the interpoly insulating film 32, the charge storage layer 31, and the tunnel gate insulating film 30 are covered with a gate sidewall insulating film 35, and these form a gate electrode 36. The gate length is 0.5 μm or less and 0.01 μm or more.

  As shown in FIG. 15, an N-type diffusion layer 37 serving as a source or drain electrode is formed on one side of these gate electrodes 36 with a gate sidewall insulating film 35 interposed therebetween. On the other side of the gate electrode 36, an N-type diffusion layer 18 serving as a source or drain electrode connected to the data transfer line 19 via the contact 61 with the gate sidewall insulating film 35 interposed therebetween is formed. The N-type diffusion layers 18 and 37 and the gate electrode 36 form a floating gate type EEPROM cell in which the amount of charge stored in the charge storage layer 31 is an information amount.

  These source / drain N-type diffusion layers 18 and 37 are shared by adjacent memory cells, and a NOR connection is realized.

Further, the space between the data transfer line 19 and the P-type well 6 is filled with an interlayer film 24 made of, for example, SiO ₂ or SiN and having a thickness of, for example, 5 nm to 200 nm.

  Further, an insulating film protective layer 25 is formed on the data transfer line 19. An upper wiring is formed thereon, although not shown in the figure. Note that a cross-sectional view of the floating gate on the “CD” line in FIG. 14B is the same as the structure shown in FIG.

  Next, the configuration when this modification is applied to a MONOS gate by a NOR type EEPROM will be described with reference to FIG.

  In this modification, the equivalent circuit diagram is the same as FIG. 14A, the top view is the same as FIG. 14B, and the cross section on the “AB” line in FIG. This corresponds to FIG. 16, and the cross section on the “CD” line in FIG. 14B is the same as FIG. 5B.

  In the cross section shown in FIG. 16, the structure of the gate electrode 13 of MONOS type shown in FIG. 5A is used in place of the structure of the gate electrode 36 of floating gate type in FIG. Is the same as FIG.

  (Second Modification of Second Embodiment) This modification is an example applied to an AND-type EEPROM. 17 and 18 show an example in the case of having a floating gate type memory cell structure.

  FIG. 17A shows an equivalent circuit diagram of the AND memory cell array. Non-volatile memory cells M0 to M15 made of MOS transistors having floating gate electrodes have current terminals connected in parallel, and one end connected to a data transfer line BL via a select transistor S1. The other end is connected to the common source line SL via the selection transistor S2. Each transistor is formed on the same well.

  The control electrodes of the respective memory cells M0 to M15 are connected to data selection lines WL0 to W15. Further, in order to select one memory cell block from a plurality of memory cell blocks along the data transfer line and connect it to the data transfer line, the control electrode of the selection transistor S1 is connected to the block selection line SSL.

  Further, the control electrode of the selection transistor S2 is connected to the block selection line GSL to form an AND type memory cell block 65 (dotted line region). In this modification, an example in which 16 memory cells, that is, 2 4 memory cells, are connected to the memory cell block 65 is shown. However, the memory cell blocks 65 are connected to the data transfer lines BL and the data selection lines WL0 to W15. The number may be plural, and it is desirable for address decoding to be 2 n (n is a positive integer).

  Further, FIG. 17B shows a top view of the memory cell block 65, and only the structure below the gate electrode is shown for easy understanding of the cell structure. In FIG. 17B, a bit line contact 66 is provided on the block selection line SSL extending in the left-right direction, and a potential is applied from the bit line BL extending in the up-down direction in FIG. This is applied to the diffusion layer of the selection transistor S1. In addition, a common source line contact 67 is provided below the block selection line GSL extending in the left-right direction in FIG. 17B, and a potential is applied from the common source line SL to the selection transistor S2.

18A shows a cross section taken along the line “AB” in FIG. 17B, and FIG. 18B shows a cross section taken along the line “CD” in FIG. 17B. For example, it is made of, for example, polysilicon added with 10 ¹⁸ to 10 ²¹ cm ^{−3 of} phosphorus or arsenic through a tunnel gate insulating film 30 formed of a silicon oxide film or oxynitride film having a thickness of 3 nm to 15 nm. The charge storage layer 31 is formed with a thickness of 10 nm to 500 nm. These are formed in a self-aligned manner with the P-type well 6 on a region where the element isolation insulating film 26 made of, for example, a silicon oxide film is not formed.

  On this, an interpoly insulating film 32 made of, for example, a silicon oxide film or oxynitride film having a thickness of 5 nm to 30 nm or a silicon oxide film / silicon nitride film / silicon oxide film is formed. For example, the tunnel gate insulating film 30 and the charge storage layer 31 are deposited on the entire surface of the P-type well 6 and then patterned and etched to a depth of, for example, 0.05 to 0.5 μm until reaching the P-type well 6. It can be formed by embedding an insulating film.

  As described above, the tunnel gate insulating film 30 and the charge storage layer 31 in the memory cell portion can be formed on the entire surface on a plane with few steps, so that film formation with improved uniformity and uniform characteristics can be performed.

  Further, the interlayer insulating film 68 and the N-type diffusion layer 37 in the cell portion are formed by, for example, forming a mask material made of polysilicon in a portion where the tunnel insulating film 30 is formed in advance before forming the tunnel insulating film 30 and performing ion implantation. After the N-type diffusion layer 37 is formed, an interlayer insulating film 68 is deposited on the entire surface, and the mask material in a portion corresponding to the tunnel insulating film 30 is selectively removed by CMP and etch back to form a self-alignment. be able to.

  Furthermore, a stack structure of WSi (tungsten silicide) and polysilicon, a stack structure of CoSi and polysilicon, a stack structure of metal and polysilicon, or a single structure such as metal, polysilicon, WSi, NiSi, MoSi, TiSi, and CoSi. A control gate 33 having a layer structure is formed with a thickness of 10 nm to 500 nm. This control gate 33 is formed up to the block boundary in the left-right direction in FIG. 18B so as to be connected by adjacent memory cell blocks in FIG. 10B, and the data selection lines WL0 to WL15, and Block select line SSL. GSL is formed.

  Note that it is desirable that the P-type well 6 can be applied with a voltage independently of the P-type semiconductor substrate 4 by the N-type well 5 in order to reduce the booster circuit load during erasing and to reduce the power consumption. The P-type well 6 in the memory cell portion is surrounded by the N-type well 5, and when an erasing voltage is applied to the P-type well 6, power consumption can be suppressed because no voltage is boosted except for the memory cell portion.

  As shown in FIG. 18B, an interlayer insulating film 68 made of, for example, a silicon oxide film or an oxynitride film having a thickness of 5 nm to 200 nm is formed below these gate electrodes in the cross section corresponding to the memory cell. An N-type diffusion layer 37 serving as a source or drain electrode is formed on both sides. The N-type diffusion layer 37, the charge storage layer 31, and the control gate 33 form a floating gate type EEPROM cell having the amount of charge stored in the charge storage layer as an information amount, and the gate length is 0 .5 μm or less and 0.01 μm or more.

As shown in FIG. 18B, the interlayer insulating film 68 is also formed on the channel so as to cover the source / drain electrodes 37 in order to prevent abnormal writing due to electric field concentration at the source / drain ends. desirable. The source / drain N-type diffusion layer 37 is formed of, for example, phosphorus, arsenic, and antimony at a depth of 10 nm to 500 nm so that the surface concentration is 10 ¹⁷ to 10 ²¹ cm ⁻³ . Further, these N-type diffusion layers 37 are shared by memory cells adjacent in the direction of the bit line BL, and an AND connection is realized.

  The block selection lines SSL and GSL are connected to the control gate 33. In the block selection line portion, the interpoly insulating film 32 between the charge storage layer 31 and the control gate 33 is peeled off, and the data selection line of the EEPROM. It is formed in the same layer as WL0 to WL15.

  Here, as shown in FIGS. 17B and 18A, the block selection transistor S1 is formed as a MOSFET having an N-type diffusion layer 37 as a source / drain electrode and a control gate 33 as a gate electrode. The block selection transistor S2 is formed as a MOSFET having the N-type diffusion layer 37 as a source / drain electrode and the control gate 33 as a gate electrode.

  Here, the gate length of the gate electrodes of the block selection transistors S1 and S2 is longer than the gate length of the gate electrode of the memory cell. For example, the gate length is 1 μm or less and 0.02 μm or more. A large ON / OFF ratio can be secured, and erroneous writing and erroneous reading can be prevented.

  Next, a case where the charge storage layer has a MONOS type memory cell structure using an insulating film such as SiN will be described.

  FIG. 19A shows an equivalent circuit diagram of an AND memory cell array. Non-volatile memory cells M0 to M15 made of MOS transistors having a MONOS type gate electrode have current terminals connected in parallel, and one end connected to a data transfer line BL via a select transistor S1. The other end is connected to the common source line SL via the selection transistor S2. Each transistor is formed on the same well.

  The control electrodes of the respective memory cells M0 to M15 are connected to data selection lines WL0 to W15. Further, in order to select one memory cell block from a plurality of memory cell blocks along the data transfer line BL and connect it to the data transfer line BL, the control electrode of the selection transistor S1 is connected to the block selection line SSL.

  Further, the control electrode of the selection transistor S2 is connected to the block selection line GSL to form an AND type memory cell block 65 (dotted line region). In this modification, an example in which 16 memory cells, that is, 2 4 memory cells, are connected to the memory cell block 65 is shown. However, the memory cell blocks 65 are connected to the data transfer lines BL and the data selection lines WL0 to W15. The number may be plural, and it is desirable for address decoding to be 2 n (n is a positive integer).

  Further, FIG. 19B shows a top view of the memory block 65, and only the structure below the gate electrode is shown for easy understanding of the cell structure. In FIG. 19B, a bit line contact 66 is provided on the block selection line SSL extending in the left-right direction, and from the bit line BL extending in the up-down direction in FIG. 19B. A potential is applied to the diffusion layer of the selection transistor S1. In FIG. 19B, a common source line contact 67 is provided below the block selection line GSL extending in the left-right direction, and a potential is applied from the common source line SL to the selection transistor S2.

  20A shows a cross section taken along the line “AB” in FIG. 19B, and FIG. 20B shows a cross section taken along the line “CD” in FIG. 19B. For example, via a tunnel gate insulating film 7 made of a silicon oxide film or an oxynitride film having a thickness of 0.5 to 10 nm, for example, a stack structure of polysilicon or WSi (tungsten silicide) and polysilicon, or A control gate 10 having a stack structure of NiSi, MoSi, TiSi, CoSi and polysilicon is formed with a thickness of 10 nm to 500 nm.

  As shown in the cross section of FIG. 20B, on the tunnel gate insulating film 7, a charge storage layer 8 made of, for example, a silicon nitride film is formed with a thickness of 4 nm to 50 nm. On this, for example, a block insulating film 9 made of a silicon oxide film or oxynitride film having a thickness of 2 nm to 30 nm is formed. On the control gate 10, for example, a gate cap insulating film 11 is formed with a polysilicon layer having a thickness of 10 nm to 500 nm. These are regions where the element isolation insulating film 26 made of, for example, a silicon oxide film is not formed. On top, it is formed in self-alignment with the P-type well 6.

  For example, the tunnel gate insulating film 7, the charge storage layer 8, the block insulating film 9, and the control gate 10 are deposited on the entire surface of the P-type well 6 and then patterned until reaching the P-type well 6. It can be formed by etching to a depth of 05 to 0.5 μm and embedding an insulating film. As described above, since the tunnel gate insulating film 7, the charge storage layer 8, and the block insulating film 9 can be formed on the entire surface on a plane with few steps, it is possible to form a film with improved uniformity and uniform characteristics.

  Further, the interlayer insulating film 68 and the N-type diffusion layer 37 in the cell portion are formed by forming a mask material made of polysilicon, for example, in a portion where the tunnel gate insulating film 7 is formed in advance before the tunnel gate insulating film 7 is formed. After the N-type diffusion layer is formed by implantation, an interlayer insulating film 8 is deposited on the entire surface, and the mask material corresponding to the tunnel gate insulating film 7 is selectively removed by CMP (Chemical Mechanical Polishing) and etch back. Can be formed in a self-aligning manner. Since other structures are the same as those in FIG.

  5, 6, 16, and 20 use the MONOS type cell, the write voltage and the erase voltage can be lowered as compared with the floating gate type EEPROM cell, and the element isolation interval is narrowed. The breakdown voltage can be maintained even if the gate insulating film thickness is reduced.

  Therefore, the area of the circuit to which the high voltage is applied can be reduced, and the chip area can be further reduced. Furthermore, compared with the floating gate type memory cell, the thickness of the charge storage layer 8 can be reduced to 20 nm or less in the MONOS type memory cell, the aspect at the time of gate formation can be further reduced, and the processing shape of the gate electrode can be improved. Further, the filling of the interlayer insulating film 24 between the gates can be improved, and the breakdown voltage can be further improved.

  Further, the process for forming the floating gate electrode and the slit creation process are unnecessary, and the process steps can be further shortened. In addition, since the charge storage layer 8 is an insulator and charges are trapped in each charge trap, it is possible to impart a strong resistance to radiation that is difficult to escape.

  19 and 20, the selection transistor has a MOS structure, but may have the same MONOS structure as the memory cell. In this case, the manufacturing process is reduced because the process for making the selection transistor and the memory cell transistor can be omitted, and the distance between the selection transistor and the memory cell is reduced because it is not necessary to have a margin for making the selection transistor. The device area can be reduced.

  Since both the writing state and the erasing state use the negative charge accumulation state, the data retention characteristic of the nonvolatile memory can be improved. In particular, the data retention characteristic in the erased state after repeated rewriting is improved.

  Also, in the MONOS type memory cell, the erase time can be shortened and the deterioration of data retention characteristics due to the thinning of SiN can be avoided, so that it is possible to reduce the thickness of SiN to 12 nm or less. Since it is not used, the reliability after repeated rewriting can be improved.

  Further, when the neutral threshold is higher than 0 V, for example, “the negative charge accumulation state is used in both the writing and erasing states” means that both the writing and erasing thresholds are positive. Therefore, in such a case, the first embodiment has the same effect as the present embodiment.

  (Third Embodiment) FIG. 21A shows a data storage state in the present embodiment. What is characteristic of this embodiment is that the threshold values of both the write state and erase state of the memory cell are higher than the threshold value of the select transistor. In FIG. 21, the horizontal axis indicates the number of memory cells, and the vertical axis indicates the threshold value.

  Here, in the write state, the threshold distribution is larger than Vref both at the upper limit and the lower limit. In the erased state, the threshold distribution is lower than Vref both at the upper and lower limits, and is larger than the threshold Vthsg of the selection transistor.

  In some cases, as shown in FIG. 21B, the threshold values of all memory cells in the writing state and some memory cells in the erasing state are higher than the threshold values of the selection transistors. It is to come again.

  Here, in the writing state, the distribution of the threshold values is larger than Vref both at the upper limit and the lower limit. In the erased state, the threshold distribution has an upper limit smaller than Vref and larger than the threshold Vthsg of the selection transistor. The lower limit is a value smaller than Vthsg.

  Next, a read operation when this embodiment is applied to a NAND-type EEPROM will be described with reference to FIG. The bit line BL is precharged and then floated, the voltage of the control gate of the memory cell M2 selected for reading is set to the read voltage Vref, and the voltages of the other control gates of the memory cells M0, M1, M3 to M15 are unselected read voltages. This is done by detecting whether or not a current flows through the memory cell M2 selected for reading, with Vread, the gate voltage of the selection transistors S1 and S2 being the power supply voltage Vcc and the source line being 0V.

  That is, if the threshold value Vth of the memory cell M2 selected for reading is in a writing state larger than Vref, the memory cell is turned off, so that the bit line BL maintains the precharge potential.

  On the other hand, if the threshold value Vth of the memory cell M2 selected for reading is in a read state smaller than Vref, the memory cell is turned on, so that the potential of the bit line BL decreases by ΔV from the precharge potential. Data in the memory cell is read by detecting this potential change with a sense amplifier in a data circuit (not shown).

  Here, Vref is an intermediate voltage between the write state threshold and the erase state threshold, Vread is a voltage higher than the write state threshold, and Vcc is a voltage higher than the threshold of the selection transistor.

  Further, Vref may be applied as the voltage applied to the gates of the selection transistors S1 and S2 as shown in FIG.

  Further, as shown in FIG. 22C, the selection gates S1. Vread may be given to S2.

  In FIG. 22C, Vread may be set equal to Vcc, or Vref may be set equal to Vcc. In these cases, since the types of voltages handled at the time of reading are reduced, the peripheral circuit can be simplified and the area and the number of processes can be reduced.

  Next, a data read operation when this embodiment is applied to an AND-type EEPROM will be described with reference to FIG. First, the bit line BL is precharged and then floated, the voltage of the control gate of the memory cell M2 selected for reading is set to the read voltage Vref, and the voltages of the control gates of other memory cells are set to the non-selected read voltage Vread. This is done by setting the gate voltage of the selection transistors S1 and S2 to the power supply voltage Vcc and the source line Source to 0 V and detecting whether or not a current flows through the memory cell M2 selected for reading by the bit line BL.

  That is, if the threshold value Vth of the memory cell M2 selected for reading is in a writing state larger than Vref, the memory cell M2 is turned off, so that the bit line BL maintains the precharge potential. On the other hand, if the threshold value Vth of the memory cell M2 selected for reading is smaller than Vref, the memory cell M2 is turned on, so that the potential of the bit line BL is lowered by ΔV from the precharge potential. Data in the memory cell is read by detecting this potential change with a sense amplifier.

  Here, Vref is an intermediate voltage between the threshold value in the write state and the threshold value in the erase state, Vread is a voltage lower than the threshold value in the erase state, and Vcc is a voltage higher than the threshold values of the selection transistors S1 and S2.

  Further, as a voltage to be applied to the gates of the selection transistors S1 and S2, Vref may be applied instead of Vcc as shown in FIG.

  Further, Vread may be given as shown in FIG. In FIG. 23C, Vread may be Vcc, and Vref may be Vcc. In these cases, since the types of voltages handled at the time of reading are reduced, the peripheral circuit can be simplified to reduce the area and the number of processes.

  Note that in the equivalent circuit diagrams shown in FIGS. 22 and 23, the selection transistor has a structure without the charge storage layer, but may have the same nonvolatile memory structure as the memory cell. In this case, the manufacturing process is reduced because the process for making the selection transistor and the memory cell transistor can be omitted, and the distance between the selection transistor and the memory cell is reduced because it is not necessary to have a margin for making the selection transistor. The device area can be reduced.

  In a read operation of a NAND or AND type EEPROM, the current flowing through the bit line is mainly determined by the channel conductance of the memory cell selected for reading, but is also affected by the channel conductance of the selection transistor. In other words, it is influenced by the variation in threshold value of the selection transistor, and causes erroneous reading. In order to avoid this, it is desirable that the threshold distribution of the selection transistor is sufficiently lower than the voltage applied to the selection gate at the time of reading, and therefore the channel conductance of the selection transistor is sufficiently larger than that of the memory cell.

Here, that the channel conductance of the selection transistor is sufficiently larger than that of the memory cell indicates a range in which the current flowing through the bit line during reading does not vary depending on the threshold value of the selection transistor. For example, when the threshold value of the selection transistor is Vthsg and the threshold value of the write memory is Vthw, the selection gate voltage Vsg and the read non-selection gate voltage are Vread.

  In this embodiment, since the threshold value of the selection transistor is the same as or lower than the threshold value of the erase state of the memory cell, the channel conductance of the selection transistor is always sufficiently high, and the threshold variation of the selection transistor is bit line. The current is not affected.

Further, the voltage applied to the select gate in a read operation in the present embodiment, it is possible to common with the voltage applied to the control gate of the selected Memorise Le, it is possible to simplify the circuit.

  In this embodiment, when the selection transistor has the same nonvolatile memory structure as that of the memory cell, the threshold value of the selection transistor can be stored in the memory by erasing the memory cell by applying a voltage similar to that of the memory cell to the selection transistor. It can be the same as the cell erasure threshold. Further, if a voltage higher than that of the memory cell is applied to the selection transistor, an erasing threshold lower than that of the memory cell can be obtained.

  An equivalent circuit diagram, a plan view, and a cross-sectional view when this embodiment is applied to a NAND type EEPROM are as shown in FIGS. Also, an equivalent circuit diagram, a plan view, and a cross-sectional view when applied to an AND type EEPROM are as shown in FIGS.

  In the above description, NAND, NOR, and AND-type EEPROM are taken as an example, but the embodiment of the invention is not limited to this, and can be applied to a storage device such as DINOR-type.

  Further, the floating gate type and the MONOS type have been described as examples of the memory cell structure. Here, in the MONOS memory, since the gate electrode has a single layer structure, all of the voltage applied to the gate is applied to the ONO (Oxide-Nitride-Oxide) film under the charge storage layer, and low voltage operation is achieved. Is possible.

  On the other hand, in the floating gate type memory, since the interpoly insulating film exists between the control gate and the floating gate, all the voltages applied to the gate electrode are not applied to the tunnel oxide film, and the interpoly insulating film and Since it is applied to both of the tunnel oxide films, the operation requires higher voltage than the MONOS type memory.

  In each embodiment, as shown in FIG. 24A, a write state having a threshold value equal to or higher than Vref and an erase state having a threshold value equal to or lower than Vref are provided, and “write” and “erase” are performed in one memory cell. Although a binary memory cell that stores two states has been described as an example, the present invention can be applied to a multilevel memory cell that stores three or more states. A data storage state in this case will be described with reference to FIG.

  In a multi-level memory cell, the number of states stored in one memory cell is n (n is a natural number of 2 or more), and “1” state, “2” state. And If the voltage for distinguishing between the “1” state and the “2” state is Vref1, the “erased state” of the binary memory cell described above is changed to the “1” state of the multi-level memory cell and “Vref” of the binary memory cell. In place of “Vref1” of the multilevel memory cell, the present invention can be implemented in the same manner as in the above embodiments.

  In the third embodiment, the threshold value Vthsg of the selection transistor can be the same (included in the distribution) as any of the “1” state to the “n” state. Further, the same effect as that of the third embodiment can be obtained by making the voltage applied to the selection gate the same as any one of Vref1 to Vrefn-1 during the read operation.

  Embodiments of the invention are not limited to the above-described embodiments, and various modifications can be used without departing from the spirit of the invention. Each embodiment is not necessarily used alone, and a plurality of embodiments can be used in combination.

(A) is a circuit diagram showing a data read operation in the first embodiment, (B) is a threshold distribution diagram showing an example of a data storage state in the first embodiment. C) is a threshold value distribution diagram showing an example of a data storage state in the first embodiment. (A) is a threshold value distribution diagram representing threshold setting in consideration of read disturb in the first embodiment, and (B) is a diagram showing read disturb characteristics of the nonvolatile memory. FIG. 6 is a relationship diagram between a threshold value representing threshold setting in consideration of read disturb and Vread in the first embodiment. (A) is an equivalent circuit diagram of an example of the NAND memory cell in the first embodiment, and (B) is a top view of the NAND memory cell in the first embodiment. FIG. 4A is a cross-sectional view of the MONOS type NAND memory cell according to the first embodiment on the “AB” line in FIG. 4B, and FIG. 4B is a MONOS type according to the first embodiment. FIG. 5 is a cross-sectional view of the NAND memory cell taken along the “CD” line in FIG. (A) is an equivalent circuit diagram of a second example of the MONOS type NAND memory cell in the modification of the first embodiment, and (B) is in the first modification of the first embodiment. FIG. 5 is a cross-sectional view of the MONOS NAND memory cell taken along the line “AB” in FIG. 4B. (A) is sectional drawing on the "AB" line in FIG.4 (B) of the floating gate type NAND memory cell in the 2nd modification of 1st Embodiment, (B) is 1st FIG. 6 is a cross-sectional view taken along the line “CD” in FIG. 4B of a floating gate type NAND memory cell according to a second modification of the embodiment. (A) is a distribution diagram of threshold values representing an example of a data storage state in the second embodiment, and (B) represents a write state of an example of a data storage state in the second embodiment. It is a schematic diagram, and (C) is a schematic diagram showing an erased state of an example of a data storage state in the second embodiment. (A) is a distribution diagram of threshold values representing a second example of the data storage state in the second embodiment, and (B) is a second data storage state in the second embodiment. It is a schematic diagram showing the write state of an example, (C) is a schematic diagram showing the erased state in the 1st case of the 2nd example of the storage state of the data in 2nd Embodiment, (D) These are schematic diagrams showing the erased state in the second case of the second example of the data storage state in the second embodiment. (A) is an equivalent circuit diagram of the NAND memory cell in the second embodiment, (B) is an equivalent circuit diagram of the AND memory cell in the second embodiment, and (C) is the first circuit diagram. FIG. 3 is an equivalent circuit diagram of a NOR memory cell in the second embodiment. (A) is a diagram showing data retention characteristics of a nonvolatile memory, (B) is a schematic diagram showing a nonvolatile memory in a state where a lot of negative charges are accumulated, and (C) shows a small number of It is a schematic diagram showing the non-volatile memory in a state where negative charges are accumulated, and (D) is a schematic diagram showing the non-volatile memory in a state where positive charges are accumulated. (A) is a diagram showing the relationship between the erase time of the MONOS memory and the threshold value, and (B) is a schematic diagram showing the erase operation in the MONOS memory. (A) is a figure showing the charge storage layer SiN film thickness dependence of the data retention characteristic of a MONOS memory, (B) is a schematic diagram showing the non-volatile memory in the state where the positive charge was accumulated, ( C) is a schematic diagram showing a nonvolatile memory in a state where negative charges are accumulated. (A) is an equivalent circuit diagram of the NOR memory cell in the first modification of the second embodiment, and (B) is an equivalent circuit diagram of the NOR memory cell in the first modification of the second embodiment. It is a top view. Sectional drawing on the "AB" line | wire of FIG.14 (B) of the NOR floating gate type memory in the 1st modification of 2nd Embodiment. Sectional drawing on the "AB" line | wire of FIG. 14 (B) of the NOR MONOS type | mold memory in the 1st modification of 2nd Embodiment. (A) is an equivalent circuit diagram of an AND floating gate type memory in a second modification of the second embodiment, and (B) is in a second modification of the second embodiment. It is a top view of an AND floating gate type memory. FIG. 17A is a cross-sectional view taken along the line “AB” in FIG. 17B, and FIG. 17B is a cross-sectional view taken along the line “CD” in FIG. (A) is an equivalent circuit diagram of an ANDMONS type memory in the second modification of the second embodiment, and (B) is an AND MONOS in the second modification of the second embodiment. It is a top view of a type memory. FIG. 19A is a cross-sectional view taken along line “AB” in FIG. 19B, and FIG. 19B is a cross-sectional view taken along line “CD” in FIG. (A) is a distribution diagram of threshold values representing an example of the data storage state in the third embodiment, and (B) represents a second example of the data storage state in the third embodiment. It is a distribution map of a threshold value. (A) is a circuit diagram of a first example showing a read operation in the NAND memory of the third embodiment, and (B) is a second diagram showing a read operation in the NAND memory of the third embodiment. FIG. 10C is a circuit diagram of a third example illustrating a read operation in the NAND memory according to the third embodiment. (A) is a circuit diagram of a first example showing a read operation in the AND type memory of the third embodiment, and (B) is a second diagram showing a read operation in the AND type memory of the third embodiment. FIG. 10C is a circuit diagram of a third example illustrating a read operation in the AND type memory according to the third embodiment. (A) is a figure showing the data storage state in a binary cell, (B) is a figure showing the data storage state in a multi-value cell. (A), (B), and (C) are schematic diagrams showing an erasing operation in a conventional floating gate nonvolatile memory, and (D), (E), and (F) are conventional MONOS nonvolatiles. It is a schematic diagram showing the erasing operation in the memory. (A) is a diagram showing a data storage state in the prior art, (B) is a schematic diagram showing a writing state in the prior art, and (C) is a schematic diagram showing an erasing state in the prior art. . The figure showing the data storage state of the conventional NAND type memory cell. FIG. 10 is a circuit diagram illustrating a read operation of a conventional NAND memory cell. (A) is a figure showing the threshold value change of the non-selection cell of the conventional NAND type memory cell, (B) is a figure showing the change of the memory | storage state of the conventional NAND type memory cell.

Explanation of symbols

1, 27, 55, 56, 65 Memory cell block 2, 61 BL contact 3 SL contact 4 P-type semiconductor substrate 5 N-type well 6 P-type well 7, 30 Tunnel gate insulating film 8, 31, 52, 59 Charge storage layer 9 Block insulating film 10, 33, 53, 60 Control gate (word line)
11, 34 Gate cap insulating films 12, 35 Gate sidewall insulating films 13, 36 Memory cell gates 14, 18, 21, 37 Source / drain N-type diffusion layers 15, 16, 38, 39 Gate electrode 17 Gate insulating film 19 Data transfer Line (bit line)
20, 22 Contact 23 Source line 24 Interlayer film 25 Insulating film protective layer 26 Element isolation region 32 Interpoly insulating film 50, 57 Semiconductor substrate 51, 58 Source / drain diffusion layer 66 Bit line contact 67 Common source line contact 68 Interlayer insulating film BL, BL1, BL2 bit lines, data transfer lines GSL, SSL block selection lines M0 to M15, M0 ′ to M2 ′ memory cells S1 and S2 selection transistors Source common source lines WL0 to WL15 data selection lines (word lines)

Claims (7)

An information storage unit having at least one control terminal, electrically erasable, and storing discrete n-value (n is an integer of 2 or more) data, and being connected in series between at least two current terminals Comprising a plurality of memory elements connected and arranged;
All of the discrete first to nth threshold voltages in which the n-value data is determined in the order of the threshold value are higher than the lower one of the voltages applied to the current terminals at the time of data reading,
The memory element and the current terminal are arranged in common and have a control terminal electrically separated from the control terminal of the plurality of memory elements, and the conduction state and the cutoff state between the current terminals are switched. A semiconductor memory device comprising: a selection element having a threshold voltage lower than a threshold voltage in an erased state of the plurality of memory elements, where the voltage of the control terminal is a threshold. An information storage unit having at least one control terminal, electrically erasable, and storing discrete n-value (n is an integer of 2 or more) data, and being connected in series between at least two current terminals Comprising a plurality of memory elements connected and arranged ;
A selection element is arranged sharing the current terminal with the memory element,
A control terminal electrically separated from the control terminal of the memory element;
When the voltage of the control terminal that switches between the conduction state and the interruption state between the current terminals is set as a threshold value, the n-value data is associated with discrete first to nth threshold voltages determined in order of the threshold value, A semiconductor memory device comprising: a memory element having a threshold voltage in a data storage state corresponding to an erased state higher than a threshold voltage of the selected element; and a memory element lower than a threshold voltage of the selected element. The potential applied to the gate terminal of the selection element when reading data is higher than the threshold voltage of the memory element k (k is an integer between 1 and n−1) and lower than the threshold voltage of the (k + 1) th. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is a semiconductor memory device.   A plurality of the memory elements form a memory cell unit. One end of the memory cell unit is electrically connected to the first signal line, and the other end is electrically connected to a wiring common to adjacent memory cell units. 4. The semiconductor memory device according to claim 1, further comprising a data circuit that senses the potential of the first signal line charged through the memory element. 5.   5. The semiconductor memory device according to claim 1, wherein the memory element and the selection element are transistors provided on a semiconductor substrate, and the control terminal is a gate electrode of the transistor.   6. The semiconductor memory according to claim 1, wherein the information storage unit is provided on a semiconductor substrate with an insulating film interposed therebetween, and the thickness of the insulating film is 4 nm or less. apparatus.   7. The semiconductor memory according to claim 1, wherein the insulating film of the information storage part is a silicon nitride film, and the physical film thickness of the insulating film that becomes the information storage part is 15 nm or less. apparatus.

Images