JP2001057095A - Semiconductor device and driving method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To accelerate the cell reading speed of a flash memory in which bit lines are divided by a selection transistor. SOLUTION: Threshold voltage of a selection transistor Qs is lowered so that when a well 12 of a non-selection block B2 or a gate electrode 15 of a selection transistor Qs is 0 V at the time of write-in, the device is turned on by voltage of a main bit line MBL, but when voltage of -0.5 V to -2 V is applied to the well 12 of the non-selection block B2 or the gate electrode 15, the device is turned off. And at the time of write-in, voltage of -0.5 V to -2 V is applied to the well 12 of the non-selection block B2 or the gate electrode 15, or both of then.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of driving the same, and more particularly to a technique effective for improving the read speed of an electrically rewritable nonvolatile semiconductor memory device.

[0002]

2. Description of the Related Art An electrically rewritable batch-erasable non-volatile memory, so-called flash memory, is known as 199
Various types are known as described in “Applied Physics”, Vol. 65, No. 11, p1114 to p1124, published on November 10, 2006 by the Japan Society of Applied Physics.

Further, as for a NOR type flash memory in which a bit line is divided by a selection transistor, for example, as described in Japanese Patent Publication No. 4-208566, erasing of information is performed by FN (Fowler- Nordh
eim) It is known that writing of information is performed by an FN tunnel current at a drain end by a tunnel current.

[0004]

SUMMARY OF THE INVENTION The present inventor has studied a NOR type flash memory in which the above-mentioned bit line is divided by a selection transistor, and has recognized the following problems.

That is, when a structure in which a bit line (main bit line) is divided by a selection transistor is adopted, a plurality of sub-bit lines connected via the selection transistor are provided for one main bit line. . This sub-bit line is generally provided for each block. When performing a write operation or a read operation on a memory cell having such a configuration, it is necessary to apply a predetermined voltage to the source / drain region of the memory cell to be subjected to the operation.
This voltage is supplied from a sub-bit line connected to the main bit line. The voltage applied to the main bit line is transmitted to the sub-bit line via the selection transistor, and is supplied to the drain of the memory cell.

However, as described above, a plurality of sub-bit lines are connected to a main bit line, and a voltage is applied only to a sub-bit line (selected sub-bit line) connected to a memory cell to be operated. In addition, it is necessary that a sub-bit line (non-selected sub-bit line) to which no memory cell to be operated is connected is disconnected from the main bit line. When a voltage is applied to the non-selected sub-bit line at the time of writing information, data disturbance occurs.When the non-selected sub-bit line is connected to the main bit line at the time of reading information, the capacity of the main bit line is reduced. This is because the reading speed is increased and the reading speed is reduced.

Therefore, a selection transistor for separating the sub-bit line from the main bit line is provided, and the threshold value of the selection transistor is set to a value high enough not to turn on depending on the voltage applied to the main bit line. You. As a result, the sub-bit line is reliably separated from the main bit line, and data disturbance to the non-selected memory cell at the time of writing is suppressed. Further, an increase in the capacity of the main bit line is suppressed.

However, increasing the threshold voltage of the selection transistor as described above raises the problem that the on-resistance of the transistor is increased and the read time cannot be reduced.

That is, the read time of the flash memory generally includes a precharge time, a sensing time, and a discharge time. The precharge time is a time required for charging the drain voltage of the memory cell to a predetermined potential (for example, +1 V) prior to sensing, and the discharge time is a time required for setting the drain of the memory cell to 0 V after sensing. Time. If these times are not sufficient, the drain voltage will not reach the predetermined value, differential sensing will not be performed normally,
This may cause erroneous determination.

[0010] Precharge and discharge time T
Includes the sum R1 of the wiring resistance and the diffusion layer resistance of the main bit line and the selected sub-bit line, and the resistance M of the selection transistor.
The OS resistance (ON resistance) R2 and the parasitic capacitance C of the main bit line and the selected sub-bit line are related. That is,
T = C × (R1 + R2).

Here, the value of the MOS resistor R2 is determined by the threshold voltage, gate width, gate length, and other material constants of the selection transistor, and the value of R2 increases as the threshold voltage increases. Also, generally, R2 is compared with the value of R1.
Is larger, and the ratio contributing to T is the MOS resistance R2
Is dominant.

That is, when the threshold voltage of the selection transistor is increased, the MOS resistance R2 is increased, and the precharge and discharge time T is lengthened.
As a result, the read cycle of the flash memory cannot be shortened, and there is a limitation in increasing the speed of the semiconductor device.

In particular, when a flash memory is mounted on a one-chip microcomputer, the operating frequency f of the 0.35-μm process generation microcomputer reaches 60 MHz,
The microcomputer of the μm process generation is going to be 100 MHz. In this case, in order to read data from the built-in ROM (flash memory) in one cycle, the read speed must be 1 / f or less, which is 16.7 ns or less for the 0.35 μm process generation and 0.18 μm for the 0.18 μm process generation. 10
ns or less.

An object of the present invention is to increase the reading speed of a flash memory while ensuring normal operation.

Another object of the present invention is to perform normal and high-speed reading of a flash memory without changing the manufacturing process and without increasing the memory mat size.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0017]

According to the present invention, there is provided a semiconductor device comprising:
The threshold voltage of the selection transistor of the flash memory included therein is set low, and M0S
This is to lower the resistance. Simply setting the threshold voltage low may cause punch-through in the select transistor of the unselected block at the time of writing, and the bit line voltage may also be applied to the memory cell drain of the unselected block, causing data disturbance. There is. Therefore, in order to prevent this, a back bias is applied to the well of the unselected block at the time of writing. Alternatively, a negative bias is applied to the gate electrode of the selection transistor in the unselected block at the time of writing.

By applying a back bias to the wells of the non-selected blocks as described above, the threshold voltage of the selection transistor can be increased. This can prevent punch-through. Further, punch-through can be prevented by applying a negative bias to the gate electrode of the selection transistor in the unselected block.

Also at the time of reading, the gate of the selection transistor of the non-selected block is negatively biased to prevent punch-through at the time of reading.

The parasitic capacitance of the main bit line and the sub-bit line is reduced by using a low dielectric constant material for the interlayer insulating film for insulating the main bit line or the sub-bit line.

As described above, the precharge time is C
× (R1 + R2). Generally, metal wiring is used for the main bit line and the sub bit line. Further, if the contact is arranged closer to the gate, the resistance of the diffusion layer is reduced.
Therefore, the relationship of Rl << R2 is satisfied, and C or R2 needs to be reduced to shorten the precharge time. Generally, the memory cell mat is laid out with the minimum processing size of each process generation, so it is difficult to reduce the area component of the parasitic capacitance. To reduce C in areas other than the area, it is necessary to reduce the junction capacitance by increasing the film thickness between the wiring and the substrate or adding an implantation process. However, as the film thickness increases, the aspect ratio of the contact increases, and the process becomes difficult. Further, if the number of in-bra processes is increased, the number of process steps is increased. Even with such measures, the reduction of C is 10-20%
Stop to the extent.

On the other hand, with respect to R2, 40
% Or more. Hereinafter, the calculation of the value of R2 will be attempted.

Since the selection transistor is operated in the linear region, its drain current Ids is given by: Ids = (1/2) · (W / L) · μ · Cox · (2 · (Vg−Vth) · Vd−Vd
² ), Where W is the channel width, L is the channel length, μ
Is the electron mobility, Cox is the gate capacitance per unit area, and Vth is the threshold voltage. This is when the source is grounded.

The gate capacitance Cox per unit area
Becomes Cox = ε ₀ · εox / Tox. However, ox is the dielectric constant of the oxide film, epsilon ₀ is the dielectric constant in vacuum, Tox is the gate oxide thickness.

Therefore, when the source voltage is 0 V, the MOS
The resistance R2 is calculated as follows: R2 = Vd / Ids = Vd / ((1/2) ・ (W / L) ・ μ ・ Cox ・ (2 ・ (Vg-Vt
h) · Vd-Vd ² )). For simplicity, Vd = + 1V, Vg = Vcc =
+ When 3V, MOS resistor R2, R2 = 2 / ((W / L) · μ · (ε 0 · εox / Tox) · (2 · (3-Vth) -
1)), Therefore, to reduce R2, increase W,
What is necessary is just to make L small, Tox small, and Vth small. mu, ox, a material, impurity concentration, a gate length, and depends on the temperature, epsilon ₀ is the physical constants.

Here, W is determined by the horizontal size of the memory cell, and L and Vth are determined by the punch-through breakdown voltage at the time of writing. Tox is determined by a voltage applied to the gate oxide film at the time of erasing or writing. For example, in the case of the conventional 0.35 μm process generation, W = 2.1 μm
m, Tox = 20 nm, L = 0.9 μm, Vth = 0.6 V
And μ is generally about 300 (cm ² / V · s), ε ox = 3.9, ε ₀ = 8.854 × 10
^-14 (F / cm), the conventional MOS resistor R21
Is, R21 = 2 / ((2.1 / 0.9) · μ · (ε 0 · εox / 20nm) · (2 · (3-0.6) -1)) = 2 / ((2.1 / 0.9) · 300 · (3.9・ 8.854 × 10 ^-14 / 200 × 10 ^-8 ) ・ (2 ・ (3-0.6) -1)) ~ 4350Ω.

On the other hand, in the case of the present invention, the p-type well of the unselected block is back-biased to about -0.5 to -2 V at the time of writing. Alternatively, set the gate of the selection transistor to -0.
A negative bias is applied to about 5 to -2V. This prevents punch-through of the selection transistor in the unselected block. When the back bias is applied to prevent punch-through, the gate length L can be set short and Vth can be set low. FIG. 13 is a graph showing characteristics of a selection transistor applicable to the present invention.
And (b) shows a change in the drain breakdown voltage BVds with respect to the gate length L. As shown in the figure, when the conventional gate length L is 0.9 μm, the threshold voltage Vth is 0.6 V, but the gate length L is set to 0.6.
By setting the threshold voltage to 6V, the threshold voltage Vth can be reduced to 0.4V. If the gate length L is 0.9 μm, the drain withstand voltage BVds can be maintained at 5 V or more. However, by setting the gate length L to 0.6 V, the drain withstand voltage BVds becomes 5 V.
V or less. However, as described above, if a back bias is applied, the drain withstand voltage to the extent that punch-through can be prevented is maintained. In such a case, W = 2.1 μm, Tox
= 20 nm, L = 0.6 μm, and Vth = 0.4V. Accordingly, MOS resistor R22 of the present invention, R22 = 2 / ((2.1 / 0.6) · μ · (ε 0 · εox / 20nm) · (2 · (3-0.4) -1)) = 2 / ((2.1 /0.6) · 300 · (3.9 · 8.854 × 10 ^-14 / 200 × 10 ^-8 ) · (2 · (3-0.4) -1)) ~ 2630Ω.

The MOS resistance ratio R22 / R21 is about 0.6.
0, the MOS resistance can be reduced by 40% according to the present invention. Thereby, the precharge time can be reduced. Discharging is to set the bit line voltage to 0 V. If the MOS resistance can be reduced, the electric charge accumulated in the drain of the memory cell can be discharged quickly. Therefore, the discharge time can be reduced. Further, at the time of reading, the gate of the selection transistor of the non-selected block is negatively biased to prevent punch-through due to the bit line voltage, so that L and Vth can be set even lower. Can be improved.

The present invention is as follows.

(1) The method of driving a semiconductor device according to the present invention
A plurality of wells; a floating gate MISFET type memory cell formed in a matrix on the main surface of the well;
A word line extending in the first direction, a sub-bit line extending in a second direction substantially perpendicular to the first direction, and a sub-bit line formed on the main surface of the well. MI
An SFET, a main bit line connected to the plurality of MISFETs via a MISFET (selection MISFET) connected by a sub-bit line, the word line functions as a control gate of the memory cell, and the sub-bit line is a well. A driving method of a semiconductor device connected to drain regions of a plurality of memory cells arranged in a second direction and a source region of the select MISFET, and wherein the main bit line is connected to a drain region of the select MISFET. When writing to a memory cell, the main bit line (selected main bit line) connected to the sub-bit line (selected sub-bit line) to which the memory cell to be written (selected memory cell) belongs among the memory cells Of the word line (selected word line) to which the selected memory cell belongs, and the MISFE
A voltage of a predetermined first polarity is applied to each of the gate electrodes of the MISFETs (selected MISFETs) connected to the selected sub-bit line in T, and the selected sub-bit line connected to the selected main bit line is selected. A first (unselected well) to which a sub-bit line (unselected sub-bit line) other than the bit line belongs is set to the first
A voltage having a second polarity opposite to the polarity is applied.

Alternatively, instead of applying a voltage to the unselected well, the MISFE connected to the unselected sub-bit line
A voltage having a second polarity opposite to the first polarity is applied to the gate electrode of T (unselected MISFET).

Alternatively, the unselected well and the unselected MI
A second electrode, opposite to the first polarity, is applied to both gate electrodes of the SFET.
A voltage of a polarity is applied.

Further, the method for driving a semiconductor device according to the present invention comprises:
When reading a memory cell, a predetermined voltage is applied to a selected main bit line, a voltage of a first polarity is applied to a selected word line and a gate electrode of a selected MISFET, and a gate of an unselected MISFET is applied. A voltage having a second polarity opposite to the first polarity is applied to the electrode.

The threshold voltage of the MISFET is such that when the gate electrode and the well are at the ground potential, the MISFET is turned on by a predetermined voltage applied to the main bit line, but the second polarity voltage is applied to the gate electrode or the well. Is adjusted to such a value that the MISFET is not turned on by a predetermined voltage applied to the main bit line.

The memory cell and the MISFET are n
It is a channel type, and the voltage applied to the main bit line and the voltage of the first polarity can be a positive voltage, and the voltage of the second polarity can be a negative voltage.

(2) The semiconductor device of the present invention comprises a plurality of wells, a floating gate MISFET type memory cell formed in a matrix on the main surface of the well, and a word formed extending in the first direction. Line and a second substantially perpendicular to the first direction
And a MISFET formed on the main surface of the well and provided for each sub-bit line.
And a plurality of MIs connected to a plurality of MISFETs by sub-bit lines.
A main bit line connected via an SFET (select MISFET), the word line functions as a control gate of the memory cell, and the sub-bit line includes a plurality of memory cells arranged in the second direction in the well. A semiconductor device connected to a drain region and a source region of the select MISFET, and the main bit line connected to a drain region of the select MISFET, wherein a threshold voltage of the MISFET is M
If the gate electrode and the well of the ISFET are at the ground potential, the MISFE is applied by a predetermined voltage applied to the main bit line.
Although T is turned on, when the reverse bias voltage is applied to the gate electrode or the well, the predetermined voltage applied to the main bit line does not turn on the MISFET.

The interlayer insulating film that insulates the sub-bit line or the main bit line can be made of low dielectric constant silicon oxide, resin or SOG.

[0038]

Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for describing the embodiments, components having the same functions are denoted by the same reference numerals, and repeated description thereof will be omitted.

FIG. 1 is a block diagram showing a configuration of a semiconductor device according to the present invention. The semiconductor device of the present embodiment
Calculation unit CPU, volatile memory unit RAM,
It has a read-only memory section ROM and a rewritable nonvolatile memory section FEEPROM. In addition, an analog / digital conversion unit A / D, an interface unit INT, a power supply unit CPG, an input output port unit IOP1
It has an IOP 9, a bus, etc., but details are omitted.

In such a semiconductor device, the arithmetic unit CPU
As described above, there is a strong demand for improving the reading speed from the nonvolatile memory unit FEEPROM. In the present embodiment, the nonvolatile memory unit FEEP
The reading speed from the ROM is improved as described later, and the reading can be performed within one cycle of the clock frequency (for example, 100 MHz) in the arithmetic unit CPU of the 0.18 μm process generation.

FIG. 2 is a circuit block diagram showing a main part of a rewritable nonvolatile memory section FEEPROM of the semiconductor device of the present embodiment. X is attached to one end in the left-right direction of the memory array 1 in which the memory cells M are arranged in a matrix.
A Y gate sense and latch circuit 3 is arranged at one end of the decoder 2 in the vertical direction. X decoder 2 has X
An X address latch circuit 4 having an address signal XA as an input signal is connected, and a Y gate sense and latch circuit 3 is connected.
Is connected to a Y address counter circuit 5 having the Y address signal YA as an input signal. Data D is input / output to / from the Y gate sense / latch circuit 3 via an I / O buffer 7 controlled by the control signal input circuit 6, and is input to the X decoder 2 and the Y gate sense / latch circuit 3. Is applied with a voltage from the internal voltage circuit 8.

FIG. 3 is a circuit diagram showing a part of the memory array. Non-volatile memory unit FEEPR of the present embodiment
In the OM, as shown in FIG. 3, the main bit line MBL (MB
L1 to MBL4) and select transistor Qs (Qs11 to Qs11).
Qs42), the sub-bit lines SBL (SBL11 to SB
L42). That is, select transistors Qs11 and Qs12 are connected to main bit line MBL1, and sub-bit line SBL1 is connected to select transistor Qs11.
1 is connected to the sub-bit line SBL in the selection transistor Qs12.
12 are connected. In other words, electrically, the sub-bit line SBL11 or SBL12 can be selected by selecting the selection transistor Qs11 or Qs12, and the main bit line MBL1 is connected to the sub-bit lines SBL11 and SBL12.
Is divided. Note that the main bit line MBL
2, MBL3 and MBL4. Also,
Although four main bit lines MBL are shown in the drawing, it goes without saying that more main bit lines MBL, sub-bit lines SBL, and select transistors Qs are formed.

The 1- to 64-bit memory cells M (M111 to M411) are connected to the sub-bit line SBL. FIG.
Shows a state in which four memory cells M are connected for simplicity. That is, the memory cells M111, M211, M311, and M411 are connected to the sub-bit line SBL11.
Is connected. The same applies to other sub-bit lines SBL. The sub-bit line SBL is connected to the drain of the memory cell M, and the source of the memory cell M is connected to the source line S.

One block B1 is constituted by the memory cells M111 to M441. Memory cells M112 to M44
The block B2 is similarly configured for No. 2. In the present embodiment, erasing is performed in block units. Therefore, the memory cell M and the select transistor Qs in the block are formed in one well. Although two blocks are shown in the figure for simplicity, it goes without saying that more blocks are formed.

The control gates of the memory cells M are connected between adjacent memory cells in the row direction to form a word line WL. That is, the memory cells M111, M121, M13
1 and M141 are connected by one word line WL11.
The same applies to the other word lines WL21 to WL42.

FIG. 4 is a conceptual sectional view taken along the main bit line MBL1. A deep n-type well 11 is formed in the main surface of the semiconductor substrate 10, and a plurality of shallow p-type wells 12 are formed in the well 11. In the well 12, a memory cell M and a select transistor Qs belonging to one block are formed.

The p-type well 12 is divided into erase units. This means that when erasing block B1, block B
A high voltage is applied to one well 12 to prevent this voltage from being applied to the well 12 of the block B2.

The memory cell M includes a floating gate 13, a control gate 14, and impurity semiconductor regions (source / drain) 16 on both sides of the floating gate 13. An n-type impurity is introduced into the impurity semiconductor region 16 at a high concentration.
The control gates 14 of the adjacent memory cells M are connected to each other to form the word line WL as described above. The gate oxide film of the memory cell M is formed of a tunnel oxide film (silicon oxide film) of about 10 nm, and an insulating film between the control gate 14 and the floating gate 13 is an ONO (Oxide-Nitride) having an equivalent oxide thickness of about 15 nm. -Oxide) film (laminated film of silicon oxide film and silicon nitride film).

The sub bit line SBL is connected to one impurity semiconductor region 16, and the source line is connected to the other impurity semiconductor region 16. The sub-bit line SBL is formed of a metal film such as aluminum, and the source line S is formed of the impurity semiconductor region 16.

One selection transistor Qs is arranged on one sub-bit line SBL. The selection transistor Q is formed in the well 12 and includes a gate electrode 15 and a source / drain on both sides of the gate electrode 15. One of the source and the drain of the selection transistor Qs is the impurity semiconductor region 16 shared with the source and the drain of the memory cell M located at the end, and the other source and the drain is n
This is the impurity semiconductor region 17 in which the type impurity is introduced at a high concentration. Main bit line MBL is connected to impurity semiconductor region 17. The gate oxide film thickness of the selection transistor Qs is
It is composed of a silicon oxide film of about 20 nm.

In the present embodiment, the selection transistor Qs
Is set low, that is, low enough to turn on the selection transistor Qs by the voltage applied to the main bit line MBL at the time of writing or reading. That is, when the threshold voltage of the selection transistor Qs is 0 V in the gate electrode 15 and the well 12, the transistor is turned on by the voltage of the main bit line MBL at the time of writing. About -0.5 to -2 to the gate electrode 15.
By applying a voltage of about V, the threshold voltage is reduced to such an extent that the selection transistor Qs is turned off.

By setting the threshold value of the selection transistor Qs to a low value in this manner, the selection transistor Qs which is not originally selected, ie, the voltage is not applied to the gate electrode 15, is selected.
May be turned on, and a voltage is also applied to the sub-bit line SBL connected thereto. Such a situation causes data disturb at the time of writing, and at the time of reading, the capacity of the main bit line MBL is increased and the reading speed is reduced. However, in the present embodiment, a negative bias is applied to the gate electrode 15 of the unselected selection transistor Qs, or a back bias is applied to the unselected well 12 to prevent the non-selected transistor from turning on. I do.

On the other hand, by setting the threshold value of the selection transistor Qs to a low value, the MOS resistance of the selection transistor Qs can be reduced. As described above, the main bit line MBL and the sub-bit line SBL are formed of a metal layer, and the longer the interval between contact portions becomes so large that diffusion resistance becomes a problem, it is almost impossible in a highly integrated semiconductor device. Absent. Therefore, by lowering the MOS resistance, which is a major factor in lowering the reading speed,
The reading speed can be increased.

Note that, in this embodiment, -0.5 to -2 V
A negative voltage generating circuit for generating a negative voltage of the order and a control signal for applying a negative voltage to the substrate (well 12) of the unselected block or the gate electrode 15 of the selection transistor Qs at the time of writing are added.

FIG. 5 is a conceptual sectional view showing an example of a write operation to the memory cell M according to the present embodiment. Writing is performed in bytes on the same word line WL or in units of a plurality of bytes.

+8 V is applied to the control gate 14 (selected word line) of the memory cell M to be written,
A voltage of 0 V is applied to the control gate 14 (non-selected word line). A ground potential is applied to the source line S and the well 12 (B1) to which the memory cell M to be written belongs, and a ground potential or Vcc is applied to the well 11. A voltage of +5 V is applied to the drain (one of the impurity semiconductor regions 16) of the cell (M111) where writing is performed, electrons are injected from the channel region at the drain end to the floating gate 13 by channel / hot electron injection, and the threshold voltage is reduced. Make it higher. In order to prevent the voltage of +5 V applied to the main bit line MBL from causing a drop in Vth due to the selection transistor Qs (Qs11), the sub bit line SBL on which writing is performed is performed.
(SBL11) connected to the selection transistor Qs (QS
A voltage of +8 V is applied to the gate electrode 15 of 11).

On the other hand, the control gate 14 and the source line S of the unselected block (B2) are at 0 V, and the selection transistor Qs (Q
The gate electrode 15 in s12) is set to 0V. In this case, if the well 12 of the non-selected block (B2) is at 0V, the selection transistor Qs12 is connected to the + 5V main bit line MBL.
The memory drain of the unselected block (B2) is biased due to the voltage, and a drain disturbance occurs. To prevent this, a voltage of -0.5 to -2 V is applied to the well 12 of the unselected block (B2). As a result, the threshold voltage is increased, and the non-selected selection transistor Qs (Qs1
2) is not turned on.

FIG. 6 is a conceptual sectional view showing another example of the write operation to the memory cell M of the present embodiment. The write operation of the selected block (B1) is the same as that of FIG. The control gate 14, source line S, and well 12 of the unselected block (B2) are set to 0V. In this case, if the gate electrode 15 of the selection transistor Qs (Qs12) of the unselected block (B2) is 0 V, the selection transistor Qs
(Qs12) is turned on by the voltage of the main bit line MBL of + 5V, and the memory drain of the non-selected block (B2) is biased to generate a drain disturbance. To prevent this, a non-selected block (B
2) A voltage of -0.5 to -2 V is applied to the gate electrode 15 of the selection transistor Qs (Qs12). This allows
At the bit line voltage of +5 V, the unselected selection transistor Q
s (Qs12) is not turned on.

FIG. 7 is a conceptual sectional view showing still another example of the write operation to the memory cell M of the present embodiment.
The write operation of the selected block (B1) is the same as that of FIG. The control gate 14 of the unselected block (B2),
The source line S is set to 0V. In this case, the well 12 of the unselected block (B2) and the selection transistor Qs (Qs1
If the gate electrode 15 of (2) is 0 V, the selection transistor Qs is turned on by the main bit line MBL voltage of +5 V, and the memory drain of the unselected block (B2) is biased to generate a drain disturbance. I will. To prevent this, a voltage of -0.5 to -2 V is applied to the well 12 of the unselected block (B2) and the gate electrode 15 of the selection transistor Qs (Qs12). Thus, at the bit line voltage of +5 V, the selection transistor Qs1
2 is not turned on.

As described above, the threshold value of the selection transistor Qs is set low, and the well 12 of the non-selection block (B2), the selection transistor Qs (Qs12) of the non-selection block (B2), or both are negative. By applying the voltage, the MOS resistance of the selection transistor can be reduced while preventing data disturbance to an unselected cell. Thereby, the reading speed of the flash memory can be improved.

FIG. 8 is a conceptual sectional view showing an example of the read operation of the memory cell M of the present embodiment. First, the selection block B1 will be described. A voltage of Vcc is applied to the control gate 14 of the bit to be read (memory cell M111) and the gate electrode 15 of the selection transistor Qs11, and the control gate 14 of the memory cell not to be read is grounded. The source line S and the well 12 are grounded, and the well 11 is grounded or Vcc is applied. +1 for drain
A voltage of V is applied. The reason why the drain is lowered to +1 V is to prevent soft write or data disturbance. A channel current flows when the threshold voltage of the memory cell from which data is read is lower than Vcc, and does not flow when the threshold voltage is high. This is read by a differential or current sense amplifier, and the former is made to correspond to "0" data, and the latter to "1" data.

On the other hand, the control gate 14, the source line S, and the well 12 of the unselected block (B2) are set to 0V. At this time, the threshold voltage of the selection transistor Qs (Qs12) may be turned on by the bit line voltage of + 1V, and the parasitic capacitance of the bit line may increase. To prevent this,
By applying a voltage of −0.5 to −2 V to the gate electrode 15 of the selection transistor Qs (Qs 12), it is prevented from being re-energized by the bit line potential of +1 V.

As described above, even when the threshold voltage of the selection transistor Qs is further reduced, the selection transistors in the non-selected blocks are surely turned off, the bit line capacitance is reduced, and the MOS resistance is reduced to read data. Speed can be improved.

FIGS. 9A and 9B show a read sequence of a memory cell, wherein FIG. 9A is a circuit diagram and FIG. 9B is a time chart. As shown in FIG. 9, one cycle of the read sequence includes a time for precharging the memory drain to +1 V, a time for reading by the sense amplifier SA, and a discharge time for grounding the memory drain. At the time of reading, when the threshold voltage of the memory cell is low, a channel current flows and the drain voltage drops. When the drain voltage is high, the channel current does not flow and the drain voltage is 1
V. In the case of the differential sensing method, this voltage is compared with a reference voltage. Here, the reference voltage is set to the intermediate voltage of +1 V and the drain voltage when the channel current flows. If the same bit is read out in the next cycle unless the drain is set to 0 V by discharging, the remaining charge causes the drain voltage after precharge to be higher than +1 V. If the read time is short, the bit line voltage does not drop sufficiently even in the case of "0" data, and becomes higher than the reference voltage. In such a situation, there is a high possibility that the data is determined to be “1” data. Pre-charge the main bit line +
1V, the gate of the select transistor is applied to Vcc.

The precharge time depends on the main bit line MB
If the parasitic capacitance associated with L and the selected sub-bit line SBL is C, the sum of the wiring resistance and diffusion layer resistance of the main bit line MBL and the sub-bit line SBL is R1, and the MOS resistance of the selection transistor is R2, then C As described above, it becomes about × (R1 + R2). Further, R1 hardly causes a problem when considering that the main bit line MBL and the sub-bit line SBL are formed of a metal layer and the plane distance between the contacts is not long, and R1 << R2 may be satisfied. I mentioned above. As described above, in the present embodiment, the threshold voltage of the selection transistor Qs is set low, so that R2 can be significantly reduced, for example, by about 40%. As a result, the precharge time can be reduced, the read cycle can be shortened, and the read speed of the flash memory can be improved.

FIG. 10 is a conceptual sectional view showing the erasing operation of the memory cell M of the present embodiment. Erasing is performed in block units. A high voltage of -8 V is applied to the control gate 14 of the selected block (B1) to be erased, and 5 V is applied to the source.
Is applied. The well 12 is grounded, the well 11 is grounded or Vcc, the drain is open, and electrons are drawn from the floating gate 13 to the source by FN (Fowler-Nordheim) tunnel to lower the threshold voltage. At this time, the gate electrode 15 of the selection transistor Qs is grounded. On the other hand, the control gate 14 of the unselected block (B2)
The well 12 is grounded, the source is open, and the gate electrode 15 of the selection transistor Qs is grounded.

FIGS. 11 and 12 are sectional views showing an example of a method of manufacturing a semiconductor device according to the present embodiment in the order of steps. 11 and 12 show a selection transistor Qs, a memory cell M, a high voltage MISFET (peripheral high voltage MOS) of a peripheral circuit, and a MISFET (logic M) of a logic circuit.
OS) are shown. Here, an n-channel type M
The case of the ISFET will be described.
Needless to say, an FET may be included. In the present embodiment, the select transistor Qs, the memory cell M and the peripheral high voltage MOS are formed in a shallow P well (well 12) in a deep N well (well 11). In addition, the selection transistor Qs, the memory cell M, the peripheral high voltage MOS
Is formed in a two-layer gate structure, and the first and second layer gates of the select transistor Qs and the peripheral high voltage MOS are shown in FIG.
Connect as shown.

In the manufacturing method of this embodiment, first, a field oxide film 20 and wells 11 and 1 are formed on a semiconductor substrate 10.
2 is formed (FIG. 11A).

Next, a sacrificial oxide film 21 is formed on the main surface of the semiconductor substrate 10, and the memory cell M and the peripheral high withstand voltage MOS are formed.
A photoresist film 22 is formed in a region other than the above, boron (B) ions are implanted using the photoresist film 22 as a mask, and channel doping is performed on the memory cell M and the peripheral high-voltage MOS (FIG. 11B). Select transistor Q
The threshold voltage is lowered by not performing channel doping on s. Further, the threshold voltage can be further reduced by performing counter doping.

Next, a gate oxide film 23 having a thickness of, for example, 20 nm is formed, and the gate oxide film 23 in the memory cell M region is removed by photolithography and etching. Thereafter, a tunnel oxide film 25 having a thickness of, for example, 10 nm is formed, and a polysilicon film 24 is formed. Further, the polysilicon film 24 is patterned to form a floating gate of the memory cell M (FIG. 11C).

Next, after the ONON film (laminated film of the silicon oxide film and the silicon nitride film) 26 is deposited, the ONON film 26 and the polysilicon film 24 in the logic portion are removed by dry etching by a photolithography process.
After forming a gate oxide film 27 (for example, having a thickness of 4 to 8 nm) of the ISFET, a laminated film 28 of polysilicon and tungsten silicide is formed (FIG. 11D).

Next, the selection transistor Qs, the memory cell M, the second-layer gate of the high-breakdown-voltage MISFET, and the gate of the logic MISFET are patterned (FIG. 12).
(A)).

Next, the selection transistor Qs, the memory cell M, and the first-layer gate of the high-breakdown-voltage MISFET are patterned while the resist is left on the logic gate (FIG. 1).
2 (b)). Thereafter, it can be formed by an ordinary method such as formation of source / drain of the MISFET, passivation, contact, metal wiring, final passivation, and the like. Note that the metal wiring is the main bit line MBL,
Although the sub-bit line SBL is formed, an insulating material having a low dielectric constant can be used for an interlayer insulating film that insulates these metal wirings. For example, a silicon oxide film (Si
OF), fluororesin (PTFE: polytetrafluoroethylene), polyimide resin, BCB (Benzocyclobu
tene), SOG (Spin On Glass) containing hydrogen, organic S
OG and the like. If the main bit line and the sub bit line are insulated from these low dielectric constant materials, the capacitance (parasitic capacitance) associated with the bit line can be reduced, and the read speed of the flash memory can be improved.

Although the invention made by the inventor has been specifically described based on the embodiment, the invention is not limited to the embodiment and can be variously modified without departing from the gist of the invention. Needless to say,

That is, in the embodiment, the case where writing is performed by channel hot electron injection has been described. However, the present invention can be applied to other writing methods, for example, the case of FN tunnel at the drain end. Further, the present invention is also applied to the case where the FN tunnel at the drain end is defined as erase.

Although the embodiment has been described with reference to the case where the memory cells are of the n-channel type, they may be of the p-channel type.

[0077]

Advantageous effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows.

That is, the read speed of the flash memory can be increased while the normal operation of the flash memory is ensured. Further, the flash memory can be read normally and at high speed without changing the manufacturing process and without increasing the memory mat size.

That is, since the threshold voltage of the selection transistor can be lowered and the MOS resistance of the selection transistor can be reduced, the precharge and discharge time when reading out the flash memory can be reduced, and the reading speed can be increased. .

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a semiconductor device of the present invention.

FIG. 2 is a circuit block diagram illustrating a main part of a rewritable nonvolatile memory unit of the semiconductor device according to one embodiment of the present invention;

FIG. 3 is a circuit diagram showing a part of a memory array.

FIG. 4 is a conceptual sectional view taken along a main bit line.

FIG. 5 is a conceptual sectional view showing an example of a write operation to a memory cell according to an embodiment of the present invention.

FIG. 6 is a conceptual cross-sectional view showing another example of a write operation to a memory cell according to an embodiment of the present invention.

FIG. 7 is a conceptual sectional view showing still another example of a write operation to a memory cell according to an embodiment of the present invention.

FIG. 8 is a conceptual sectional view showing an example of a read operation of a memory cell according to an embodiment of the present invention.

FIG. 9 shows a read sequence of a memory cell,
(A) shows a circuit diagram, and (b) shows a time chart.

FIG. 10 is a conceptual sectional view showing an erase operation of a memory cell according to an embodiment of the present invention.

FIGS. 11A to 11D are cross-sectional views illustrating an example of a method of manufacturing a semiconductor device according to an embodiment of the present invention in the order of steps; FIGS.

12A and 12B are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device according to an embodiment of the present invention in the order of steps. FIG. 3C is a cross-sectional view showing a connection portion between the first transistor and the second layer of the selection transistor and the peripheral high voltage MOS.

13A and 13B are graphs showing characteristics of a selection transistor applicable to the present invention, wherein FIG. 13A shows a change in threshold voltage with respect to a gate length, and FIG. 13B shows a change in drain withstand voltage with respect to a gate length.

[Explanation of symbols]

 Reference Signs List 1 memory array 2 X decoder 3 Y gate sense and latch circuit 4 X address latch circuit 5 Y address counter circuit 6 control signal input circuit 7 I / O buffer 8 internal voltage circuit 10 semiconductor substrate 11 well 12 well 13 floating gate 14 control Gate 15 Gate electrode 16, 17 Impurity semiconductor region 20 Field oxide film 21 Sacrificial oxide film 22 Photoresist film 23 Gate oxide film 24 Polysilicon film 25 Tunnel oxide film 26 ONON film 27 Gate oxide film 28 Stacked film INT Interface section IOP Input output Port section M Memory cell MBL Main bit line Qs Select transistor R2 MOS resistance S Source line SA Sense amplifier SBL Sub bit line Vth Threshold voltage W Channel width WL Word line XA X address Address signal YA Y address signal

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI theme coat ゛ (Reference) H01L 21/8247 H01L 29/78 371 29/788 29/792 F term (Reference) 5B025 AA03 AB01 AC01 AE05 AF04 5F001 AA25 AB08 AC02 AC06 AD12 AD41 AD51 AD61 AE02 AE03 AE08 AF10 5F083 EP02 EP23 EP77 ER02 ER05 ER09 ER14 ER16 ER22 ER30 GA02 GA03 HA04 JA56 JA57 KA06 LA04 LA05 LA07 LA10 ZA12 ZA13 ZA14

Claims (8)

[Claims] A plurality of wells; a floating gate MISFET type memory cell formed in a matrix on a main surface of the well; a word line extending in a first direction; A sub-bit line extending in a second direction substantially perpendicular to the sub-bit line; a MISFET formed on the main surface of the well and provided for each sub-bit line; MISFET connected
A main bit line connected through a (select MISFET), the word line functions as a control gate of the memory cell, and the sub bit line is arranged in the well in the second direction. A method for driving a semiconductor device connected to a drain region of the memory cell and a source region of the select MISFET, wherein the main bit line is connected to a drain region of the select MISFET. At this time, a predetermined voltage is applied to a main bit line (selected main bit line) connected to a sub bit line (selected sub bit line) to which a memory cell to be written (selected memory cell) among the memory cells belongs. A word line (selected word line) to which the selected memory cell belongs among the word lines; and a selected sub-bit line among the MISFETs. MISFET (Select MISF
ET), and a voltage of a predetermined first polarity is applied to each of the sub-bit lines connected to the selected main bit line and other than the selected sub-bit line (non-selected sub-bit lines). A voltage of a second polarity opposite to the first polarity is applied to the well (unselected well) to which the bit line belongs. 2. A plurality of wells, a floating gate MISFET type memory cell formed in a matrix on a main surface of the well, a word line extending in a first direction, and a first direction. A sub-bit line extending in a second direction substantially perpendicular to the sub-bit line; a MISFET formed on the main surface of the well and provided for each sub-bit line; MISFET connected
A main bit line connected through a (select MISFET), the word line functions as a control gate of the memory cell, and the sub bit line is arranged in the well in the second direction. A method for driving a semiconductor device connected to a drain region of the memory cell and a source region of the select MISFET, wherein the main bit line is connected to a drain region of the select MISFET. At this time, a predetermined voltage is applied to a main bit line (selected main bit line) connected to a sub bit line (selected sub bit line) to which a memory cell to be written (selected memory cell) among the memory cells belongs. A word line (selected word line) to which the selected memory cell belongs among the word lines; and a selected sub-bit line among the MISFETs. MISFET (Select MISF
And a gate electrode of the selected MISFET connected to the selected main bit line and a sub-bit line other than the selected sub-bit line (non-selected sub-bit line). ) Connected to the MISFET (unselected MISFE)
T) A method of driving a semiconductor device, wherein a voltage having a second polarity opposite to the first polarity is applied to the gate electrode. 3. A plurality of wells, a floating gate MISFET type memory cell formed in a matrix on a main surface of the well, a word line extending in a first direction, and a first direction. A sub-bit line extending in a second direction substantially perpendicular to the sub-bit line; a MISFET formed on the main surface of the well and provided for each sub-bit line; MISFET connected
A main bit line connected through a (select MISFET), the word line functions as a control gate of the memory cell, and the sub bit line is arranged in the well in the second direction. A method for driving a semiconductor device connected to a drain region of the memory cell and a source region of the select MISFET, wherein the main bit line is connected to a drain region of the select MISFET. At this time, a predetermined voltage is applied to a main bit line (selected main bit line) connected to a sub bit line (selected sub bit line) to which a memory cell to be written (selected memory cell) among the memory cells belongs. A word line (selected word line) to which the selected memory cell belongs among the word lines; and a selected sub-bit line among the MISFETs. MISFET (Select MISF
ET), and a voltage of a predetermined first polarity is applied to each of the sub-bit lines connected to the selected main bit line and other than the selected sub-bit line (non-selected sub-bit lines). The well (non-selected well) to which the bit line belongs, and
The MISFET (unselected MISFE) connected to the selected main bit line and connected to a sub-bit line (unselected sub-bit line) other than the selected sub-bit line
T) A method of driving a semiconductor device, wherein a voltage having a second polarity opposite to the first polarity is applied to the gate electrode. 4. A plurality of wells, a floating gate MISFET type memory cell formed in a matrix on a main surface of the well, a word line extending in a first direction, and a first direction. A sub-bit line extending in a second direction substantially perpendicular to the sub-bit line; a MISFET formed on the main surface of the well and provided for each sub-bit line; MISFET connected
A main bit line connected through a (select MISFET), the word line functions as a control gate of the memory cell, and the sub bit line is arranged in the well in the second direction. A method for driving a semiconductor device connected to a drain region of the memory cell and a source region of the select MISFET, and wherein the main bit line is connected to a drain region of the select MISFET. A predetermined voltage is applied to a main bit line (selected main bit line) connected to a sub bit line (selected sub bit line) to which a memory cell to be read (selected memory cell) among the memory cells belongs; The word line (selected word line) to which the selected memory cell belongs among the word lines and the selected sub-bit line of the MISFET ISFET (Select MISF
And a gate electrode of the selected MISFET connected to the selected main bit line and a sub-bit line other than the selected sub-bit line (non-selected sub-bit line). ) Connected to the MISFET (unselected MISFE)
T) A method of driving a semiconductor device, wherein a voltage having a second polarity opposite to the first polarity is applied to the gate electrode. 5. The method of driving a semiconductor device according to claim 1, wherein the threshold voltage of the MISFET is such that the main bit is provided when the gate electrode and the well are at ground potential. The MISFET is turned on by the predetermined voltage applied to the line, but when the voltage of the second polarity is applied to the gate electrode or the well, the MISFET is controlled by the predetermined voltage applied to the main bit line. Is adjusted to a value that does not turn on. 6. The method for driving a semiconductor device according to claim 1, wherein the memory cell and the MISFET are of an n-channel type, and the voltage applied to the main bit line and the voltage applied to the main bit line are different from each other. The method of driving a semiconductor device, wherein the voltage of the first polarity is a positive voltage, and the voltage of the second polarity is a negative voltage. 7. A plurality of wells, a floating gate MISFET type memory cell formed in a matrix on the main surface of the well, a word line extending in a first direction, and a first direction. A sub-bit line extending in a second direction substantially perpendicular to the sub-bit line; a MISFET formed on the main surface of the well and provided for each sub-bit line; MISFET connected
A main bit line connected through a (select MISFET), the word line functions as a control gate of the memory cell, and the sub bit line is arranged in the well in the second direction. A semiconductor device connected to a drain region of the memory cell and a source region of the select MISFET, and the main bit line is connected to a drain region of the select MISFET; MISFET
If the gate electrode and the well are at the ground potential, the MISF is applied by a predetermined voltage applied to the main bit line.
ET is turned on, but when a reverse bias voltage is applied to the gate electrode or well, the MISFET is turned on by the predetermined voltage applied to the main bit line.
A semiconductor device characterized in that the value is not set. 8. The semiconductor device according to claim 7, wherein low-permittivity silicon oxide, resin, or SOG is applied to an interlayer insulating film that insulates the sub-bit line or the main bit line. Characteristic semiconductor device.