JP2001284473A - Nonvolatile semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory by which voltage can be lowered and miniaturizing can be attained. SOLUTION: An N type source region 3 and an N type drain region 4 are formed at a prescribed interval on the surface of a P type silicon substrate 2, and a source electrode 5 is formed on the source region 3. And then, on a channel region 6 between the source region 3 and the drain region 4, a floating gate electrode 9 and a control gate electrode 14 are formed adjoining, having an insulation film between, on the source region 3 side and the drain region 4 side, respectively, and moreover, the floating gate electrode 9 is formed on the side wall of the source electrode 5.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory, and more particularly to a nonvolatile semiconductor memory which requires a large capacitance ratio between a floating gate and a source diffusion layer.

[0002]

2. Description of the Related Art Memory cells (memory cell transistors) constituting a flash EEPROM are roughly classified into a stacked gate type and a split gate type. Flash EEPROM using stacked gate type memory cells
M has no function of selecting itself for each memory cell. Therefore, when extracting charges from the floating gate electrode during data erasing, if the charges are excessively extracted, a predetermined voltage (for example, 0 V) for bringing the memory cell into a non-conductive state is used.
Is applied to the control gate electrode, the channel region becomes conductive. As a result, the memory cell is always in a conductive state, a cell current always flows between the source region and the drain region, and a problem that reading of stored data becomes impossible, that is, a problem of so-called excessive erasure occurs. In order to prevent over-erasing, it is necessary to devise an erasing procedure. It is necessary to control the erasing procedure in a peripheral circuit of the memory device or to control the erasing procedure in an external circuit of the memory device.

A split gate type memory cell has been developed in order to avoid the problem of excessive erasure in such a stacked gate type memory cell. Flash EEPROM using split gate memory cells
Are disclosed in WO 92/18980 (G11C 13/00). FIG. 14 is a sectional view of a conventional split gate memory cell 101. As shown in FIG. The split gate memory cell (split gate transistor) 101 mainly includes a source region 103, a drain region 104, and a channel region 1.
06, a floating gate electrode 109, and a control gate electrode 114.

An N type source region 103 and a drain region 104 are formed on a P type single crystal silicon substrate 102. A floating gate electrode 109 is formed over a channel region 106 interposed between the source region 103 and the drain region 104 with a gate insulating film 107 interposed therebetween. On the floating gate electrode 109, LOCOS (Local Oxidation on Sil
The control gate electrode 114 is formed via the insulating film 110 formed by the (icon) method. Floating gate electrode 1
A corner is formed by the LOCOS method in the peripheral portion of 09,
Between the control gate electrode 114 and the thin tunnel insulating film 1
13 are formed.

Here, a part of the control gate electrode 114 is
It is arranged on the channel region 106 via the insulating film 111 and forms a select gate. A selection transistor is formed by the selection gate, the source region 103, and the drain region 104. That is, the split gate type memory cell 101 includes the gate electrodes 109 and 114
Are configured as transistors connected in series.

In the split gate type memory cell 101, in a write operation for accumulating electrons in the floating gate electrode 109, electrons in the channel 106 of the semiconductor substrate are converted into hot electrons and injected into the floating gate electrode 109. , It is necessary to apply a voltage of more than ten V to the source region 103. In the erasing operation for extracting electrons from the floating gate electrode 109, more than ten V
And electrons are extracted from the floating gate electrode 109 to the control gate electrode 114 via the tunnel insulating film 113.

However, as the split-gate memory cell is further miniaturized, the withstand voltage of the drain-source region is reduced. Therefore, it is necessary to lower the voltage applied to the source region during source writing. Then, it is necessary to increase the coupling capacitance ratio between the source region and the floating gate so that the floating gate potential can be sufficiently increased at a low voltage to maintain the writing speed. In order to increase the capacitance ratio, it is effective to increase the contact area between the source region and the floating gate and to reduce the thickness of the capacitance insulating film.

[0008]

In a conventional split gate type memory cell 101, a floating gate electrode 10 is provided.
In order to secure a predetermined capacitance by increasing the contact area between the source region 103 and the source region 103, it is necessary to form the source region 103 deeper than the drain region 104. There is a problem that the punch-through withstand voltage between the layers 104 is reduced, which hinders miniaturization.

In the conventional split gate type memory cell 101, the tunnel insulating film 113 has a LOC
It was formed by a locally thin insulating film between the corner of the floating gate electrode 109 formed by the OS method and the control gate electrode 114. However, in the LOCOS method, it is difficult to lower the process temperature, which hinders miniaturization.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a nonvolatile semiconductor memory which can be miniaturized simultaneously with a low voltage operation.

[0011]

A nonvolatile semiconductor memory according to a first aspect of the present invention is formed at a predetermined interval in a first layer made of a semiconductor of one conductivity type, and is formed opposite to the first layer. A first region and a second region having the same conductivity type, a first electrode formed on the first region, and a side wall of the first electrode formed between the first region and the second region. A floating gate electrode, and a control gate electrode adjacent to the floating gate electrode with a first insulating film interposed therebetween and formed on the opposite side to the first electrode, wherein the floating gate electrode and the first electrode The gist is that the sum of the capacitance between the floating gate electrode and the first region is larger than the sum of the capacitance between the floating gate electrode and the first layer and between the floating gate electrode and the control gate electrode.

A nonvolatile semiconductor memory according to a second aspect of the present invention is formed at a predetermined interval in a first layer made of a semiconductor of one conductivity type, and has a first conductivity type opposite to that of the first layer. A region, a second region, a first electrode formed on the first region, a floating gate electrode formed on a side wall of the first electrode between the first region and the second region, A control gate electrode adjacent to the floating gate electrode with a first insulating film interposed therebetween and formed on a side opposite to the first electrode, wherein the control gate electrode includes a part of the second region and The floating gate electrode is electrically insulated by a first layer and a second insulating film, and is connected to the first region and the first layer by a third layer.
And the first electrode is electrically insulated from the first electrode and between the floating gate electrode and the first electrode and between the floating gate electrode and the first region. The gist is that the sum of the capacitances is larger than the sum of the capacitances between the floating gate electrode and the first layer and between the floating gate electrode and the control gate electrode.

Therefore, according to the present invention, since the floating gate faces the side wall of the first electrode, the electrostatic capacitance between the floating gate electrode and the first electrode and between the floating gate electrode and the first region even with a small cell size. It is possible to increase the sum of the capacitances, so that miniaturization and low voltage can be achieved. In this case, the floating gate electrode is desirably formed in an L-shape or an inverted L-shape on the first region and the first layer and on the side wall of the first electrode.

This makes it possible to increase the thickness of the first insulating film between the floating gate electrode and the control gate electrode, to reduce the capacitance between the two, and to relatively reduce the floating gate electrode even in a small cell size. And the capacitance between the first electrode and between the floating gate electrode and the first region can be increased, so that miniaturization and low voltage can be achieved. The erasing operation of the nonvolatile semiconductor memory according to the present invention is performed by the FN tunneling phenomenon, in which the L-shaped floating gate electrode passes through the first insulating film between the control gate and the end adjacent to the control gate, from the floating gate electrode to the control gate electrode. This is done by drawing electrons to

[0015]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a cross-sectional view of a main part of a memory cell 1 of the present embodiment. p-type single crystal silicon substrate 2
An n-type source region 3 and an n-type drain region 4 are formed at predetermined intervals on the surface. Source area 3
Is connected to the source electrode 5. On the side of the source region 3 on the channel region 6 between the source region 3 and the drain region 4 on the surface of the substrate 2, a floating gate electrode 9 made of an n-type polycrystalline silicon film is formed on the side wall of the source electrode 5. Have been. The floating gate electrode 9 is electrically separated from the source region 3 and the channel region 6 by a floating gate insulating film 7 made of a silicon oxide film, and is electrically insulated from the source electrode 5 by a capacitive insulating film 8. I have. On the floating gate electrode 9, a second insulating layer 10 is formed. Further, on the drain region 4 side on the channel region 6 between the source region 3 and the drain region 4 on the surface of the substrate 2, a control gate insulating film 11, a control gate electrode 14 made of a polycrystalline silicon film, and a silicon oxide film A third insulating layer 15 is formed.

The silicon substrate 2 corresponds to the "first layer" in the present invention, and the source region 3 corresponds to the "first layer" in the present invention.
The drain region 4 corresponds to the “second region” in the present invention, the source electrode 5 corresponds to the “first electrode” in the present invention, and the floating gate insulating film 7 corresponds to the “third electrode” in the present invention. The control gate insulating film 11 corresponds to the “second insulating film” in the present invention, and the second insulating layer 10
The tunnel insulating film 13 corresponds to the “first insulating film” in the present invention.

A tunnel insulating film 13 is formed on the control gate insulating film 11, so that tunnel electrons can pass from the floating gate electrode 9 to the control gate electrode 14. Here, the film thickness of each of the above members is set as follows.・ Thickness of source electrode 5: 300 to 500 nm ・ Thickness of floating gate insulating film 7: 8 nm ・ Thickness of capacitive insulating film 8: 8 to 15 nm ・ Thickness of floating gate electrode 9: 30 to 50 nm ・ Second insulation Thickness of layer 10: 200 to 400 nm Thickness of gate insulating film 11: 10 to 20 nm Thickness of control gate electrode 14: 200 to 400 nm Thickness of third insulating layer 15: 50 to 200 nm The sum of the capacitance between the gate electrode 9 and the source region 3 and the capacitance between the floating gate electrode 9 and the source electrode 5 is determined between the floating gate electrode 9 and the channel region 6 and between the floating gate electrode 9 and the control gate electrode 14. Is larger than the sum of the capacitances.

FIG. 2 shows an entire configuration of a nonvolatile semiconductor memory 50 using the memory cell 1. Memory cell array 5
Reference numeral 1 denotes a configuration in which a plurality of memory cells 1 are arranged in a matrix (in FIG. 2, for simplification of the drawing,
Only four memory cells are shown). In each memory cell 1 arranged in rows (row) direction, each of the control gate electrode 14 is connected to a common word line WL ₁ to WL _n.

In each of the memory cells 1 arranged in the column direction, the drain region 4 has a common bit line BL.
It is connected to ₁ to BL _n, the source electrode 5 is connected to a common source line SL. Each word line WL ₁ to WL _n are connected to a row decoder 52, the bit lines BL ₁ ~BLd _n is connected to the column decoder 53.

A row address and a column address specified from the outside are input to an address pin 54. The row address and the column address are applied to the address pins 5
4 to the address latch 55. Of the addresses latched by the address latch 55, the row address is transferred to the row decoder 52 via the address buffer 56, and the column address is transferred to the column decoder 53 via the address buffer 56.

The row decoder 52 is connected to each of the word lines WL ₀ to WL ₀ .
Of WL _n, selects a word line corresponding to the latched row address in the address latch 55, on the basis of a signal from the gate voltage control circuit 57, the word lines WL ₁ to WL _n
Is controlled in accordance with each operation mode described later. Column decoder 53, among the bit lines BL ₁ to BL _n, selects a bit line corresponding to the latched column address in the address latch 55, on the basis of a signal from the drain voltage control circuit 58, the bit lines BL and corresponding control to the operation mode described below the potential of ₁ to BL _n.

Externally designated data is input to data pin 59. The data is transferred from the data pin 59 to the column decoder 53 via the input buffer 60. The column decoder 53 is connected to each of the bit lines BL _{1 to} BL _n
Is controlled in accordance with the data as described later. Data read from an arbitrary memory cell 1 is transferred from each of the bit lines BL _{1 to} BL _n to the sense amplifier group 61 via the column decoder 53. The sense amplifier 61 is a current sense amplifier. The data determined by the sense amplifier group 61 is output from the output buffer 62 to the outside via the data pin 59.

The source voltage control circuit 63
The potential is controlled according to each operation mode described later. still,
The operation of each of the above circuits (52 to 63) is controlled by a control core circuit.
64. Then configured as above
Operation (write operation, erase operation, read operation)
Out operation) will be described. Source region 3 (source electrode
In 5), the source voltage Vs is applied via the source line SL.
And the drain region 4 has a bit line BL₁~ BL_nThrough
The drain voltage Vd is applied, and the control gate electrode 14
Word line WL ₀~ WL_nControl gate voltage Vcg
Then, a substrate voltage Vsub is applied to the substrate 2.

(Writing Operation) Before performing this writing operation, the floating gate electrode 9 is in an erased state (a state in which electrons are extracted). In the present embodiment, the floating gate electrode 9 in the erased state is A potential of about 2 V is maintained. Further, in the present embodiment, the respective threshold voltages Vt of the transistor having the floating gate electrode 9 as the gate and the transistor having the control gate electrode 14 as the gate
Are both set to 0.5V.

In the write operation, the operating voltage of the memory cell 1 is set to a source voltage Vs: 8 V and a drain voltage Vd:
1.3 V, control gate voltage Vcg: 2 V, substrate voltage (well voltage when memory cell 1 is formed in a p-type well formed on a silicon substrate: well voltage)
b: Set to 0V. The control gate transistor is in a weak ON state, and a channel current flows from the source region 3 to the drain region 4. At this time, as described above, since the source electrode 5 (source region 3) and the floating gate electrode 9 are strongly coupled capacitively, the potential of the floating gate electrode 9 rises to about 8V. Then, a strong electric field is generated at the boundary portion 16 of the channel region 7 immediately below the control gate 14 and the floating gate 9, and hot electrons are generated. The hot electrons are generated in the channel region 7
To the floating gate electrode 9. As a result, electrons are accumulated in the floating gate 9, and data is written.

(Erase Operation) In the erase operation, the operating voltages of the memory cell 1 are set to a source voltage Vs: 0 V, a drain voltage Vd: 0 V, a control gate voltage Vcg: 9 V, and a substrate voltage (well voltage) Vsub: 0 V. I do. Then, since the source electrode 5 and the floating gate electrode 9 are strongly coupled in terms of capacitance, the potential of the floating gate electrode 11 becomes almost 0V.

On the other hand, the potential of the control gate 14 is 9 V, and a high electric field of about 10 MV is generated in the interpoly tunnel insulating film 13 located between the control gate 14 and the floating gate electrode 9. As a result, an FN tunnel current flows, electrons are extracted from the floating gate electrode 9 to the control gate electrode 14, and data is erased. (Read Operation) In the read operation, the operating voltages of the memory cell 1 are set to a source voltage Vs: 0 V, a drain voltage Vd: 2 V, a control gate voltage Vcg: 2 V, and a substrate voltage (well voltage) Vsub: 0 V.

In a state where electrons are not accumulated in the floating gate electrode 9 (erasing state), the floating gate electrode 9 is positively charged (in the present embodiment, the floating gate electrode 9 has a potential of 2 V). Therefore, the channel region 7 below the floating gate electrode 9 is turned on. In a state where electrons are accumulated in the floating gate electrode 9 (writing state), the floating gate electrode 9 is negatively charged, and thus the channel region 7 below the floating gate electrode 9 is turned off.

When the channel region 7 is on, a current flows between the source region 3 and the drain electrode 4 than when the channel region 7 is off. Therefore, by detecting the current (cell current) flowing between the source region 3 and the drain electrode 4, it is possible to determine whether or not electrons are accumulated in the floating gate electrode 9. 1 can be read.

In the above read operation, the same read operation can be performed even if the potential relationship between the source voltage Vs and the drain voltage Vd is reversed. According to the present embodiment, the following operations and effects can be obtained. (1) Compared to the conventional cell structure 101, the memory cell 1 has a large capacitance coupling with the floating gate electrode 11 because the source electrode 5 is provided in addition to the source region 3. .

Therefore, during the write operation, even if the same source voltage is applied, the potential of the floating gate electrode 11 can be raised to a higher potential, and a higher accelerating electric field can be generated in the channel region 16. That is, electrons can be efficiently injected from the channel region 16 to the floating gate electrode 9, and the writing characteristics are improved. as a result,
It is possible to reduce the write voltage, particularly the source voltage, without deteriorating the write characteristics, which can contribute to miniaturization as a semiconductor memory.

(2) The conventional memory cell 101 has no source electrode 5 as compared with the cell 1 of the present invention.
The facing area between the floating gate and the source region 3 is small. Therefore, the source region is formed deep to secure a sufficient capacitance ratio. Therefore, when the cell 1 of the present invention is compared with the same memory cell size, the cell 1 of the present invention has a higher punch-through breakdown voltage between the source and the drain, and is suitable for miniaturization.

Next, a method of manufacturing the memory cell 1 according to the present embodiment will be described with reference to FIGS. Step 1 (see FIG. 3): A silicon oxide film 21 and a silicon nitride film 22 are formed on the p-type single crystal silicon substrate 2. Step 2 (see FIG. 4): A portion to be a source region is opened to the substrate, an n-type impurity is implanted to form a source region 3, and then a source electrode 5 made of n-type doped polysilicon is formed by a CMP method. And embed. As an embedding method, an etch-back method may be used instead of the CMP method. Thereafter, the first insulating layer 12 is formed by selective oxidation on the source electrode.

Step 3 (see FIG. 5); silicon nitride film 22
And the silicon oxide film 21 is removed. Step 4 (see FIG. 6): After forming the floating gate oxide film 7 and the capacitance insulating film 8 by the dry oxidation method,
Is deposited to form n-type doped polysilicon 23. Here, there are the following methods for forming the doped polysilicon film.

Method 1: When a polysilicon film is formed by using the LPCVD method, a gas containing impurities is mixed into a source gas. Method 2: After forming a non-doped polysilicon film using the LPCVD method, an impurity diffusion source layer (such as POCl ₃ ) is formed on the polysilicon film, and impurities are diffused from the impurity diffusion source layer into the polysilicon film. .

Method 3: After forming a non-doped polysilicon film by using the LPCVD method, impurity ions are implanted. Step 5 (see FIGS. 7 and 8): formation of a floating gate and formation of an isolation region from an adjacent memory cell. (FIG. 7 is a top view, FIG. 8 is a cross section taken along the line AA ′ in FIG. 7) Step 6 (see FIGS. 9 and 10): depositing a silicon oxide film by a CVD method, and then performing etch-back, 10 and an element isolation film 24 are formed. (FIG. 10 is a BB ′ cross section in FIG. 9) Step 7 (see FIG. 11); n-type doped polysilicon 23
Is etched back to form the floating gate electrode 9 on the side wall portion of the source electrode 5 and on the channel region 6 near the source region 3.

Step 8 (see FIG. 12): A control gate insulating film 11 is formed. As a method for forming the control gate insulating film, there are an oxidation method and a CVD method. Step 9 (see FIG. 13): A control gate electrode 14 is formed on the side wall of the first silicon insulating layer 10 by depositing a doped polysilicon film and then performing etch back. Further, a silicon oxide film is deposited and then etched back to form a third insulating layer 1 on the side wall of the control gate electrode 14.
5 is formed. Third insulating layer 15, control gate electrode 14,
Using the second insulating layer 10 and the first insulating layer 12 as a mask,
An n-type impurity is implanted into the substrate 2 to form a drain region 4.

Thus, the memory cell 1 is completed. After that, an interlayer insulating film (not shown) is formed on each memory cell 1 and word lines WL _{0 to} W connected to each control gate electrode 14 are formed.
L _n , bit lines BL _{0 to} BL connecting the drain regions 4
_The memory cell array 50 is formed by forming a source line SL that connects _n and the source electrodes 5 in common.

[0039]

According to the present invention, since the floating gate is formed on the side wall of the first electrode, the capacitance between the floating gate electrode and the first region is equal to the capacitance between the first electrodes. Since it is added, the capacitance between the floating gate electrode and the first region can be substantially increased even with a small cell size, and miniaturization and low voltage can be achieved.

[Brief description of the drawings]

FIG. 1 is a partial cross-sectional view of a memory cell according to an embodiment of the invention.

FIG. 2 is a block circuit diagram of a semiconductor memory according to an embodiment of the present invention;

FIG. 3 is a process sectional view illustrating the method for manufacturing the memory cell according to the embodiment;

FIG. 4 is a process sectional view illustrating the method for manufacturing the memory cell of the embodiment.

FIG. 5 is a process cross-sectional view for explaining the method for manufacturing the memory cell of the present embodiment.

FIG. 6 is a process sectional view illustrating the method for manufacturing the memory cell of the embodiment.

FIG. 7 is a top view for explaining the method for manufacturing the memory cell of the present embodiment.

FIG. 8 is a process sectional view illustrating the method for manufacturing the memory cell of the embodiment.

FIG. 9 is a process sectional view illustrating the method for manufacturing the memory cell of the embodiment.

FIG. 10 is a process sectional view illustrating the method for manufacturing the memory cell of the embodiment.

FIG. 11 is a process cross-sectional view for explaining the method for manufacturing the memory cell of the present embodiment.

FIG. 12 is a process cross-sectional view for explaining the method for manufacturing the memory cell of the present embodiment.

FIG. 13 is a process sectional view illustrating the method for manufacturing the memory cell of the embodiment.

FIG. 14 is a partial cross-sectional view of a memory cell according to an embodiment of the related art.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 memory cell 2 p-type single crystal silicon substrate 3 source region 4 drain region 5 source electrode 6 channel region 7 floating gate insulating film 8 capacitive insulating film 9 floating gate electrode 10 second insulating layer 11 control gate insulating film 12 first insulating layer 13 Tunnel insulating film 14 Control gate electrode 15 Third insulating layer

Continued on front page F-term (reference) 5F001 AA02 AA05 AA32 AA33 AB03 AC01 AD05 AD33 5F083 EP03 EP13 EP25 EP43 EP48 EP53 EP67 ER02 ER09 ER14 ER17 ER21 GA05 GA09 PR40 5F101 BA02 BA14 BA15 BA22 BB04 BC01 BD20 BD31

Claims (4)

[Claims] 1. A first layer made of a semiconductor of one conductivity type, which is formed at a predetermined distance from a first layer, and a first region and a second region of a conductivity type opposite to the first layer, and on the first region. A first electrode formed on the first region; a floating gate electrode formed on a side wall of the first electrode between the first region and the second region;
A control gate electrode adjacent to the floating gate electrode with a first insulating film interposed therebetween and formed on a side opposite to the first electrode, wherein a control gate electrode is provided between the floating gate electrode and the first electrode; A nonvolatile semiconductor memory, wherein the sum of the capacitances between the first regions is larger than the sum of the capacitances between the floating gate electrode and the first layer and between the floating gate electrode and the control gate electrode. 2. A first region and a second region, which are formed at a predetermined interval in a first layer made of a semiconductor of one conductivity type, and are opposite in conductivity type to the first layer, and on the first region. A first electrode formed on the first region; a floating gate electrode formed on a side wall of the first electrode between the first region and the second region;
A control gate electrode adjacent to the floating gate electrode with a first insulating film interposed therebetween and formed on a side opposite to the first electrode, wherein the control gate electrode includes a part of the second region and Electrically insulated by the first layer and the second insulating film,
The floating gate electrode is electrically insulated from the first region and the first layer by a third insulating film, and is electrically insulated from the first electrode by a fourth insulating film. The sum of the capacitances between the first electrodes and between the floating gate electrode and the first region is larger than the sum of the capacitances between the floating gate electrode and the first layer and between the floating gate electrode and the control gate electrode. Nonvolatile semiconductor memory. 3. The L-shaped or inverted L-shaped floating gate electrode is formed on the first region and the first layer, and on the side wall of the first electrode. Item 2
3. The non-volatile semiconductor memory according to claim 1. 4. An electron is drawn from the floating gate electrode to the control gate electrode through a first insulating film between the control gate and an end of the L-shaped floating gate electrode adjacent to the control gate. The nonvolatile semiconductor memory according to claim 3.