JP2000022115A - Semiconductor memory and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor memory which has a stable writing characteristic and a fast operating speed, can be made finer in size, is free of over- etching, and can be improved in writing and read-out characteristics. SOLUTION: A memory cell 1 is composed of source/drain regions 3, channel regions 4, floating gate electrodes 5 and 6, and control gate electrodes 7. A tunnel insulating film 10 is provided on insulating films 9, source/drain regions 3, and channel regions 4 formed above the floating gate electrodes 5 and 6. Insulating films 30 are provided on the insulating films 9 and source/drain regions 3 and selective gates 11 are provided on the insulating films 30 and selective gates 11 above the channel regions 4. At both corner sections of the electrodes 5 and 6, projections 5a and 6a are formed. A selective transistor 12 is constituted of the source/drain regions 3 which hold each selective gate 11 in between and the gate 11.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor memory and a method for manufacturing the same.

[0002]

2. Description of the Related Art In recent years, as a nonvolatile semiconductor memory, for example, an EEPROM (Electrically Erasable and Prog
Rammable Read Only Memory) is attracting attention. In this EEPROM, data is stored by accumulating charges in a floating gate and detecting a change in threshold voltage due to the presence or absence of charges by a control gate.
The EEPROM includes a flash EEPROM which erases data in the entire memory chip or divides a memory cell array into arbitrary blocks and erases data in each block unit.

[0003] There are a split gate type, a stacked gate type and the like as memory cells constituting a flash EEPROM. In a flash EEPROM using a stacked gate memory cell, a predetermined voltage (for example, a predetermined voltage (for example,
Even when 0 V) is applied to the control gate electrode, the channel region is turned on. As a result, the memory cell is always turned on, and reading of stored data becomes impossible, that is, a problem of so-called excessive erasure occurs.
In order to prevent excessive erasure, the erasing procedure needs to be devised, and it is necessary to control the erasing procedure in a peripheral circuit of the memory device or to control the erasing procedure in an external circuit of the memory device.

A split gate type memory cell has been developed in order to avoid the problem of excessive erasure in such a stacked gate type memory cell. Flash EEPROM using split gate memory cells
Are disclosed in WO 92/18980 (G11C 13/00).

FIG. 26 is a sectional view of a conventional split gate type memory cell 201. As shown in FIG. The split gate type memory cell (split gate type transistor) 201
Source region 203, drain region 204, channel region 205, floating gate electrode 206, and control gate electrode 2
07.

An N-type source region 203 and a drain region 204 are formed on a P-type single crystal silicon substrate 202. On the channel region 205 sandwiched between the source region 203 and the drain region 204, a floating gate electrode 206 is formed via a gate insulating film 208. LOCOS (Local Oxidation of Sil
icon) method, the insulating film 209 and the tunnel insulating film 21
0 is formed, and the control gate electrode 207 is formed on the tunnel insulating film 210. A protrusion 206 a is formed above the floating gate electrode 206 by the insulating film 209.

Here, a part of the control gate electrode 207 is
It is arranged on the channel region 205 via each of the insulating films 208 and 210, and forms a selection gate 211. The select gate 211, the source region 203 and the drain region 2
04 forms the selection transistor 212.
That is, the split gate memory cell 201 has a configuration in which a transistor including each of the gate electrodes 206 and 207 and each of the regions 203 and 204 and a selection transistor 212 are connected in series.

FIG. 27 shows a memory cell array 302 of a flash EEPROM using the split gate type memory cells 201. FIG. 27B is a partial plan view of the memory cell array 302, and FIG.
It is XX sectional drawing in (b).

The memory cell array 302 includes a plurality of memory cells 20 formed on a P-type single crystal silicon substrate 202.
1. In order to reduce the occupied area on the substrate 202, the two memory cells 201
(Hereinafter, "201a" and "201b" to distinguish the two
), The source region 203 is made common, and the floating gate electrode 20 is formed around the common source region 203.
6 and the control gate electrode 207 are arranged to be line-symmetric.

A field insulating film 213 is formed on the substrate 202.
Are formed, and element isolation between the memory cells 201 is performed by the field insulating film 213. FIG.
Each memory cell 201 arranged in the vertical direction in FIG.
Are common. FIG.
Each memory cell 201 arranged in the vertical direction in FIG.
Are common, and the control gate electrode 207 forms a word line.
Further, each drain region 204 arranged in the horizontal direction in FIG. 27B is connected to a bit line (not shown) via a bit line contact 214.

Next, each operation mode (write operation, read operation, erase operation) of the flash EEPROM will be described with reference to FIG. (A) Write operation (see FIG. 28A) The drain region 204 of the selected memory cell 201
It is connected to a constant current source 310a provided in the sense amplifier 310, and its potential is set to about 1.2V. The potential of the drain region 204 of each memory cell 201 other than the selected memory cell 201 is set to 3V.

The potential of the control gate electrode 207 of the selected memory cell 201 is set to 2V. The potential of the control gate electrode 207 of each memory cell 201 other than the selected memory cell 201 is set to 0V.

The source regions 20 of all the memory cells 201
The potential of 3 is set to 12V. In the memory cell 201, the threshold voltage Vth of the selection transistor 212 is about 0.5.
5V. Therefore, in the selected memory cell 201, the electrons in the drain region 204 move into the channel region 205 in the inverted state. Therefore, the source region 203
, A cell current flows toward the drain region 204.
On the other hand, since the potential of the source region 203 is 12 V, the floating gate electrode 206 is coupled by coupling between the source region 203 and the floating gate electrode 206 through the capacitance.
Rises to near 12V. for that reason,
A high electric field is generated between the channel region 205 and the floating gate electrode 206. Therefore, the electrons in the channel region 205 are accelerated to become hot electrons, and are injected into the floating gate electrode 206 as shown by an arrow A in FIG. As a result, charges are accumulated in the floating gate electrode 206 of the selected memory cell 201, and 1-bit data is written and stored.

This write operation can be performed for each selected memory cell 201. (B) Read operation (see FIG. 28B) The potential of the drain region 204 of the selected memory cell 201 is set to 2V. In addition, the selected memory cell 201
The potential of the drain region 204 of each of the other memory cells 201 is set to 0V.

The potential of the control gate electrode 207 of the selected memory cell 201 is set to 4V. The potential of the control gate electrode 207 of each memory cell 201 other than the selected memory cell 201 is set to 0V.

Source regions 20 of all memory cells 201
The potential of No. 3 is set to 0V. As will be described later, no charge is stored in the floating gate electrode 206 of the memory cell 201 in the erased state. In contrast, as mentioned above,
Electric charges are accumulated in the floating gate electrode 206 of the memory cell 201 in the written state. Therefore, the channel region 205 immediately below the floating gate electrode 206 of the memory cell 201 in the erased state is in the ON state, and the channel region 205 immediately below the floating gate electrode 206 of the memory cell 201 in the written state is close to the OFF state. ing. Therefore, when 4 V is applied to the control gate electrode 207, the cell current flowing from the drain region 204 toward the source region 203 is larger in the erased memory cell 201 than in the written memory cell 201.

The value of the data stored in the memory cell 201 can be read by determining the magnitude of the cell current between the memory cells 201 by the sense amplifier 310. For example, reading is performed with the data value of the memory cell 201 in the erased state set to “1” and the data value of the memory cell 201 in the written state set to “0”. In other words, in each memory cell 201, two values of the data value "1" in the erased state and the data value "0" in the written state can be stored, and the data values can be read.

(C) Erasing Operation (See FIG. 28C) The potentials of the drain regions 204 of all the memory cells 201 are set to 0V. The potential of the control gate electrode 207 of the selected memory cell 201 is set to 15V. The potential of the control gate electrode 207 of each memory cell 201 other than the selected memory cell 201 is set to 0V.

Source regions 20 of all memory cells 201
The potential of No. 3 is set to 0V. Source region 203 and substrate 2
When the capacitance between the gate electrode 02 and the floating gate electrode 206 is compared with the capacitance between the control gate electrode 207 and the floating gate electrode 206, the former is overwhelmingly larger. That is,
The floating gate electrode 206 includes the source region 203 and the substrate 2
02 is strongly coupled. Therefore, even when the control gate electrode 207 becomes 15V and the drain region 204 becomes 0V, the potential of the floating gate electrode 206 does not change so much from around 0V, and the potential difference between the control gate electrode 207 and the floating gate electrode 206 becomes large. A high electric field is generated between the electrodes 207 and 206.

As a result, Fowler-Nordheim Tunnel Current (hereinafter, referred to as Fowler-Nordheim Tunnel Current)
FN tunnel current) flows, and electrons in the floating gate electrode 206 are drawn out to the control gate electrode 207 side as shown by an arrow B in FIG.
Is erased.

At this time, since the projection 206a is formed on the floating gate electrode 206, the floating gate electrode 20
The electrons in 6 jump out of the protrusion 206a and move to the control gate electrode 207 side. Therefore, the movement of the electrons is facilitated, and the electrons in the floating gate electrode 206 can be efficiently extracted.

Here, a common word line is formed by the control gate electrodes 207 of the memory cells 201 arranged in the row direction. Therefore, the erase operation is performed on all the memory cells 201 connected to the selected word line.

By simultaneously selecting a plurality of word lines, an erasing operation can be performed on all the memory cells 201 connected to each word line. The erase operation of dividing the memory cell array 302 into arbitrary blocks for each of a plurality of sets of word lines and erasing data in each block is called block erase.

A flash EEPROM using the split gate type memory cell 201 configured as described above is
Since the selection transistor 212 is provided, each memory cell 201 has a function of selecting itself. In other words, even if the charge is excessively extracted from the floating gate electrode 206 during data erasing, the selection gate 2
11, the channel region 205 can be turned off. Therefore, even if excessive erasure occurs, the selection transistor 212 turns on / off the memory cell 201.
The off state can be controlled, and excessive erasure is not a problem. That is, the on / off state of the memory cell itself can be selected by the selection transistor 212 provided inside the memory cell 201.

Next, a method of manufacturing the memory cell array 302 will be described step by step. Step 1 (see FIG. 29A): A field insulating film 213 (not shown) is formed on the substrate 202 by using the LOCOS method. Next, the field insulating film 2 on the substrate 202
A gate insulating film 208 made of a silicon oxide film is formed by using a thermal oxidation method in a portion (element region) where 13 is not formed. Subsequently, a doped polysilicon film 215 to be the floating gate electrode 206 is formed on the gate insulating film 208. And LPCVD (Low Pressure Chemical Vapor)
A silicon nitride film 216 is formed on the entire surface of the doped polysilicon film 215 by using a pour deposition method. Next, after applying a photoresist on the entire surface of the silicon nitride film 216, using a normal photolithography technique,
An etching mask 217 for forming the floating gate electrode 206 is formed.

Step 2 (see FIG. 29B): The silicon nitride film 216 is etched by anisotropic etching using the etching mask 217. Then, the etching mask 217 is removed. Next, an insulating film 209 is formed by oxidizing the doped polysilicon film 215 by using the etched silicon nitride film 216 as an oxidation mask by using the LOCOS method. At this time, the end of the insulating film 209 enters the end of the silicon nitride film 216, and a bird's beak 209a is formed.

Step 3 (see FIG. 29C): The silicon nitride film 216 is removed. Next, the floating gate electrode 206 is formed by etching the doped polysilicon film 215 by anisotropic etching using the insulating film 209 as an etching mask. At this time, since the bird's beak 209a is formed at the end of the insulating film 209, the upper edge of the floating gate electrode 206 becomes sharp along the shape of the bird's beak 209a, and the projection 206a is formed.

Step 4 (see FIG. 29 (d)): A tunnel insulating film 210 made of a silicon oxide film is formed on the entire surface of the device formed in the above-described steps by using a thermal oxidation method, an LPCVD method, or a combination thereof. . Then, the stacked insulating films 208 and 210 and the insulating films 209 and 210 are integrated, respectively.

Step 5 (see FIG. 30E): A control gate electrode 207 is formed on the entire surface of the device formed in the above step.
A doped polysilicon film 218 is formed. Step 6 (see FIG. 30 (f)): After applying a photoresist to the entire surface of the device formed in the above step, the control gate electrode 2 is formed using ordinary photolithography technology.
An etching mask 219 for forming 07 is formed.

Step 7 (see FIG. 30G): The doped polysilicon film 218 is etched by anisotropic etching using an etching mask 219 to form a control gate electrode 207. Then, etching mask 2
19 is removed.

Step 8 (see FIG. 31 (h)): After applying a photoresist to the entire surface of the device formed in the above step, ions for forming the source region 203 are formed by using ordinary photolithography technology. Injection mask 22
0 is formed. Next, phosphorus ions (P +) are implanted into the surface of the substrate 202 to form a source region 203 by using a normal ion implantation method. After that, the ion implantation mask 22
Remove 0.

At this time, the ion implantation mask 220 is
It is formed so as to cover at least a portion to be the drain region 204 on the substrate 202 and the floating gate electrode 206
It is formed so as not to protrude above. As a result, the position of the source region 203 is defined by the end of the floating gate electrode 206.

Step 9 (see FIG. 31 (i)): After a photoresist is applied to the entire surface of the device formed in the above step, ions for forming the drain region 204 are formed by using ordinary photolithography technology. Injection mask 2
21 are formed. Next, the drain region 204 is formed by implanting arsenic ions (As +) into the surface of the substrate 202 using a normal ion implantation method.

At this time, the ion implantation mask 221 is
It is formed so as to cover at least the source region 203 and not to protrude above the control gate electrode 207. As a result, the position of the drain region 204 is defined by the end of the control gate electrode 207 on the select gate 211 side.

Then, when the ion implantation mask 221 is removed, the memory cell array 302 is completed.

[0036]

However, the flash EEPROM using the split gate type memory cell 201 has the following problems.

(1) Due to the displacement of the etching mask 219 for forming the control gate electrode 207,
A problem that the write characteristics of each memory cell 201 vary.

As shown in FIG. 32A, in the step 6, the position of the etching mask 219 for forming the control gate electrode 207 is changed to the position of each of the memory cells 201a and 201a.
01b, the shape of the control gate electrode 207 formed in step 7 is
1a and 201b are different.

When the drain region 204 is formed by the ion implantation method in the step 9, the drain region 20 is formed.
4 corresponds to the position of the selection gate 211 of the control gate electrode 207.
Side edge.

Therefore, when the position of the etching mask 219 is shifted as shown in FIG.
As shown in (b), each memory cell 201a, 201b
Of channel region 205 (channel length) L1, L2
Will be different. For example, when the position of the etching mask 219 is shifted toward the memory cell 201b, the channel length L2 of the memory cell 201b is shorter than the channel length L1 of the memory cell 201a.

When the channel lengths L1 and L2 are different, the resistance of the channel region 205 is also different, so that a difference occurs in the cell current value flowing during the write operation. In other words, the longer the channel length, the greater the resistance of the channel region 205, and the smaller the cell current flowing during the write operation. If a difference occurs in the cell current value flowing during the write operation, a difference also occurs in the generation rate of hot electrons. As a result, the write characteristics of the memory cells 201a and 201b are different.

(2) A problem that the miniaturization of the memory cell 201 is hindered in order to avoid the problem (1). In designing the split gate memory cell 201, not only the processing line width dimensional accuracy of the gate electrodes 206 and 207 but also the overlapping dimensional accuracy of the gate electrodes 206 and 207 are taken into consideration. , 207 and the regions 203, 204 need to have a margin in advance. However, in recent semiconductor fine processing technology, when processing a fine line having a line width of about 0.5 μm, the processing line width dimensional accuracy can be obtained up to about 0.05 μm, while the overlapping dimensional accuracy is 0.1. ~ 0.2 μm
Can only be obtained to the extent. That is, in the split-gate memory cell 201, the low overlay dimensional accuracy of the gate electrodes 206 and 207 is an obstacle, which prevents miniaturization.

(3) Split gate type memory cell 20
The problem 1 is that miniaturization is more difficult than a stacked gate type memory cell. The widths of the floating gate electrode and the control gate electrode in the stacked gate type memory cell are the same, and the two gate electrodes are stacked without being shifted from each other. On the other hand, in the split gate type memory cell 201,
A part of the control gate electrode 207 is arranged on the channel region 205, and forms the selection gate 211. Therefore, as compared with the stacked gate type memory cell, in the split gate type memory cell 201, the occupied area of the element on the substrate 202 is increased by the amount of the selection gate 211. That is, although the split gate memory cell does not have the problem of excessive erasure, it is difficult to achieve high integration by the above (2) and (3).

(4) Split Gate Memory Cell 20
The problem is that the memory cell array 302 using No. 1 has a complicated structure and takes much time to manufacture. The present invention has been made in order to solve the above-described problems, and has as its object that there is no variation in writing characteristics, the operation speed is high, miniaturization is possible, and excessive erasure does not occur. An object of the present invention is to provide a semiconductor memory capable of improving characteristics and read characteristics and a method for manufacturing the same.

[0045]

According to the present invention, a plurality of floating gate electrodes sharing a control line, a channel region and a source / drain alternately provided between the floating gate electrodes of a semiconductor substrate are provided. A semiconductor memory having a region, wherein the capacitance between the control line and the semiconductor substrate in the channel region is set to be larger than the capacitance between the control line and the semiconductor substrate in the source / drain region. I do.

According to a second aspect of the present invention, there are provided a plurality of floating gate electrodes sharing a control line, and a channel region and a source / drain region provided alternately between the floating gate electrodes of the semiconductor substrate, The capacitance between the control line in the channel region and the semiconductor substrate is set to be larger than the capacitance between the control line in the source / drain region and the semiconductor substrate, and the capacitance between the floating gate electrode and the semiconductor substrate. The gist of the present invention is a semiconductor memory in which the capacitance is set to be larger than the capacitance between the floating gate electrode and the control line.

The third aspect of the present invention provides the first and second aspects.
In the semiconductor memory according to any one of the above, the control line may constitute a control gate electrode of the semiconductor memory on each floating gate electrode, and constitute a select gate electrode of the semiconductor memory on each channel region. Make a summary.

According to a fourth aspect of the present invention, there is provided the semiconductor memory according to any one of the first to third aspects, wherein the plurality of floating gate electrodes sharing a control line are provided between the floating gate electrodes of the semiconductor substrate. The alternately provided channel regions and source / drain regions are arranged in a matrix corresponding to a plurality of control lines arranged in a predetermined direction.
The gist is that the drain region is commonly connected to the bit line in the matrix.

According to a fifth aspect of the present invention, in the semiconductor memory according to any one of the first to fourth aspects, the semiconductor memory has non-conductivity on each source / drain region and has conductivity on each channel region. The gist of the present invention is to provide an underlying layer below the control line.

According to a sixth aspect of the present invention, in the semiconductor memory of the fifth aspect, the underlayer is a conductor layer partially oxidized on each of the source / drain regions.

According to a seventh aspect of the present invention, in the semiconductor memory according to any one of the first to fourth aspects, the semiconductor memory is selectively formed on each source / drain region while maintaining electrical continuity with the same region. It is essential that each floating gate electrode is disposed adjacent to the conductive block layer via a dielectric.

According to an eighth aspect of the present invention, in the semiconductor memory according to the seventh aspect, an underlayer having conductivity is provided below the control line, and the underlayer is divided into a plurality of portions. The gist is that the underlayer on the channel region maintains electrical conduction with the control line, and the underlayer on each source / drain region is insulated from the control line to form a conductive block layer.

According to a ninth aspect of the present invention, in the semiconductor memory according to any one of the first to eighth aspects, the control line is formed such that its line width is smaller than the electrode width of each floating gate electrode. The gist is to become

The tenth aspect of the present invention provides the first to eighth aspects.
The gist of the present invention is that the control line is formed such that the line width on the source / drain region is smaller than the line width on the channel region.

According to an eleventh aspect of the present invention, in the semiconductor memory according to the tenth aspect, the line width of the control line on the channel region is substantially equal to the electrode width of the floating gate electrode, and the source / drain region of the control line is provided. The point is that the upper line width is formed smaller than the electrode width of the floating gate electrode.

The twelfth aspect of the present invention relates to the first to first aspects.
The gist of the semiconductor memory according to any one of the first to eighth aspects is to provide an acute-angled projection on an upper part of each floating gate electrode facing the control line.

According to a thirteenth aspect of the present invention, there is provided a semiconductor device comprising: a first source / drain region formed on a semiconductor substrate; a channel region sandwiched between the first and second source / drain regions; First and second floating gate electrodes juxtaposed on the channel region with a gate insulating film interposed therebetween, and first and second floating gate electrodes formed on the first and second floating gate electrodes with a tunnel insulating film interposed therebetween; A plurality of transistors each having a control gate electrode shared by the floating gate electrode are arranged in a matrix, and a common control line is formed by the control gate electrodes of the transistors arranged in a predetermined direction. A method of manufacturing a semiconductor memory in which a common bit line is formed by source / drain regions of respective transistors arranged in a direction intersecting with the arrangement direction of the control gate electrodes A step of forming a gate insulating film on the semiconductor substrate; a step of forming a first conductive film on the gate insulating film; and etching the first conductive film and disposing the first conductive film in parallel with the source / drain regions. Forming a first and second floating gate electrodes, forming a tunnel insulating film over the entire surface of the exposed gate insulating film and the first conductive film, and forming a second conductive film on the tunnel insulating film. Forming, partially oxidizing a portion corresponding to the source / drain region of the second conductive film,
Forming a third conductive film on the first conductive film, and simultaneously separating the third conductive film, the second conductive film, the tunnel insulating film, and the first conductive film in the row direction to perform element isolation. When,
The gist is to provide.

According to a fourteenth aspect of the present invention, the first and second source / drain regions formed in the semiconductor substrate, the channel region sandwiched between the first and second source / drain regions, First and second floating gate electrodes juxtaposed on the channel region with a gate insulating film interposed therebetween, and first and second floating gate electrodes formed on the first and second floating gate electrodes with a tunnel insulating film interposed therebetween; A plurality of transistors each having a control gate electrode shared by the floating gate electrode are arranged in a matrix, and a common control line is formed by the control gate electrodes of the transistors arranged in a predetermined direction. A method of manufacturing a semiconductor memory in which a common bit line is formed by source / drain regions of respective transistors arranged in a direction intersecting with the arrangement direction of the control gate electrodes A step of forming a gate insulating film on the semiconductor substrate, a step of forming a first conductive film on the gate insulating film, and forming the first conductive film and the gate insulating film into a source / drain region. Etching simultaneously on the portions, forming insulating walls on side surfaces of the etched first conductive film and the gate insulating film, and forming a first insulating film on the semiconductor substrate surface exposed by the etching and on the entire surface of the remaining first conductive film. Forming a conductive block layer on the source / drain region by selectively oxidizing an upper portion of the second conductive film on the source / drain region; and forming a conductive block layer on the source / drain region on the source / drain region. Forming a first and a second floating gate electrode by using the second conductive film and the first conductive film left by etching the first conductive film at the same time; A step of forming a tunnel insulating film over the entire surface of the selectively oxidized second conductive film, a step of forming a third conductive film on the tunnel insulating film, a step of forming the third conductive film, the tunnel insulating film, and A step of simultaneously etching the second conductive film and the first conductive film in the row direction to perform element isolation.

According to a fifteenth aspect of the present invention, a first and second source / drain regions formed in a semiconductor substrate, a channel region sandwiched between the first and second source / drain regions, First and second floating gate electrodes juxtaposed on the channel region with a gate insulating film interposed therebetween, and first and second floating gate electrodes formed on the first and second floating gate electrodes with a tunnel insulating film interposed therebetween; A plurality of transistors each having a control gate electrode shared by the floating gate electrode are arranged in a matrix, and a common control line is formed by the control gate electrodes of the transistors arranged in a predetermined direction. A method of manufacturing a semiconductor memory in which a common bit line is formed by source / drain regions of respective transistors arranged in a direction intersecting with the arrangement direction of the control gate electrodes A step of forming a gate insulating film on the semiconductor substrate; a step of forming a first conductive film on the gate insulating film; and etching the first conductive film and disposing the first conductive film in parallel with the source / drain regions. Forming a first and a second floating gate electrode, forming a tunnel insulating film on the entire surface of the exposed gate insulating film and the first conductive film, and forming a tunnel insulating film and a gate on the source / drain region. A step of etching the insulating film, a step of forming a second conductive film over the semiconductor substrate surface and the entire surface of the tunnel insulating film exposed by the etching, and forming the second conductive film into first and second conductive films.
Etching at a portion corresponding to the floating gate electrode, oxidizing the surface of the portion corresponding to the source / drain region of the etched second conductive film, and etching at the channel region of the etched second conductive film Forming a third conductive film on the portion corresponding to the above and on the oxidized second conductive film, and forming the third conductive film, the second conductive film, the tunnel insulating film, and the first conductive film in a row. And simultaneously performing element isolation by etching in the directions.

[0060]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) A first embodiment of the present invention will be described below with reference to FIGS.

FIG. 1 shows a memory cell array 1 of a flash EEPROM 101 using the memory cells 1 of the present embodiment.
02 is shown. FIG. 1B shows a memory cell array 1
02 is a partial plan view, and FIG. 1A is a sectional view taken along line YY in FIG. 1B.

The memory cell 1 has two source / drain regions 3, a channel region 4, two floating gate electrodes 5,
6 and a control gate electrode 7. N-type source / drain region 3 on P-type single crystal silicon substrate 2
Are formed. A gate insulating film 8 is formed on a channel region 4 sandwiched between two source / drain regions 3 having a symmetric structure.
Through the two floating gate electrodes 5 and 6 having the same size and shape.
Are formed side by side. Each floating gate electrode 5, 6
An insulating film 9 is formed thereon by the LOCOS method, and a tunnel insulating film 10 is formed on the insulating film 9 and the gate insulating film 8. Due to the insulating film 9, each floating gate electrode 5,
At the upper part of the projection 6, projections 5a and 6a are formed. Further, on the tunnel insulating film 10, the insulating film 9 and the source
An insulating film 30 is formed on the drain region 3. Each insulating film 8, on the channel region 4 between the insulating films 30,
A selection gate 11 is formed via the reference numeral 10. In the present embodiment, the insulating film 30 is formed by oxidizing a part of a conductor layer as a base layer formed on the tunnel insulating film 10, and the remaining part is the select gate 11. As a material for forming the conductor layer, a semiconductor such as doped amorphous silicon, doped single crystal silicon, or doped polycrystalline silicon, or a conductor such as aluminum can be used.

The control gate electrode 7 is formed on the insulating film 30 and the select gate 11. Since the control gate electrode 7 and the selection gate 11 are in direct contact, there is electrical conduction.

Here, each of the sources sandwiching the selection gate 11
The selection transistor 12 is constituted by the drain region 3 and the selection gate 11. That is, the memory cell 1
Two transistors each including the floating gate electrodes 5 and 6 and the control gate electrode 7 and each source / drain region 3 and a selection transistor 12 formed between the respective transistors are connected in series.

In memory cell 1, control gate electrode 7
In addition, since only the gate insulating film 8 and the tunnel insulating film 10 are interposed between the selection gate 11 and the channel region 4, the capacitance is large.
Further, the tunnel insulating film 10 and the insulating film 30 are interposed between the control gate electrode 7 and the floating gate electrodes 5 and 6, and the capacitance thereof is compared with that between the control gate electrode 7 and the channel region 4. And become smaller. Further, since the control gate electrode 7 and the source / drain regions 3 have the gate insulating film 8, the tunnel insulating film 10 and the insulating film 30 interposed therebetween, the capacitance is controlled by the control gate electrode 7 and the floating gate. It is smaller than that between the electrodes 5 and 6.

The memory cell array 102 includes a plurality of memory cells 1 formed on a substrate 2.
In order to reduce the occupied area on the substrate 2, the adjacent memory cells 1 are arranged so that the source / drain regions 3 are shared.

A field insulating film 13 is formed on the substrate 2, and the field insulating film 13 performs element isolation between the memory cells 1. In FIG. 1B, the source / drain regions 3 of the memory cells 1 arranged in the vertical direction are common, and the source / drain regions 3
Form a bit line. FIG. 1 (b)
, The control gate electrode 7 of each memory cell 1 arranged in the horizontal direction is common, and the control gate electrode 7 forms a word line as a control line.

FIG. 2 shows an overall configuration of a flash EEPROM 101 using the memory cells 1. The memory cell array 102 includes a plurality of memory cells 1 arranged in a matrix. The common word line WL is controlled by the control gate electrodes 7 of the memory cells 1 arranged in the row direction.
1 to WLn are formed. The source / drain regions 3 of each memory cell 1 arranged in the column direction form common bit lines BL1 to BLn.

That is, the memory cell array 102 includes the memory cells 1 connected to the common word lines WL1 to WLn.
Floating gate electrodes 5 and 6 are arranged in series, and their circuits are connected in parallel to common bit lines BL1 to BLn in an AND-NOR type configuration.

Each word line WL 1 -WLn is connected to a row decoder 103, and each bit line BL 1 -BLn is connected to a column decoder 104. The row address and column address specified from the outside are applied to the address pins 10
5 is input. The row address and the column address are transferred from the address pins 105 to the address latch 107. Among the addresses latched by the address latch 107, the row address is transferred to the row decoder 103 via the address buffer 106, and the column address is transferred to the column decoder 10 via the address buffer 106.
4 is transferred.

The address latch 107 may be omitted as appropriate. The row decoder 103 includes the address latch 10
7, one word line WL1 to WLn (for example, WLm (not shown)) corresponding to the row address latched is selected, and the potential of each word line WL1 to WLn is controlled in accordance with each operation mode described later. I do. That is, each word line WL1
To WLn to control each memory cell 1
Of the control gate electrode 7 is controlled.

The column decoder 104 has one bit line BL1 to BLn (for example, BLm (not shown)) corresponding to the column address latched by the address latch 107.
Is selected, the potential or the open state of each of the bit lines BL1 to BLn is controlled in accordance with each operation mode described later. That is, by controlling the potential or the open state of each of the bit lines BL1 to BLn, the potential or the open state of the source / drain region 3 of each memory cell 1 is controlled.

Data specified externally is input to data pin 108. The data is transferred to data pin 108
From the column decoder 104 via the input buffer 109
Transferred to The column decoder 104 is connected to each bit line B
The potentials or open states of L1 to BLn are controlled in accordance with the data as described later.

Data read from an arbitrary memory cell 1 is supplied to the column decoder 10 from the bit lines BL1 to BLn.
4 to the sense amplifier 110. The sense amplifier 110 is a current sense amplifier. The column decoder 104 connects the selected bit lines BL1 to BLn to the sense amplifier 110. The data determined by the sense amplifier 110 is output from the output buffer 111 to the data pin 10.
8 to the outside.

The operation of each of the above circuits (103 to 111) is controlled by the control core circuit 112. next,
Each operation mode (write operation, read operation, erase operation) of the flash EEPROM 101 will be described with reference to FIGS. FIGS. 3, 5, and 7 show FIG.
FIGS. 4 and 6 show only a part of FIG.
FIG. 8 shows only a part of FIG.

(A) Write operation (see FIGS. 3 and 4) Memory cell 1 (hereinafter referred to as "1m (m)") connected to the intersection of word line WLm and each of bit lines BLm and BLm + 1 ) Is selected and data is written to the floating gate electrode 6 among the floating gate electrodes 5 and 6 of the memory cell 1m (m).

The bit line BLm corresponding to the source / drain region 3 (hereinafter referred to as “3a”) on the side closer to the floating gate electrode 5 among the source / drain regions 3 of the memory cell 1m (m) is It is connected to a constant current source 110a provided in the sense amplifier 110, and its potential is set to about 1.2V.

In each source / drain region 3 of memory cell 1m (m), bit line BLm + 1 corresponding to source / drain region 3 (hereinafter referred to as “3b”) on the side closer to floating gate electrode 6. Is set to 10V.

The potential of each bit line (BL1... BLm-1, BLm + 2... BLn) corresponding to the source / drain region 3 of each memory cell 1 other than the selected memory cell 1m (m) is 3V. Is done.

The potential of word line WLm corresponding to control gate electrode 7 of memory cell 1m (m) is set to 2V. Each word line (WL1... WLm-1) corresponding to the control gate electrode 7 of each memory cell 1 other than the selected memory cell 1m (m).
, WLm + 2... WLn) are set to 0V.

In memory cell 1m (m), threshold voltage Vth of select transistor 12 is about 0.5V. Therefore, in the memory cell 1m (m), the source / drain region 3a
The electrons inside move into the channel region 4 in the inverted state. Therefore, cell current Iw flows from source / drain region 3b toward source / drain region 3a. On the other hand, since the potential of the source / drain region 3b is 10 V, the coupling between the source / drain region 3b and the floating gate electrode 6 via the capacitance causes the floating gate electrode 6
Is raised to approach 10V. for that reason,
A high electric field is generated between the channel region 4 and the floating gate electrode 6. Accordingly, the electrons in the channel region 4 are accelerated to become hot electrons, and as shown by an arrow C in FIG.
It is injected into the floating gate electrode 6. As a result, charges are accumulated in the floating gate electrode 6 of the memory cell 1m (m), and 1-bit data is written and stored.

At this time, due to the coupling between the source / drain region 3a and the floating gate electrode 5 via the capacitance, the potential of the floating gate electrode 5 is raised to be about 1.2V. However, at such a low potential, hot electrons are not substantially injected into the floating gate electrode 5. That is, in the memory cell 1m (m), hot electrons are injected only into the floating gate electrode 6.

The word line WLm and each bit line BLm-
1 and a memory cell 1 connected to the intersection with BLm
The cell current Iw also flows between the source / drain regions 3 of "1 m (m-1)". However, the memory cell 1m (m-
In 1), since the potential of the source / drain region 3 corresponding to the bit line BLm-1 is 3 V, the potentials of the floating gate electrodes 5 and 6 are not raised. for that reason,
Hot electrons are not injected into the floating gate electrodes 5 and 6 of the memory cell 1m (m-1).
No data is written to (m-1).

Then, the word line WLm and each bit line BL
For the memory cell 1 (hereinafter, referred to as “1m (m + 1)”) connected to the intersection of m + 1 and BLm + 2, the bit line B
The potential of the source / drain region 3 corresponding to Lm + 2 is 3 V
Since the potential is higher than the potential (= 2 V) of the control gate electrode 7 (word line WLm), no cell current flows between the source / drain regions 3. Therefore, the memory cell 1m (m + 1)
Hot electrons are not injected into the respective floating gate electrodes 5 and 6, and no data is written into the memory cell 1m (m + 1).

The memory cells 1 other than the memory cells 1m (m), 1m (m-1), and 1m (m + 1) connected to the word line WLm are also referred to as memory cells 1m (m + 1). For the same reason, no data is written.

Therefore, the above-described write operation is performed only on the floating gate electrode 6 of the selected memory cell 1m (m). Here, by optimizing the value of the cell current Iw flowing between the source / drain regions 3b and 3a and the time of the write operation (the time of injecting hot electrons into the floating gate electrode 6), the memory cell 1m (m 2) optimize the amount of charge stored in the floating gate electrode 6.

More specifically, the amount of charge stored in the floating gate electrode 6 of the memory cell 1m (m) is
The amount is set to be smaller than the amount of charge stored in one floating gate electrode 206 so that an overwriting state is not caused. In the write operation, the potential of the source region 203 of the conventional memory cell 201 is set to 12 V, whereas the potential of the source / drain region 3b (bit line BLm + 1) of the memory cell 1m (m) of the present embodiment is set. The potential is set as low as 10 V in order to prevent an overwriting state.

When data is written to the floating gate electrode 6 of the memory cell 1m (m), data may already be written to the floating gate electrode 5. In this case, if a large amount of electric charge is accumulated in the floating gate electrode 5 and the overwriting state occurs, the channel region 4 immediately below the floating gate electrode 5 is completely turned off, and the source-drain regions 3b and 3a No cell current Iw flows. Therefore, when data is written to the floating gate electrode 5, similarly to the case of the floating gate electrode 6, the amount of charge accumulated in the floating gate electrode 5 is reduced so that an overwriting state does not occur. Then, the floating gate electrode 5
Even if data is written in the channel region 4, the channel region 4 immediately below the floating gate electrode 5 is not completely turned off, and the cell current I between the source and drain regions 3b and 3a is not changed.
w flows.

To put it the other way around, a cell current Iw of a value necessary for writing data to the floating gate electrode 6 flows so that
That is, the amount of charge stored in the floating gate electrode 5 is set in advance. That is, the amount of charge stored in the floating gate electrode 6 is set to be small enough to allow the cell current Iw of a value necessary for writing data to the floating gate electrode 5 to flow.

The floating gate electrode 5 of the memory cell 1m (m)
When writing data to the source / drain region 3b
Is connected to the constant current source 110a provided in the sense amplifier 110, so that the potential of the bit line BLm corresponding to the source / drain region 3a becomes 10
V. Other potential conditions are the same as in the case where data is written to the floating gate electrode 6 of the memory cell 1m (m).

Therefore, this write operation can be performed for each of the floating gate electrodes 5 and 6 for one selected memory cell 1. (B) Read operation (see FIGS. 5 and 6) The memory cell 1m (m) is selected, and data is read from the floating gate electrode 6 among the floating gate electrodes 5 and 6 of the memory cell 1m (m). The case will be described.

The potential of bit line BLm corresponding to source / drain region 3a of memory cell 1m (m) is set to 3V.
The potential of the bit line BLm + 1 corresponding to the source / drain region 3b of the memory cell 1m (m) is set to 0V.

Each bit line (BL1... BLm-1, BLm + 2... BLn) corresponding to the source / drain region 3 of each memory cell 1 other than the selected memory cell 1m (m) is
Opened.

The potential of the word line WLm corresponding to the control gate electrode 7 of the memory cell 1m (m) is set to 4V. Also, each word line (WL1... WLm + 1) corresponding to the control gate electrode 7 of each memory cell 1 other than the selected memory cell 1m (m).
, WLm + 2... WLn) are set to 0V.

In the memory cell 1m (m), when the source / drain region 3a is set to 3 V, the floating gate electrode is coupled by coupling between the source / drain region 3a and the floating gate electrode 5 via the capacitance. The potential of 5 is raised to near 3V. As a result, the channel region 4 immediately below the floating gate electrode 5 is turned on irrespective of the presence or absence of the charge stored in the floating gate electrode 5.

As described later, no charge is stored in the floating gate electrode 6 in the erased state. On the other hand,
As described above, the floating gate electrode 6 in the written state
Has accumulated electric charge. Therefore, the channel region 4 immediately below the floating gate electrode 6 in the erased state is in the ON state, and the channel region 4 immediately below the floating gate electrode 6 in the written state is close to the OFF state.

Therefore, when 4 V is applied to control gate electrode 7, the cell current Ir flowing from source / drain region 3a toward source / drain region 3b is smaller when floating gate electrode 6 is in the erased state. , In the writing state.

The value of the cell current Ir is applied to the sense amplifier 11
By detecting 0, the value of the data stored in the floating gate electrode 6 of the memory cell 1m (m) can be read. For example, reading is performed with the data value of the floating gate electrode 6 in the erased state being “1” and the data value of the floating gate electrode 6 in the written state being “0”. In this case, the sense amplifier 110 may be connected to the source / drain region 3b to detect the cell current Ir.

The floating gate electrode 5 of the memory cell 1m (m)
When reading data from the source / drain region 3,
The potential of bit line BLm + 1 corresponding to b is set to 3V, and the potential of bit line BLm corresponding to source / drain region 3a is set to 0V. Other potential conditions or open states are the same as in the case of reading data from the floating gate electrode 6 of the memory cell 1m (m).

That is, for the selected memory cell 1m (m), one of the floating gate electrodes 5 and 6
Two values (= 1 bit) of the data value “1” in the erased state and the data value “0” in the written state are stored, and the data values can be read.

(C) Erasing Operation (See FIG. 7 or FIG. 8) A case where data stored in the floating gate electrodes 5 and 6 of all the memory cells 1 connected to the word line WLm is erased will be described.

The potentials of all bit lines BL1 to BLn are 0
V. The potential of the word line WLm is set to 15V.
Each word line (WL1... WL) other than the word line WLm
m + 1, WLm + 2... WLn) are set to 0V.

The capacitance between each source / drain region 3a, 3b and the substrate 2 and each floating gate electrode 5, 6 and the capacitance between the control gate electrode 7 and each floating gate electrode 5, 6 The former is overwhelmingly larger. That is,
Each floating gate electrode 5, 6 is connected to each source / drain region 3.
a, 3b and the substrate 2 are strongly coupled. Therefore, even if the control gate electrode 7 becomes 15V and the source / drain regions 3a and 3b become 0V, the potentials of the floating gate electrodes 5 and 6 do not change so much from around 0V, and the control gate electrode 7 and each floating gate The potential difference between the electrodes 5 and 6 increases, and a high electric field is generated between the control gate electrode 7 and each of the floating gate electrodes 5 and 6.

As a result, the FN tunnel current flows, and FIG.
As shown by the arrow D, electrons in the floating gate electrodes 5 and 6 are extracted to the control gate electrode 7 side, and the data stored in each memory cell 1 is erased.

At this time, since the projections 5a and 6a are formed on the floating gate electrodes 5 and 6, electrons in the floating gate electrodes 5 and 6 jump out of the projections 5a and 6a to control the control gate electrode 7a. Move to the side. Therefore, the movement of the electrons is facilitated, and the electrons in the floating gate electrodes 5, 6 can be efficiently extracted.

By simultaneously selecting a plurality of word lines WL1 to WLn, an erasing operation can be performed on all the memory cells 1 connected to each word line. The erase operation of dividing the memory cell array 102 into arbitrary blocks for each of a plurality of sets of word lines WL1 to WLn and erasing data in each block is called block erase.

Next, a method of manufacturing the memory cell array 102 will be described step by step with reference to FIGS. Step 1 (see FIG. 9A): A field insulating film 13 (shown in FIG. 1B) is formed on the substrate 2 by using the LOCOS method. Next, the field insulating film 13 on the substrate 2
A gate insulating film 8 made of a silicon oxide film is formed by using a thermal oxidation method in a portion (element region) where is not formed. Subsequently, the floating gate electrodes 5 and 6 are formed on the gate insulating film 8.
Doped polysilicon film 2 as a first conductive film to be formed
Form one. Then, a silicon nitride film 22 is formed on the entire surface of the doped polysilicon film 21 by using the LPCVD method. Next, after a photoresist is applied to the entire surface of the silicon nitride film 22, an etching process for forming both side walls of the floating gate electrodes 5 and 6 parallel to the source / drain regions 3 is performed by using ordinary photolithography technology. Mask 2
Form 3

Step 2 (see FIG. 9B): The silicon nitride film 22 is etched by anisotropic etching using the etching mask 23. Then, the etching mask 23 is removed. Next, the insulating film 9 is formed by oxidizing the doped polysilicon film 21 using the etched silicon nitride film 22 as an oxidation mask using the LOCOS method. At this time, the end of the insulating film 9 penetrates into the end of the silicon nitride film 22, and a bird's beak 9a is formed.

Step 3 (see FIG. 9C): The silicon nitride film 22 is removed. Next, the doped polysilicon film 21 is etched by anisotropic etching using the insulating film 9 as an etching mask, and the floating gate electrode 5,
6 is formed. This film 24 has a shape in which the floating gate electrode 5 arranged in parallel with the source / drain region 3 is continuous, and
Has a shape in which floating gate electrodes 6 arranged in parallel with each other are continuous. That is, both side walls of the film 24 become both side walls of the floating gate electrodes 5 and 6. At this time, since the bird's beak 9a is formed at the end of the insulating film 9, the upper edge of the film 24 becomes sharp along the shape of the bird's beak 9a, and the projections 5a and 6a are formed.

Step 4 (see FIG. 10D): After applying a photoresist to the entire surface of the device formed in the above step, the source / drain region 3 is formed by using ordinary photolithography technology. Is formed. Next, using a normal ion implantation method,
N-type impurity ions (such as phosphorus ions and arsenic ions) are implanted into the surface of the substrate 2 to form source / drain regions 3. After that, the ion implantation mask 25 is removed.

At this time, the ion implantation mask 25 is formed so as to cover at least a portion of the substrate 2 where the source / drain regions 3 are not formed and so as not to protrude from the film 24. As a result, the positions of the source / drain regions 3 are defined by the side walls of the film 24 (that is, the ends of the floating gate electrodes 5 and 6).

Step 5 (see FIG. 10 (e)): Tunnel insulating film 10 made of a silicon oxide film is formed on the entire surface of the device formed in the above steps by using the thermal oxidation method or the LPCVD method or a combination thereof. . Then, the stacked insulating films 8 and 10 and the insulating films 9 and 10 are integrated.

Step 6 (see FIG. 10F): An insulating film 30 (underlying layer) is formed on the entire surface of the device formed in the above step.
Then, a doped polysilicon film 31 as a second conductive film to be the selection gate 11 (underlying layer) is formed.

Step 7 (see FIG. 11G): A silicon nitride film 32 is formed on the entire surface of the device formed in the above step. Next, after a photoresist is applied to the entire surface of the silicon nitride film 32, an etching mask 33 for etching the silicon nitride film 32 is formed by using a normal photolithography technique.

Step 8 (see FIG. 11H): An oxidation mask for forming a boundary between the select gate 11 and the insulating film 30 by etching the silicon nitride film 32 by etching using the etching mask 33. To form After removing the etching mask 33, the doped polysilicon film 31 is
Is partially oxidized. Thus, the selection gate 11 and the insulating film 30 are formed from the doped polysilicon film 31. After that, the silicon nitride film 32 is removed.

Step 9 (see FIG. 11I): A doped polysilicon film 26 as a third conductive film to be the control gate electrode 7 is formed on the entire surface of the device formed in the above step.

Each doped polysilicon film 21 and
6, 31 are formed as follows. Method 1: When a polysilicon film is formed by using the LPCVD method, a gas containing impurities is mixed into a source gas.

Method 2: After forming a non-doped polysilicon film by using the LPCVD method, an impurity diffusion source layer (such as POCl3) is formed on the polysilicon film, and an impurity is diffused from the impurity diffusion source layer into the polysilicon film. Spread.

Method 3: After forming a non-doped polysilicon film by using the LPCVD method, impurity ions are implanted. Step 10 (see FIG. 12 (j)): After applying a photoresist to the entire surface of the device formed in the above step, the respective floating gate electrodes 5 and 6 and the control gate electrode 7 are formed by using ordinary photolithography technology. Is formed for forming an etching mask 27.

Step 11 (see FIG. 12 (k)): Controlling the etching gas for the doped polysilicon film 26, the tunnel insulating film 10, the insulating film 9, and the film 24 by anisotropic etching using the etching mask 27. While simultaneously etching. Thereby, the doped polysilicon film 26 is formed.
, The control gate electrode 7 is formed, and the floating gate electrodes 5, 6 are formed from the film 24.

Then, when the etching mask 27 is removed, the memory cell array 102 is completed. As described in detail above, according to the present embodiment, the following operations and effects can be obtained.

[1] The memory cell 1 has two floating gate electrodes 5 and 6, and each floating gate electrode 5 and 6 is juxtaposed on a channel region 4 sandwiched between two source / drain regions 3. . Each floating gate electrode 5 and 6 shares one control gate electrode 7. One memory cell 1 can store 1-bit data for each of the floating gate electrodes 5 and 6, and can store 2-bit data in total.

Therefore, under the same design rule, according to the memory cell 1, the memory cell 1
The occupied area on the substrate per bit can be reduced to about 66%. That is, according to the memory cell 1, high integration comparable to that of the stacked gate memory cell is possible.

[2] Each memory cell 1 arranged in the row direction
, Common word lines WL1 to WLn as control lines are formed. That is, the control gate electrodes 7 of the memory cells 1 arranged in the row direction are continuous without being separated.

Therefore, the problem (1) in the prior art can be completely avoided. [3] According to the above [2], there is no need to consider the overlapping dimensional accuracy of each of the floating gate electrodes 5 and 6 and the control gate electrode 7, so that the above-mentioned (2)
Problem can be completely avoided.

[4] In the present embodiment, only the gate insulating film 8 is provided between each of the floating gate electrodes 5 and 6 and the source / drain region 3. On the other hand, an insulating film 9 and a tunnel insulating film 10 are provided between the control gate electrode 7 and each of the floating gate electrodes 5 and 6, and an insulating film 30 is provided by oxidizing the conductor layer to form the control gate electrode. The distance between the floating gate electrode 7 and each of the floating gate electrodes 5 and 6 is increased as much as possible. Therefore, the floating gate electrodes 5 and 6 with respect to the capacitance between the control gate electrode 7 and the floating gate electrodes 5 and 6
It is possible to increase the ratio of the capacitance between the source and the drain region 3. Thereby, at the time of writing data to the memory cell 1, the potential of the floating gate electrodes 5, 6 can be easily raised to a high potential based on the high voltage applied to the source / drain region 3, and the writing characteristics are improved. can do. Further, the control gate electrode 7 is in direct contact with the select gate 11, and only the gate insulating film 8 is provided between the select gate 11 and the channel region 4, and the control gate electrode 7 and the select gate 11 are connected to the channel region 4. Is large, a large cell current can flow during data reading, and the reading characteristics can be improved.

[5] Memory cell array 10 of the present embodiment
In FIG. 2, common word lines WL1 to WLn are formed by the control gate electrodes 7 of the memory cells 1 arranged in the row direction, and the control gate electrodes 7 are directly in contact with the selection gates 11 and have the same wiring. It is formed in a layer. Therefore, since no insulating film is interposed between the word lines WL1 to WLn and the control gate electrode 7, it is possible to prevent the device from increasing in the height direction and to increase the size of the word lines WL1 to WLn (control gates). The upper wiring layer of the electrode 7) can be effectively used when another wiring is provided.

[6] In the step 11 of the present embodiment, the doped polysilicon film 26, the tunnel insulating film 10, the insulating film 9, and the film 24 are simultaneously etched while controlling the etching gas, so that the doped polysilicon film is formed. Membrane 26
To form a control gate electrode 7, and from the film 24 to each floating gate electrode 5, 6. In the memory cell array 102, the source / drain region 3 of each memory cell 1 arranged in the column direction allows the common bit line BL1
~ BLn are formed. Therefore, it is not necessary to form the bit line contacts 214 in the memory cell array 102 as in the conventional memory cell array 302. Therefore, the memory cell array 102 of the present embodiment
Has a simpler structure and is easier to manufacture than the conventional memory cell array 302.

[7] Flash E Using Memory Cell 1
Since the EPROM 101 is provided with the selection transistor 12, each of the memory cells 1 has a function of selecting itself. In other words, the floating gate electrode 5,
Even if the charge is extracted too much when extracting the charge from 6,
The channel region 4 can be turned off by the selection gate 11. Therefore, even if excessive erasure occurs, the ON / OFF state of the memory cell 1 can be controlled by the selection transistor 12, and excessive erasure does not pose a problem. That is, the on / off state of the memory cell itself can be selected by the selection transistor 12 provided inside the memory cell 1.

[8] In the write operation, in order to optimize the amount of charge stored in the floating gate electrodes 5 and 6 of the memory cell 1, the memory cell 1 must have the erased state and the written state
A technique (multi-value storage technique) for storing not only a value (= 1 bit) but also three or more values may be applied. That is, in the multi-value storage technology, it is essential to precisely control the write state by precisely controlling the potential of the floating gate electrode of the memory cell during the write operation. If the technique of controlling the potential of the floating gate electrode is used, it is easy to optimize the amount of charge stored in the floating gate electrodes 5 and 6 of the memory cell 1 during a write operation.

[0131]

[9] In the write operation, in order to prevent an excessive write state, the source of the memory cell 1m (m) is
The potential of the drain region 3b (bit line BLm + 1) is 10 V
And it is set low. Therefore, Flash EEPR
Even when the power supply voltage of the OM 101 is lowered to 3.3 V, the load on the charge pump is reduced, and it is possible to easily cope with the voltage reduction.

On the other hand, in the conventional memory cell 201, the potential of the source region 203 in the write operation becomes 1
It is set to 2V. Therefore, Flash EEPR
When the power supply voltage of the OM 301 is 3.3 V, the voltage supplied to the source region 203 using the charge pump (= 1
2V) is difficult to generate, and a special circuit is required to generate the voltage, which complicates the circuit configuration.

[10] The length of the channel region 4 of the memory cell 1 is
It is longer than. Therefore, the breakdown voltage of the channel region 4 is higher than the breakdown voltage of the channel region 205.
As a result, in the write operation, data is less likely to be written to each of the floating gate electrodes 5 and 6 of the memory cell 1 other than the selected memory cell 1, and the operation and effect of the write operation can be more reliably obtained. it can.

[11] In the read operation, when the value of the cell current Ir of the memory cell 1 is detected by the sense amplifier 110, a multi-value storage technique may be applied. That is, in the multivalued storage technology, it is indispensable to accurately detect the cell current during the read operation. If the cell current detection technique is used, the value of the cell current Ir of the memory cell 1 can be accurately detected during the read operation.

[12] In the write operation, the amount of charge stored in the floating gate electrodes 5 and 6 of the memory cell 1 is set to be small to prevent an excessive write state. Therefore, in the erasing operation, the amount of electrons drawn from each of the floating gate electrodes 5 and 6 toward the control gate electrode 7 is reduced.

(Second Embodiment) Next, a second embodiment will be described with reference to the drawings. FIG. 15H shows a part of a memory cell array 170 of a flash EEPROM using the memory cells 40 of the present embodiment. The memory cell 40 includes two source / drain regions 42, a conductive block layer 43, a channel region 44, two floating gate electrodes 45 and 46, and a control gate electrode 47.

An N-type source / drain region 42 is formed on a P-type single crystal silicon substrate 41. Each source
A conductive block layer 43 is formed on the drain region 42. As a material for forming this conductive film, a semiconductor such as doped amorphous silicon, doped single crystal silicon, or doped polycrystalline silicon can be used.

On each source / drain region 42, two floating gate electrodes 45 and 46 having the same size and shape are formed symmetrically with the conductive block layer 43 interposed therebetween. An insulating film 49 as a dielectric is provided between the floating gate electrodes 45 and 46 and the conductive block layer 43, and the floating gates 45 and 46 are formed of two symmetrical sources / sources.
On the channel region 44 sandwiched between the drain regions 42, they are arranged side by side with a gate insulating film 48 interposed therebetween.

On the conductive block layer 43 on each source / drain region 42 and the floating gate electrodes 45 and 46, L
An insulating film 50 is formed by the OCOS method.
A tunnel insulating film 51 is formed on the gate insulating film 48 and the gate insulating film 48. Due to the insulating film 50, each floating gate electrode 4
Protrusions 45a, 46a are formed on the upper portions of 5, 46, respectively. A control gate electrode 47 is formed on the tunnel insulating film 51.

Here, a part of the control gate electrode 47 is arranged on the channel region 44 via the respective insulating films 48 and 51 to form the select gate 52. Select gate 5
2 and source / drain regions 42 and select gate 52
Thus, the selection transistor 53 is configured. That is, in the memory cell 40, two transistors each including the floating gate electrodes 45 and 46, the control gate electrode 47, and each source / drain region 42, and the selection transistor 53 formed between each transistor are connected in series. Take the connected configuration.

In the memory cell 40, since the control gate electrode 47 and the channel region 44 only have the gate insulating film 48 and the tunnel insulating film 51 interposed therebetween, the capacitance is large. . Further, the tunnel insulating film 51 and the insulating film 50 are interposed between the control gate electrode 47 and the floating gate electrodes 45 and 46, and the capacitance thereof is compared with that between the control gate electrode 47 and the channel region 44. And become smaller. Furthermore, since the control gate electrode 47 and the source / drain regions 42 have the insulating film 50 and the tunnel insulating film 51 interposed therebetween, the capacitance is reduced.
And between the floating gate electrodes 45 and 46. The floating gate electrodes 45 and 46 face the source / drain regions 42 via the insulating film 48, and the side walls of the floating gate electrodes 45 and 46 have the conductive block layer 43 (ie, the source・
Drain region 42). Therefore, the capacitance between the source / drain region 42 and each of the floating gate electrodes 45 and 46 can be increased.

Next, a method of manufacturing the memory cell array 170 will be described step by step with reference to FIGS. Step 1 (see FIG. 13A): After a field insulating film is formed on the substrate 41 using the LOCOS method, a portion (element region) where the field insulating film is not formed on the substrate 41 is thermally oxidized. Is used to form a silicon oxide film 60 to be the gate insulating film 48. Subsequently, the conductive block layer 43 and the floating gate electrode 4 are formed on the silicon oxide film 60.
A doped polysilicon film 61 is formed as a first conductive film, which will be 5 and 46. Then, after forming a silicon oxide film 62 on the doped polysilicon film 61, the LPCV
Using method D, a silicon nitride film 63 is formed on the entire surface of the silicon oxide film 62.

Step 2 (see FIG. 13B): After a photoresist is applied to the entire surface of the silicon nitride film 63, an etching mask for forming the source / drain regions 42 by using ordinary photolithography technology To form By anisotropic etching using this etching mask, the silicon nitride film 63, the silicon oxide film 62, and the doped polysilicon film 61 are simultaneously etched while controlling an etching gas. Thereafter, a silicon oxide film is formed on the entire surface of the device and etched back to form a gate insulating film 48 from the silicon oxide film 60 and a sidewall 65 as an insulating wall. Then, N-type impurity ions (phosphorus ions, arsenic ions, etc.) are implanted into the surface of the substrate 41 by using an ordinary ion implantation method with the opening between the side walls 65 as an ion implantation mask to form the source region / drain region 42. Form.

Step 3 (see FIG. 13C): A doped polysilicon film 66 as a second conductive film is formed on the entire surface of the device.
Is formed and planarized using a CMP (Chemical Mechanical Polishing) method.

Step 4 (see FIG. 14D);
Silicon nitride film 63 etched by COS method
The insulating film 50 is formed by oxidizing the doped polysilicon film 66 using as a mask for oxidation. At this time,
A conductive block layer 43 is formed on the source / drain region 42 from the doped polysilicon film 66, and an insulating film 49 is formed on both sides of the conductive block layer 43 from the sidewall 65.

Step 5 (see FIG. 14E): The silicon nitride film 63 is removed. Step 6 (see FIG. 14F); silicon oxide films 50 and 6
2 is etched to remove the silicon oxide film 62.

Step 7 (see FIG. 15G): The doped polysilicon film 61 is etched by anisotropic etching using the silicon oxide film 50 as an etching mask to form the floating gate electrodes 45 and 46. Is formed. At this time, the film 64 becomes sharp along the shape of the end of the insulating film 50, and the projection 64a is formed. Then, a tunnel insulating film 51 made of a silicon oxide film is formed on the entire surface of the device by a thermal oxidation method, an LPCVD method, or a combination thereof. Then, the laminated insulating films 48 and 51 and the respective insulating films 50 and 51 are integrated.

Step 8 (see FIG. 15H): A doped polysilicon film as a third conductive film to be the control gate electrode 47 is formed on the entire surface of the device formed in the above step. Then, an etching mask for forming each of the floating gate electrodes 45 and 46 and the control gate electrode 47 is formed by using a normal photolithography technique, and doped by anisotropic etching using the etching mask. The polysilicon film, the tunnel insulating film 51, the insulating film 50, and the film 64 are simultaneously etched while controlling the etching gas. As a result, the control gate electrode 47 is formed from the doped polysilicon film, and the floating gate electrodes 45 and 46 are formed from the film 64. Then, when the etching mask is removed, the memory cell array 170 is completed.

According to the present embodiment configured as described above, the following operation and effect can be obtained in addition to the operation and effect of the first embodiment. [13] The floating gate electrodes 45 and 46 face the source / drain regions 42 via the insulating film 48, and the side walls of the floating gate electrodes 45 and 46 have the conductive block layer 43 (ie, the insulating film 49). Source / drain regions 42). That is, each floating gate electrode 4
5 and 46 are coupled with the source / drain region 42 in the substrate 41 and also with the conductive block layer 43 connected to the source / drain region 42. Therefore, when writing data to the memory cell 40, the potential of the floating gate electrodes 45 and 46 is
It can be easily lifted based on the coupling between the drain region 42 side and the conductive block layer 43 side, and the writing characteristics can be improved.

[14] Each of the floating gate electrodes 45 and 46 is coupled to the source / drain region 42 in the substrate 41 and also to the conductive block layer 43 connected to the source / drain region 42. In order to miniaturize the memory cell array, an impurity diffusion layer (source
It is necessary to reduce the diffusion area by setting the drain region to be shallow. In this embodiment, the floating gate electrodes 45, 4
6 is also coupled to the conductive block layer 43 provided on the source / drain region 42, so that the facing area between the floating gate electrodes 45, 46 and the source / drain region 42 can be reduced, and therefore, furthermore Can be miniaturized.

(Third Embodiment) Next, a third embodiment will be described with reference to FIG. In the present embodiment, the first
The same components as those in the embodiment will be described with the same reference numerals.

FIG. 16 shows a memory cell array 18 of a flash EEPROM using the memory cells 71 of this embodiment.
Indicates a part of 0. FIG. 16B shows the memory cell array 1
FIG. 16A is a partial plan view of FIG.
It is a ZZ line sectional view in (b).

The memory cell 71 of the present embodiment differs from the memory cell 1 of the first embodiment in the following points, and the other configuration is the same. (1) As shown in FIG. 16A, the memory cell 71
In the memory cell 1, the insulating film 30 and the selection gate 11 are omitted, and the control gate electrode 7 (word line) is provided on the tunnel insulating film 10.

(2) As shown in FIG. 16B, the control gate electrode 7 of the memory cell 71 has a wide portion 7A on the channel region 4, the floating gate electrodes 5, 6 and the source / drain regions 3 ( Narrow portion 7 on impurity diffusion layer)
B. Such a narrow portion 7B of the control gate 7 can be applied to a portion other than the portion for controlling the substrate 2.

According to the present embodiment configured as described above, the above [1] to [3] and [5] in the first embodiment.
In addition to the functions and effects of [12], the following functions and effects can be obtained.

[15] In the memory cell 71, the narrow area 7B of the control gate electrode 7 is arranged on the floating gate electrodes 5 and 6 so that the opposing area between the control gate electrode 7 and the floating gate electrodes 5 and 6 can be reduced. I try to make it a little smaller. Therefore, the control gate electrode 7 and the floating gate electrode 5,
6, the ratio of the capacitance between the floating gate electrodes 5, 6 and the source / drain region 3 to the capacitance between the floating gate electrodes 5, 6 can be increased. Thereby, at the time of writing data to the memory cell 71, the potential of the floating gate electrodes 5, 6 can be easily raised to a high potential based on the high voltage applied to the source / drain region 3, and the write characteristics are improved. can do. In addition, since the wide portion 7A of the control gate electrode 7 is disposed on the channel region 4 and has a large facing area, the capacitance between the control gate electrode 7 and the channel region 4 is large, and data is read. In some cases, a large cell current can flow, and the reading characteristics can be improved.

(Fourth Embodiment) Next, a fourth embodiment will be described with reference to FIGS. In the present embodiment, the same components as those in the first embodiment have the same reference numerals, and a detailed description thereof will be partially omitted.

FIG. 20 (k) shows the memory cell 7 of this embodiment.
5 shows a part of a memory cell array 180 of a flash EEPROM using the same. Memory cell 7 in the present embodiment
5 is different from the memory cell 1 of the first embodiment in the following points, and other configurations are the same.

In the memory cell 75 of this embodiment, the gate insulating film 8 and the insulating film 30 on the source / drain region 3 in the memory cell 1 are omitted, and the conductive block layer 76 is directly provided on the source / drain region 3. ing. This conductive block layer 76 faces the floating gate electrodes 5 and 6 via the tunnel insulating film 10. The select gate 11 is provided between the conductive block layers 76 on the channel region 4 via the gate insulating film 8 and the tunnel insulating film 10. In the present embodiment, the conductive block layer 76 and the select gate 11 are formed by etching and separating a conductive layer as a base layer. As a material for forming the conductor layer, a semiconductor such as doped amorphous silicon, doped single crystal silicon, or doped polycrystalline silicon, or a conductor such as aluminum can be used.

A control gate electrode 7 is formed on select gate 11, and control gate electrode 7 extends to pass over conductive block layer 76 via insulating film 77. Since the control gate electrode 7 and the selection gate 11 are in direct contact, there is electrical conduction.

In the memory cell 75, since the control gate electrode 7, the select gate 11, and the channel region 4 only have the gate insulating film 8 and the tunnel insulating film 10 interposed therebetween, the capacitance is It will be big. In addition, the control gate electrode 7 and the floating gate electrodes 5 and 6 have an insulating film 77 and an insulating film 9 interposed therebetween, and the capacitance thereof is compared with that between the control gate electrode 7 and the channel region 4. Small. Further, each of the floating gate electrodes 5 and 6 is connected to a source electrode via a gate insulating film 8.
In addition to facing the drain region 3, the side walls of the floating gate electrodes 5 and 6 face the conductive block layer 76 (that is, the source / drain region 3) via the tunnel insulating film 10. Therefore, the capacitance between the source / drain region 3 and each of the floating gate electrodes 5 and 6 can be increased.

Next, a method of manufacturing the memory cell array 180 will be described step by step with reference to FIGS. Note that steps similar to the manufacturing steps of the first embodiment are described with the same reference numerals.

FIG. 17A shows a step 1, and FIG.
(B) shows a step 2, FIG. 17 (c) shows a step 3,
FIG. 18D shows Step 4. These steps 1 to 4 are the same as steps 1 to 4 for manufacturing the memory cell array 102 of the first embodiment.

Step 5 (see FIG. 18E): Tunnel insulating film 10 made of a silicon oxide film is formed on the entire surface of the device formed in the above-described steps by using the thermal oxidation method, the LPCVD method, or a combination thereof. . Thereafter, the source / drain regions 3 are formed by using ordinary photolithography technology.
The contact hole 80 is formed by removing the upper gate insulating film 8 and the tunnel insulating film 10.

Step 6 (see FIG. 18F): The conductive block layer 76 is formed on the entire surface of the device formed in the above-described step.
(Underlying layer) and a doped polysilicon film 81 as a second conductive film to be the selection gate 11 (underlying layer),
A silicon nitride film 82 is formed on the doped polysilicon film 81. Since the doped polysilicon film 81 is in direct contact with the source / drain region 3, there is electrical conduction.

Step 7 (see FIG. 19G): After a photoresist is applied to the entire surface of the silicon nitride film 82, etching is performed to cut and separate the doped polysilicon film 81 using ordinary photolithography technology. Mask 83
To form Then, the silicon nitride film 82 on the insulating film 9 is etched by using the etching mask 83,
The doped polysilicon film 81 and the tunnel insulating film 10 are etched. The doped polysilicon film 81 is cut and separated into a portion 84 to be the select gate 11 and a portion 85 to be the conductive block layer 76. Thereafter, the etching mask 83 is removed.

Step 8 (see FIG. 19 (h)): An etching mask is formed on the entire surface of the device formed in the above-mentioned step by using a usual photolithography technique, and the source and the source are formed by using the etching mask. The silicon nitride film 82 on the drain region 3 is removed by etching, leaving the silicon nitride film 82 on the channel region 4.

Step 9 (see FIG. 19I): Using the silicon nitride film 82 remaining on the channel region 4 as an oxidation mask, the surface of the doped polysilicon film 85 on the source / drain region 3 and the insulating film 9 are removed. Oxidation forms an insulating film 77. Thus, the selection gate 11 and the insulating film 30 are formed from the doped polysilicon film 31.

Step 10 (see FIG. 20 (j)): A silicon nitride film 82 is formed on the entire surface of the device formed in the above step.
Is removed. Step 11 (see FIG. 20 (k)); A doped polysilicon film as a third conductive film to be the control gate electrode 7 is formed on the entire surface of the device formed in the above step. Then, an etching mask for forming each of the floating gate electrodes 5 and 6 and the control gate electrode 7 is formed by using ordinary photolithography technology, and the doped mask is formed by anisotropic etching using the etching mask. A polysilicon film, an insulating film 77, an insulating film 9, a tunnel insulating film 10,
The film 24 is simultaneously etched while controlling the etching gas. Thus, the control gate electrode 7 is formed from the doped polysilicon film, and the floating gate electrodes 5 and 6 are formed from the film 24. Then, when the etching mask is removed, the memory cell array 180 is completed.

According to the present embodiment configured as described above, the following operation and effect can be obtained in addition to the operation and effect of the first embodiment. [16] Each floating gate electrode 5, 6 faces the source / drain region 3 via the gate insulating film 8, and the side wall of each floating gate electrode 5, 6 has a conductive block layer 76 ( That is, they face the source / drain regions 3). That is, each of the floating gate electrodes 5 and 6 is coupled with the source / drain region 3 in the substrate 2 and also with the conductive block layer 76 connected to the source / drain region 3. Therefore, at the time of writing data to the memory cell 75, the potentials of the floating gate electrodes 5 and 6 can be easily raised based on the coupling between the source / drain region 3 and the conductive block layer 76, and the write characteristics can be improved. Can be improved.

[17] Each floating gate electrode 5, 6 is connected to the substrate 2
And the conductive block layer 76 connected to the source / drain region 3. In order to miniaturize the memory cell array, it is necessary to make the impurity diffusion layer (source / drain region) shallow to reduce the diffusion area. In this embodiment, since the floating gate electrodes 5 and 6 are also coupled to the conductive block layer 76 provided on the source / drain regions 3, the facing area between the floating gate electrodes 5 and 6 and the source / drain regions 3 is reduced. It can be reduced, so that further miniaturization can be achieved.

(Fifth Embodiment) Next, a fifth embodiment of the present invention will be described with reference to the drawings. In this embodiment, each memory cell employs any one of the memory cell structures exemplified in the first to fourth embodiments. Further, in the present embodiment, the same components as those in the first embodiment have the same reference numerals, and detailed description thereof will be omitted.

FIG. 21 shows the flash EEP of this embodiment.
2 shows a part of the configuration of a ROM 120. In this embodiment, the flash EEPROM of the first embodiment shown in FIG.
It differs from M101 only in the following points.

{1} In the memory cell array 102,
The source / drain regions 3 of each memory cell 1 arranged in the row direction are separated. {2} In the memory cell array 102, the source / drain regions 3 of the memory cells 1 arranged in the column direction form independent bit lines BL1 to BLn for each memory cell 1 arranged in the row direction. .

That is, the bit line BLm connected to the memory cell 1m (m) is separated from the bit line BLm-1 connected to the memory cell 1m (m-1). Also, memory cell 1
m (m) connected to the bit line BLm + 1 and the memory cell 1m
The bit line BLm + 2 connected to (m + 1) is separated.

According to the present embodiment configured as described above, the following operation and effect can be obtained in addition to the operation and effect of the first embodiment. In the first embodiment, in the read operation, each bit line (BL1... BLm-1, BLm + 2... BLn) corresponding to the source / drain region 3 of each memory cell 1 other than the selected memory cell 1m (m). Is opened, a charge / discharge current flows through each bit line. Therefore, the value of the cell current Ir of the memory cell 1m (m) cannot be accurately detected by the sense amplifier 110 until the respective bit lines are completely charged and discharged. In other words, the speed of the read operation may be reduced, albeit slightly, by the time required for charging and discharging each bit line to be opened.

On the other hand, in the present embodiment, an independent bit line BL1 is provided for each memory cell 1 arranged in the row direction.
To BLn. Therefore, in the read operation, each bit line (BL1... BLm-1, BLm + 2... BLn) corresponding to the source / drain region 3 of each memory cell 1 other than the selected memory cell 1m (m) is opened. Even if the above operation is performed, no charge / discharge current flows through each bit line. Therefore, according to the present embodiment, it is possible to prevent a reduction in the speed of the read operation due to the charging / discharging current of the bit lines BL1 to BLn as in the first embodiment, thereby realizing a high-speed read operation. Can be.

In this embodiment, independent bit lines BL1 to BLn are provided for each memory cell 1 arranged in the row direction.
Is provided, an erase operation can be performed for each selected memory cell 1.

(Sixth Embodiment) Hereinafter, a sixth embodiment of the present invention will be described with reference to the drawings. In this embodiment, each memory cell employs any one of the memory cell structures exemplified in the first to fourth embodiments. In the present embodiment, the same components as those in the fifth embodiment have the same reference numerals, and detailed description thereof will be omitted.

FIG. 22 shows the flash EEP of this embodiment.
2 shows a part of the configuration of the ROM 130. This embodiment differs from the flash EEPROM 120 of the fifth embodiment only in the following points.

{1} The memory cell array 102 is divided into a plurality of cell blocks 102a to 102z in the row direction corresponding to the bit lines BL1 to BLn. That is,
The cell block 102m includes bit lines BLm-3 to BLm-
Each memory cell 1 is connected to the memory cell 1. Further, the cell block 102n includes each bit line BLm
To BLm + 2. That is, each of the cell blocks 102a to 102z
Have three bit lines BL1 to BLn.

{2} Each cell block 102a-102z
, A common bit line is formed by the source / drain regions 3 of each memory cell 1 arranged in the column direction.

{3} Separate cell blocks 102a to 102a
In 2z, the source / drain regions 3 of each memory cell 1 arranged in the row direction are separated. In the adjacent cell blocks 102a to 102z, the source / drain regions 3 of the memory cells 1 arranged in the column direction are arranged.
And separate bit lines are formed. That is, in each of the cell blocks 102m and 102n, the source / drain regions 3 corresponding to the independent bit lines BLm-1 and BLm are separated.

That is, each of the memory cells 1m (m), 1m (m + 1) is connected to the common bit line BLm + 1, and
(m-2) and 1m (m-1) are connected to a common bit line BLm-2. The bit line BLm connected to the memory cell 1m (m) is separated from the bit line BLm-1 connected to the memory cell 1m (m-1).

According to the present embodiment configured as described above, the following operation and effect can be obtained in addition to the operation and effect of the first embodiment. In the fifth embodiment, although the read operation speed is increased, the memory cell array 10
2 as a whole, source / drain regions 3 corresponding to independent bit lines for each memory cell 1 arranged in the row direction.
Are formed, the area of the memory cell array 102 is increased.

On the other hand, in the present embodiment, in the adjacent cell blocks 102a to 102z, the source / drain regions 3 of each memory cell 1 arranged in the column direction are separated, and separate bit lines are formed. . That is, in the same cell blocks 102a to 102z, as in the first embodiment, the source / drain regions 3 corresponding to the common bit line are formed by the source / drain regions 3 of the memory cells 1 arranged in the column direction. Is formed. Therefore, according to the present embodiment, the area of the memory cell array 102 can be reduced as compared with the fifth embodiment.

However, in the present embodiment, a charge / discharge current flows through the bit line BLm + 2 connected to the selected memory cell 1m (m) and the adjacent memory cell 1m (m + 1). However, other bit lines (BL1... BLm-1, BLm + 3... BLn)
Since the charging / discharging current does not flow in the first embodiment, a high-speed reading operation can be performed as compared with the first embodiment.

In this embodiment, of the memory cells 1 connected to the selected one of the word lines WL1 to WLn, any selected one of the cell blocks 102a to 102 is selected.
The erase operation can be performed only for all the memory cells 1 in z. For example, the erasing operation is performed only on each of the memory cells 1m (m-2) and 1m (m-1) in the cell block 102m, and the erasing operation is performed on the other memory cells 1 connected to the same word line WLm. Can not be. Further, each of the memory cells 1m (m-2), 1m (m-1), 1m (m), 1m (m + 1) in each of the cell blocks 102m and 102n.
Of the other memory cells 1 connected to the same word line WLm.

(Seventh Embodiment) Hereinafter, a seventh embodiment of the present invention will be described with reference to the drawings. In this embodiment, each memory cell employs any one of the memory cell structures exemplified in the first to fourth embodiments. Further, in the present embodiment, the same components as those in the first embodiment have the same reference numerals, and detailed description thereof will be omitted.

FIG. 23 shows the flash EEP of this embodiment.
2 shows a part of the configuration of a ROM 140. In this embodiment, the flash EEPROM of the first embodiment shown in FIG.
It differs from M101 only in the following points.

{1} The memory cell array 102 is divided into a plurality of cell blocks 102α to 102ω in the column direction corresponding to the word lines WL1 to WLn. That is,
The cell block 102λ includes the word lines WLm-1 and WLm
Are connected to each other.
In addition, the cell block 102μ includes each word line WLm + 1,
Each memory cell 1 is connected to WLm + 2.

{2} Each cell block 102α-102ω
, Common local short bit lines BLs1 to BLsn are formed by the source / drain regions 3 of the memory cells 1 arranged in the column direction.

{3} Each local short bit line BLs
1 to BLsn, each global bit line BLg1
To BLgn. Global bit line BL
g1 to BLgn are formed by wiring layers made of various metals including refractory metals.

{4} Each cell block 102α-102ω
, Each of the local short bit lines BLs1 to BLs
sn and each of the global bit lines BLg1 to BLgn
It is connected via a MOS transistor 141. In each of the cell blocks 102α to 102ω, the gate of each MOS transistor 141 provided for each of the local short bit lines BLs1 to BLsn is connected to a common gate line G1 to Gn.

That is, in the cell block 102λ, the gate of each MOS transistor 141 provided for each of the local short bit lines BLs1 to BLsn is
They are connected to a common gate line Gm. In the cell block 102 μ, each local short bit line B
The gate of each MOS transistor 141 provided for each of Ls1 to BLsn is connected to a common gate line Gm + 1.

{5} Each of the gate lines G1 to Gn is connected to the row decoder 103. The row decoder 103 is connected to a word line WL in an arbitrary cell block 102α to 102Ω.
When 1 to WLn are selected, the corresponding cell block 10
The gate lines G1 to Gn corresponding to 2α to 102ω are selected. As a result, the MOS transistors 141 connected to the selected gate lines G1 to Gn are turned on, and the local short bit lines BLs1 to BLsn are connected to the global bit lines BLg1 to BLgn.

That is, when any one of the word lines in the cell block 102λ is selected, the gate line Gm
Is selected. When any one of the word lines in the cell block 102μ is selected, the gate line Gm + 1
Is selected.

According to the present embodiment thus configured, each of the local short bit lines BLs1 to BLs formed by the source / drain regions 3 of each memory cell 1
sn are provided independently for each of the cell blocks 102α to 102ω. Therefore, the length of each local short bit line BLs1 to BLsn is shorter than the length of the bit lines BL1 to BLn of the first embodiment. Each of the local short bit lines BLs1 to BLsn is connected to a global bit line BLg1 formed by a metal wiring layer.
ＧBLgn.

Therefore, each local short bit line BL
Since the capacitance of s1 to BLsn is reduced and the time required for charging and discharging each of the local short bit lines BLs1 to BLsn is reduced, the speed of the read operation can be increased.

Each of the above embodiments may be modified as follows, and even in such a case, similar functions and effects can be obtained. In the write operation according to the first to fourth embodiments, the amount of charge stored in the floating gate electrodes 5 and 6 of the memory cell 1 is set to be large, and an overwrite state is set.

However, when writing data to the floating gate electrode 6 of the memory cell 1m (m), the floating gate electrode 5 is already in an overwritten state, and the channel region 4 immediately below the floating gate electrode 5 is completely turned off. In this state, the cell current Iw stops flowing between the source / drain regions 3b and 3a.

Therefore, in this case, at least either the gate length of each floating gate electrode 5 or 6 or the impurity concentration of the substrate 2 is set so that a constant leakage current flows in the channel region 4 immediately below the floating gate electrodes 5 and 6. Set either one. In this way, a necessary cell current Iw can be obtained by a leak current even if the floating gate electrodes 5 and 6 are in an overwritten state.

By the way, when the memory cell 1 is miniaturized,
Accordingly, the gate length of each of the floating gate electrodes 5 and 6 also becomes smaller, and a leak current easily flows through the channel region 4. In other words, it can be said that a method of flowing a constant leak current to the channel region 4 instead of setting the floating gate electrodes 5 and 6 in the overwritten state is more effective when the memory cell 1 is miniaturized.

In the sixth embodiment, the bit lines BL1 to BLn provided in each of the cell blocks 102a to 102z
Is 4 or more. The eighth embodiment is implemented by combining the fifth embodiment and the seventh embodiment. FIG. 24 shows a part of the configuration of the flash EEPROM 150 in that case. In this case, the speed of the read operation can be further increased by the synergistic action of each embodiment.

The ninth embodiment is implemented by combining the sixth embodiment and the seventh embodiment. FIG. 25 shows a part of the configuration of the flash EEPROM 160 in that case. In this case, the speed of the read operation can be further increased by the synergistic action of each embodiment. still,
In this case, the local short bit lines (BLsm-2, BLsm +) shared by the two memory cells 1
1) are also connected to global bit lines (dotted lines in FIG. 25) via MOS transistors.

The insulating films 8 and 10 are made of silicon oxide,
The insulating film is replaced with another insulating film containing at least one of silicon nitride oxide and silicon nitride as a main component. In order to form the insulating film, at least one of a thermal oxidation method, a thermal nitridation method, a thermal oxynitridation method, and a CVD method may be used. Further, a structure in which a plurality of these different insulating films are stacked is replaced.

The material of each of the gate electrodes 5 to 7 is replaced with a conductive material other than doped polysilicon (amorphous silicon, single crystal silicon, various metals including high melting point metal, metal silicide, etc.).

The P-type single crystal silicon substrate 2 is replaced with a P-type well. The source / drain region 3 is replaced by replacing the P-type single crystal silicon substrate 2 with an N-type single crystal silicon substrate
P-type impurity ions (boron, indium, or the like) are used as impurity ions to be implanted for forming the impurity.

The global bit lines BLg1 to BLg
Replace n with a conductive material other than metal (such as doped polysilicon or metal silicide). The multi-value storage technology is used to store data of three or more values for each floating gate electrode 5 and 6 of each memory cell 1.

In each embodiment, a verify write method is used at the time of a write operation. In the control gate electrode 7 of the first embodiment, a wide portion on the channel region 4 and a narrow portion on the floating gate electrodes 5 and 6 and the source / drain region 3 are provided. According to such a configuration, the capacitance between the control gate electrode 7 and the source / drain region 3 can be further reduced, and the write characteristics and read characteristics can be further improved.

In the third embodiment, the width of the control gate electrode 7 is smaller than the width of the floating gate electrodes 5 and 6. In each of the fifth to ninth embodiments, each memory cell has a structure obtained by combining the first and third embodiments, or a second or third structure.
A structure combining the embodiments or a structure combining the fourth and third embodiments may be adopted.

Next, other technical ideas that can be grasped from the above embodiments will be described. (A) The semiconductor memory according to any one of claims 1 to 12, wherein an insulating film formed by a LOCOS method is formed on the floating gate electrode.

(B) The method of manufacturing a semiconductor memory according to any one of claims 13 to 15, wherein
A method for manufacturing a semiconductor memory, comprising a step of forming an insulating film on the first conductive film by using a method.

According to the above (a) and (b), a projection can be formed above the floating gate electrode. By the way, in this specification, the members according to the configuration of the present invention are defined as follows.

The semiconductor substrate includes not only a single crystal silicon semiconductor substrate but also a well, a single crystal silicon film, a polycrystalline silicon film, an amorphous silicon film, a compound semiconductor substrate, and a compound semiconductor film.

The conductive film includes not only a doped polysilicon film but also any conductive material film such as an amorphous silicon film, a single crystal silicon film, various metal films containing a high melting point metal, and a metal silicide film.

The capacitance between the floating gate electrode and the substrate refers to the capacitance between the floating gate electrode and one or both of the source / drain region and the channel region formed on the substrate. Shall be included.

In the writing operation, setting the amount of charge accumulated in the other floating gate electrode so that a cell current of a value necessary for writing data to one floating gate electrode flows is defined as In this case, it is assumed that the charge amount is zero.

[0219]

According to the present invention, there is no variation in writing characteristics, miniaturization is possible, and there is little problem of excessive erasure.
Further, by optimizing the capacitance in the channel region portion and the capacitance in the source / drain region portion, it is possible to provide a semiconductor memory capable of improving write characteristics and read characteristics.

According to the present invention, variation in writing characteristics is small, miniaturization is possible, there is no problem of excessive erasure, and the capacitance in the channel region and the capacitance in the source / drain region are properly adjusted. As a result, it is possible to provide a method for manufacturing a semiconductor memory capable of improving write characteristics and read characteristics.

[Brief description of the drawings]

FIG. 1B is a partial plan view of the first embodiment, FIG.
1A is a sectional view taken along line YY in FIG.

FIG. 2 is a block circuit diagram of the first embodiment.

FIG. 3 is a partial cross-sectional view for explaining the operation of the first embodiment.

FIG. 4 is a partial circuit diagram for explaining the operation of the first embodiment.

FIG. 5 is a partial cross-sectional view for explaining the operation of the first embodiment.

FIG. 6 is a partial circuit diagram for explaining the operation of the first embodiment.

FIG. 7 is a partial cross-sectional view for explaining the operation of the first embodiment.

FIG. 8 is a partial circuit diagram for explaining the operation of the first embodiment.

FIG. 9 is a sectional view showing the manufacturing process of the first embodiment.

FIG. 10 is a sectional view showing the manufacturing process of the first embodiment.

FIG. 11 is a sectional view showing the manufacturing process of the first embodiment.

FIG. 12 is a sectional view showing the manufacturing process of the first embodiment.

FIG. 13 is a cross-sectional view illustrating a manufacturing process of the second embodiment.

FIG. 14 is a cross-sectional view showing a manufacturing step of the second embodiment.

FIG. 15 is a sectional view showing the manufacturing process of the second embodiment.

FIG. 16B is a partial plan view of the third embodiment,
FIG. 16A is a cross-sectional view taken along the line ZZ of FIG.

FIG. 17 is a cross-sectional view showing a manufacturing step of the fourth embodiment.

FIG. 18 is a cross-sectional view showing a manufacturing step of the fourth embodiment.

FIG. 19 is a sectional view showing the manufacturing process of the fourth embodiment.

FIG. 20 is a sectional view showing the manufacturing process of the fourth embodiment.

FIG. 21 is a partial circuit diagram of the fifth embodiment.

FIG. 22 is a partial circuit diagram of the sixth embodiment.

FIG. 23 is a partial circuit diagram of the seventh embodiment.

FIG. 24 is a partial circuit diagram of the eighth embodiment.

FIG. 25 is a partial circuit diagram of the ninth embodiment;

FIG. 26 is a schematic sectional view of a conventional embodiment.

27 (b) is a partial plan view of a conventional embodiment, and FIG. 27 (a) is a sectional view taken along line XX of FIG. 27 (b).

FIG. 28 is a partial cross-sectional view for explaining the operation of the conventional embodiment.

FIG. 29 is a partial cross-sectional view for describing a conventional manufacturing method.

FIG. 30 is a cross-sectional view for explaining a conventional manufacturing method.

FIG. 31 is a cross-sectional view for explaining a conventional manufacturing method.

FIG. 32 is a partial cross-sectional view for explaining the operation of the conventional embodiment.

[Explanation of symbols]

1, 40, 71, 75 memory cell 2, 41 single crystal silicon substrate as semiconductor substrate 3, 42 source / drain region 4, 44 channel region 5, 6, 45, 46 floating gate electrode 5a, 6a 45a, 46a Projection 7, 47 Control gate electrode 7A Wide section 7B Narrow section 8, 48 Gate insulating film 10, 51 Tunnel insulating film 11 Selection gate as base layer 21 First Doped polysilicon film as a conductive film 24 first film 26 doped polysilicon film as a second conductive film 30 insulating layer 43 as a base layer 43 conductive block layer 49 insulating film as a dielectric 76: conductive block layers 101, 120, 130, 140, 150, 160 as base layers Flash EEPROMs 102, 117 as nonvolatile semiconductor memories , 180, 190 ... memory cell arrays (transistor arrays) 102a to 102z, 102a to 102w ... cell blocks 141 ... MOS transistors BL1 to BLm to BLn ... bit lines BLs1 to BLsm to BLsn ... local short bit lines BLg1 to BLgm .About.BLgn... Global bit lines WL1 .about.WLm .about.WLn... Word lines as control lines

 ──────────────────────────────────────────────────続 き Continued on the front page F-term (reference) ER14 ER17 ER22 GA01 GA09 GA17 GA30 JA02 JA32 JA36 KA01 LA12 LA16 NA02 PR03 PR12 PR21 PR36 ZA21

Claims (15)

[Claims] 1. A semiconductor device comprising: a plurality of floating gate electrodes sharing a control line; and channel regions and source / drain regions provided alternately between the floating gate electrodes of a semiconductor substrate, wherein the control line in the channel region is provided. A semiconductor memory in which a capacitance between the semiconductor substrate and a semiconductor substrate is set to be larger than a capacitance between the control line and the semiconductor substrate in the source / drain region. 2. A semiconductor device comprising: a plurality of floating gate electrodes sharing a control line; and channel regions and source / drain regions alternately provided between the floating gate electrodes of the semiconductor substrate, wherein the control line in the channel region is provided. The capacitance between the semiconductor substrate and the control line in the source / drain region is set to be larger than the capacitance between the control line and the semiconductor substrate. A semiconductor memory having a capacitance set to be larger than a capacitance between the floating gate electrode and a control line. 3. The semiconductor memory according to claim 1, wherein said control line forms a control gate electrode of said semiconductor memory on each of said floating gate electrodes, and said control line on each of said channel regions. And a semiconductor memory constituting a select gate electrode of the semiconductor memory. 4. The semiconductor memory according to claim 1, wherein a plurality of floating gate electrodes sharing the control line and a channel alternately provided between the floating gate electrodes of the semiconductor substrate. A region and a source / drain region are arranged in a matrix corresponding to a plurality of control lines arranged in a predetermined direction, and each of the source / drain regions is commonly connected to a bit line in the matrix. . 5. The semiconductor memory according to claim 1, wherein the base layer having non-conductivity on each of the source / drain regions and having conductivity on each of the channel regions is provided. A semiconductor memory provided below a control line. 6. The semiconductor memory according to claim 5, wherein said underlayer is a conductor layer partially oxidized on each of said source / drain regions. 7. The semiconductor memory according to claim 1, further comprising a conductive block layer selectively formed on each of said source / drain regions while maintaining electrical conduction with said regions. A semiconductor memory, wherein each of the floating gate electrodes is disposed adjacent to the conductive block layer via a dielectric. 8. The semiconductor memory according to claim 7, wherein a conductive underlying layer is provided below said control line,
The underlayer is separated into a plurality of portions, the underlayer on each of the channel regions is kept electrically conductive with the control line, and the underlayer on each of the source / drain regions is insulated from the control line and A semiconductor memory that forms a conductive block layer. 9. The semiconductor memory according to claim 1, wherein said control line has a line width smaller than an electrode width of each of said floating gate electrodes. 10. The semiconductor memory according to claim 1, wherein said control line is formed such that a line width on said source / drain region is smaller than a line width on said channel region. Semiconductor memory. 11. The semiconductor memory according to claim 10, wherein a line width of said control line on said channel region is substantially equal to an electrode width of said floating gate electrode.
A semiconductor memory wherein a line width on a drain region is formed smaller than an electrode width of the floating gate electrode. 12. The semiconductor memory according to claim 1, further comprising an acute-angled projection on an upper part of each floating gate electrode facing said control line. 13. A first and a second formed on a semiconductor substrate.
A source / drain region, a channel region sandwiched between the first and second source / drain regions, and first and second floating gate electrodes juxtaposed on the channel region via a gate insulating film. A plurality of transistors arranged on the first and second floating gate electrodes via a tunnel insulating film and having a control gate electrode shared by the first and second floating gate electrodes are arranged in a matrix. A common control line is formed by the control gate electrodes of the transistors arranged in a predetermined direction, and the source / drain regions of the transistors arranged in a direction intersecting the arrangement direction of the control gate electrodes. A method of manufacturing a semiconductor memory in which a common bit line is formed, comprising: forming a gate insulating film on the semiconductor substrate; Forming a first conductive film on the film; etching the first conductive film to form the first and second floating gate electrodes arranged in parallel with the source / drain regions; Forming a tunnel insulating film over the entire surface of the exposed gate insulating film and the first conductive film; forming a second conductive film on the tunnel insulating film; and forming the source of the second conductive film. A step of partially oxidizing a portion corresponding to the drain region; a step of forming a third conductive film on the partially oxidized second conductive film; And etching the conductive film, the tunnel insulating film, and the first conductive film in the row direction at the same time to perform element isolation. 14. A first and a second formed on a semiconductor substrate.
A source / drain region, a channel region sandwiched between the first and second source / drain regions, and first and second floating gate electrodes juxtaposed on the channel region via a gate insulating film. A plurality of transistors arranged on the first and second floating gate electrodes via a tunnel insulating film and having a control gate electrode shared by the first and second floating gate electrodes are arranged in a matrix. A common control line is formed by the control gate electrodes of the transistors arranged in a predetermined direction, and the source / drain regions of the transistors arranged in a direction intersecting the arrangement direction of the control gate electrodes. A method of manufacturing a semiconductor memory in which a common bit line is formed, comprising: forming a gate insulating film on the semiconductor substrate; Forming a first conductive film on the membrane, the and said gate insulating film and the first conductive film source
Simultaneously etching a portion corresponding to the drain region; forming an insulating wall on a side surface of the etched first conductive film and the gate insulating film; Forming a second conductive film on the entire surface of the conductive film, and selectively oxidizing an upper portion of the second conductive film on the source / drain region to form a conductive block layer on the source / drain region And forming the first and second floating gate electrodes by the first conductive film left after the second conductive film and the first conductive film on the channel region are simultaneously etched. Forming a tunnel insulating film over the entire surface of the gate insulating film exposed by the etching and the selectively oxidized second conductive film; and forming a third conductive film on the tunnel insulating film. Forming a film, and simultaneously separating the third conductive film, the tunnel insulating film, the second conductive film, and the first conductive film in the row direction to perform element isolation. A method for manufacturing a semiconductor memory. 15. A first and a second formed on a semiconductor substrate.
A source / drain region, a channel region sandwiched between the first and second source / drain regions, and first and second floating gate electrodes juxtaposed on the channel region via a gate insulating film. A plurality of transistors arranged on the first and second floating gate electrodes via a tunnel insulating film and having a control gate electrode shared by the first and second floating gate electrodes are arranged in a matrix. A common control line is formed by the control gate electrodes of the transistors arranged in a predetermined direction, and the source / drain regions of the transistors arranged in a direction intersecting the arrangement direction of the control gate electrodes. A method of manufacturing a semiconductor memory in which a common bit line is formed, comprising: forming a gate insulating film on the semiconductor substrate; Forming a first conductive film on the film; etching the first conductive film to form the first and second floating gate electrodes arranged in parallel with the source / drain regions; Forming a tunnel insulating film on the entire surface of the exposed gate insulating film and first conductive film; etching the tunnel insulating film and the gate insulating film on the source / drain regions; Forming a second conductive film over the semiconductor substrate surface and the entire surface of the tunnel insulating film; etching the second conductive film at portions corresponding to the first and second floating gate electrodes; Oxidizing a surface of a portion of the etched second conductive film corresponding to the source / drain region; and etching the channel region of the etched second conductive film. Forming a third conductive film on a portion corresponding thereto and on the oxidized second conductive film; and forming the third conductive film, the second conductive film, the tunnel insulating film, and the first conductive film. And etching the film simultaneously in the row direction to separate elements.