JP2001057397A - Semiconductor memory and operating method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor memory which can be improved in service life, lowered in operating voltage, enhanced in operation speed, lessened in power consumption, and enhanced in degree of integration. SOLUTION: This semiconductor memory is equipped with an N-type source region 3 and an N-type drain region 4 which are formed on a P-type single crystal silicon substrate 2, a control gate electrode 7 and a floating gate electrode 11 formed between the source region 3 and the drain region 4, an intergate 9 formed of N-type semiconductor film formed between the control gate electrode 7 and the floating gate electrode 11, a first tunnel insulating film 8 provided between the control gate electrode 7 and the N-type intergate 9, and a second tunnel insulating film 10 which is formed between the N-type intergate 9 and the floating gate electrode 11. A prescribed potential difference is produced between the drain region 4 and the source region 3, by which electrons are moved from the control gate electrode 7 to the N-type intergate 9 and furthermore accelerated to be injected into the floating gate electrode 11.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor memory and a method of operating the semiconductor memory.

[0002]

2. Description of the Related Art In recent years, an EPROM (Erasable and Programmable Read-Only Memory) has been used as a semiconductor memory that can be substituted for a hard disk and a floppy disk as magnetic memories.
nly Memory) and EEPROM (Electrically Erasable)
and non-volatile semiconductor memories such as Programmable Read Only Memory).

In an EPROM or EEPROM memory cell, carriers are stored in a floating gate electrode, data is stored depending on the presence or absence of carriers, and data is read out by detecting a change in threshold voltage due to the presence or absence of carriers. Is going. In particular, in the EEPROM, data is erased in the entire memory cell array, or
There is a flash EEPROM that divides a memory cell array into arbitrary blocks and erases data in each block unit. This flash EEPROM is also called a flash memory, and is used in various portable devices because it has features of being able to have a large capacity, low power consumption, high speed, and excellent shock resistance. Also, Flash EEPROM
M memory cells are formed of one transistor, and E
There is an advantage that higher integration is easier than EPROM.

Conventionally, a stacked gate type and a split gate type have been proposed as memory cells constituting a flash EEPROM.

In a stacked gate type memory cell,
In a write operation for accumulating electrons in the floating gate electrode, electrons in the channel of the semiconductor substrate are converted into hot electrons and injected into the floating gate electrode. At this time, it is necessary to apply a voltage of more than ten volts to the control gate electrode. In a stacked gate memory cell, in an erasing operation for extracting electrons accumulated in a floating gate electrode, a Fowler-Nordheim Tunnel Current (hereinafter, referred to as an FN tunnel current) flows from a drain region to a floating gate electrode. Flow. At this time, more than 10 V
Must be applied.

In a split gate type memory cell,
In a write operation for accumulating electrons in the floating gate electrode, electrons in the channel of the semiconductor substrate are converted into hot electrons and injected into the floating gate electrode. At this time, it is necessary to apply a voltage of more than 10 V to the drain region. In a split gate memory cell, in an erase operation of extracting electrons from the floating gate electrode, an FN tunnel current flows from the control gate electrode to the floating gate electrode. At this time, it is necessary to apply a voltage of more than ten volts to the control gate electrode.

As described above, in the conventional stacked gate type and split gate type memory cells, hot electrons are used to inject electrons into the floating gate electrode in a writing operation, and are stored in the floating gate electrode in an erasing operation. The FN tunnel current is used to extract the electrons.

Incidentally, in order to hold carriers accumulated in the floating gate electrode for a long period of time, it is necessary to increase the thickness of an insulating film surrounding the floating gate electrode. However, when injecting or extracting electrons from the floating gate electrode,
Hot electron or FN tunnel current is used. Therefore, as the thickness of the insulating film surrounding the floating gate electrode is increased, the voltage applied to the control gate electrode and the drain region in the writing operation or the erasing operation (hereinafter, referred to as the operating voltage of the memory cell) must be increased. No.

The operating voltage of the memory cell is generated by a booster circuit. In this case, the voltage that can be generated practically is more than ten V
Up to. On the other hand, in the case where a silicon oxide film is used as an insulating film surrounding the floating gate electrode, if the operating voltage of the memory cell is set at more than ten volts, the thickness of the silicon oxide film is 8 to
It cannot be made 10 nm or more. Therefore, conventionally, when a silicon oxide film is used as an insulating film surrounding the floating gate electrode in order to suppress the operating voltage of the memory cell to more than ten volts,
The thickness is set to 8 to 10 nm. If the thickness of the silicon oxide film is about 8 to 10 nm, electrons accumulated in the floating gate electrode can be held for a practically satisfactory period.

In the case where holes are accumulated in the floating gate electrode, the thickness of the silicon oxide film as an insulating film surrounding the floating gate electrode is set to 8 to 10 nm, as in the case of accumulating electrons. Thereby, the operating voltage of the memory cell is suppressed to more than ten volts, and the holes accumulated in the floating gate electrode are held for a practically satisfactory period.

[0011]

SUMMARY OF THE INVENTION In recent years, flash EE
Also in the PROM, after extending the holding period of the carriers accumulated in the floating gate electrode to extend the life, a lower voltage, faster operation, lower power consumption, and higher integration than ever before are achieved. It is required to aim at the conversion.

As described above, conventionally, when a silicon oxide film is used as an insulating film surrounding a floating gate electrode, the thickness of the silicon oxide film is set to 8 to 10 nm. It is necessary to avoid making the thickness less than 8 nm.

By the way, if the operating voltage of the memory cell is reduced, the time for boosting (lead time) is shortened, and the writing and erasing operations can be speeded up accordingly. Further, low power consumption can be achieved.

[0014] Further, a booster circuit for generating an operating voltage of a memory cell has a larger circuit scale as the generated voltage becomes higher. The occupied area (transistor size) of a transistor constituting a peripheral circuit (decoder, sense amplifier, buffer, etc.) of the flash EEPROM on the substrate increases as the withstand voltage increases. Therefore, when the operating voltage of the memory cell is reduced, the circuit scale of the booster circuit is reduced, and the size of the transistor included in the peripheral circuit is also reduced, so that high integration can be achieved.

Therefore, by reducing the operating voltage of the memory cell, it is possible to simultaneously achieve high-speed operation, low power consumption, and high integration.

However, in the conventional stacked gate type and split gate type memory cells, hot electrons or FN tunnel current is used when injecting or extracting electrons from the floating gate electrode. Therefore, when a silicon oxide film is used as an insulating film surrounding the floating gate electrode, it is difficult to lower the operating voltage of the memory cell from the present level, while maintaining the film thickness at 8 to 10 nm as before. . That is, unless the structure of the conventional stacked gate type and split gate type memory cells is changed, it is difficult to reduce the operating voltage of the memory cells while maintaining the same level of life as at present.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a longer life, lower voltage, higher operation speed, lower power consumption, and higher integration. To provide a semiconductor memory capable of achieving the above.

Another object of the present invention is to realize the above-described semiconductor memory with a simple structure.

Still another object of the present invention is to provide a method of operating a semiconductor memory capable of easily operating such a semiconductor memory as described above.

[0020]

According to one aspect of the present invention, a semiconductor memory includes a first gate electrode, a second gate electrode, a semiconductor region formed of a conductive film, and one surface of the semiconductor region. A first insulating film, and a second insulating film formed on the other surface of the semiconductor region. Then, carriers are injected into the second gate electrode through the first insulating film, the semiconductor region, and the second insulating film. Here, injecting carriers includes not only injecting electrons but also extracting electrons. In this case, the semiconductor region preferably includes a second conductivity type semiconductor film formed on the first layer made of the first conductivity type semiconductor.

A semiconductor memory according to another aspect of the present invention includes a first region and a second region of a second conductivity type formed in a first layer made of a semiconductor of a first conductivity type, and a first region in the first layer. A first gate electrode and a second gate electrode formed between the first region and the second region; and a second gate made of a conductive film formed between the first gate electrode and the second gate electrode in the first layer. A third region of conductivity type, a first insulating film formed between the first gate electrode and the third region, and a second insulating film formed between the second gate electrode and the third region. Have.

Therefore, according to the present invention, the potential of the third region is increased only by applying a predetermined voltage to the second region,
An electric field can be easily generated between the third region and the first gate electrode. As a result, carriers that have passed through the barrier of the first insulating film between the first gate electrode and the third region are accelerated by the electric field generated in the third region, and the carrier between the third region and the second gate electrode is accelerated. It is injected and accumulated in the second gate electrode beyond the barrier of the second insulating film. Therefore, data can be stored depending on the presence or absence of carriers accumulated in the second gate electrode, and the semiconductor device operates as a nonvolatile semiconductor memory.

In the semiconductor memory according to another aspect, the first gate electrode is formed on the first layer via the first gate insulating film, and the second gate electrode is formed on the first layer via the second gate insulating film. Is desirably formed through the intermediary.

The capacitance between the second region and the second gate electrode is set to be larger than the capacitance between the third region and the second gate electrode, and is applied to the second region. A voltage is transmitted to the second gate electrode by electrostatic coupling between the second gate electrode and the second gate electrode, so that the potential of the third region connected to the second region via the first layer is substantially equal to that of the second region. Is desirable. Thus, the potential of the second gate electrode can be easily controlled only by controlling the potential of the second region.

The thickness of the third region is equal to the energy required for carriers transmitted through the barrier of the first insulating film between the first gate electrode and the third region to cross the barrier of the second insulating film. It is desirable that the distance is set to be approximately equal to or less than the mean free path.

In this case, almost all carriers that have passed through the barrier of the first insulating film between the first gate electrode and the third region acquire energy exceeding the barrier of the second insulating film and become hot carriers. That is, it is injected into the second gate electrode with extremely high probability without staying in the third region. Therefore, the effect of the present invention can be more reliably obtained.

The first gate electrode and the second gate electrode are formed on the main surface of the first layer, and the third region made of a conductive film is formed on the main surface of the first layer. It is preferably formed between the gate electrode and the second gate electrode. When the first gate electrode, the second gate electrode, and the third region are formed on the first layer as described above, a groove for embedding the first gate electrode, the second gate electrode, and the third region is formed in the first layer. No need to do. Therefore, the structure can be simplified as compared with the case where the groove is formed, and as a result, the semiconductor memory of the present invention can be realized with a simple structure. Further, since it is not necessary to form a groove in the first layer, a structure having the first gate electrode, the third region, and the second gate electrode can be formed by a simple process.
Further, since it is not necessary to form a tunnel insulating film or the like on the side surface of the first layer damaged by the etching for forming the groove, the film quality of the tunnel insulating film does not deteriorate.

In this case, preferably, at least a part of the third region is formed on an upper surface of the second gate electrode, and at least a part of the first gate electrode is formed on an upper surface of the third region. ing. Thus, the first gate electrode,
By arranging the second gate electrode and the third region in the vertical direction, it is possible to easily obtain a structure that does not require a groove in the first layer.

Preferably, the third region includes a single crystal silicon film. According to this structure, the first insulating film can be formed by oxidizing the single crystal silicon film, so that a first insulating film having good film quality can be obtained.

Further, the third region may include a first sidewall film made of a first conductive film formed in a self-aligned manner. With this configuration, the third region made of the first conductive film can be formed without causing a problem of misalignment of the mask in the mask process.

In this case, the first sidewall film made of the first conductive film is formed of a second sidewall film made of the second conductive film formed on the side surface of the second gate electrode with the second insulating film interposed therebetween. , The side surface of the second sidewall film and the first side wall film.
And a third sidewall film made of a third conductive film formed so as to be in contact with the surface of the layer. According to this structure, the third region can be connected to the first layer by the third sidewall film, whereby the third region can be connected to the second region via the first layer.
Therefore, the effect of the present invention can be more reliably obtained.

In this case, the second sidewall film is formed by depositing a second conductive film on the side surface of the second gate electrode via the second insulating film and then etching back the third conductive film. The film is formed so as to be in contact with the side surface of the second sidewall film and the surface of the first layer by depositing a third conductive film so as to cover the first layer and the second sidewall film and then performing etch back. Preferably.

With this configuration, the thickness of the second sidewall film and the third sidewall film can be controlled by the thickness of the second conductive film and the third conductive film, respectively. The width of the third region composed of the sidewall film and the third sidewall film can be formed to a fine width equal to or smaller than the minimum critical dimension (minimum exposure dimension) of the mask process. Further, by controlling the thicknesses of the second and third conductive films, the widths of the second and third sidewall films can be controlled with high precision.
Also, the width of the third region composed of the third sidewall film can be controlled with high accuracy. As a result, the third region can be further miniaturized, and variation in the width of the third region can be suppressed.

Preferably, the second region includes a fourth sidewall film made of a fourth conductive film formed on the side surface of the second gate electrode through a third insulating film in a self-aligned manner. According to this structure, the facing area between the second region and the second gate electrode can be increased by the fourth sidewall film. Thereby, the capacitance between the second region and the second gate electrode can be easily increased. As a result, the capacitance between the second region and the second gate electrode can be easily made larger than the capacitance between the third region and the second gate electrode. Therefore, the potential of the second gate electrode can be easily controlled by changing the voltage applied to the second region.

In this case, the fourth sidewall film is preferably formed by a fifth conductive film formed of a fifth conductive film formed on the side wall of the second gate electrode via a third insulating film, and And a sixth sidewall film made of a sixth conductive film formed to be in contact with the side surface of the sidewall film and the surface of the first layer. With this configuration,
The sixth side wall film enables connection with the first layer, whereby the fifth and sixth side wall films can be connected to each other.
The second region including the impurity region formed in the first layer can be easily connected. As a result, the fifth and sixth
The sidewall film can be easily used as a part of the second region.

The fourth sidewall film serving as the second region is preferably formed simultaneously with the first sidewall film serving as the third region. With this configuration, even if the fourth sidewall film is provided, the manufacturing process does not become complicated.

[0037] In another aspect of the present invention, a method of operating a semiconductor memory includes a first region and a second region of a second conductivity type formed in a first layer made of a semiconductor of a first conductivity type; Between a first region and a second region in one layer, a first gate electrode formed on the first layer via a first gate insulating film, and a first gate electrode and a second region in the first layer. A second gate electrode formed between the first layer and the second gate electrode in the first layer, and a conductive film formed between the first gate electrode and the second gate electrode in the first layer. A third region of the second conductivity type, a first insulating film formed between the first gate electrode and the third region, and a second insulating film formed between the second gate electrode and the third region A method of operating a semiconductor memory, comprising: a first gate electrode to a first insulating film; And the second gate electrode via a second insulating film, writing data by injecting hot carriers.

That is, at the beginning of the writing operation, a predetermined potential difference is generated between the first gate electrode and the third region and between the first gate electrode and the second gate electrode. Done. Then, as the writing operation proceeds, hot carriers are continuously injected into the second gate electrode, so that the potential of the second gate electrode gradually decreases from the initial value. As the potential of the second gate electrode decreases, the potential of the third region also gradually decreases.
The potential difference between the gate electrode and the third region becomes lower than a predetermined value. As a result, hot carriers in the first gate electrode cannot pass through the barrier of the first insulating film, and the writing operation is automatically terminated.

Further, it is desirable to erase data by extracting hot carriers from the second gate electrode to the third region via the second insulating film.

The capacitance between the second region and the second gate electrode is set to be larger than the capacitance between the third region and the second gate electrode, and is applied to the second region. The voltage is transmitted to the second gate electrode by electrostatic coupling between the second gate electrode and the second gate electrode, so that the potential of the third region connected to the second region via the first layer is the same as that of the second region. Is desirable. Thus, the potential of the second gate electrode can be easily controlled only by controlling the potential of the second region.

The thickness of the third region is equal to the energy required for carriers passing through the barrier of the first insulating film between the first gate electrode and the third region to cross the barrier of the second insulating film. It is desirable that the distance is set to be approximately equal to or less than the mean free path.

Thus, almost all of the carriers that have passed through the barrier of the first insulating film between the first gate electrode and the third region acquire energy exceeding the barrier of the second insulating film and become hot carriers. That is, it is injected into the second gate electrode with extremely high probability without staying in the third region. Therefore, the effect of the present invention can be more reliably obtained.

When erasing data, it is desirable to set the voltage of the second region, which is coupled to the second gate electrode, to a predetermined value once, and then keep the second region open. .

That is, at the beginning of the erasing operation, a predetermined potential difference is generated between the second gate electrode and the third region, so that the erasing is continued. Then, as the erase operation proceeds, the potential of the second gate electrode gradually increases. When the potential difference between the second gate electrode and the third region becomes smaller than a predetermined value, electrons in the second gate electrode cannot pass through the barrier of the second insulating film, and the erasing operation cannot be further performed. Will not be done. Thus, the erasing operation automatically ends.

[0045]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) A first embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a partial cross-sectional view of the memory cell of the first embodiment. The structure of the memory cell 1 according to the first embodiment will be described below with reference to FIG.

In the memory cell 1 of the first embodiment, p
An n-type source region 3 is formed on the surface of
And n-type drain region 4 is formed at a predetermined interval so as to sandwich channel region 5. A second gate insulating film 12a made of a silicon oxide film and a third insulating film 1 are formed on the channel region 5 and a part of the drain region 4.
A floating gate electrode 11 made of an n-type polysilicon film is formed via 2b.

On the side and upper surfaces of the floating gate electrode 11, an intergate 9 made of an n-type single crystal silicon film is formed via a second tunnel insulating film 10. The bottom of the intergate 9 is in contact with the surface of the p-type single crystal silicon substrate 2 via the opening 15. Below the contact surface between the intergate 9 and the p-type single-crystal silicon substrate 2, an n-type diffusion layer 14 is formed.

A control gate electrode 7 made of an n-type polysilicon film is formed on a side surface and an upper surface of the intergate 9 via a first tunnel insulating film 8. The bottom of the control gate electrode 7 is formed on the channel region 5 via a first gate insulating film 6 made of a silicon oxide film.

Here, the film thickness of each of the above members is set as follows.

The thickness of the first gate insulating film 6: 16 to 20 nm The thickness of the first tunnel insulating film 8: 3 to 4 nm The thickness of the second tunnel insulating film 10: 8 to 20 nm The third insulating film The thickness of the second gate insulating film 12a: 8 to 10 nm The width of the intergate 9 (the first tunnel insulating film 8 and the second
Distance between tunnel insulating film 10): 20 to 40 nm
(The width of the intergate 9 is set to 20 to 30 nm so that electrons having energy of 3 to 5 eV used for writing reach the floating gate electrode 11 by several percent or more.
Here, the area of the third insulating film 12b located between the drain region 4 and the floating gate electrode 11 is
Is larger than the area of the second tunnel insulating film 10 located between the third insulating film 12 and the floating gate electrode 11.
The thickness of b is smaller than the thickness of the second tunnel insulating film 10.

Therefore, the memory cell 1 in the present embodiment
In this case, the capacitance between the drain region 4 and the floating gate electrode 11 is larger than the capacitance between the intergate 9 and the floating gate electrode 11. Thereby, the coupling ratio between the intergate 9 and the floating gate electrode 11 becomes larger than the coupling ratio between the drain region 4 and the floating gate electrode 11. As a result, the potential of the drain region 4 is easily transmitted to the floating gate electrode 11.

FIG. 2 shows an overall configuration of a nonvolatile semiconductor memory 50 using the memory cell 1.

As shown in FIG. 2, the memory cell array 51 is configured by arranging a plurality of memory cells 1 in a matrix.
Only memory cells are shown).

In each memory cell 1 arranged in the row direction, each control gate electrode 7 is connected to a common word line W
It is connected to L ₁ to WL _n.

In each of the memory cells 1 arranged in the column direction, the drain region 4 is connected to a common bit line BL.
Is connected to ₁ to BL _n, the source region 3 is connected to a common source line SL.

Each of the word lines WL _{1 to} WL _n is connected to a row decoder 5.
2 and the bit lines BL _{1 to} BL _n are connected to a column decoder 53.

A row address and a column address specified from the outside are input to an address pin 54. The row address and the column address are applied to the address pins 5
4 to the address latch 55. Of the addresses latched by the address latch 55, the row address is transferred to the row decoder 52 via the address buffer 56, and the column address is transferred to the column decoder 53 via the address buffer 56.

The row decoder 52 is connected to each of the word lines WL ₀ to WL ₀ .
Of WL _n, with selecting the word line corresponding to the latched row address in the address latch 55, on the basis of a signal from the gate voltage control circuit 57, the word line W
The potentials of L _{1 to} WL _n are controlled in accordance with each operation mode described later.

The column decoder 53 controls each bit line BL ₁
Of to BL _n, selects a bit line corresponding to the latched column address in the address latch 55, on the basis of a signal from the drain voltage control circuit 58, each of the bit lines BL ₁
Controlling in response to each operation mode described below the potential of to BL _n.

Data specified externally is input to data pin 59. The data is transferred from the data pin 59 to the column decoder 53 via the input buffer 60. The column decoder 53 is connected to each of the bit lines BL _{1 to} BL _n
Is controlled in accordance with the data as described later.

[0062] Data read from any memory cell 1, the column decoder 53 from the bit lines BL ₁ to BL _n
Is transferred to the sense amplifier group 61 via The sense amplifier 61 is a current sense amplifier. Sense amplifier group 61
Is output from the output buffer 62 to the outside via the data pin 59.

The source voltage control circuit 63 is connected to the source line SL
Is controlled in accordance with each operation mode described later.

The operation of each of the circuits (52 to 63) is controlled by the control core circuit 64.

Next, each operation (write operation, erase operation, read operation) of the memory cell 1 configured as described above will be described. A source voltage Vs is applied to the source region 3 via a source line SL. The drain region 4 a drain voltage Vd through the bit lines BL ₁ to BL _n is applied. The control gate voltage Vcg via the word line WL ₀ to WL _n is applied to the control gate electrode 7. Substrate voltage Vsub is applied to p-type single crystal silicon substrate 2.

(Write Operation) Before this write operation is performed, the floating gate electrode 11 is in an erased state (a state in which electrons are extracted). In the first embodiment, the floating gate electrode 11 in the erased state is , About 2V. In the first embodiment, the floating gate electrode 11
Threshold voltage Vt of the transistor whose gate is the gate and the transistor whose gate is the control gate electrode 7
Are both set to 0.5V.

In the write operation, the operating voltage of the memory cell 1 is set to a source voltage Vs: 0 V and a drain voltage Vd:
3 V, control gate voltage Vcg: -3 V, substrate voltage (well voltage when memory cell 1 is formed in a p-type well formed on a silicon substrate: well voltage)
b: Set to 0V.

As described above, since the drain region 4 and the floating gate electrode 11 are strongly coupled capacitively, about ／ of the drain voltage (3 V) is the potential of the floating gate electrode 11 in the erased state. (Approximately 2 V). Thereby, the potential of the floating gate electrode 11 increases to about 4V. As a result, the transistor whose gate is the floating gate electrode 11 is turned on, and the
Is substantially equal to the potential of the drain region 4.

That is, the potential of the intergate 9 is 3 V
(Up to the drain voltage Vd, the floating gate electrode 11
(A voltage level-shifted by the threshold voltage Vt from the above potential), and a high electric field is generated between the intergate 9 and the control gate electrode 7. As a result, the Fowler-Nordheim Tunnel Curve
rent (hereinafter, referred to as FN tunnel current) flows, and electrons move from the control gate electrode 7 to the intergate 9. The electrons transmitted (tunneled) through the barrier of the first tunnel insulating film 8 between the control gate electrode 7 and the intergate 9 are
It is accelerated by the high electric field generated between the intergate 9 and the control gate electrode 7 and is injected into the floating gate electrode 11 through the second tunnel insulating film 10. As a result, electrons are accumulated in the floating gate electrode 11, and data is written.

Here, the energy required for electrons to cross the barrier of the second tunnel insulating film 10 made of a silicon oxide film is 3.2 eV, and the potential difference required for obtaining the energy is 3.2 V. is there. Therefore, between the control gate electrode 7 and the inter-gate 9 and between the control gate electrode 7 and the floating gate electrode 11, 3.2
The operating voltage at the time of writing is set so that a potential difference of V or more is generated.

That is, when the drain voltage Vd is set to 3 V and the control gate voltage Vcg is set to -3 V, the voltage of the floating gate electrode 11 is increased due to the electrostatic coupling between the drain region 4 and the floating gate electrode 11 as described above. Becomes about 4V, and the potential of the intergate 9 becomes 3V. Therefore, a potential difference of 6 V is initially generated between the control gate electrode 7 and the intergate 9, and a potential difference of about 7 V is initially generated between the control gate electrode 7 and the floating gate electrode 11.

When the energy of the electrons is 3.2 eV, the mean free path (the average value of the distance traveled by the electrons) is about 30.
４０40 nm. Here, the width of the intergate 9 is set to 30 nm, which is thinner than the mean free path. Therefore, the first gate between the control gate electrode 7 and the
The electrons that have passed through the barrier of the tunnel insulating film 8 have a distance of 3.2 eV over a short distance equal to or less than the mean free path (= about 30 to 40 nm).
It is accelerated above.

Therefore, almost all of the electrons that have passed through the barrier of the first tunnel insulating film 8 acquire energy exceeding the barrier (= 3.2 eV) of the second tunnel insulating film 10 to become hot electrons, resulting in inter-electrons. Floating gate electrode 1 with very high probability without staying in gate 9
1 is injected.

The energy of electrons and the probability of passing through the barrier of the first tunnel insulating film 8 can be adjusted by the source voltage Vs, the drain voltage Vd, and the control gate voltage Vcg. Therefore, the hot electrons can be injected into the floating gate electrode 11 when the hot electrons obtain energy slightly exceeding the barrier of the second tunnel insulating film 10.

By the way, as described above, in the present embodiment, at the beginning of the writing operation, between the control gate electrode 7 and the intergate 9 and between the control gate electrode 7 and the floating gate electrode 3. Since a potential difference of 2 V or more is generated, writing is continuously performed (floating gate electrode 1
1 is injected with electrons). On the other hand, as the writing operation proceeds, electrons are continuously injected into the floating gate electrode 11, so that the potential of the floating gate electrode 11 gradually decreases from 4V. As described above, the potential of the intergate 9 is a value obtained by level-shifting the potential of the floating gate electrode 11 by the threshold voltage Vt with the drain voltage Vd as an upper limit. For this reason, the potential of the intergate 9 gradually decreases in accordance with the decrease of the potential of the floating gate electrode 11, and finally, the potential difference between the control gate electrode 7 and the intergate 9 becomes less than 3.2V. Then, the electrons in the control gate electrode 7 cannot pass through the barrier of the first tunnel insulating film 8, and no further write operation is performed.

That is, in the present embodiment, since the write operation is automatically terminated by the change in the potential of the floating gate electrode 11, a separate circuit for detecting the end of the write operation becomes unnecessary. This makes it possible to simplify the structure of the peripheral circuit, reduce the area, and reduce power consumption. Furthermore, in the present embodiment, the writing operation does not end in a fixed writing time, but the writing operation is automatically ended by a change in the potential of the floating gate electrode 11, so that a variation in the writing level between the memory cells 1 occurs. Can be effectively prevented. As a result, the write level of each memory cell 1 can be made substantially uniform.

(Erase Operation) In the erase operation, the operating voltages of the memory cell 1 are set to a source voltage Vs: 8 V, a drain voltage Vd: 0 V, a control gate voltage Vcg: 9 V, and a substrate voltage (well voltage) Vsub: 0 V. I do. In this case, since the drain region 4 and the floating gate electrode 11 are strongly coupled capacitively, the potential of the floating gate electrode 11 becomes almost 0V.

On the other hand, since the potential of the control gate electrode 7 is 9 V, the transistor having the control gate electrode 7 as a gate is turned on. As a result, the potential of the inter gate 9 becomes substantially equal to the potential of the source region 3. That is, the potential of the intergate 9 is 8 V (up to the source voltage Vs, the threshold voltage V
(voltage shifted by t). As a result, a high electric field of about 10 MV is generated in the second tunnel insulating film 10 located between the intergate 9 and the floating gate electrode 11. As a result, an FN tunnel current flows, electrons are extracted from the floating gate electrode 11 to the intergate 9, and data is erased.

(Read Operation) In the read operation, the operating voltage of the memory cell 1 is changed to the source voltage Vs: 0.
V, drain voltage Vd: 3 V, control gate voltage Vcg: 3
V, the substrate voltage (well voltage) Vsub: 0 V.

In a state where electrons are not accumulated in the floating gate electrode 11 (erased state), the floating gate electrode 11 is positively charged (in the first embodiment, the floating gate electrode 11 has a potential of 2V. Therefore, the channel region 5 below the floating gate electrode 11 is turned on. In the state where electrons are accumulated in the floating gate electrode 11 (writing state), the floating gate electrode 11 is negatively charged, and thus the channel region 5 below the floating gate electrode 11 is turned off.

When the channel region 5 is on, a current flows more easily between the source region 3 and the drain electrode 4 than when the channel region 5 is off. Therefore, the source region 3 and the drain electrode 4
By detecting the current (cell current) flowing between the floating gate electrode 11 and the floating gate electrode 11, it is possible to determine whether or not electrons are accumulated in the floating gate electrode 11. Thereby, data stored in the memory cell 1 can be read.

In the above read operation, the same read operation can be performed even if the potential relationship between the source voltage Vs and the drain voltage Vd is reversed.

According to the first embodiment, the following operations and effects can be obtained.

(1) The structure of the memory cell 1 is completely different from a conventional stack gate type or split gate type memory cell. Specifically, in the memory cell 1, between the control gate electrode 7 and the floating gate electrode 11, an n-type polysilicon film is interposed between the control gate electrode 7 and the floating gate electrode 11 via an insulating film (the first tunnel insulating film 8 and the second tunnel insulating film 10). Is provided. Then, in the write operation, the intergate 9
By generating a high electric field between the gate electrode 7 and the control gate electrode 7, electrons are moved from the control gate electrode 7 to the intergate 9, and the electrons are further accelerated in the first tunnel insulating film 8 and the intergate 9. It is injected into the floating gate electrode 11.

Therefore, electrons can be efficiently injected from the control gate electrode 7 to the floating gate electrode 11, thereby improving the writing characteristics (according to the experiment conducted by the present inventors, the control gate electrode 7 can make the injection efficiency of electrons into the floating gate electrode 11 10 to 100 times that of the stacked gate type or split gate type of the conventional channel hot electron writing method). As a result, writing can be performed in a shorter time than in the related art, so that the writing operation can be speeded up. Further, since it is possible to realize a low writing voltage, it is possible to contribute to a reduction in power consumption as a semiconductor memory.

(2) The potential of the intergate 9 is equal to or close to that of the drain region 4 in a write operation, and is equal to or close to that of the source region 3 in an erase operation.

Therefore, a circuit for controlling the potential of the inter gate 9 is not required, thereby realizing a reduction in layout area and a reduction in power consumption.

Further, due to the synergistic effect with the above (1),
In the write operation, the operation voltages (source voltage Vs, drain voltage Vd, control gate voltage Vcg) of the memory cell 1 can be kept within a range of ± 3V. Thus, the operating voltage of the memory cell 1 can be reduced to a fraction of the operating voltage of the conventional stacked gate type or split gate type memory cell. As a result, power consumption during a write operation can be reduced.

(3) In the erase operation, the source voltage Vs
By controlling the control gate voltage Vcg, the potential of the intergate 9 can be controlled regardless of the potential of the floating gate electrode 11.

Therefore, a circuit for controlling the potential of the inter gate 9 is not required, and as a result, a reduction in layout area and a reduction in power consumption can be realized. In the erasing operation, the operating voltage of the memory cell 1 can be set to 9 V or less.

(4) The width of the intergate 9 is set so that the mean free path of electrons during the write operation (30 to 40 nm)
Almost all the electrons transmitted through the barrier of the first tunnel insulating film 8 acquire energy exceeding the barrier (= 3.2 eV) of the second tunnel insulating film 10 and become hot electrons because of the following setting. At the same time, the electrons are injected into the floating gate electrode 11 with high probability without remaining in the intergate 9. As a result, high writing efficiency can be obtained.

(5) Since the write operation is automatically completed, a separate circuit for detecting the end of the write operation becomes unnecessary. This makes it possible to simplify the structure of the peripheral circuit, reduce the area, and reduce power consumption. Further, when writing to a plurality of memory cells 1, the write operation is not forcibly terminated after a certain write time has elapsed, regardless of the write level of each memory cell 1.
The writing operation is automatically terminated by the change in the potential of.
Therefore, variation in the write level between the memory cells 1 hardly occurs, and as a result, the write level of each memory cell 1 can be made substantially uniform.

(6) Drain region 4 and floating gate electrode 1
1 is larger than the capacitance between the intergate 9 and the floating gate electrode 11.

Therefore, the potential of the floating gate electrode 11 can be easily controlled by changing the drain voltage Vd.

(7) Since the floating gate electrode 11, the intergate 9, and the control gate electrode 7 are formed on the p-type single crystal silicon substrate 2, the floating gate electrode 11 and the like are formed on the p-type single crystal silicon substrate 2. It is not necessary to form a groove for embedding. As a result, the structure can be simplified as compared with the case where a groove is formed. Further, since it is not necessary to form a groove in the p-type single crystal silicon substrate 2, the control gate electrode 7, the intergate 9, and the floating gate electrode 11
Can be formed by a simple process. Further, since there is no need to form a tunnel insulating film or the like on the side surface of the p-type single crystal silicon substrate 2 damaged by the etching for forming the groove, the film quality of the tunnel insulating film does not deteriorate.

(8) Since the intergate 9 is formed of a single crystal silicon film, the first tunnel insulating film 8 can be formed by oxidizing the single crystal silicon film. Thereby, the first tunnel insulating film 8 having good film quality can be obtained.

Next, a method of manufacturing the memory cell 1 of the first embodiment will be described with reference to FIGS.

Step 1 (see FIG. 3): A silicon oxide film 12 is formed on the p-type single crystal silicon substrate 2 by 8n using a thermal oxidation method.
It is formed with a thickness of about m to 10 nm. Silicon oxide film 1
A doped polysilicon film doped with an n-type impurity such as phosphorus is formed at a deposition temperature of about 620 ° C. with a thickness of about 200 nm on the substrate 2 by LPCVD. further,
A silicon oxide film is deposited on the doped polysilicon film. Then, the silicon oxide film and the doped polysilicon film are patterned by using the photolithography technology and the dry etching technology, so that the floating gate electrode 11 composed of the n-type doped polysilicon film and the silicon oxide film thereon are formed. 21 are formed. Note that the p-type single crystal silicon substrate 2 corresponds to the “first layer” in the present invention, and the floating gate electrode 11 corresponds to the “second gate electrode” in the present invention.

Here, there are the following methods for forming the doped polysilicon film.

Method 1: When a polysilicon film is formed by using the LPCVD method, a gas containing impurities is mixed into a source gas.

Method 2: After forming a non-doped polysilicon film by using the LPCVD method, an impurity diffusion source layer (such as POCl ₃ ) is formed on the polysilicon film, and an impurity is diffused from the impurity diffusion source layer to the polysilicon film. To spread.

Method 3: After forming a non-doped polysilicon film by using the LPCVD method, impurity ions are implanted.

Step 2 (see FIG. 4): A resist film 22 is formed so as to cover the source forming region. The resist film 2
2 is used as a mask, phosphorus ions are implanted into the surface of the p-type single crystal silicon substrate 2 under the conditions of about 50 keV and about 1E15 to form the drain region 4. The drain region 4 is formed so that the area of the overlapping portion with the floating gate electrode 11 is increased.
Is formed so as to extend to about half below. The portion of the silicon oxide film 12 sandwiched between the floating gate electrode 11 and the p-type single crystal silicon substrate 2 constitutes a second gate insulating film 12a, and is sandwiched between the floating gate electrode 11 and the drain region 4. The portion constitutes the third insulating film 12b.
Note that the drain region 4 corresponds to the “second region” of the present invention.

Step 3 (see FIG. 5): After removing the resist film 22, the silicon oxide film 21 on the floating gate electrode 11 is removed.
Is removed. Further, the silicon oxide film 12 other than the second gate insulating film 12a and the third insulating film 12b is removed.
Using a thermal oxidation method, the upper surface and side surfaces of the floating gate electrode 11 and the surface of the p-type
A silicon oxide film having a thickness of about 20 nm is formed. Portions of the silicon oxide film formed on the side surface and the upper surface of the floating gate electrode 11 on the side where the inter gate 9 is formed constitute the second tunnel insulating film 10 and
The portion located between the single-crystal silicon substrate 2 and the portion where the control gate electrode 7 is formed constitutes a first gate insulating film 6. Note that the second tunnel insulating film 10 corresponds to the “second insulating film” in the present invention.

Step 4 (see FIG. 6): An opening 15 is formed by using a lithography technique and a dry etching technique. An amorphous silicon film 9a is deposited on the entire surface at a deposition temperature of about 560 ° C.
It is formed with a thickness of 0 nm. Phosphorus ions are implanted into the amorphous silicon film 9a under the conditions of 3 keV and 1E14.

Step 5 (see FIG. 7): The intergate 9 is formed by patterning the amorphous silicon film 9a. Further, by performing a heat treatment at about 600 ° C. for about 2 hours, the intergate 9 is monocrystallized and the n-type diffusion layer 14 is formed on the p-type single crystal silicon substrate 2. The intergate 9 corresponds to the “third region” or the “semiconductor region” of the present invention.

Thereafter, 3n is formed on the side and upper surfaces of the intergate 9 made of a single crystal silicon film by using a thermal oxidation method.
A first tunnel insulating film 8 having a thickness of about m to 4 nm is formed. Note that the first tunnel insulating film 8 corresponds to the “first insulating film” in the present invention. Further, a doped polysilicon film or a WSi film is deposited so as to cover the entire surface.

Note that the width of the intergate 9 (the distance between the first tunnel insulating film 8 and the second tunnel insulating film 10)
Is 30 nm. The width of the inter gate 9 is suitably 50 nm or less, preferably 30 to 40 nm or less, which is less than the mean free path of the carrier, and most preferably 20 to 30 nm. Intergate 9
When the width is larger than 50 nm, writing efficiency and erasing efficiency tend to decrease. Thereafter, as shown in FIG. 1, the control gate electrode 7 is formed by patterning the doped polysilicon film or the WSi film. Then, after forming a resist film (not shown) so as to cover the drain region 4, an n-type impurity such as phosphorus is ion-implanted into the p-type single crystal silicon substrate 2 using the resist film as a mask, thereby forming a source. Region 3 is formed. Note that the control gate electrode 7 corresponds to the “first gate electrode” in the present invention, and the source region corresponds to the “first region” in the present invention.

Thus, the memory cell 1 is completed.

After that, an interlayer insulating film (not shown) is formed on each memory cell 1. Then, word lines WL _{0 to} WL _n connecting the control gate electrodes 7, bit lines BL _{0 to} BL _n connecting the drain regions 4, and source lines SL commonly connecting the source regions 3 are formed. Thus, the memory cell array 50 is configured.

(Second Embodiment) FIG. 8 is a partial cross-sectional view of a memory cell according to a second embodiment of the present invention, and FIGS. 9 to 23 show the fabrication of the memory cell according to the second embodiment. It is a top view and a sectional view for explaining a method.

First, referring to FIG. 8, in the memory cell 71 of the second embodiment, unlike the first embodiment, an intergate is formed in a self-aligned manner by two sidewall films, and a drain region is formed. A part is formed in a self-aligned manner by the two sidewall films. Other basic structures are almost the same as those of the memory cell 1 of the first embodiment. Hereinafter, a specific description will be given.

First, the memory cell 71 of the second embodiment
Then, as shown in FIG. 8, a p-type single crystal silicon substrate 72 is formed.
Are formed at predetermined intervals so that a channel region 75 is interposed between the source region 73 and the n-type drain region 74. A floating gate electrode 8 made of a doped polysilicon film is formed on the channel region 75 and a part of the drain region 74 via a second gate insulating film 83a and a third insulating film 83b made of a silicon oxide film.
2 are formed. On the side surface of the floating gate electrode 82, an inter gate 81a made of an n-type polysilicon film is formed via a second tunnel insulating film 84a.

The inter gate 81a is composed of a sidewall film 79a made of an n-type polysilicon film and a sidewall film 80a made of an n-type polysilicon film. The bottom of the sidewall film 80a is in contact with the surface of the p-type single crystal silicon substrate 2.

On the drain region 74, a drain region 81b is formed by a sidewall film 79b and a sidewall film 80b made of a polysilicon film. Sidewall film 80b and drain region 7
4 is electrically connected. A third insulating film 84b is formed between the drain region 81b and the floating gate electrode 82. That is, the drain regions 74 and 81b
And a third insulating film 83b between the floating gate electrode 82
And 84b are formed.

On the side surface of the inter gate 81a, a control gate electrode 7 made of an n-type polysilicon film is formed via a first tunnel insulating film 78. The bottom of the control gate electrode 7 is formed on the channel region 75 via a first gate insulating film 76a made of a silicon oxide film.

An interlayer insulating film 91 is formed to cover the whole. A plug electrode 92 is formed in a contact hole provided in the interlayer insulating film 91. On the interlayer insulating film 91, a bit line 93 connected to the plug electrode 92 is formed so as to extend.

Note that the write operation of the second embodiment
The erase operation and the read operation are the same as those in the first embodiment.

In the second embodiment, the following operation and effect can be obtained in addition to the operation and effect of the first embodiment.

(9) By forming the inter gate 81a from the side wall films 79a and 80a formed in a self-aligned manner, the thickness of the side wall films 79a and 80a is reduced by the polysilicon film used for forming them. Each can be controlled by the film thickness. Thus, the width of the inter gate 81a including the sidewall films 79a and 80a can be formed to a fine width equal to or smaller than the minimum critical dimension (minimum exposure dimension) of the mask process.

Further, by controlling the thickness of the polysilicon film, the width of the sidewall films 79a and 80a can be controlled with high precision. Therefore, the width of the inter gate 81a formed of the sidewall films 79a and 80a is also reduced. It can be controlled with high precision. As a result, variations in the width of the intergate 81a can be suppressed.

(10) On the drain region 74, the sidewall films 79b and 8 made of a polysilicon film are formed.
By forming the drain region 81b from 0b, the area of the drain region 81b facing the floating gate electrode 82 can be increased by the drain region 81b. Thus, the capacitance between drain regions 74 and 81b and floating gate electrode 82 can be easily increased. As a result, drain regions 74 and 81
b and the floating gate electrode 82 can be easily made larger than the capacitance between the intergate 81a and the floating gate electrode 82. Therefore, by changing the drain voltage Vd, the floating gate electrode 8
2 can be easily controlled.

(11) In the manufacturing process described later, the side wall films 79b and 80b forming the drain region 81b are formed simultaneously with the side wall films 79a and 80a forming the inter gate 81a. Is provided, the manufacturing process does not become complicated.

Next, a method of manufacturing a memory cell according to the second embodiment will be described with reference to FIGS. Step 6 (see FIG. 9 and FIG. 10): STI (Shallow Trench Isolation)
An element isolation insulating film 85 is formed by using the n) method. This p-type single crystal silicon substrate 72 is the “first
Layer). Note that the element isolation insulating film 85 is
It may be formed using another method such as an OS (Local Oxidation of Silicon) method.

Step 7 (see FIG. 11): A silicon oxide film 83 is formed on the p-type single crystal silicon substrate 72 to a thickness of about 8 nm to 10 nm using a thermal oxidation method. On the silicon oxide film 83, an n-type doped polysilicon film 82 is formed with a thickness of about 150 nm by using the LPCVD method.
Note that the method of forming the doped polysilicon film 82 is the same as that in Step 1.

Step 8 (see FIG. 12): A silicon oxide film 90 is deposited on the doped polysilicon film 82 to a thickness of about 200 nm.

Step 9 (see FIG. 13); silicon oxide film 9
After a resist film 94 is selectively formed on the substrate 0 using photolithography technology, the silicon oxide film 90 and the doped polysilicon film 82 are selectively etched using the resist film 94 as a mask. Thus, the patterned floating gate electrode 82 made of an n-type doped polysilicon film and the silicon oxide film 90 thereon are formed.
To form Note that the floating gate electrode 82 corresponds to the “second gate electrode” of the present invention.

Step 10 (see FIG. 14); resist film 94
Is removed, the silicon oxide film 83 other than under the floating gate electrode 82 is removed by wet etching using hydrofluoric acid. At this time, the side surface of the silicon oxide film 90 located on the floating gate electrode 82 is also slightly removed. After this,
After forming a second tunnel insulating film 84a and a third insulating film 84b made of a silicon oxide film with a thickness of about 10 nm on the side surface of the floating gate electrode 82, a doped polysilicon film 179 is formed to a thickness of about 25 nm by LPCVD. Formed. The method of forming the doped polysilicon film 179 is the same as in the first step. Further, the second tunnel insulating film 84a corresponds to the “second insulating film” of the present invention.

Step 11 (see FIG. 15); RIE (Reacti
ve Ion Etching) doped polysilicon film 1
By etching back the entire surface of the floating gate electrode, a sidewall film 79 made of a doped polysilicon film is formed on the side surface of the floating gate electrode.

Step 12 (see FIG. 16): The silicon oxide film 83 is selectively removed by etching the silicon oxide film 83 using the side wall film 79 as a mask. Thereafter, a non-doped polysilicon film 180 is formed to a thickness of about 25 nm by using the LPCVD method.

Step 13 (see FIG. 17); RIE (Reacti
The entire surface of the non-doped polysilicon film 180 is etched back by using a ve ion etching method to form a sidewall film 80 made of a non-doped polysilicon film on the side surface of the sidewall film 79. In a later heat treatment step, the n-type impurities in the side wall film 79 diffuse into the side wall film 80 to impart conductivity to the side wall film 80. Thereby, the side wall film 7
9 and the sidewall film 80 are integrated.

Here, the reason why the sidewall film 80 is not formed of the doped polysilicon film is as follows.
That is, in the step shown in FIG. 16, when the polysilicon film 180 for forming the sidewall film 80 is formed of a doped polysilicon film, the polysilicon film 18
Since 0 is in contact with the surface of the p-type single crystal silicon substrate 72, there is a disadvantage that impurities in the polysilicon film 180 diffuse into the surface of the p-type single crystal silicon substrate 72. For this reason, in the second embodiment, after the non-doped polysilicon film 180 is formed, the side wall film 80 made of the non-doped polysilicon film is formed, and the side wall film 79 is formed by a heat treatment step. Is diffused into the sidewall film 80 to impart conductivity to the sidewall film 80.

The polysilicon films 179 and 180
Is etched back, the thickness of each of the formed sidewall films 79 and 80 becomes about 60% of the deposited thickness (each 25 nm) of the polysilicon films 179 and 180. Therefore, the thickness of each of the sidewall films 79 and 80 is about 15 nm, which is about 30 nm in total.

Step 14 (see FIGS. 18 and 19): As shown in FIG. 18, a resist film 95 is formed on the silicon oxide film 90 so that the end of the floating gate electrode 82 in the Y direction is exposed. Using the resist film 95 as a mask, the sidewall films 79 and 80 located at the ends of the floating gate electrode 82 in the Y direction are selectively removed. Thereby, as shown in FIG. 19, in the cross section in the X direction, the inter-gate 81a including the sidewall film 79a and the sidewall film 80a and the drain region 81b including the sidewall film 79b and the sidewall film 80b are electrically connected. Is separated into As a result, an electrically separated inter-gate 81a and a drain region 81b are simultaneously formed. Thereafter, a silicon oxide film 76 serving as a first gate insulating film is formed on the surface of the p-type single crystal silicon substrate 72.

The inter gate 81a corresponds to the "third region", "semiconductor region" or "first side wall film" of the present invention. The sidewall films 79a and 80a correspond to the “second sidewall film” and the “third sidewall film” in the present invention, respectively. Further, the drain region 81b corresponds to the “second region” or the “fourth sidewall film” in the present invention. Furthermore, the sidewall films 79b and 80b correspond to the “fifth sidewall film” and the “sixth sidewall film” in the present invention, respectively.

Step 15 (see FIG. 20); resist film 95
Is removed, a resist film 9 is formed so as to cover the source region side.
6 is formed. By using the resist film 96 as a mask, for example, As ions are implanted into the surface of the p-type single crystal silicon substrate 72 under the conditions of about 40 keV and 5E15 / cm ² to form the n-type drain region 74. The drain region 74 is formed so that the area of the overlapping portion with the floating gate electrode 82 is increased.
2 and extend to about half below.

The portion of the silicon oxide film 83 sandwiched between the floating gate electrode 82 and the p-type single crystal silicon substrate 72 constitutes a second gate insulating film 83a, and is formed between the floating gate electrode 82 and the drain region 74. The portion sandwiched forms the third insulating film 83b. Note that the drain region 74 corresponds to the “second region” of the present invention. Also, the third insulating film 83b
Is used together with the third insulating film 84b as an insulating film between the drain regions 74 and 81b and the floating gate electrode 82.

Step 16 (see FIG. 21); resist film 96
Is removed, a silicon oxide film is formed with a thickness of about 3 nm to 4 nm. Portions of the silicon oxide film formed on the side surfaces of the side wall film 79a and the side wall film 80a constitute a first tunnel insulating film 78. Note that the first tunnel insulating film 78 constitutes the “first insulating film” of the present invention. Thereafter, a doped polysilicon film 177 is formed on the entire surface. The method for forming the doped polysilicon film 177 is the same as that in Step 1. For example, after depositing a non-doped polysilicon film, 4 ions of phosphorus ions are deposited on the non-doped polysilicon film.
A doped polysilicon film 177 is formed by implanting about E15 / cm ² to impart conductivity.

Step 17 (see FIG. 22): After forming a resist film 97 on a predetermined region of the doped polysilicon film 177, control is performed by etching the doped polysilicon film 177 using the resist film 97 as a mask. A gate electrode 77 is formed. This control gate electrode 77
On a p-type single crystal silicon substrate 72, a first gate insulating film 7
6a. The control gate electrode 7
7 corresponds to the “first gate electrode” of the present invention.

Step 18 (see FIG. 23); resist film 97
After the removal, a resist 98 is formed so as to cover the drain region 74. Using the resist film 98 and the control gate electrode 77 as a mask, the p-type single crystal silicon substrate 72
Then, an n-type source region 73 is formed by ion-implanting an n-type impurity. Note that the source region 73
This corresponds to the “first region” of the present invention. After that, the resist film 98 is removed.

Thereafter, as shown in FIG. 8, after forming an interlayer insulating film 91, a bit line 93 (BL _{0 to} BL _n ) connecting each drain region 74 via a plug electrode 92 is formed.

Thus, the memory cell 1 is completed.

It should be noted that the embodiment disclosed this time is an example in all respects and is not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description of the embodiments, and includes all modifications within the scope and meaning equivalent to the terms of the claims.

For example, each of the above embodiments may be changed as follows, and even in such a case, the same operation and effect as those of the above embodiments can be obtained.

(I) P-type single crystal silicon substrate 2 (7
The conductivity type of 2) is n-type, and n-type source region 3 (73), n
The conductivity type of the drain region 4 (74, 81b) and the intergate 9 (81a) is set to p-type. This allows
Even if the potential difference between the control gate electrode 7 (77) and the control gate electrode 7 (77) is further reduced, electrons can be transferred from the control gate electrode 7 (77), and as a result, a further lower voltage can be realized.

(Ii) In the erase operation, after the drain voltage Vd is set to 0 V, the drain region 4 (74) (bit line) is kept open.

As described above, at the beginning of the erasing operation, the second tunnel insulating film 10 (84a) located between the floating gate electrode 11 (82) and the intergate 9 (81a)
Since an electric field of about 10 MV is applied, erasing is continuously performed (electrons are extracted to the inter gate 9 (81a)). Then, as the erase operation proceeds, electrons are continuously extracted from the floating gate electrode 11 (82), so that the potential of the floating gate electrode 11 (82) gradually increases. Then, when the potential of the floating gate electrode 11 (82) exceeds the threshold voltage Vt, the floating gate electrode 11 (8)
The channel region 5 (75) under 2) is turned on.

As a result, electrons are also extracted from the drain region 4 (74), so that the potential of the drain region 4 (74) also increases. Then, the potential difference between the floating gate electrode 11 (82) and the intergate 9 (81a) decreases. As a result, the floating gate electrode 11
The electrons in (82) are changed to the second tunnel insulating film 10 (84a).
Cannot be transmitted through this barrier, and no further erasing operation is performed.

That is, since the erasing operation is automatically terminated, a separate circuit for detecting the ending of the erasing operation is not required. Therefore, the structure of the peripheral circuit can be simplified, the area can be reduced, and the power consumption can be reduced. Can be realized. Further, the erase level of each memory cell becomes substantially uniform.

(Iii) In the erase operation, after the drain voltage Vd is set to 0 V, the drain region 4 (74) (bit line) is connected to the sense amplifier group 61. The above (ii)
As described above, when the erase operation proceeds, the drain region 4
Since potential rises (74) detects that the potential of the bit line BL _n is changed more than a predetermined value in the sense amplifier group 61, judges an end of the erase operation.

(Iv) In the above (iii), when the erasing operation is performed in word line units, it is determined that the erasing operation is completed when a potential change of a plurality of bit lines is detected. That is, the memory cells connected to one word line are:
The timing at which erasing ends depends on variations in the characteristics. Therefore, taking into account the variation in this point, 1
The potential change of not only the bit lines but also a plurality of bit lines is checked.

(V) In the erase operation of the first embodiment,
The operating voltage of the memory cell is set to source voltage Vs: 6V, drain voltage Vd: -3V, control gate voltage Vcg: 6V, and substrate voltage (well voltage) Vsub: -3V.

As described above, by setting the substrate (well) to the negative potential, the source voltage Vs and the control gate voltage Vcg for the erasing operation can be set lower.

In recent years, the power supply voltage has been reduced in order to reduce the power consumption of electronic equipment, and the power supply voltage of a semiconductor integrated circuit is generally 3.3 V or less. In the first and second embodiments, the scale of the booster circuit for generating the erasing operation voltage of the memory cell can be reduced even for such a low voltage.

(Vi) In each of the above embodiments, electrons are injected into the floating gate electrode 11 (82) in the writing operation, and electrons are extracted from the floating gate electrode 11 (82) in the erasing operation. May be set in the opposite relationship. That is, a state where electrons are accumulated in the floating gate electrode 11 (82) is defined as an erased state of the memory cell, and a state where electrons are not accumulated in the floating gate electrode 11 (82) is defined as a written state of the memory cell. May be.

(Vii) In the second embodiment, a structure in which the control gate electrode 77 runs over the floating gate electrode 82 may be employed. Specifically, as shown in FIG. 24, a structure may be employed in which the control gate electrode 77a overlaps above the floating gate electrode 82.

[0157]

According to the present invention, since hot electrons can be efficiently injected from the first gate electrode to the second gate electrode, the writing or erasing characteristics can be improved. Thus, the speed of the writing or erasing operation can be increased. Further, it is possible to realize a lower writing or erasing voltage, which can contribute to a reduction in power consumption as a semiconductor memory. As a result, it is possible to provide a semiconductor memory which operates as a nonvolatile semiconductor memory capable of achieving a long life, low voltage, high-speed operation, low power consumption, and high integration.

By forming the first gate electrode, the second gate electrode, and the third region on the first layer, the first gate electrode, the second gate electrode, and the third region are formed.
It is not necessary to form a groove for burying the gate electrode, the second gate electrode, and the third region in the first layer. Therefore, the structure and the manufacturing process can be simplified as compared with the case where the groove is formed.

[Brief description of the drawings]

FIG. 1 is a partial sectional view of a memory cell according to a first embodiment of the present invention;

FIG. 2 is a block circuit diagram of a semiconductor memory according to a first embodiment of the present invention;

FIG. 3 is a process sectional view illustrating the method for manufacturing the memory cell according to the first embodiment.

FIG. 4 is a process cross-sectional view for explaining the method for manufacturing the memory cell of the first embodiment.

FIG. 5 is a process sectional view illustrating the method for manufacturing the memory cell of the first embodiment.

FIG. 6 is a process sectional view illustrating the method for manufacturing the memory cell of the first embodiment.

FIG. 7 is a process sectional view for describing the method for manufacturing the memory cell of the first embodiment.

FIG. 8 is a partial cross-sectional view of a memory cell according to a second embodiment of the present invention;

FIG. 9 is a process sectional view in the X direction for describing the method for manufacturing the memory cell of the second embodiment.

FIG. 10 is a process sectional view in the Y direction in the process shown in FIG. 9;

FIG. 11 is a process sectional view in the X direction for describing the method for manufacturing the memory cell of the second embodiment.

FIG. 12 is a process sectional view in the X direction for describing the method for manufacturing the memory cell of the second embodiment.

FIG. 13 is a process sectional view in the X direction for describing the method for manufacturing the memory cell of the second embodiment.

FIG. 14 is a process sectional view in the X direction for describing the method for manufacturing the memory cell of the second embodiment.

FIG. 15 is a process sectional view in the X direction for describing the method for manufacturing the memory cell of the second embodiment.

FIG. 16 is a process sectional view in the X direction for describing the method for manufacturing the memory cell of the second embodiment.

FIG. 17 is a process sectional view in the X direction for describing the method for manufacturing the memory cell of the second embodiment.

FIG. 18 is a process sectional view in the Y direction for describing the method for manufacturing the memory cell of the second embodiment.

FIG. 19 is a process sectional view in the X direction in the process shown in FIG. 18;

FIG. 20 is a process sectional view in the X direction for describing the method for manufacturing the memory cell of the second embodiment.

FIG. 21 is a process sectional view in the X direction for describing the method for manufacturing the memory cell of the second embodiment.

FIG. 22 is a process sectional view in the X direction for describing the method for manufacturing the memory cell of the second embodiment.

FIG. 23 is a process sectional view in the X direction for describing the method for manufacturing the memory cell of the second embodiment.

FIG. 24 is a partial cross-sectional view showing a modification of the memory cell of the second embodiment.

[Explanation of symbols]

1, 71 memory cell 2, 72 p-type single crystal silicon substrate (first layer) 3, 73 source region (first region) 4, 74 drain region (second region) 5, 75 channel region 6, 76a first gate Insulating film 7, 77 Control gate electrode (first gate electrode) 8, 78 First tunnel insulating film (first insulating film) 9 Intergate (third region) 10, 84a Second tunnel insulating film (second insulating film) 11, 82 Floating gate electrode (second gate electrode) 12b, 83b, 84b Third insulating film 12a, 83a Second gate insulating film 79a Side wall film (second side wall film; third region) 80a Side wall film (second 81a Intergate (first sidewall film; third region)
Region) 79b sidewall film (fifth sidewall film; second region) 80b sidewall film (sixth sidewall film; second region) 81b drain region (fourth sidewall film; second region)

 ────────────────────────────────────────────────── ─── Continued from the front page (72) Inventor Hideaki Fujiwara 2-5-5 Keihanhondori, Moriguchi-shi, Osaka Sanyo Electric Co., Ltd. F-term (reference) 5F001 AA21 AB03 AB09 AC01 AD51 AD52 AE02 AE03 AE08 AF07 AG02 AG10 AG12 AG30 5F083 EP14 EP26 EP30 EP61 ER03 ER07 ER08 ER14 ER18 ER22 GA01 GA05 GA09 GA17 GA21 JA35 JA39 PR21 PR29 PR36

Claims (20)

[Claims] A first gate electrode, a second gate electrode,
A first insulating film formed on a surface of the semiconductor region, a first insulating film formed on one surface of the semiconductor region, and a second insulating film formed on the other surface of the semiconductor region; A semiconductor memory, wherein carriers are injected into the second gate electrode via the semiconductor region and the second insulating film. 2. The semiconductor memory according to claim 1, wherein said semiconductor region includes a second conductivity type semiconductor film formed on a first layer made of a first conductivity type semiconductor. 3. A method according to claim 1, wherein the first region and the second region of the second conductivity type are formed in a first layer made of a semiconductor of the first conductivity type, and the first region and the second region of the first layer. A first gate electrode and a second gate electrode formed between the first gate electrode and the second gate electrode, and a second conductive type of a conductive film formed between the first gate electrode and the second gate electrode in the first layer. Three regions, a first insulating film formed between the first gate electrode and the third region, and a second insulating film formed between the second gate electrode and the third region. Equipped, semiconductor memory. 4. The first gate electrode is formed on the first layer via a first gate insulating film, and the second gate electrode is formed on the first layer by a second gate insulating film. The semiconductor memory according to claim 3, wherein the semiconductor memory is formed via a via. 5. The capacitance between the second region and the second gate electrode is set to be larger than the capacitance between the third region and the second gate electrode. The voltage applied to the region is transmitted to the second gate electrode by electrostatic coupling between the second region and the second gate electrode, whereby the second region is connected via the first layer. The semiconductor memory according to claim 3, wherein a potential of the third region connected to the third region is substantially equal to a potential of the second region. 6. The width of the third region is set so that carriers transmitted through the barrier of the first insulating film between the first gate electrode and the third region exceed the barrier of the second insulating film. The semiconductor memory according to any one of claims 3 to 5, wherein the semiconductor memory is set to be substantially equal to or less than a mean free path when having necessary energy. 7. The first gate electrode and the second gate electrode are formed on a main surface of the first layer, and a third region made of the conductive film is formed on a main surface of the first layer. The semiconductor memory according to claim 3, wherein the semiconductor memory is formed between the first gate electrode and the second gate electrode. 8. At least a portion of the third region is formed on an upper surface of the second gate electrode, and at least a portion of the first gate electrode is formed on an upper surface of the third region. The semiconductor memory according to claim 7, wherein: 9. The semiconductor memory according to claim 3, wherein said third region includes a single crystal silicon film. 10. The semiconductor memory according to claim 3, wherein said third region includes a first sidewall film made of a first conductive film formed in a self-aligned manner. 11. The first sidewall film includes a second sidewall film made of a second conductive film formed on a side wall of the second gate electrode with the second insulating film interposed therebetween, and the second sidewall film includes: The semiconductor memory according to claim 10, further comprising: a third sidewall film made of a third conductive film formed so as to contact a side surface of the wall film and a surface of the first layer. 12. The second side wall film is formed by depositing a second conductive film on a side surface of the second gate electrode via the second insulating film and then etching back the second conductive film. The wall film is formed by depositing a third conductive film so as to cover the first layer and the second sidewall film and then performing etch-back, thereby forming a side surface of the second sidewall film and a surface of the first layer. The semiconductor memory according to claim 11, wherein the semiconductor memory is formed so as to be in contact with the semiconductor memory. 13. The second region includes a fourth sidewall film made of a fourth conductive film formed in a self-aligned manner on a side surface of the second gate electrode via a third insulating film. The semiconductor memory according to any one of items 3 to 12. 14. The fifth sidewall film, comprising: a fifth sidewall film made of a fifth conductive film formed on a side wall of the second gate electrode via the third insulating film; The semiconductor memory according to claim 13, further comprising: a sixth sidewall film made of a sixth conductive film formed so as to contact a side surface of the wall film and a surface of the first layer. 15. The semiconductor memory according to claim 13, wherein said fourth sidewall film is formed simultaneously with said first sidewall film. 16. The first and second regions of a second conductivity type formed in a first layer made of a semiconductor of a first conductivity type, and the first region and the second region of the first layer. A first gate electrode formed on the first layer with a first gate insulating film interposed therebetween, and the first layer between the first region and the second region in the first layer. On the other hand, a second conductivity type including a second gate electrode formed via a second gate insulating film, and a conductive film formed between the first gate electrode and the second gate electrode in the first layer. A third region, a first insulating film formed between the first gate electrode and the third region, and a second insulating film formed between the second gate electrode and the third region. A method of operating a semiconductor memory, comprising: An edge film, the third region, and the second insulating film to the second gate electrode;
A method of operating a semiconductor memory in which data is written by injecting hot carriers. 17. The method of operating a semiconductor memory according to claim 16, wherein data is erased by extracting hot carriers from said second gate electrode to said third region via said second insulating film. 18. A capacitance between the second region and the second gate electrode is set to be larger than a capacitance between the third region and the second gate electrode. The voltage applied to the region is transmitted to the second gate electrode by electrostatic coupling between the second region and the second gate electrode, whereby the second region is connected via the first layer. The potential of the third region connected to the second region is substantially equal to the potential of the second region.
3. The method of operating a semiconductor memory according to claim 1. 19. The width of the third region is set so that carriers transmitted through the barrier of the first insulating film between the first gate electrode and the third region exceed the barrier of the second insulating film. 19. The method of operating a semiconductor memory according to claim 16, wherein the semiconductor memory is set to be substantially equal to or less than a mean free path when having necessary energy. 20. When erasing data, after the voltage of the second region coupled to the second gate electrode is once set to a predetermined value, the second region is held in an open state. An operation method of the semiconductor memory according to claim 18.