JPH06163916A - Non-volatile semiconductor memory and fabrication thereof - Google Patents

Abstract

PURPOSE:To provide a flash memory in which current leak from a nonselected cell is prevented. CONSTITUTION:Silicon oxide layer is deposited on the surface of a substrate and a laminate of a floating gate 112, an interlayer dielectric film 13, and a control electrode 5 is formed thereon. The silicon oxide is then etched back isotropically followed by oxidation of the surface of substrate and the surface of the laminate 114. Consequently, silicon oxide 8 on the surface of substrate can be formed thicker than the silicon oxide layer. This method allows formation of a tunneling oxide film 7 which is thicker in the vicinity of a drain 3 as compared with the part underneath the floating gate 112.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor nonvolatile memory device, and more particularly to stabilization of its reading.

[0002]

^2. Description of the Related Art Today, a flash type E ² PROM (hereinafter referred to as a flash memory) is known as a rewritable nonvolatile memory. A part of the equivalent circuit of the flash memory is shown in FIG. 6A. When reading the cell C11 as the selected cell, the sense voltage of 5 V is applied to the word line WLn + 1, the read voltage of 2 V is applied to the bit line BLn, and 0 V is applied to the others, and the sense amplifier is connected to the bit line BL.

If the cell C12 is in a writing state as shown in FIG. 3B, the hot electron flowing into the floating gate 112 causes the channel forming region 1 to be formed.
The threshold voltage for forming a channel in 16 rises, said threshold voltage becoming higher than 5V. Therefore, even if the sense voltage 5V is applied to the control gate electrode 5,
No channel is formed in the channel forming region 116, and no current flows between the drain 3 and the source 4.

On the other hand, if the cell C12 is in the non-writing state as shown in FIG.
The threshold voltage at which a channel is formed is lowered and becomes lower than 5V. Therefore, by applying the sense voltage 5V to the control gate electrode 5, a channel is formed in the channel formation region 116, and the drain 3 and the source 4 are formed.
An electric current flows between them. This is read by the sense amplifier connected to the bit line BLn. In this way, it is possible to determine whether the selected cell C12 is in the written state or the non-written state.

As for the non-selected cells C11 and C13, since 0 V is applied to the word lines WLn and WLn + 2, the sense voltage is not applied to the control gate electrode 5 even in the written state, so that the drain is drained. No current flows between 3 and source 4.

[0006]

However, the above flash memory has the following problems.

Since the read voltage is applied to the drain 3, a capacitance C4 is parasitically generated between the drain 3 and the floating gate 112 as shown in FIG. 7A. The equivalent circuit in this state is shown in FIG. in this case,
Control gate electrode 5 and floating gate 11
The capacitance between the two is the capacitance C1, the capacitance between the floating gate 112 and the source 4 is the capacitance C2, the floating gate 1
Assuming that the capacitance between the P-well 12 and the P well 2 is C3, the capacitance between the floating gate 112 and the drain 3 is C4, and the potential of the floating gate 112 is Vfg, the potential Vfg is expressed by the following equation.

Vfg = 2.multidot.C4 / C1 + C2 + C3 + C4 As described above, the potential Vfg of the floating gate 112, which is supposed to be 0V in the non-selected cell, is
It rises according to the parasitically generated capacitance C4. Due to this potential increase, a channel is formed in the channel formation region 116 of the non-selected cell, current leaks, and erroneous information is read.

An object of the present invention is to solve the above problems and to provide a semiconductor nonvolatile memory device capable of preventing erroneous reading.

[0010]

According to a first aspect of the semiconductor nonvolatile memory device of the present invention, at least the thickness of the first insulating film in the vicinity of the second region is larger than that of the lower portion of the floating electrode.

According to a second aspect of the present invention, there is provided a method of manufacturing a semiconductor nonvolatile memory device, comprising: A) a step of forming a first insulating film on the surface of a semiconductor substrate; B1) floating type electrode that stores electric charge; b2) second insulating film provided on the floating type electrode; b3) control provided on the second insulating film. Electrode, C) a step of isotropically etching the first insulating film, D) a step of forming a third insulating film on the surface of the semiconductor substrate and the surface of the stacked layer, E) using the stacked layer as a mask, And a step of forming a first region and a second region in the semiconductor substrate.

[0012]

The semiconductor nonvolatile memory device according to claim 1 is
At least the thickness of the first insulating film in the vicinity of the second region is thicker than that of the lower portion of the floating electrode. Here, the capacitance between the second region and the lower portion of the floating electrode is inversely proportional to the thickness of the insulating film. Therefore, it is possible to prevent the potential of the floating electrode from rising.

In a method of manufacturing a semiconductor nonvolatile memory device according to a second aspect of the present invention, after the first insulating film is isotropically etched, a third insulating film is formed on the surface of the semiconductor substrate and the surface of the stack. . Therefore, the thickness of the first insulating film in the vicinity of the second region can be made thicker than that under the floating electrode. This can reduce the parasitic capacitance between the second region and the lower portion of the floating electrode.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to the drawings. As shown in FIG. 1, in a flash memory 41, a source 4 as a first region and a drain 3 as a second region are formed in a P well 2. Both the drain 3 and the source 4 are n ⁺ layers. A channel forming region 116 is between the drain 3 and the source 4.

The channel forming region 116 is covered with the tunnel oxide film 7 which is the first insulating film. Tunnel oxide film 7
A laminated layer 114 having the following three layers is formed on the above. The bottom layer of the stack 114 is the floating gate 112, which is a floating electrode. The layer above the floating gate 112 is the interlayer insulating film 13. The layer above the interlayer insulating film 13 is the control gate electrode 5 which is a control electrode. The interlayer insulating film 13 has a three-layer structure (silicon oxide layer, silicon nitride layer, silicon oxide layer).

The stack 114 and the substrate surface are covered with an insulating film (SiO ₂ ) 8 which is a third insulating film.

The thickness of the tunnel oxide film 7 is not constant, and the tunnel oxide film 7 near the drain 3 is formed.
Is thicker than that under the floating gate 112.

[Manufacturing Method] Next, a manufacturing method of the flash memory 41 will be described with reference to FIG. First, in order to perform element isolation, a field oxide layer is formed by the LOCOS method, and a tunnel oxide film (SiO ₂ ) is formed on the entire surface by dilute oxidation. Further thereon, a three-layer stack 114 including the floating gate 112, the interlayer insulating film 13 and the control electrode 5 is formed (A in the same figure).

In this embodiment, the floating gate 112 is made of polysilicon and the control electrode 5 is made of polycide. Further, the interlayer insulating film 13 is
A silicon oxide film was formed by dilute oxidation, a silicon nitride film was formed thereon by a low pressure CVD method, and a silicon oxide film was formed thereon by wet oxidation.

From this state, the silicon oxide layer 71 is etched back by isotropic etching. By such etching, the silicon oxide layer 71 is formed into an undercut shape as shown in FIG.

Next, as shown in FIG. 6C, the surface of the substrate and the surface of the laminated layer 114 are oxidized. In this case, since the silicon oxide layer 71 is covered with the floating gate 112, it is hardly oxidized. Therefore, the thickness of the silicon oxide film 8 on the surface of the substrate is set to the silicon oxide layer 7
It can be formed thicker than 1. At that time, as shown in FIG. 6C, the silicon oxide film 8 has a shape that is etched by the gate bird's beak. In this way, thick film portions 72 and 73 are formed on both ends of the thin silicon oxide layer 71. The silicon oxide layer 71 and the thick film portions 72 and 73 form the tunnel oxide film 7.

Next, as shown in FIG. 6D, impurities are ion-implanted by using the stack 114 and the silicon oxide film 8 on the sidewall of the stack 114 as a mask to form an n ⁺ layer. afterwards,
By the annealing, the implanted impurities diffuse into the lower portions of the insulating sidewalls 11 and 12, and the source 4 and the drain 3
Are formed (Fig. 1).

Next, after depositing polycide on the entire surface, patterning is performed to form a source electrode, and an interlayer film (silicon oxide film) is formed by a CVD method (not shown). Then, an opening for exposing the drain 3 region is formed, AL-Si is deposited and patterned on the entire surface to form a bit line (drain line) (not shown). Finally, a passivation film (not shown) is formed and completed.

[How to use] The flash memory 41 is connected in a matrix and used. Equivalent circuit 15 of matrix circuit in which a plurality of flash memories 41 are combined
Is shown in FIG. 3A. Here, when they are combined in a matrix as shown in the figure, the control gate electrodes and the drains are connected in the row direction and the column direction, and further, all the sources are connected. Therefore, there is a possibility that data may be written in or read from the non-selected cells. Therefore, in the equivalent circuit 15, the selected cell and the non-selected cell can be surely distinguished from each other as described below.

FIG. 9B shows an example of the voltage applied at the time of writing, erasing and reading when the cell C11 is the selected cell.

First, when writing, the word line WL
2 is applied to 12V, bit line BL1 is applied to 6V, and others are applied to 0V.

Returning to FIG. A, a potential higher than the potential of the P well 2 by 12 V is applied to the control gate electrode 5 of the selected cell C11. By applying such a voltage, the hot electrons generated in the vicinity of the drain 3 jump over the potential barrier of the silicon oxide film 7 and flow into the floating gate 112. As a result, the threshold value of the control gate voltage required to form a channel in the channel forming region 116 rises. This state is a state in which the information "1" is written in the flash memory cell 1.

With respect to the non-selected cells C10 and C12, since 0 V is applied to the control gate electrode 5, no channel is formed in the channel forming region 116,
Information "1" is never written. Further, in the non-selected cells C10 and C12, 0V is applied to the control gate electrode 5, but 0V is applied to the bit line BL2.
Since "1" is applied, the information "1" is never written.

On the other hand, when the information "0" is stored (erased) in the cell C11, the electrons flowing into the floating gate 112 may be returned to the drain 3. In the flash memory, cells connected to the same source line S as the cell C11 are collectively erased. In particular,
As shown in FIG. 9B, 12V is opened to the source line S, the bit lines BL1 and BL2 are opened, and 0V is applied to the others. As a result, an electric field in the opposite direction to that at the time of writing is generated, and electrons are pulled back to the drain 3 by FN (Fowler-Nordheim) tunneling.

By pulling back the electrons in this way,
The threshold value of the control gate voltage required to form a channel in the channel formation region 116 drops. As a result, the selected cell C11 enters a state where the information "0" is stored (erased state).

Next, the read operation of the flash memory 41 will be described. When the cell C11 is selected, the word line WL2 is 5V, the bit line BL1 is 5V.
2V is applied to and a sense amplifier is connected. Further, the bit line BL2 is opened, and 0V is applied to the others.

Looking at the selected cell C11, if the cell C11 is in the written state, the channel is not formed in the channel forming region 116 as described above, and the drain 3
Current does not flow between the source and the source 4. On the other hand, in the non-written state, a channel is formed in the channel formation region 116, and a current flows between the drain 3 and the source 4, which can be read by the sense amplifier connected to the bit line BL1.

Looking at the non-selected cells C10 and C12, 2V is applied to the drain 3 because 2V is applied to the bit line BL1. But,
In the flash memory 41, as shown in FIG.
The film thickness of the tunnel oxide film 7 near the drain is larger than the film thickness under the floating gate 112. Here, the capacitance between the drain 3 and the floating gate 112 is inversely proportional to the film thickness of the oxide film between the drain 3 and the floating gate 112. Therefore, it is possible to reduce the capacitance and prevent an increase in the potential of the floating gate 112 of the non-selected cell. This prevents erroneous reading due to leakage of current.

[Other Embodiments] FIG. 4 shows a flash memory 1 according to another embodiment. The difference between the flash memory 1 and the flash memory 41 is that the film thickness of the tunnel oxide film 7 is constant and the insulating sidewalls 11 and 12 which are insulating sidewalls are provided on the sidewalls of the stack 114. . The other structure is the same, and the description is omitted.

Next, a method of manufacturing the flash memory 1 will be described with reference to FIG. Silicon oxide layer 7 on the substrate surface
1 is formed on the floating gate 112,
The process is the same as that of the flash memory 41 until the three-layer stack 114 including the interlayer insulating film 13 and the control electrode 5 is formed (see FIG. A).

Thereafter, as shown in FIG. 3B, a silicon oxide film 18 is deposited by the CVD method to have a thickness of 10 μm. From this state, by anisotropic etching using reactive ion etching (RIE),
Etching back is performed so that the insulating sidewalls 11 and 12 remain as shown in FIG.

The etch back may be finished after the etching reaches the surface of the substrate. Even if the etch back proceeds deeply, the anisotropic etching proceeds only in the vertical direction. Therefore, even if the etch back proceeds deeply, the width D of the insulating sidewalls 11 and 12 has almost no influence. Because I do not receive it.

Next, as shown in FIG. 4D, the stack 114 and the insulating sidewalls 11 and 12 are used as masks.
Impurities are ion-implanted to form an n ⁺ layer. After that, the impurities that have been implanted are annealed so that the implanted sidewalls 1
Sources 4 and drains 3 are formed by diffusing under 1 and 12 (FIG. 4).

After that, the source electrode, the interlayer film, the bit line (drain line), and the passivation film (not shown) are formed in the same manner as the flash memory 41.

In this way, the insulating sidewalls 11 and 12 are provided adjacent to the laminated layer 114, and the ion implantation is performed using the laminated layer 114 and the insulating sidewalls 11 and 12 as a mask.
No ions are implanted into the lower part of 12. That is, the insulating sidewalls 11 and 12 function as an impurity injection preventing film. Therefore, even if the implanted impurities are diffused by the subsequent annealing, the drain 3 and the source 4 do not expand to the lower portion of the floating gate 112.

Insulating side walls 11 and 12
Is formed by anisotropically etching the silicon oxide film 18, so that the insulating sidewalls 11 and 12 are formed.
Width D is determined by the thickness of the silicon oxide film 18. As described above, the silicon oxide film 18 is formed by CVD.
Since it is formed by the method, its thickness can be precisely controlled. Therefore, the width D of the insulating sidewalls 11 and 12 can be precisely controlled.

On the other hand, the region in which the impurities diffuse can be precisely controlled by performing the annealing. Therefore, the positional relationship between the n ⁺ layer of the drain 3 and the floating gate 112 can be precisely controlled. As a result, the capacitance generated between the drain 3 and the floating gate 112 can be reduced. This is because the capacitance is proportional to the area between the drain 3 and the floating gate 112.

Further, in this embodiment, the insulating sidewalls 11 and 12 are formed by using the CVD method.
Therefore, a thick silicon oxide film can be formed on the side surface of the stack 113.

The method of using the matrix circuit in which a plurality of flash memories 1 are combined is the same as that shown in FIG.

[Other applications] The flash memory 4
In No. 1, the silicon oxide layer 71 is isotropically etched before the surface of the substrate and the surface of the laminated layer 114 are oxidized. However, the isotropic etching of the silicon oxide layer 71 may be omitted. Even in this case, by oxidizing the surface of the stacked layer 114 before the ion implantation, the silicon oxide film 8 on the side surface of the stacked layer 114 is subjected to the ion implantation.
Function as an impurity injection preventing film. Therefore, the overlap amount W (see FIG. 7) between the drain 3 and the floating gate 112 can be reduced. In this case, the silicon oxide film 8 needs to have a film thickness that functions as a mask.

In addition, the tunnel oxide film 7 near the drain 3
Is thicker than the floating gate 112, and the insulating sidewall 1 is formed on the side wall of the stack 114.
It may be configured as a flash memory in which 1 and 12 are provided. With such a configuration, it is possible to more reliably prevent the current from leaking from the non-selected cell, and
Stable operation becomes possible.

In each of the above embodiments, the source 4
The vicinity also has the same structure as the vicinity of the drain 3. However, the structure near the source 4 may be similar to the conventional structure without necessarily having such a configuration. This is because even with such a configuration, only 0 V is applied to the source 4 of the non-selected cell, so that leakage of current from the non-selected cell does not occur.

In the present embodiment, the tunnel oxide film 7 has a three-layer structure (a silicon oxide layer 6a, a silicon nitride layer).
6b, silicon oxide layer 6c) is used, but a two-layer structure (silicon oxide layer 6a, silicon nitride layer 6b) may be used.

In the flash memory 1, the silicon oxide film 18 is deposited and then etched to leave the insulating sidewalls 11 and 12. However, the unnecessary portion may be removed by covering with a resist.

[0050]

According to the first aspect of the present invention, the semiconductor nonvolatile memory device is characterized in that the thickness of at least the first insulating film in the vicinity of the second region is made thicker than the lower portion of the floating electrode. Therefore, the potential rise of the floating electrode can be prevented, and the current does not leak from the non-selected cells. That is, it is possible to provide a semiconductor nonvolatile memory device capable of preventing erroneous reading.

In the method of manufacturing a semiconductor nonvolatile memory device according to a second aspect, after the first insulating film is isotropically etched, the first region and the second region are formed in the semiconductor substrate using the stack as a mask. Form. Therefore, the thickness of the first insulating film in the vicinity of the second region can be made thicker than the lower portion of the floating electrode, and the current does not leak from the non-selected cells. That is, it is possible to provide a semiconductor nonvolatile memory device capable of preventing erroneous reading.

[Brief description of drawings]

FIG. 1 is a diagram showing a flash memory 41.

FIG. 2 is a diagram showing a manufacturing process of a flash memory 41.

FIG. 3 is a diagram in which flash memories 41 are combined in a matrix. A is an equivalent circuit diagram combined in a matrix, and B is an example showing voltages in each operation.

FIG. 4 is a diagram showing a flash memory 1 according to another embodiment.

FIG. 5 is a diagram showing a manufacturing process of the flash memory 1.

FIG. 6 is a diagram showing a structure of a conventional flash memory. A is a diagram in which flash memories are combined in a matrix, and B and C are diagrams showing a selected cell C12.

FIG. 7 is a diagram showing a state in which a capacity is generated in a conventional flash memory. A is an enlarged view of the vicinity of the drain 3, and B is a view showing an equivalent circuit.

[Explanation of reference numerals] 3 ... Drain 4 ... Source 5 ... Control gate electrode 7 ... Tunnel oxide film 11, 12 ... Insulating sidewall 13 ... Interlayer insulating film 112 ... Floating gate 116 ... Channel formation region

Claims (2)

[Claims] 1. A first region, a second region provided so as to form an electric path formable region between the first region, a first insulating film covering the electric path formable region, and a first insulating film on the first insulating film. A semiconductor non-volatile memory device provided with a floating electrode for storing electric charge, a second insulating film provided on the floating electrode, and a control electrode provided on the second insulating film; A semiconductor nonvolatile memory device, wherein the thickness of the first insulating film in the vicinity of the second region is made thicker than the lower portion of the floating electrode. 2. A) a step of forming a first insulating film on the surface of a semiconductor substrate, B) a step of forming a laminate having the following three layers on a part of the first insulating film, b1) Floating type electrode for storing electric charge, b2) second insulating film provided on the floating type electrode, b3) control electrode provided on the second insulating film, C) the first insulating film, etc. Isotropic etching, D) a step of forming a third insulating film on the surface of the semiconductor substrate and the surface of the stacked layer, E) using the stacked layer as a mask to form a first region and a second region in the semiconductor substrate A method of manufacturing a semiconductor nonvolatile memory device, comprising: