JP3090739B2 - Manufacturing method of nonvolatile semiconductor memory element - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION The present invention relates to an EEPROM (electr
The present invention relates to a method for manufacturing a non-volatile semiconductor storage element such as an electronic erasable and programmable ROM.

[0002]

2. Description of the Related Art Heretofore, a full-future type EEPROM and a flash type EEPROM have been known as this type of nonvolatile semiconductor memory element.

FIG. 6 shows a full-future type EEPROM.
FIG. 7 shows an equivalent circuit diagram of a storage device in which the elements are connected in a matrix. As shown in FIG. 6, this element includes a memory cell including a memory transistor MTr and a select transistor STr in a P well 2 formed in an N-type silicon substrate 1. The memory transistor MTr has a gate structure including a tunnel oxide film 30, a floating gate 31, an insulating film 32, and a control gate 33, and N ⁺ diffusion layers 34 and 35 formed in the P well 2 on both sides thereof. ing. On the other hand, select transistor STr has a gate structure including a gate oxide film 36 and a gate 37, and N ⁺ diffusion layers 3 formed in P wells 2 on both sides thereof.
5 and 38.

Referring to FIG. 7, writing / erasing / reading of data to / from a full-future type EEPROM will be described. Data writing is performed as follows. The memory line ML connected to the control gate 33 of the memory transistor MTr of the selection element
Then, a positive voltage is applied to each of the bit lines BL. At this time, a positive voltage is applied to the word line WL connected to the gate 37 of the select transistor STr of the selection element, and the source line SL is grounded. As a result, hot electrons generated near the N ⁺ diffusion layer (drain) 34 of the memory transistor MTr are transferred to the tunnel oxide film 30.
, And is injected into the floating gate 31 to write a signal charge.

[0005] Data is erased as follows.
A positive voltage is applied to the bit line BL of the selected element, and the memory line ML is grounded. As a result, the charges stored in the floating gate 3 are transferred to the tunnel oxide film 3
The signal charge is erased by the N ⁺ diffusion layer 34 through 0.

Data reading is performed as follows. The source line SL of the selection element is grounded, a positive voltage is applied to the word line WL, and a positive voltage is applied to the bit line BL of the selection element and a positive low voltage is applied to the memory line ML. At this time, the select transistor S
If no current flows through Tr, the memory transistor MTr
, That is, data “1” is read. On the other hand, if a current flows through the select transistor STr, the memory transistor MTr is in a non-write state,
That is, data “0” is read.

Next, the configuration of a flash EEPROM will be described. Representative examples include a stack gate structure shown in FIG. 8 and a split gate structure shown in FIG.

The flash type EEPROM having the stacked gate structure shown in FIG. 8 has a gate structure composed of a tunnel oxide film 40, a floating gate 41, an insulating film 42, and a control gate 43. N ⁺ diffusion layers 44 and 45 are formed. Between the N ⁺ diffusion layer 44 as a drain and the P well 2,
A P ⁺ diffusion layer 46 for increasing the injection efficiency of hot electrons is formed. An N ^- diffusion layer 47 is formed between the N ⁺ diffusion layer 45 as a source and the P well 2 in order to suppress generation of hot holes due to an inter-band tunnel effect at the time of data erasing.

Flash type EEP with stack gate structure
Writing data to the ROM is performed by applying a positive voltage to each of the gate G and the drain D, grounding the source S, and injecting hot electrons into the floating gate 41 from near the drain. In erasing data, a signal charge is drawn from the floating gate 41 by applying a positive voltage to a source S commonly connected to each element of the substrate. Data reading is performed by applying a positive voltage to each of the gate G and the drain D to determine whether a current flows between the drain and the source.

The flash type EEPROM of the split gate structure shown in FIG. 9 has a floating gate 51 on a tunnel oxide film 50 on the drain D side, and a select gate 53 on the floating gate 51 via an insulating film 52. Are formed. The writing of data into this element is performed by applying a positive voltage to each of the gate G and the drain D and injecting hot electrons into the floating gate 51. To erase data, the gate G is grounded or a negative voltage is applied, and a positive voltage is applied to the drain D, so that signal charges accumulated in the floating gate 51 are drawn out to the drain D. For data reading, a positive low voltage is applied to the gate G,
By applying a positive voltage to the drain D, whether or not a current flows between the drain and the source is determined. In addition, flash type EEP with a split gate structure
Since the ROM includes the selection gate 53, a flash type EEPROM having a stack gate structure is used as described later.
The problem of excessive erasure as shown in FIG.

[0011]

However, the prior art having such a structure has the following problems.

In a full-future type EEPROM,
Since one memory cell is composed of the memory transistor MTr and the select transistor STr, there is a problem that the cell area is large, which is disadvantageous for high integration.

In a flash type EEPROM having a stacked gate structure, one cell is one transistor, which is advantageous for integration. However, since all cells on a substrate or all cells in a P well are collectively erased, a signal is erased. The overall erasing time is set longer according to the element that requires the longest time to erase the charges. Therefore, in a device in which signal charges are erased relatively quickly, a phenomenon occurs in which positive charges are accumulated in the floating gate 41 of the device due to excessive removal of signal charges. This is so-called excessive erasure. When excessive erasing occurs, the threshold value at the time of reading out signal charges varies among the elements, and the reading operation becomes unstable. For example, when excessive erasure occurs, a channel is formed by positive charges accumulated in the floating gate even in a non-selected element, and the source-
This causes a problem that current flows between the drains.

On the other hand, in a flash type EEPROM having a split gate structure, even if positive charges are accumulated in the floating gate 51 due to excessive erasing, no channel is formed in the P well 2 immediately below the select gate 53. There is no problem that a current flows between them. However, there is a problem in that the degree of integration is lower than that of a flash type EEPROM having a stacked gate structure due to the element structure.

The conventional E shown in FIGS.
In EPROM, the area of the insulating film between the floating gate and the control gate,
The area of the tunnel oxide film between the wells is substantially the same. That is, the capacitance C ₀ between the floating gate and the control gate is substantially the same as the capacitance C ₀ between the floating gate and the P well. Therefore,
The voltage applied to the control gate is divided into substantially the same value for the insulating film and the tunnel oxide film. In order to efficiently inject and emit electrons into the floating gate, the partial pressure applied to the tunnel oxide film may be increased.
Therefore, it is conceivable to reduce the thickness of the insulating film between the floating gate and the control gate to increase the capacitance ratio C ₀ / C. This causes a problem that the current increases.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and is intended to achieve high integration, stable read operation, and to improve insulation between a floating gate and a control gate. It is an object of the present invention to provide a method for manufacturing a non-volatile semiconductor storage element that can be used.

[0017]

The present invention has the following configuration in order to achieve the above object. That is, the present invention provides a method of manufacturing a nonvolatile semiconductor memory element including a memory transistor that performs nonvolatile storage by accumulating and emitting electrons to and from a floating gate via a tunnel insulating film, and a select transistor that selects the memory transistor. Depositing a thin film on a semiconductor substrate in which an element region is separately formed, and etching away the thin film in a common gate region of both transistors, and leaving an end of the remaining thin film in the floating gate portion. Forming a tunnel insulating film on the substrate in the common gate region; depositing a first conductive film on the substrate on which the tunnel insulating film is formed; Anisotropically etching the substrate on which the first conductive film is deposited, so that the first conductive film is formed on the edge of the thin film. Forming a floating gate having a convex-curved upper surface in a self-aligned manner, a step of forming an inter-gate insulating film on the upper surface of the floating gate, and a substrate corresponding to a gate region other than the floating gate region Forming a gate insulating film thereon, depositing a second conductive film on the substrate on which the inter-gate insulating film and the gate insulating film are formed, and a gate region portion of the second conductive film And removing the other portion by etching, so that one end is on the floating gate via the inter-gate insulating film and the other end is on the gate insulating film. Forming a gate, and using the common gate as a mask, a first impurity diffusion layer also serving as a drain and a source of the two transistors. Forming in self-alignment with the second impurity diffusion layer, said first impurity diffusion layer, the second
Forming wirings individually connected to the impurity diffusion layer and the common gate, respectively.

[0018]

The operation of the present invention is as follows. That is,
According to the present invention, the first impurity diffusion layer and the second impurity diffusion layer which also serve as the drain and the source of the memory transistor and the select transistor are provided on the tunnel insulating film in the vicinity of the first impurity diffusion layer. A floating gate formed by self-alignment and having a convex curved upper surface, one end of which is disposed on the upper surface of the floating gate via an insulating film, and the other end of which is gate insulating near the second impurity diffusion layer. A non-volatile semiconductor storage element having a common gate, which is disposed via the film and is also used as the control gate of the memory transistor and the gate of the select transistor, can be obtained.

According to this nonvolatile semiconductor memory device, the first impurity diffusion layer and the second impurity diffusion layer also serve as the drain and source of each of the memory transistor and the select transistor, and the substrate between the two impurity layers is provided. A floating gate formed by self-alignment and a common gate having one end positioned above the floating gate and serving as a control gate of a memory transistor and the other end serving as a gate of a select transistor are provided. Therefore, two transistors are formed in one transistor region.

Also, ON / OF of the select transistor
Since the memory transistor can be selected by F, data is erased in bit units, and there is no problem of excessive erasure, and the read operation is stabilized.

Furthermore, since the upper surface of the floating gate is a convex curved surface, the capacitance C ₀ between the floating gate and the common gate, increases relative to the electrostatic capacitance C between the floating gate and the substrate. That is, when a voltage is applied to the common gate, the partial pressure acting on the tunnel insulating film becomes larger than the partial pressure acting on the insulating film between the floating gate and the common gate, so that the efficiency of carrier injection into the floating gate is increased. Increase. Therefore, the voltage applied to the word line connected to the common gate during data writing / erasing can be set relatively low.

Conversely, if the capacitance C ₀ and the capacitance C are made substantially the same to obtain the same carrier injection efficiency as in the prior art, the area between the floating gate and the control gate is increased. Since the thickness of the insulating film between the two gates can be increased by that much, the insulation between the floating gate and the control gate is increased, and the leak current can be reduced.

[0023]

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a plan view of a memory cell of an EEPROM manufactured by a method according to an embodiment of the present invention, and FIG.
It is sectional drawing in the -A arrow direction.

In the figure, reference numeral 1 denotes an N-type silicon substrate;
Well 3 is a field oxide film. An N ⁺ drain diffusion layer 11 and an N ⁺ source diffusion layer 12 are formed in an element formation region separated by the field oxide film 3. On the tunnel oxide film 6 near the drain diffusion layer 11,
There is a floating gate 7a formed by self-alignment and having a convex curved upper surface. 10a is a common gate, one end on the drain side is located on the upper surface of the floating gate 7a via the insulating film 8, and the other end on the source side is located on the gate oxide film 9. In the drawing, reference numeral 14 denotes a metal wiring electrically connected to the drain diffusion layer 11 and the source diffusion layer 12, and 16 denotes a common gate 10a.
, And 15 and 15 are interlayer insulating films.

As shown in FIG. 2, the memory cell according to the present embodiment has a memory transistor and a select transistor in one transistor region. The drain diffusion layer 11 and the source diffusion layer 12 are also used as the drain and the source of the two transistors. The gate structure of the memory transistor includes the above-described tunnel oxide film 6, floating gate 7a, insulating film 8, and common gate 10a, and one end of the common gate 10a on the drain side serves as a control gate. The gate structure of the select transistor includes the gate oxide film 9 and the other end on the source side of the common gate 10a.

Hereinafter, the operation of this embodiment will be described with reference to FIG. FIG. 3 shows a random access EE according to the embodiment.
FIG. 3 is an equivalent circuit diagram showing a part of a storage device using a PROM. One memory cell includes a memory transistor MTr and a select transistor STr, and each memory cell is arranged in a matrix. Both transistors MTr, common gate 10a of the STr is connected word line W _n corresponding to each to W _{n +} 1, W _{n + 2,} the drain of the memory transistor MTr (drain diffusion layer 11)
Are connected to the bit lines B _m and B _{m + 1,} and the source (source diffusion layer 12) of the select transistor STr is connected to the source lines S _m and S _{m + 1} . In the figure, reference numeral 20 denotes a word line _{W n, W n + 1,} W n + 2 X decoder for selecting, 21 is a Y decoder for selecting the source line S _m, the S m _{+ 1} .

Data writing to the memory cell (n, m) shown in FIG. 3 is performed as follows. Bit line B
the voltage V _p writing the _m, and the word line W _n to the "H" level, to ground the source line S _m. Memory cells (n, m) connected to the same word line W _n and has been that memory cells (n, m + 1), by making the bit line B _{m + 1} and the source line S _{m + 1} to open or grounded, Writing is prohibited. In the other memory cells (n + 1, m) and (n + 1, m + 1), since the word line W _{n + 1} is grounded or at the “L” level, the select transistor STr is turned off and writing does not occur.

In the write memory cell (n, m), hot electrons are injected into the floating gate 7a as follows. That is, the drain diffusion layer 1
1, the write voltage _Vp is applied, the source diffusion layer 12 is grounded, and the common gate 10a becomes "H" level.
A channel is formed from the source diffusion layer 12 to the drain diffusion layer 11. By appropriately setting the write voltage V _p, the channel, the bottom of the select transistor STr (i.e., just below the gate oxide film 9 on the right-hand common gate 10a of Figure 2) exceeds a, and the drain diffusion layer 11 Extend to a position where it cannot be reached. Then, the electric field is concentrated just below the floating gate 7a, and many hot electrons are generated. Some of the hot electrons flow into the drain diffusion layer 11, but some are accelerated by the electric field of the common gate 10a and injected into the floating gate 7a via the tunnel oxide film 6.
This is the data write state.

Since the upper surface of the floating gate 7a of the memory cell according to the present embodiment has a convex curved shape, the area of the upper surface is larger than the area of the lower surface.
That is, the common gate 10a and the floating gate 7
capacitance C ₀ between a, the floating gate 7a
The capacitance C is larger than the capacitance C between the P well 2 and the P well 2. The voltage applied to the common gate 10a is divided between the tunnel oxide film 6 and the insulating film 8, and the divided voltage acting on the tunnel oxide film 6 is proportional to the capacitance ratio C ₀ / C. Therefore, as compared with the conventional memory cell in which the upper and lower capacitances C ₀ and C of the floating gate are substantially the same, the memory cell of the present embodiment has a larger capacitance ratio C ₀ / C in the tunnel oxide film 6 because of the larger capacitance ratio C ₀ / C. The applied partial pressure increases, and hot electrons are efficiently injected into the floating gate 7a. In other words, if hot electrons are injected with the same efficiency as that of the conventional memory cell, the voltage applied to the common gate 10a (word line) can be set to a small value. The configuration can be simplified. Further, when the capacitances C ₀ and C are set to the same level, the thickness of the insulating film 8 can be increased by the increase in the area between the floating gate 7a and the common gate 10a. The insulation between the gate 7a and the common gate 10a is improved, and the leakage current between the two gates can be reduced.

Erasure of data in the memory cell (n, m) is performed as follows. The word line W _{n is set} to “L” level, and the erase voltage _VE is applied to the bit line B _m and the source line S _m , respectively. The memory cell (n, m + 1) connected to the same word line W _n as the memory cell (n, m) has the bit line B _{m + 1} and the source line S _{m + 1} grounded or open. Erasing is prohibited. In addition, other memory cells (n +
1, m) and (n + 1, m + 1) are the word lines W _{n + 1}
Is at the "H" level, no erasure occurs. When the common gate 10a of the memory cell (n, m) is at the "L" level and the erasing voltage _VE is applied to the drain diffusion layer 11, the electrons accumulated in the floating gate 7a are transferred to the tunnel oxide film 6a. Through the drain diffusion layer 11 to erase data.

Reading of data from the memory cell (n, m) is performed as follows. Grounding the source line S _m, by applying a sense voltage V _SENSE word line W _n, for detecting the presence or absence of the potential drop by applying a voltage V _CC through a resistor to the bit line B _m. That is,
If data is written in the memory cell (n, m),
Since the memory transistor MTr is turned off, a state where no voltage drop occurs, that is, data “1” is read. On the other hand, if no data is written in the memory cell (n, m), the memory transistor MTr is turned on.
In this state, a state in which a voltage drop occurs, that is, data “0” is read.

Hereinafter, a method of manufacturing the memory cell according to the above-described embodiment will be described with reference to FIGS.

Referring to FIG. Here, after a P well 2 is formed in an N-type silicon substrate 1, a field oxide film 3 for element region isolation and an oxide film 4 are formed.

Referring to FIG. As described above, a silicon oxide film 5 corresponding to a thin film in the method of the present invention, for example, is formed on
It is deposited by VD (Chemical Vapor Deposition) method.

Next, the oxide film 5 is anisotropically etched, and a region corresponding to a common gate of the memory transistor and the select transistor is removed by etching. At this time, patterning is performed so that the end of the oxide film 5 is located at a portion where the floating gate 7a is formed.

Referring to FIG. Here, in order to remove the roughness of the substrate surface, after reoxidizing the substrate surface, the oxide film is removed by wet etching. Subsequently, for example, a tunnel oxide film 6 corresponding to the tunnel insulating film of the method of the present invention is formed in the transistor region.

On the substrate on which the tunnel oxide film 6 is formed,
A polysilicon film 7 corresponding to the first conductive film of the method of the present invention is deposited. The polysilicon film 7 has conductivity by being doped with, for example, phosphorus (P) or arsenic (As).

Referring to FIG. Here, etching back is performed until the polysilicon film 7 on the oxide film 5 is entirely removed. Thereby, a polysilicon sidewall is formed on the end surface of oxide film 5. Among them, the sidewall formed in the common gate region becomes the floating gate 7a of the memory transistor MTr described above. The gate length of the floating gate 7a is
By changing the thickness of the oxide film 5 and the etching conditions, it is possible to control the dimensions below the design rule.

Referring to FIG. Here, the substrate on which the floating gate 7a is formed is re-oxidized,
An insulating film (silicon oxide film) 8 corresponding to the inter-gate insulating film in the method of the present invention is formed on the floating gate 7a. Then, after removing an oxide film on the substrate corresponding to a gate region other than the region of the floating gate 7a by a photoetching method, a gate oxide film 9 corresponding to a gate insulating film in the method of the present invention is formed. Thereafter, a polysilicon film 10 corresponding to the second conductive film in the method of the present invention is deposited. A portion corresponding to the gate region of the polysilicon film 10 is masked with a photoresist 17 and the other portion is removed by anisotropic etching, so that one end of the polysilicon film 10 has a floating gate 7 via an insulating film 8.
a common gate 10a on the gate oxide film 9 at the other end.

Referring to FIG. Here, after removing the oxide film 9 in the drain and source regions, the common gate 10a and the field oxide film 3 are used as masks.
By ion-implanting N-type impurities such as phosphorus and arsenic,
The drain diffusion layer 11 and the source diffusion layer 12 are formed by self-alignment.

Referring to FIG. After ion implantation of the drain and the source, thermal oxidation is performed again to form an oxide film on the substrate surface. Then, after depositing an interlayer insulating film 13 such as phosphor glass (PSG), contact holes for drain and source regions are formed, and a metal film such as Al-Si is deposited. This metal film is patterned by a photoetching method to form a metal wiring 14 electrically connected to the drain and the source.

Referring to FIG. Here, after further depositing the interlayer insulating film 15, a contact hole is formed in the gate region, and a metal layer is further deposited. This metal layer is patterned to form a metal wiring 16 connected to the common gate 10a.

In the above-described embodiment, an N-channel type EEPROM has been described as an example. However, it is needless to say that the present invention can be applied to a P-channel type EEPROM.

As described in the conventional example shown in FIGS. 8 and 9, also in the memory cell shown in FIG. 2, the injection efficiency of hot electrons between the drain diffusion layer 11 and the P well 2 is increased. P ⁺ diffusion layer may be provided. Further, an N ^- diffusion layer may be provided between the source diffusion layer 12 and the P well 2 to improve the breakdown voltage.

[0045]

As is apparent from the above description, according to the method of the present invention, it is possible to easily realize a nonvolatile semiconductor memory element having two transistors, a memory transistor and a select transistor, in one transistor region. Thus, the area of the memory cell is reduced, and the degree of integration of the semiconductor memory device can be increased.

Further, the nonvolatile semiconductor memory element realized by the method of the present invention is capable of turning on / off select transistors.
As a result, data can be erased in units of bits, so that there is no problem of excessive erasing as in a conventional flash type EEPROM having a stacked gate structure, so that the data reading operation is stabilized.

Further, since the upper surface of the floating gate has a convex curved shape, the capacitance between the floating gate and the common gate becomes larger than the capacitance between the floating gate and the substrate, and the tunnel insulating film The partial pressure acting on the As a result, the efficiency of carrier injection into the floating gate is increased, and the voltage applied to the word line at the time of writing / erasing data can be set relatively small, which simplifies the configuration of the booster circuit of the storage device.

When the carrier injection / emission efficiency to the floating gate is set to be the same as the conventional one, the thickness of the insulating film between the floating gate and the control gate is reduced by the increase in the area between the floating gate and the control gate. Since the thickness can be increased, insulation between both gates is improved, and leakage current can be reduced.

[Brief description of the drawings]

FIG. 1 is a plan view showing an element structure of one embodiment of a nonvolatile semiconductor memory element according to the present invention.

FIG. 2 is a sectional view taken along the line AA of FIG.

FIG. 3 is an equivalent circuit diagram showing a part of a storage device configured using a random access EEPROM according to the embodiment.

FIG. 4 is an explanatory diagram of a method for manufacturing a memory cell according to an example.

FIG. 5 is an explanatory diagram of a method for manufacturing a memory cell according to an example.

FIG. 6 shows a conventional full-future type EEPROM.
FIG. 3 is a cross-sectional view showing the element structure of FIG.

FIG. 7 is an equivalent circuit diagram of the element shown in FIG.

FIG. 8 is a cross-sectional view showing an element structure of a flash EEPROM having a stack gate structure according to a conventional example.

FIG. 9 is a sectional view showing an element structure of a flash EEPROM having a split gate structure according to a conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Silicon substrate 2 ... P well 3 ... Field oxide film 6 ... Tunnel oxide film 7a ... Floating gate 8 ... Insulating film 9 ... Gate oxide film 10a ... Common gate 11 ... Drain diffusion layer (first impurity diffusion layer) 12 ... Source diffusion layer (second impurity diffusion layer) 13, 15 ... interlayer insulating film 14, 16 ... metal wiring

──────────────────────────────────────────────────続 き Continuation of front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/8247 G11C 16/04 H01L 29/788 H01L 29/792

Claims (1)

(57) [Claims] 1. A method of manufacturing a nonvolatile semiconductor memory device, comprising: a memory transistor for performing nonvolatile storage by accumulating and emitting electrons to and from a floating gate via a tunnel insulating film; and a select transistor for selecting the memory transistor. A step of depositing a thin film on a semiconductor substrate in which an element region is separately formed; and etching away the thin film in a common gate region of both transistors, and an end of the remaining thin film is located in the floating gate portion. Forming a tunnel insulating film on the substrate in the common gate region; depositing a first conductive film on the substrate on which the tunnel insulating film is formed; Anisotropically etching the substrate on which the first conductive film is deposited to form the first conductive film on the edge of the thin film. Forming a floating gate having a convex-curved upper surface by self-alignment; forming an inter-gate insulating film on the upper surface of the floating gate; and forming a floating gate on a substrate corresponding to a gate region other than the floating gate region. Forming a gate insulating film; depositing a second conductive film on the substrate on which the inter-gate insulating film and the gate insulating film are formed; and masking a gate region of the second conductive film. Then, by etching and removing the other portion, a common gate of the two transistors, one end of which is on the floating gate via the inter-gate insulating film and the other end of which is on the gate insulating film, is formed. Forming a first impurity diffusion layer also serving as a drain and a source of the two transistors, using the common gate as a mask; Forming a second impurity diffusion layer in a self-aligned manner; and forming wirings individually connected to the first impurity diffusion layer, the second impurity diffusion layer, and a common gate. A method for manufacturing a nonvolatile semiconductor memory element.