JP3630491B2 - Semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a nonvolatile semiconductor memory device that performs data write, erase, and read operations.
[0002]
[Prior art]
In recent years, a memory cell having a MONOS (Metal-Oxide-Nitride-Oxide-Silicon) structure has been proposed as a memory cell of an electrically writable / erasable nonvolatile memory (flash EEPROM). FIG. 16 is a diagram for explaining a memory cell having a MONOS structure. In FIG. 16, 1 is a substrate or well (P-type impurity region), 2 is a drain (dense N-type impurity region), 3 is a source (dense N-type impurity region), 4 is a silicon oxide film, 5 is a SiN film, 6 Is a silicon oxide film, 7 is a control gate, and 9 is an oxide film formed after processing a laminated gate. In this type of memory cell, charges are injected into the SiN film (5) of the gate insulating film, and the charges are trapped in the charge trapping center in the SiN film (5), or the trapped charges are trapped in the SiN film (5). By pulling out from the inside, the threshold value of the cell is controlled to provide a memory function. For nonvolatile memories having MONOS type memory cells, the following writing method, erasing method, and reading method have been proposed. (Here, “write” is defined as injection of charge into the SiN film, and erasure as extraction of charge from the SiN film.) As a write method, a channel is formed in the channel region (8) near the drain (2). A method of generating hot electrons (CHE) and injecting electrons into the SiN film (5), applying a high electric field between the control gate (7) and the drain (2), the channel region (8) or the source (3). A method of injecting electrons into the SiN film (5) by FN (Fowler-Nordheim) is typical. As an erasing method, high electrolysis is applied between the control gate (7) and the source (3), the drain (2), or the channel region (8), so that electrons in the SiN film are transferred to the substrate side by FN (Fowler). -Nordheim) A typical method is to discharge as a tunnel current.
[0003]
[Problems to be solved by the invention]
In the MONOS type cell in which writing / erasing is performed at the source or drain by the FN tunnel, it is necessary to apply a high electric field in the charge injection region of the gate insulating film. In this case, if the surface impurity concentration of the source or drain region under the gate insulating film is low, depletion occurs in the region under the gate insulating film to which a high electric field is applied, and a sufficient electric field is not generated. In addition, a sufficient electric field is not generated even when the distance between the source or drain region to be an electrode and the gate electrode is large. When a high electric field is not applied in this way, a sufficient FN tunnel does not occur, and the write / erase characteristics deteriorate. Therefore, in the method using the FN tunnel of charge at the source or drain for writing / erasing, a sufficient overlap region is provided between the source or drain diffusion layer and the gate electrode, and the impurity of the source or drain below the gate electrode is provided. It is necessary to keep the concentration high. Even when CHE is written from the drain, the drain impurity concentration under the gate electrode cannot be lowered as in the case of FN writing / erasing because hot electron injection efficiency is not lowered. For the above reasons, since the impurity concentration of the source or drain cannot be lowered, a shallow junction cannot be formed, which is a big problem for miniaturization of the cell transistor. In addition, when FN injection is used, the energy of charges passing through the insulating film increases because a high electric field is applied, leading to deterioration of the insulating characteristics of the insulating film and an increase in the amount of charge traps generated in the insulating film. This causes deterioration of rewrite characteristics and data retention characteristics of the nonvolatile memory.
[0004]
In the NOR type cell in which the selection transistor is not formed in the MONOS cell, when writing / erasing is performed, a disturb phenomenon that destroys data occurs in a non-selected cell sharing the same bit line or word line as the selected cell. It becomes a problem. For example, when writing is performed by injecting electrons into an ONO (Oxide-Nitride-Oxide) insulating film by CHE on the drain side, the drain of the cell written first is completed until the writing of the cell sharing the same bit line is completed. Continues to be subjected to high potential stress. Since this stress electric field is in the direction in which electrons escape from the ONO insulating film to the drain side, when the writing of cells on the same bit line is completed, if the loss of electrons due to this stress is large, the data is inverted and the data is destroyed. The problem that happens.
[0005]
In a MONOS type cell in which writing / erasing is performed by FN tunneling in the channel region, a selection transistor is required to prevent erroneous writing when a matrix type cell array including word lines and bit lines is formed. In the case of forming a NOR type cell array, a select transistor is required for each cell, which is disadvantageous in that it is not suitable for miniaturization. In the NAND type, the number of selection transistors is two for one NAND connection, which is smaller than in the case of the NOR type connection. However, since cells are connected in series, the amount of writing at the time of writing and the erroneous writing at the time of writing are prevented. Therefore, there is a problem that the control of the potential applied to the non-write cell becomes complicated and the control circuit increases.
[0006]
[Means for Solving the Problems]
In the present invention, an offset region between the gate and the diffusion layer is formed in the channel region under the side surface of the gate of the memory cell, and an ONO structure insulating film is formed in this region. In the present invention, charge is injected into the SiN film in the ONO insulating film and trapped in the charge trapping center in the SiN film, writing is performed, and the trapped charge is extracted from the SiN film or trapped. Erasing is performed by injecting a charge having a polarity opposite to the charged charge. Since the channel resistance is modulated by the presence or absence of charge in the ONO insulating film and the polarity (positive or negative), the current flowing through the cell changes. The present invention is characterized by utilizing this phenomenon as a memory function.
Another method according to the present invention uses a polysilicon electrode doped with impurities on the gate side wall, and controls the potential under the polysilicon electrode by capacitive coupling with the gate electrode, thereby improving the efficiency of charge injection. Controllability can be improved. When the cell according to the present invention is used, a selection transistor is not required unlike a MONOS cell in which writing and erasing are performed in the channel region. Further, in the cell of the present invention, it is not necessary to form a high-concentration diffusion layer as a source or drain diffusion layer serving as an injection side electrode, so that a shallow diffusion layer can be formed and the cell transistor can be miniaturized. In the present invention, the charge injection method into the insulating film uses hot carriers or avalanche hot carriers due to band-to-band tunneling at the drain or source serving as the injection electrode. At this time, by controlling the gate potential, the charge injected into the insulating film can be selected as an electron or a hole. The energy of the hot carrier generated here is lower than that of the hot carrier generated by the FN current, and damage to the insulating film is reduced, so that the reliability of the cell can be improved. In the disturbance in the unselected cells on the same bit line, the gate potential of the non-selected cell as in Va in FIG. 14, the electronic also substantially eliminate disturbance if close to the conditions of the potential at which the well holes are not injected Can do.
That is, the semiconductor device of the present invention is formed in the semiconductor substrate, the first diffusion layer having a second conductivity type impurity to be a drain diffusion layer formed in the first conductivity type semiconductor substrate, A second diffusion layer having impurities of the second conductivity type to be a source diffusion layer, a gate electrode formed in a part on a channel region existing between the first and second diffusion layers, and the gate electrode A semiconductor device comprising: a floating gate electrode capacitively coupled to the gate electrode formed as a side wall; and a first insulating film formed between the gate electrode and the floating gate electrode. And a second insulating film having a thickness of at least three layers having a charge storage layer of 30 nm or less between the gate electrode and the semiconductor substrate and the floating gate electrode. And an end portion of the first diffusion layer or the second diffusion layer located on the gate electrode side is spaced from the gate electrode by a distance of 25 nm or less to the end of the second insulating film. It is characterized by being located directly below the bottom of the part.
[0007]
DETAILED DESCRIPTION OF THE INVENTION
Subsequently, the best embodiment of the present invention will be described with reference to FIGS.
FIG. 1 is a sectional view of a nonvolatile semiconductor memory cell according to a first embodiment of the present invention.
Next, a method for manufacturing the nonvolatile semiconductor memory cell according to the first embodiment of the present invention will be described with reference to FIGS.
[0008]
As shown in FIG. 2, after a predetermined element isolation region (10) is formed on the substrate (1) by a well-known technique, a silicon oxide film (11) is formed as a first insulating film layer on the silicon substrate in the memory cell region. Then, polysilicon (12) is deposited on the first silicon oxide film to a thickness of, for example, 100 to 200 nm, and n-type impurities such as arsenic and phosphorus are made to a concentration of, for example, about 2 to 4e20 cm −3 by a well-known technique. Doping. The first insulating film (11) is formed by oxidizing a silicon substrate or depositing a silicon oxide film. Here, when the resistance of the gate electrode is lowered, a refractory metal silicide layer such as WSi or MoSi is deposited on the polysilicon (12) to form a polycide structure, or a refractory metal such as W is deposited. And a polymetal structure.
[0009]
Subsequently, as shown in FIG. 3, the gate of the memory cell is patterned to form a gate electrode (13), and an oxide or silicon oxide film is deposited to form an oxide film (14). The thickness of the oxide film (14) is set to 10 nm or less in order to make the electric field in the charge injection region sufficiently strong and to make the tunnel to the charge storage layer sufficiently easy to occur. The lower limit of the film is preferably 2 nm or more in order to suppress back tunneling from the charge injection layer. At this time, a predetermined impurity can be introduced into the substrate by a known technique such as ion implantation before the oxidation or oxide film deposition in order to adjust the channel threshold value of the charge injection region.
[0010]
Next, when the offset region side of the cell transistor is formed on the source side as shown in FIG. 4, the source region is masked with, for example, a photoresist (15) or the like, and an N-type impurity is removed by a known technique such as ion implantation. The drain side N-type diffusion layer (16) is formed. At this time, the ion implantation amount to the drain side is, for example, 5e12 to 5e14 cm −2, and an LDD (Lightly Doped Drain) structure can be formed by an N-type diffusion layer having a low impurity concentration.
[0011]
Next, as shown in FIG. 5, a SiN layer (17) serving as a charge storage layer is deposited, and a silicon oxide film (18) is deposited on the SiN film (17) by a known technique such as a CVD method.
[0012]
As shown in FIG. 6, a gate sidewall (19) is formed by a method such as etch back, N-type impurities are introduced by a known technique such as ion implantation, and the N-type of the drain (20) and the source (21). A diffusion layer is formed. The width of the side wall (19) of the gate defines the width of the charge injection region. Here, the thickness of the SiN layer (17) is set to 7 nm or less in order to increase the electric field in the charge injection region. The lower limit of the thickness of the SiN film serving as the charge storage layer can be determined by the charge trap density, but is preferably at least 0.5 nm. In this embodiment, SiN is used as the charge storage layer. However, it is a film having a sufficiently large number of charge traps such as a tantalum oxide film, strontium titanate, and PZT, and has a sufficiently high relative dielectric constant and insulation resistance. Any film may be used as long as it does not change in quality due to the thermal process. Further, since the oxide film (18) deposited on the SiN film can prevent the electric charge stored in the SiN film from diffusing outward, the data retention characteristics of the cell can be improved. The ion implantation amount for forming the N type diffusion layers of the drain (20) and the source (21) is, for example, 5e14 to 1e16 cm −2, and a relatively dense N type diffusion layer is formed. Here, the distance between the control gate (13) and the end of the source diffusion layer (21) is determined so that an electric field can be obtained so that the generated hot carriers can sufficiently reach the charge storage layer during the charge injection operation. . For example, the distance is 25 nm or less. This distance can be adjusted by the width of the gate sidewall and the thermal diffusion process after ion implantation of the source. It can also be adjusted by the dielectric constant of the film used for the gate sidewall (19). Thereafter, as shown in FIG. 1, an interlayer insulating film (22) is formed in accordance with a normal MOS integrated circuit manufacturing method, and a part of the interlayer insulating film on the source / drain regions is opened. 23), and after forming the barrier layer (24) in the contact hole by a well-known technique, the W plug (25) is buried, and the A1 electrode (26) is formed, thereby completing the memory cell.
[0013]
FIG. 7 is a circuit block diagram of the nonvolatile semiconductor device of the present invention, and FIG. 8 shows an arrangement method when an injection region is provided on the source side as in this embodiment. FIG. 15 shows an arrangement method in the case where an injection region is provided on the drain side, writing is performed with channel hot electrons, and erasing is performed with drain avalanche hot holes. Although this embodiment has been described with respect to the case where it is formed on a P-type substrate, this structure is formed on an SOI (Silicon on Insulator) substrate when a memory cell is formed on a P-well formed on an N-type semiconductor substrate. The same applies to the case where it is formed in the P-type region. In this embodiment, it is possible to provide a charge injection region on the source side, but it is also possible to provide a charge injection region on the drain side as in this embodiment. In this embodiment, an ONO insulating film is used in the gate side wall and under the gate side wall. However, as shown in FIG. 17, the ONO insulating film is used as the gate insulating film of the cell transistor to form the gate side wall. It is also possible.
[0014]
Next, the operation of this embodiment will be described with reference to FIGS. Writing when a charge injection region is provided on the source side is performed as follows. When a positive potential is applied to the source and the drain is open, and the electric field is 7 MV / cm or more in the substrate region at the end of the source diffusion layer, the generation of avalanche hot carriers becomes significant. At this time, as shown in FIG. 14, when the gate potential is moved in a positive direction from a certain potential (Va), the charge injected into the charge injection region becomes hot electron rich, and electrons are stored in the charge storage layer. . (N. Matsukawa et al. 1995 IRPS) In this state, the channel under the charge storage layer on the source side is turned off in the read operation. For example, even if 5V is applied to the gate, 1V to the drain, and 0V to the source, Since almost no current flows, it can be determined that data has been written. There are two methods for erasing: a method using an avalanche hot carrier and a method using an FN tunnel. When using an avalanche hot hole, the charge injected into the charge injection region becomes hot hole rich when the gate potential is made to be more negative than a certain potential, as in writing, and the charge storage layer has a hole. Will be accumulated. In this state, since the channel under the charge storage layer is turned on, it can be determined that the channel has been erased because a current flows during the read operation. In the case of using the FN tunnel, the gate potential at the time of avalanche hot hole injection is further taken in the negative direction and stronger than the electric field between the gate and the source, whereby electrons in the storage layer can be extracted. If the gate potential of the non-selected cell at the time of writing / erasing is set to a condition (Va) in which neither electrons nor holes in FIG. 14 are injected, the disturb phenomenon does not occur.
[0015]
Next, when a charge storage layer is provided on the drain side, writing and erasing can be performed in the same manner as when a charge storage layer is provided on the source side. However, if the source is grounded without being opened, Since a large amount of current flows through the channel, the injection efficiency of hot electrons and hot holes can be increased. (S. Yamada et al. 1991 IEDM) At the time of writing, there is also a method in which a current is passed between the source and drain, channel hot electrons are generated on the drain side, and electrons are injected.
[0016]
Next, a nonvolatile semiconductor memory cell according to a second embodiment of the present invention will be described with reference to FIGS. The process from the patterning of the gate to the deposition of SiN (17) as the charge storage layer is the same as the process of the first embodiment. In FIG. 10, after depositing the SiN film (17), the silicon oxide film (27) is deposited, and the polysilicon (28) is deposited thereon by, for example, 20 to 200 nm, and then N-type impurities such as arsenic, phosphorus, etc. The concentration is 4e20 cm−3. Doped and metallized. Here, the film thickness of the oxide film (27) on the SiN film (17) is to prevent outward diffusion of charges stored in the SiN film or hole injection from the polysilicon sidewall (29). The film thickness is 2.5 nm or more. In FIG. 11, a polysilicon sidewall (29) is formed by a method such as etch back, an N-type impurity is introduced by a known technique such as ion implantation, and N-type diffusion of the drain (20) and the source (21). Form a layer. The ion implantation amount at this time is, for example, 5e14 to 1e16 cm −2, and a relatively dense N-type diffusion layer is formed. Thereafter, in FIG. 9, the memory cell is completed through the same steps as in the first embodiment.
[0017]
Next, the operation of this embodiment will be described with reference to FIG. Writing in the case where a charge injection region is provided on the source side is performed in the same manner as in the first embodiment. A positive potential is applied to the source to open the drain. Here, when a potential is applied to the gate, since the polysilicon electrode on the side wall is capacitively coupled to the gate, the source, and the substrate, the potential of the side wall polysilicon electrode is determined by the capacitive coupling ratio with each electrode. When the cell of this embodiment is used as a cell array, for example, when the gate height is 200 nm, the polysilicon sidewall width is 100 nm, the cell transistor gate width is 0.4 μm, and the pitch in the word line direction is 0.8 μm, the sidewall The capacity between the polysilicon and the gate is about 80% of the total capacity, and when the substrate potential is grounded, the side wall polysilicon potential is about 80% of the gate potential. Thus, the potential of the sidewall polysilicon electrode can be controlled by the gate potential. When the gate potential is applied so that the potential of the side wall polysilicon is more positive than the certain potential, the charge injected into the charge injection region among the hot carriers generated at the edge of the source diffusion layer becomes hot electron rich. Electrons are stored in the charge storage layer. In this case, during the read operation, the channel under the side wall may be turned on when the side wall potential rises. However, compared to the case where data is not written, the flowing current is extremely small, so it can be determined that data has been written. Erasing can also be performed by controlling the sidewall polysilicon potential by the gate potential, as in the writing. Even when a charge storage layer is provided on the drain side, writing and erasing can be performed as in the first embodiment.
[0018]
Similarly to the first embodiment, the structure of this embodiment is also applicable when a memory cell is formed on a P-well formed on an N-type semiconductor substrate, or when it is formed on a P-type region on an SOI (Silicon on Insulator) substrate. Applicable. The charge injection region can be provided on either the source side or the drain side. In this embodiment, an ONO insulating film is used in the gate side wall and under the gate side wall. However, in the cell transistor structure shown in FIG. 17, the gate side wall (19) is made of, for example, arsenic on polysilicon. The ONO insulating film can be used as the gate insulating film of the cell transistor by replacing it with a metallized metal doped with an N-type impurity such as phosphorus.
[0019]
【The invention's effect】
In the present invention, since the cell is composed of a series connection of an offset region under the charge injection layer and a transistor, a selection transistor is not necessary unlike the MONOS cell in which charge is injected in the channel region. Further, since a shallow diffusion layer can be formed in the source / drain of the cell transistor, the gate length of the cell transistor can be miniaturized. As a method for injecting electric charges into the insulating film, hot carriers or avalanche hot carriers are generated by band-to-band tunneling at the drain or source serving as an injection electrode, and the energy is relatively low compared to hot carriers generated by FN current. Therefore, damage to the insulating film is reduced, and the reliability of the cell can be improved. In addition, with respect to the disturbance for the non-selected cells on the same bit line, the disturbance can hardly occur by adjusting the gate potential of the non-selected cells.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view of a semiconductor memory device according to a first embodiment of the present invention.
FIG. 2 is a cross-sectional view showing the method of manufacturing the semiconductor memory device according to the first embodiment of the present invention.
FIG. 3 is a cross-sectional view showing the method of manufacturing the semiconductor memory device according to the first embodiment of the present invention.
FIG. 4 is a cross-sectional view showing the method of manufacturing the semiconductor memory device according to the first embodiment of the present invention.
FIG. 5 is a cross-sectional view showing the method of manufacturing the semiconductor memory device according to the first embodiment of the present invention.
FIG. 6 is a cross-sectional view showing the method of manufacturing the semiconductor memory device according to the first embodiment of the present invention.
FIG. 7 is a memory cell array of a semiconductor memory device using the memory cell of the present invention.
FIG. 8 is a circuit configuration diagram of a semiconductor memory device of the present invention.
FIG. 9 is a sectional view of a semiconductor memory device according to a second embodiment of the present invention.
FIG. 10 is a cross-sectional view showing the method of manufacturing the semiconductor memory device according to the second embodiment of the invention.
FIG. 11 is a cross-sectional view showing a method of manufacturing a semiconductor memory device according to a second embodiment of the present invention.
FIG. 12 is a diagram showing a method of operating a semiconductor memory device of the present invention.
FIG. 13 is a diagram showing an operation method of a semiconductor memory device of the present invention.
FIG. 14 is a graph showing characteristics of the memory cell of the present invention.
FIG. 15 is still another configuration diagram of the memorial array of the semiconductor memory device using the memory cell of the present invention.
FIG. 16 is a cross-sectional view of a conventional semiconductor memory device.
FIG. 17 is still another configuration diagram of the memorial array of the semiconductor memory device using the memory cell of the present invention.
[Explanation of symbols]
1 substrate or well (P-type impurity region),
2 ... Drain (dense N-type impurity region),
3 ... Source (dense N-type impurity region),
4 ... Silicon oxide film,
5 ... SiN film,
6 ... Silicon oxide film,
7 ... Control gate,
9: Oxide film formed after processing the stacked gate,
10: Element isolation region,
11: Gate insulating film,
12 ... polysilicon layer to be a gate electrode,
13 ... Gate electrode,
14 ... Silicon oxide film,
15 ... Photoresist,
16 ... N-type diffusion layer,
17 ... SiN layer to be a charge storage layer,
18 ... silicon oxide film,
19 ... Gate side wall,
20 ... Drain N type diffusion layer,
21 ... Source N-type diffusion layer,
22 ... interlayer insulation film,
23 ... Contact hole,
24 ... barrier layer,
25 ... W plug,
26 ... A1 electrode,
27 ... Silicon oxide film,
28 ... polysilicon layer,
29 ... polysilicon sidewall,

Claims (7)

A first diffusion layer having a second conductivity type impurity to be a drain diffusion layer formed in the first conductivity type semiconductor substrate;
A second diffusion layer having a second conductivity type impurity to be a source diffusion layer formed in the semiconductor substrate;
A gate electrode formed on a part of the channel region existing between the first and second diffusion layers;
A floating gate electrode capacitively coupled to the gate electrode formed as a sidewall on the gate electrode;
A semiconductor device having a first insulating film formed between the gate electrode and the floating gate electrode,
A second insulating film having a thickness of at least three layers having a charge storage layer of 30 nm or less between the semiconductor substrate and the gate electrode and between the semiconductor substrate and the floating gate electrode; ,
The end of the first diffusion layer or the second diffusion layer located on the gate electrode side is directly below the bottom surface of the end of the second insulating film at a distance of 25 nm or less from the gate electrode. A semiconductor device characterized by being positioned. 3. The structure of the first insulating film according to claim 1 , wherein the second insulating film includes a silicon oxide film having a thickness of 2 nm to 10 nm, a silicon nitride film having a thickness of 0.5 nm to 7 nm, and a silicon oxide film having a thickness of 2 nm to 10 nm from the semiconductor substrate. A semiconductor device having a layer structure. 2. The semiconductor device according to claim 1 , wherein the second insulating film has a three-layer structure of a silicon oxide film, a tantalum oxide film, and a silicon oxide film from the semiconductor substrate. 2. The semiconductor device according to claim 1 , wherein the second insulating film has a three-layer structure of a silicon oxide film, strontium titanate or barium strontium titanate, and a silicon oxide film on the semiconductor substrate. 2. The charge storage layer of the second insulating film according to claim 1 , wherein the first diffusion layer is opened, a potential is applied to the second diffusion layer to generate avalanche hot carriers, and the charge storage layer of the second insulating film is selected by the potential applied to the gate electrode. A semiconductor device characterized by injecting electrons or holes. 2. The charge accumulation of the second insulating film according to claim 1 , wherein a potential is applied to the second diffusion layer to generate hot carriers in a depletion layer region at an end of the second diffusion layer, and the charge applied to the second insulating film is generated by the potential applied to the gate electrode. A semiconductor device, wherein electrons or holes are selectively injected into a layer. 2. The non-selection according to claim 1 , wherein a potential applied to the second diffusion layer is shared when a potential is applied to the second diffusion layer to generate hot carriers in a depletion layer region at an end of the second diffusion layer. A semiconductor device characterized in that a potential applied to a gate electrode of a cell is set such that electrons and holes are not injected into an end of the second diffusion layer.

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