JP2007142468A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device where electrical characteristics in a gate insulating film in the vicinity of an element isolation region and electrical characteristics in a gate insulating film in a region other than the element isolation region are equal, and a method for manufacturing the same. <P>SOLUTION: The semiconductor device having a semiconductor substrate 1; a shallow trench element isolation region 13 formed in a trench formed in the semiconductor substrate 1; a source-drain region that is formed in the semiconductor substrate 1 and sandwiches the surface of the semiconductor substrate to define a channel; gate insulating films 10, 11 and 12 that are formed on the semiconductor substrate and their thicknesses are equal at the central section of the channel and a portion that contacts with the shallow trench element isolation region; and gate electrodes 14, 15 formed on the gate insulating films 10, 11 and 12. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

The present invention relates to a semiconductor device, and more particularly to a fine semiconductor device that requires high characteristics of a gate insulating film and a manufacturing method thereof.

As a kind of electrically erasable and erasable non-volatile semiconductor memory device, so-called MONOS (metal-silicon oxide film-silicon nitride film-silicon oxide film-semiconductor) stores data by trapping charges in a silicon nitride film ) Type memory cells are known. MO
The NOS type memory can perform a write / erase operation at a lower voltage compared to the floating gate type memory, and has a single layer gate structure M for a floating gate type memory cell that requires a stacked gate structure.
Since the ONOS memory cell has a small gate aspect ratio, it is suitable for miniaturization of elements.

  FIG. 94 shows a cross-sectional view of a conventional MONOS memory cell by LOCOS type element isolation.

In FIG. 94, a tunnel insulating film 101 of a memory cell is formed on a semiconductor substrate 100, and an element isolation region 102 thicker than the tunnel insulating film 101 is formed so as to sandwich the tunnel insulating film. A charge storage layer 103 made of a silicon nitride film is formed on the surface of the element isolation region 102 and the tunnel insulating film 101. This charge storage layer 103
A barrier insulating film 104 is formed thereon. Furthermore, on this barrier insulating film 104,
A gate electrode 105 is formed.

By the way, along with miniaturization, element isolation by STI has become an important technique in place of conventional LOCOS element isolation. Self-aligned STI has been proposed as an element isolation method particularly suitable for floating gate nonvolatile memories ("A 0.67 μm ² SELF-AL
IGHNED SHALLOW TRNECH ISOLATION CELL (SA-STI CELL) FOR 3V-only 256Mbit NAND EEPRO
Ms "IEDM Tech. Dig. 1994 pp61-64). Here, the thickness of the gate insulating film formed under the floating gate is formed thicker than the other portions at the gate electrode end. In self-aligned STI, by forming an element isolation trench in a self-aligned manner with respect to a floating gate that is a charge storage layer,
Electric field concentration at the element isolation end due to part of the gate electrode entering the element isolation end is prevented. As a result, variations in cell characteristics are improved, and high reliability can be realized.

A configuration is described in which the gate insulating film is entirely present in the trench in the boundary region with the peripheral selective oxide film so as to prevent the sidewalk phenomenon of the MNOS type nonvolatile semiconductor memory device (for example, patent Reference 1).

It is described that a nonvolatile memory using an insulating film as a charge storage layer like MONOS is inferior in read disturb characteristics (see, for example, Patent Document 2).
JP-A-4-12573 JP-A-11-330277

  The conventional semiconductor device as described above has the following problems.

Due to the influence of thermal oxidation that forms the element isolation region, the oxide film becomes thick at the element isolation edge portion 106, and the write / erase characteristics deteriorate in this region. That is, since the insulating film thickness is increased at the element isolation edge portion, the electric field is weakened and the threshold value is lowered.

In the MONOS structure, since charges are trapped in a silicon nitride film which is an insulating film, carriers do not move in the charge storage layer. Therefore, when a write pulse is applied, only the channel edge portion is left with a low threshold. This is observed as subthreshold leakage or hump for transistor characteristics. This phenomenon, called sidewalk, is problematic because it narrows the write / erase window of the MONOS memory cell.

Further, in Patent Document 1 (Japanese Patent Laid-Open No. 4-12573), a groove is provided in a semiconductor substrate, and an insulating film is provided in the groove, but the film thickness is thick in the vicinity of the element isolation region. Electric field concentration occurs and control characteristics deteriorate.

  An object of the present invention is to solve the above-described problems of the prior art.

In particular, an object of the present invention is to provide a semiconductor device in which the electrical characteristics of the gate insulating film near the element isolation region and the electrical characteristics of the gate insulating film outside the element isolation region are equal, and a method for manufacturing the same. is there. Furthermore, another object of the present invention is to provide a source / source among the four sides defining the element region.
An object of the present invention is to provide a highly reliable semiconductor device in which deterioration of charge retention characteristics at two edges parallel to the direction in which drain-to-drain current flows is suppressed.

Furthermore, another object of the present invention is to provide a semiconductor device that suppresses variations in write / erase characteristics and data retention characteristics at the edge portion of the gate electrode and threshold fluctuations.

To achieve the above object, a semiconductor substrate, an element region formed in the semiconductor substrate, a first gate insulating film provided on the element region, at least one gate electrode,
An element isolation region formed on the semiconductor substrate and in contact with at least a part of the gate electrode and the first gate insulating film are capable of storing data, and are electrically written and erased And a charge storage region having an end portion located in the element isolation region, and an end portion of the charge storage region is in a range of 0.5 nm to 15 nm in the element isolation region. The semiconductor device is characterized in that it has entered at a point.

Another feature of the present invention is a semiconductor substrate, a first conductivity type element region having substantially four sides formed in the semiconductor substrate, and a first gate insulating film provided on the element region. A charge storage region provided on the first gate insulating film, capable of storing data, and having an insulating film that can be electrically written and erased, and at least one provided on the charge storage region A source electrode and a drain electrode of a conductivity type opposite to the first conductivity type, and disposed between the charge storage region and the gate electrode, respectively; On the two sides where the electrode and the drain electrode are not formed, the gate electrode on the surface facing the charge storage region is lower than the lower part of the center of the gate electrode on the surface facing the charge storage region. A second gate insulating film formed thick under the edge, and on the two sides where the source electrode and the drain electrode are not formed, the thickness of the second gate insulating film is in the charge storage region. 0.6 nm to 50 nm below the edge of the gate electrode on the surface facing the charge storage region compared to below the center of the gate electrode on the facing surface
The semiconductor device is characterized in that it is formed thicker than the range of

Another feature of the present invention is a semiconductor substrate, a first conductivity type element region having substantially four sides formed in the semiconductor substrate, and a first gate insulating film provided on the element region. A charge storage region provided on the first gate insulating film, which is made of an insulating film capable of storing data and electrically writable and erasable, and has two ends on two opposite sides; At least one gate electrode provided on the charge storage region; and a first electrode provided in the semiconductor substrate.
A source electrode and a drain electrode of a conductivity type opposite to the conductivity type of the first electrode, and a source electrode and a drain electrode provided on the source electrode and the drain electrode, respectively. A current terminal that detects a state; and is disposed between the charge storage region and the gate electrode, and at least the current terminal is in a conductive state. When the direction orthogonal to the first direction is the second direction, in the second direction, in the surface facing the charge storage region compared to the lower part of the center of the gate electrode in the surface facing the charge storage region. A semiconductor device comprising: a second gate insulating film that is thick in the range of 0.6 nm to 50 nm below the edge of the gate electrode.

According to the present invention, it is possible to provide a semiconductor device in which the electrical characteristics of the gate insulating film in the vicinity of the element isolation region and the electrical characteristics of the gate insulating film other than in the vicinity of the element isolation region are equal, and a method for manufacturing the same. Furthermore, according to the present invention, it is possible to provide a highly reliable semiconductor device in which the charge retention characteristic deterioration is suppressed at the edges of two sides parallel to the direction in which the current between the source and drain flows among the four sides defining the element region. . Furthermore, according to the present invention, it is possible to provide a semiconductor device that suppresses variations in write / erase characteristics and data retention characteristics and threshold fluctuations at the edge of the gate electrode.

Next, embodiments of the present invention will be described with reference to the drawings. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, the drawings are schematic, and the relationship between the thickness and the planar dimensions, the ratio of the thickness of each layer, and the like are different from the actual ones. Accordingly, specific thicknesses and dimensions should be determined in consideration of the following description. Moreover, the part from which the relationship and ratio of a mutual dimension differ also in between drawings is contained.

First, a semiconductor device according to Embodiment 1 of the present invention will be described with reference to the drawings. In a floating gate type flash memory, self-aligned STI (Self-Aligned Sh
A prototype when a MONOS cell is formed by an allow Trench Isolation (SA-STI) process is shown in FIG.

Here, a plurality of shallow trench isolation regions 2 are formed on the semiconductor substrate 1.
A tunnel insulating film 3 made of a silicon oxide film is formed near the surface of the semiconductor substrate 1 between two adjacent shallow trench isolation regions 2. A charge storage layer 4 made of a silicon nitride film is formed on the tunnel insulating film 3. A block insulating film 5 made of a silicon oxide film is formed on the charge storage layer 4. This block insulating film 5 is integrated with the shallow trench isolation region 2 made of the same material. A gate electrode 6 is formed on the block insulating film 5 and the shallow trench isolation region 2.

In this case, the gate electrode 6 is formed with a shallow trench element isolation region after a portion sandwiched between the shallow trench element isolation regions 2 is formed first, and then an additional gate is formed on the shallow trench element isolation region 2. An electrode 6 is formed.

That is, since the gate electrode is formed in a different process depending on the location, a natural oxide film is included in the gate insulating film.

By adopting such a configuration, the sidewalk phenomenon can be improved as compared with MONOS using LOCOS type element isolation. In addition, since the charge storage layer 4 is not formed on the shallow trench element isolation region 2, data is lost due to the movement of charges to adjacent cells via the charge storage layer 4 on the element isolation region which has been generated conventionally. Can be prevented.

When SA-STI is used in this way, there is almost no thickening at the gate edge of tunnel insulating film 3 (the end of gate electrode 6 sandwiched between shallow trench isolation regions 2). However, when the semiconductor surface is oxidized for defect recovery after the trench formation, a bird's beak enters the polycrystalline silicon constituting the gate electrode 6 and the block insulating film 5 becomes thicker at the edge of the shallow trench isolation region. The bird's beak part 7 will be produced. That is, FIG. 3 shows an enlarged view of a contact portion between the shallow trench isolation region 2 and the gate electrode 6.

Furthermore, since the polycrystalline silicon constituting the gate electrode 6 recedes due to oxidation, the protruding portion 8 from which the shallow element isolation region 2 protrudes is formed. Thus, from the gate electrode 6 sandwiched between the shallow element isolation regions 2, the charge storage layer becomes larger than the width of the gate electrode 6, the charge storage layer has a longer length in the cross section of FIG. 9 is formed.

Here, even if a voltage is applied to the gate electrode 6, an electric field sufficient for writing / erasing is not applied from the gate electrode 6 to the protruding portion 9 in FIG. 2, and thus the threshold value of this region 9 cannot be controlled.

That is, FIG. 4 shows the subthreshold characteristics of the cell in the written state in the semiconductor memory device. (I) represents the characteristics at the center of the channel, whereas the characteristics at the channel edge (boundary with the element isolation region) represented by (II) indicate that the write threshold is lower than that at the center. There are features. This is because the gate insulating film is thickened at the edge portion, so that the write electric field is weakened and the write current is reduced.

The sub-threshold characteristic of such a cell as a whole cell has a hump in the low voltage portion as indicated by (III) in FIG.

FIG. 6 is a plot of subthreshold characteristics in both the written state and the erased state. The characteristic of the written state is indicated by (IV), and the characteristic of the erased state is indicated by (V). At the time of erasing, since the threshold value of the channel edge portion is higher than the threshold value of the channel central portion, the characteristics of the entire cell are not affected. Eventually, the influence of sidewalk reduction on the cell characteristics appears as deterioration of the writing characteristics.

An embodiment for solving the problem in the prototype using the SA-STI process will be described as follows.

FIG. 1 is a cross-sectional view in the row direction of a memory cell transistor and a select transistor in a memory portion of the semiconductor device of this embodiment. A tunnel insulating film 10 is formed on the semiconductor substrate 1 with a film thickness of about 0.
It is formed of a silicon oxide film or silicon oxynitride film of about 5 nm to 5 nm. here,
In the semiconductor substrate 1, a well having a conductivity type opposite to that of the semiconductor substrate may be formed in the vicinity of the surface. Further, another well having the same conductivity type as that of the semiconductor substrate may be formed on the opposite conductivity type well (the same applies hereinafter). On the tunnel insulating film 10, the charge storage layer 11 is, for example, 3
a silicon nitride film or a silicon oxynitride film having a thickness of about 30 nm to 30 nm, Ta ₂ O ₅ , TiO ₂ ,
It is formed of an insulating film such as Al ₂ O ₃ . On the charge storage layer 11, a block insulating film 12 is provided.
Is formed of, for example, a silicon oxide film or a silicon oxynitride film having a thickness of about 1 nm to 20 nm.

The tunnel oxide film 10, the charge storage layer 11 and the block insulating film 12 have a depth of about 20 for example.
Shallow trench element isolation region 13 made of a silicon oxide film or the like of about nm to 500 nm
Are separated from each other. On the shallow trench isolation region 13 and the block insulating film 12, the first gate electrode 14 of the memory cell is, for example, polycrystalline silicon and has a thickness of about 5n.
The second gate electrode 15 is formed of, for example, polycide or metal at m to 500 nm. Here, for example, WSi, NiSi, MOSi, TiSi, CoSi or the like can be applied as the polycide.

A gate cap insulating film 16 is formed on the second gate electrode 15 with a silicon nitride film or the like.
Is formed. On the gate cap insulating film 16, a barrier insulating film 31 is formed of a silicon nitride film or the like. An interlayer film 17 is formed on the barrier insulating film 31. A bit line 18 is buried near the upper surface of the interlayer film 17. A protective film 19 is formed on the bit line 18 and the interlayer film 17.

Here, the surface of the semiconductor substrate 1 below the first gate electrode 14 between the two shallow trench isolation regions 13 forms a channel. Tunnel oxide film 10, charge storage layer 11 and block insulating film 1 sandwiched between two shallow trench element isolation regions 13
No. 2 is formed so that the film thickness is substantially equal between the vicinity of the center of the channel and the portion in contact with the shallow trench isolation region 13. Note that at least the thickness of the block insulating film 12 under the first gate 14 is formed substantially equal in the vicinity of the center of the channel and in the portion in contact with the shallow trench isolation region 13.

Further, the thickness of the tunnel oxide film 10 on the semiconductor substrate 1 is formed substantially equal between the vicinity of the center of the channel and the portion in contact with the shallow trench isolation region 13. In some cases, the tunnel oxide film 10 may be formed on the semiconductor substrate 1, the charge storage layer 11 may be formed thereon, and the first gate 14 may be directly formed thereon. The tunnel oxide film 10, the charge storage layer 11, and the block insulating film 12 sandwiched between the shallow trench element isolation regions 13 are formed to have substantially the same length in the row direction. It is in contact with the side in the same horizontal plane In addition, the first gate electrode 14 also includes the tunnel oxide film 10, the charge storage layer 11, and the block insulating film 1 in which the length in the row direction sandwiched between the shallow trench element isolation regions 13 is sandwiched between the shallow trench element isolation regions 13.
2 is substantially equal to the length in the row direction.

Here, the first gate 14 is formed directly on the shallow trench isolation region 13, and the tunnel oxide film 10, the charge storage layer 11 and the block insulating film 12 are not interposed therebetween. Therefore, the charge is prevented from moving to the adjacent gate via the charge storage layer 11. In addition, a notch that is a depression may occur at the upper end of the shallow trench isolation region 13.

  Next, a cross section in the row direction of the high voltage transistor in the peripheral circuit portion is shown in FIG.

Here, a silicon oxide film or a silicon oxynitride film having a thickness of, for example, about 8 nm to 40 nm is formed on the semiconductor substrate 1 as the gate insulating film 20. Gate insulating film 2 on semiconductor substrate 1
A shallow trench isolation region 21 is formed so as to divide zero. The depth of the shallow trench isolation region 21 depends on the thickness of the gate insulating film 20 of the high breakdown voltage transistor than the thickness of the shallow trench isolation region 13 in the memory portion, and the tunnel oxide film 10 in the memory portion.
It is formed shallower by subtracting the thickness of.

On the shallow trench isolation region 21 and the gate insulating film 20, a first gate electrode 22 having the same composition and the same film thickness as the first gate electrode 14 of the memory portion is formed. This first
On the gate electrode 22, a second gate electrode 23 having the same composition and the same film thickness as the second gate electrode 15 of the memory portion is formed. On the second gate electrode 23, a gate cap insulating film 24 having the same composition as the gate cap insulating film 16 of the memory portion and having the same film thickness is formed. On this gate cap insulating film 24, as shown in FIG.
The interlayer film 17 and the like are formed, but the illustration is omitted.

Here, the gate insulating film 20 is formed so that the film thickness thereof is substantially equal at the portion in contact with the shallow trench isolation region 21 and at the center of the channel. That is, unlike the conventional example and prototype, the portion of the gate insulating film that contacts the shallow trench isolation region is not formed thicker than the other portions.

The gate insulating film 20 sandwiched between the shallow trench isolation regions 21 has a length in the row direction substantially equal to the length in the row direction of the portion where the first gate electrode 22 is sandwiched between the shallow trench isolation regions 21. Are equal. In addition, a notch that is a depression is formed at the upper end of the shallow trench isolation region 21. This notch is formed to have a larger depth than the notch of the memory portion.

Next, a cross section in the row direction of the peripheral low voltage transistor is shown in FIG. Here, the gate insulating film 25 is formed on the semiconductor substrate 1 as a silicon oxide film or silicon oxynitride film having a film thickness of, for example, about 0.5 nm to 10 nm. A shallow trench isolation region 26 is formed so as to divide the gate insulating film 25 on the semiconductor substrate 1. The thickness of the shallow trench element isolation region 26 is substantially equal to the depth of the shallow trench element isolation region 13 of the memory portion.

On the shallow trench isolation region 26 and the gate insulating film 25, a first gate electrode 27 having the same composition and the same thickness as the first gate electrode 14 of the memory portion is formed. This first
On the gate electrode 27, a second gate electrode 28 having the same composition and the same film thickness as the second gate electrode 15 of the memory portion is formed. On the second gate electrode 28, a gate cap insulating film 29 having the same composition and the same film thickness as the barrier insulating film 16 of the memory portion is formed.
On the gate cap insulating film 29, as shown in FIG. 1, a barrier insulating film 31, an interlayer film 17 and the like are formed, but illustration thereof is omitted.

Here, the gate insulating film 25 is formed so that the film thickness thereof is substantially equal at the portion in contact with the shallow trench isolation region 26 and at the center of the channel. That is, unlike the conventional example and prototype, the portion of the gate insulating film that contacts the shallow trench isolation region is not formed thicker than the other portions.

The gate insulating film 25 sandwiched between the shallow trench isolation regions 26 has a length in the row direction substantially equal to the length in the row direction of the portion where the first gate electrode 27 is sandwiched between the shallow trench isolation regions 26. Are equal. Further, a notch that is a depression is formed at the upper end of the shallow trench isolation region 26. This notch is formed to have a larger depth than the notch of the memory portion. In addition, the height from the semiconductor substrate surface to the upper portion of the shallow trench in the peripheral portion is formed lower than the height from the semiconductor substrate surface to the upper portion of the shallow trench in the memory portion.

Relationship between the gate insulating film having this structure, the STI depth as the element isolation region for each type of gate insulating film having a structure in which the gate electrode is separately formed, the size of the recess at the upper edge of the STI, the gate electrode width and the semiconductor substrate width Table 1 shows the curvature radius of the edge and the characteristics of the gate electrode.

As can be seen from Table 1, the STI depth as the element isolation region is the depth B when the gate insulating film is a thin film of ONO or a silicon oxide film and the depth B when the gate insulating film is a thick film of a silicon oxide film. It is deeper than that.

The size of the recess at the upper edge of the STI is the size C when the gate oxide film is ONO.
Is smaller than the size D of the silicon oxide film.

Regardless of the type of gate insulating film, the width of the gate electrode sandwiched between the two element isolation regions is larger than the width of the semiconductor substrate sandwiched between the same two element isolation regions.

Further, the radius of curvature at the edge portion where the gate electrode is in contact with the element isolation region is smaller than the radius of curvature at the edge portion in the vicinity of the gate electrode where the semiconductor substrate is in contact with the element isolation region. Furthermore, the gate electrode can be separately formed by a P plus electrode and an N plus electrode. That is, a P plus electrode transistor and an N plus electrode transistor are mixed in the semiconductor device, and the gate electrode films of both are formed to have the same film thickness.

Here, FIG. 9 shows a plan view of the memory section of the present embodiment. In this plan view, “
A cross-sectional view taken along line AA ″ corresponds to FIG. 1. As shown in FIG. 9, a plurality of bit lines are linearly arranged in parallel with each other at regular intervals in the vertical direction. (BL) 43 is arranged, and a plurality of data selection lines (word lines) 40 are arranged below and orthogonal to the bit line 43 and in parallel with each other below each bit line 43. Each word line 40 (WL0). To WL31), the shallow trench element isolation region 13 is formed other than under the bit line 43 to isolate the source / drain region 30. The bit line selection signal line 41 of the bit line 43 is electrically isolated. A bit line contact 44 is formed in the adjacent source / drain region 30. A ground potential is applied to the source / drain region 30 adjacent to the common source line selection signal line 42 of the bit line 43. 9, the data selection line 40 is indicated by diagonal lines, the shallow trench element isolation region 13 is indicated by a dot pattern, and the source / drain regions 30 are indicated by diagonal grids. Displayed in a pattern.

  The configuration shown in FIG. 9 is actually formed repeatedly in the vertical direction in FIG.

In the sectional view of the memory portion in the column direction shown in FIG. 10, a plurality of source / drain regions 30 are provided on the semiconductor substrate 1. A tunnel oxide film 10, a charge storage layer 11, and a block insulating film 12 are provided on the semiconductor substrate 1. A plurality of gates including the first gate electrode 14 and the second gate electrode 15 are formed on the block insulating film 12 in the gate formation portion. A gate cap insulating film 16 is provided to cover the gate forming portion.
A barrier insulating film 31 is further provided to cover the gate cap insulating film 15 and the exposed block insulating film 12.

The bit line contact 44 is formed near the right end in FIG. The bit line contact 44 is connected to a bit line lead wiring 47. This bit line lead wiring 4
The bit line lead contact 46 is connected to the bit line lead contact 46.
Is connected to the bit line 18.

The source line contact 45 is formed near the left end in FIG. The source line contact 45 is connected to the source line wiring 48.

Each gate forming portion, bit line contact 44, bit line lead wiring 47, bit line lead contact 46, source line contact 45, and source line wiring 48 are covered with an interlayer film 17.

The bit line 18 and the interlayer film 17 are covered with a protective film 19. Note that a twin well configuration may be employed in which a first well having a conductivity type opposite to that of the semiconductor substrate is provided on the semiconductor substrate, and a second well having the same conductivity type as that of the semiconductor substrate is provided thereon.

FIG. 11 is a circuit diagram showing a part of FIG. Here, the array structure of the memory cells is a NAND type, and one end of the memory cells connected in series is the selection transistor (S1) 50.
And the other end is connected to the select transistor (S2).
) 51 to the source line contact 45.

The gate electrodes of the memory cell transistors (M0 to M31) 52 connected in series are connected to the data selection lines (WL0 to WL31) 40. Select transistor (S1
) 50 is connected to the bit line selection signal line (SSL) 41, and the gate electrode of the selection transistor (S2) 51 is connected to the common source line selection signal (GSL). A column of the memory cell transistors 52 sandwiched between the selection transistor (S1) 50 and the selection transistor (S2) 51 is called a NAND string. Thousands of NAND strings are connected in series. When a semiconductor memory device is formed by connecting thousands of select lines, bit lines, and common source lines, a semiconductor memory device having a storage capacity of several M bits is obtained.

In this embodiment, the selection transistors 50 and 51 have the same MONOS structure as that of the memory cell transistor 52. For this reason, it is not necessary to separately form a gate insulating film between the memory cell and the selection transistor, which is suitable for miniaturization of the element and cost reduction. In addition, there are two types of transistors that form a peripheral circuit and have a MOS structure and different gate oxide thicknesses. Note that this embodiment can be applied to the transistors constituting the peripheral circuit even when there are three or more gate oxide film thicknesses.

According to the present embodiment, it is possible to solve the sidewalk phenomenon resulting from the deterioration of the write / erase characteristics at the edge of the element isolation region, and to speed up the write / erase operation.

Hereinafter, a method of manufacturing the semiconductor device of this example will be described with reference to FIGS. Here, a manufacturing method in the row direction in the cross section shown in FIGS. 1, 7 and 8 in which the features of the present embodiment are shown will be described. 12 to 27, (a) is a process diagram showing a method for manufacturing a memory cell transistor and a select transistor in a memory portion, and (b) is a process showing a method for manufacturing a low voltage transistor in a peripheral circuit portion. FIG. 6C is a process diagram illustrating a method for manufacturing a high voltage transistor in the peripheral circuit portion.

First, as shown in FIGS. 12A, 12 </ b> B, and 12 </ b> C, 5 nm to 20 nm on the semiconductor substrate 1.
After a sacrificial oxide film (not shown) of about nm is formed, the wells and channel impurities of the memory part and the peripheral circuit part are implanted as needed (not shown). After removing the sacrificial oxide film, a gate insulating film 20 of the high voltage transistor in the peripheral circuit portion is formed on the entire surface of the semiconductor substrate 1. here,
The gate insulating film 20 is, for example, a silicon oxide film or silicon oxynitride film having a thickness of about 8 nm to 40 nm, and is adjusted so that the film thickness finally reaches a target film thickness by calculating back from the amount of film thickness variation in a later process. It is necessary to keep.

Next, as shown in FIG. 13C, in the high breakdown voltage transistor portion, the entire resist 55 is formed.
In the memory portion and the low voltage transistor portion shown in FIGS. 13A and 13B, the gate insulating film 20 is peeled off.

Next, after removing the resist 55 as shown in FIG. 14C, FIGS.
), For example, 0.5 nm as the tunnel insulating film 10 of the MONOS memory cell
A silicon oxide film or silicon oxynitride film having a thickness of ˜5 nm is formed.

Next, as shown in FIGS. 15A, 15B, and 15C, the charge storage layer 11 is formed to 3 nm, for example.
Silicon nitride film or silicon oxynitride film having a thickness of about 30 nm, Ta ₂ O ₅ , TiO ₂ , Al ₂
A silicon oxide film or silicon oxynitride film having a thickness of 1 nm to 20 nm is formed as the block insulating film 12 by depositing with an insulating film such as O ₃ .

Next, as shown in FIGS. 16A, 16B, and 16C, for example, 10 as a stopper film 56 of CMP (Chemical Mechanical Polishing) for flattening the filling material in the element isolation region.
A silicon nitride film of about nm to 500 nm is deposited. Here, the conditions required for the stopper film 56 are: (1) that there is a sufficient selection ratio with respect to the filling material in the element isolation region as a CMP stopper film, and (2) MONOS when the stopper film 56 is peeled off. (3) After anisotropic etching for forming an element isolation region, the substrate surface is oxidized to recover damage, but at this time, the film is not oxidized. It is necessary to satisfy at least three points.

Here, when the buried film and the block insulating film in the element isolation region are oxide films, a silicon nitride film is suitable as the stopper film 56. Further, for example, a silicon oxide film is deposited to a thickness of 20 to 500 nm as a mask material 57 for anisotropic etching in the element isolation region. In the high voltage transistor region shown in FIG. 16C, the gate insulating film 20 is formed as shown in FIG.
) And (b) are thicker than the tunnel insulating film 10 in the memory portion and the low-voltage transistor region, and the upper surface of the mask material 57 shown in FIG. a), (
It is formed higher than the upper surface of the mask material 57 shown in b).

Next, as shown in FIGS. 17A, 17B, and 17C, a resist (not shown) is patterned and the mask material 57 is processed by anisotropic etching, followed by a stopper film 56 and a block. After the insulating film 12, the charge storage layer 11, the tunnel oxide film 10, and the gate insulating film 20 are processed, the semiconductor substrate 1 is etched to a desired depth to form element isolation grooves (trench grooves) 58, 59, 60.
Form.

At this time, in the region shown in FIG. 17C, the thickness of the gate insulating film 20 formed on the semiconductor substrate 1 is the thickness of the tunnel insulating film 10 shown in FIGS. Therefore, the depth of the element isolation groove 60 is shallower than the depth of the element isolation grooves 58 and 59 shown in FIGS. 17A and 17B, corresponding to the additional thickness. ing. Further, since the size of the transistor in the memory portion is smaller than that in the peripheral circuit portion, the width of the element isolation groove 58 and the interval between the element isolation grooves are smaller than the element isolation grooves 59 and 60 in the peripheral circuit portion.

Next, as shown in FIGS. 18A, 18B, and 18C, in order to recover damages such as defects that have entered the semiconductor substrate 1 by etching, an element is isolated by annealing in an oxidizing atmosphere. A silicon oxide film 61 having a thickness of 2 nm to 50 nm, for example, is formed on the surface of the semiconductor substrate 1 in the trench. At this time, the mask material 57 is not oxidized, and hence no bird's beak enters, so that the block insulating film 12 is not thickened at the element isolation end.

As described above, the thickness of the block insulating film 12 on the center of the channel region and the portion in contact with the shallow trench isolation region becomes equal. Here, the equal film thickness means that the physical film thickness is substantially equal. Specifically, the difference in film thickness between the element isolation edge and the channel center is less than about 2 nm. It is desirable to be small, preferably about 1 nm or less. That is, when the difference in film thickness is 2 nm, a side walk phenomenon occurs. As a result, it is possible to prevent the deterioration of the write / erase characteristics at the element isolation end, and it is possible to obtain good transistor characteristics without a sidewalk phenomenon.

Next, as shown in FIGS. 19A, 19B, and 19C, element isolation trenches 58, 59, and 60 are filled with element isolation insulating films (embedding materials) 62, 63, and 64, respectively, and then CMP is performed. The upper surface of each element isolation insulating film 62, 63, 64 is planarized by the method. Each element isolation insulating film is formed so that the upper surface thereof is, for example, about 100 nm to 300 nm from the surface of the semiconductor substrate.

Next, as shown in FIGS. 20A, 20 </ b> B, and 20 </ b> C, the mask material 57 is peeled off by phosphoric acid heated to 80 to 200 ° C., for example. The block insulating film 12 is exposed on the surface after the mask material 57 is peeled off. At this time, depending on the peeling condition of the mask material 57, the recesses 65 having substantially the same size are formed on the upper surface end portions of the element isolation insulating films 62, 63, 64.

Next, after the memory cell transistor region and the select transistor region are covered with a resist 66 as shown in FIG. 21A, the block insulating film in the peripheral circuit region is shown in FIGS. 21B and 21C. 12 and the charge storage layer 11 are removed using isotropic etching such as CDE (Chemical Dry Etching).

At this time, recesses 67 having substantially the same size are formed on the upper surface end portions of the element isolation insulating films 63 and 64 in the peripheral circuit portion. This dent 67 is a dent 65 formed in the previous step.
The size is larger than. The depth of the recess 67 is, for example, 5 nm or more. Further, since the element isolation insulating film 62 in the memory portion is covered with the resist 66 in this step, the size of the recess 65 does not change. Or a recessed part is not formed.

Further, the insulating film may be removed from the peripheral circuit region, for example, only the block insulating film 12 may be subjected to anisotropic etching such as RIE. In this case, the height of the upper surface of the element isolation region in the peripheral circuit region from the surface of the semiconductor substrate becomes lower than the height of the upper surface of the element isolation region in the memory portion from the surface of the semiconductor substrate by etching. In this case, the STI depth of the element isolation region from the surface of the semiconductor substrate for each type of gate insulating film, the height from the surface of the semiconductor substrate above the STI, the relationship between the gate electrode width and the width of the semiconductor substrate, the curvature of the edge Table 2 summarizes the characteristics of the radius and the gate electrode.

As can be seen from Table 2, the STI depth as the element isolation region is the depth B when the gate insulating film is a thin film of ONO or a silicon oxide film, and the depth B when the gate insulating film is a thick film of a silicon oxide film. It is deeper than that.

In addition, the height of the STI from the upper surface of the semiconductor substrate is such that the height E when the gate oxide film is ONO is higher than the height F when the gate oxide film is a silicon oxide film. Regardless of the type of gate insulating film, the width of the gate electrode sandwiched between the two element isolation regions is larger than the width of the semiconductor substrate sandwiched between the same two element isolation regions.

Further, the radius of curvature at the edge portion where the gate electrode is in contact with the element isolation region is smaller than the radius of curvature at the edge portion in the vicinity of the gate electrode where the semiconductor substrate is in contact with the element isolation region. Furthermore, the gate electrode can be separately formed by a P plus electrode and an N plus electrode.

When silicon oxide films are used for the block insulating film 12 and the element isolation insulating films 62, 63, 64, the upper portions of the element isolation insulating films 63, 64 are also etched when the block insulating film 12 is peeled off to form a recess 67. However, when the charge storage layer 11 in contact with the side surfaces of the element isolation insulating films 63 and 64 is a silicon nitride film, there is a sufficient selection ratio with the silicon oxide film at the time of etching. The side surface is side-etched and divots are not generated.

Thus, after the charge storage layer 11 is peeled off, the tunnel insulating film 10 is exposed in the low voltage transistor region as shown in FIG. 21B, and in the high voltage transistor region as shown in FIG. 21C. The gate insulating film 20 for high voltage transistors is exposed.

Next, after removing the resist 66 in the memory cell transistor region as shown in FIG. 22A, the gate insulating film 25 is formed in a low voltage transistor region as shown in FIG. A silicon oxide film or silicon oxynitride film having a thickness of 10 nm is formed.

At this time, the gate insulating film 25 is formed by thermal oxidation, so that the block insulating film 1 of the memory portion is formed.
2 and the gate insulating film 20 of the high voltage transistor can obtain a densifying effect at the same time, so that it is possible to recover damage when the mask material 57 and the charge storage layer 11 are peeled off, and the reliability of the memory cell and the peripheral circuit is improved. Can be improved.

Next, as shown in FIGS. 23A, 23B, and 23C, gate electrode materials 68, 69,
70, for example, undoped polycrystalline or amorphous silicon of 5 nm to 500 n
The film is deposited to a thickness of m.

Next, as shown in FIGS. 24A, 24B, and 24C, gate electrode materials 68, 69,
For example, a silicon oxide film 71 having a thickness of about 10 nm is deposited on 70. This is to suppress the escape of impurities from the electrode during the subsequent impurity implantation into the gate electrode.

Next, as shown in FIG. 25A, the memory cell region is covered with a resist 72, and FIG.
As shown in (b) and (c), n-type gate electrodes 27 and 22 are formed by implanting, for example, phosphorus or arsenic at 10E19 cm ⁻³ or more into the gate electrode of the peripheral transistor.

Next, as shown in FIG. 26A, after removing the resist 72, this time, only the peripheral circuit portion is covered with the resist 73, and boron is implanted into the memory cell portion by 10E19 cm ⁻³ or more, for example. A first gate electrode 14 is formed.

Next, as shown in FIGS. 27A, 27B, and 27C, the first gate electrodes 14, 27 are provided.
, 22 after peeling off the oxide film 71, WSi, NiSi, MoSi, TiSi, CoSi
Or the like is deposited to form gate electrodes 15, 28, and 23. Thereafter, although not shown, a barrier insulating film 31, an interlayer film 17, a bit line 18, a protective film 19 and the like are sequentially formed.

In this embodiment, each gate electrode has a stack structure of polysilicon doped with impurities and polycide. However, the present invention is not limited to this, and a polymetal or a metal electrode may be used. In addition, the polysilicon impurity is divided into the memory cell portion and the peripheral circuit portion. However, the present invention is not limited to this, and the method of making the impurities may be changed so as to obtain desired transistor characteristics and cell characteristics. , You don't have to make it. If not separately formed, impurity implantation into polysilicon is not limited to implantation, and polycrystalline silicon doped with arsenic, phosphorus, boron, or the like may be deposited in the step of FIG.

Note that when amorphous silicon is deposited in the process of FIG. 23, it is changed to polysilicon in the subsequent thermal process. As a material for the gate electrode, it is preferable to use a metal material when low resistance is required. However, when a metal is used, the temperature applied in the manufacturing process after the formation of the gate electrode is polysilicon or the like. Compared with this, high temperature cannot be used, and the manufacturing process is limited. Therefore, a gate electrode material is appropriately selected depending on the trade-off relationship between low resistance and heating temperature during the manufacturing process.

In the steps shown in FIGS. 25 and 26, not only the gate electrode but also channel impurity implantation and well impurity implantation may be performed. Impurity implantation after passing through high-temperature processes such as gate insulation film formation and element isolation trench surface oxidation avoids diffusion of impurities due to thermal processes, resulting in a sharper impurity profile and improved device characteristics Can do.

Although the process after gate electrode deposition is not shown, patterning is performed by lithography,
After forming the diffusion layer, an interlayer film is deposited and contacts and wirings are formed to form a MISFET.

According to this embodiment, since the gate insulating film is formed before the element isolation film forming step, it is possible to control the channel edge and the center to have the same film thickness with good control. Furthermore, since the polycrystalline silicon serving as the gate electrode is deposited after the element isolation, the bird's beak does not enter due to the oxidation after the trench formation. As a result, problems such as thickening and thinning of the gate insulating film at the channel edge can be avoided and the device characteristics can be improved.

Furthermore, since the side walls of the gate electrode are not oxidized, the side walls of the gate electrode can be positioned on the same plane as the edge of the gate insulating film, and a uniform electric field can be applied to the entire gate insulating film during writing and erasing. Further, in the present invention, the tunnel oxide film of the memory cell transistor is further oxidized to form the gate insulating film of the MOS transistor, so that the wet treatment before the gate oxidation is unnecessary and the formation of the depression on the side surface of the shallow trench isolation is avoided. it can.

In addition, since this gate oxidation acts as a densification on the barrier insulating film and the oxide film in the peripheral circuit portion, it closes the pinhole that may be formed by wet processing etc., and improves the reliability of the memory cell and the transistor in the peripheral circuit portion. Can be improved.

Further, the width in the channel direction of the gate insulating film and the width in the channel direction of the portion of the gate electrode sandwiched by the shallow trench isolation can be formed to improve the transistor characteristics.

In addition, the gate electrodes are simultaneously deposited for all the transistors, and it is not necessary to attach polycrystalline silicon twice between the part sandwiched by the element isolation region and the part on the element isolation region. This leads to a reduction in cost and a reduction in cost can be realized.

In addition, the number of steps for separately forming the gate insulating film (MONOS structure and MOS structure) and forming the gate electrode (P plus gate and N plus gate) is reduced, thereby realizing cost reduction.

If undoped polycrystalline silicon is used as the gate electrode, it is easy to make a P plus gate and an N plus gate separately for the memory cell and the peripheral transistor.

In this case, since the polycrystalline silicon of the gate electrode is formed at the same time in the P plus portion and the N plus portion, the film thickness becomes equal, so that the subsequent processing of the gate electrode becomes easy.

Furthermore, since the gate electrode of the memory part and the gate electrode of the peripheral circuit part can be formed simultaneously,
The number of manufacturing processes can be reduced.

Further, in the memory portion and the peripheral circuit portion, one can be a P plus portion and the other can be an N plus portion. Further, both the P plus portion and the N plus portion can be formed in the memory portion and the peripheral circuit portion, respectively. In this case, in the memory unit, for example, P-type impurities are introduced into a large number of cell transistors in the memory unit, N-type impurities are introduced into a smaller number of selection transistors than the cell transistors, and a large number of peripheral circuit units are formed. It can be formed by introducing a P-type impurity into a low voltage transistor and introducing an N-type impurity into a small number of high voltage transistors.

When this process is used in a NAND flash memory, the number of steps is not increased by making the selection transistor have the same gate insulating film structure as the memory cell transistor.

When the P plus portion and the N plus portion are mixed, both the P-type impurity and the N-type impurity are implanted into the semiconductor substrate, the element isolation region, or the gate electrode at the boundary between the P plus portion and the N plus portion. Yes. Depending on the size of the boundary between the P plus portion and the N plus portion, P-type impurities,
None of the N-type impurities are implanted.

The second gate electrodes 15, 28, 23 formed on the shallow trench isolation region.
Is formed between the element isolation regions without including a natural oxide film in each gate film.
The gate electrodes 14, 27, and 22 are integrally formed, the resistance value is kept constant, and the gate electrode is formed in two stages in the prior art as compared with the case where the gate electrode is formed through a natural oxide film. Controllability is improved.

This embodiment is effective when the charge storage insulating film can be formed without being damaged by processing.

In this embodiment, the semiconductor memory device having the MONOS structure has been described as an example. However, this embodiment is not limited to the semiconductor memory device having the MONOS structure, and the electrical characteristics of the gate insulating film can be improved. The present invention can be applied to all semiconductor devices having necessary miniaturized MOS transistors.

In the second embodiment of the present invention, the structure of the selection transistor in the memory section is the same as that of the low voltage transistor in the peripheral circuit section shown in FIG. Thus, the gate insulating film of the select transistor has a MOS structure instead of a MONOS structure. A cross-sectional view of the memory portion in the column direction is as shown in FIG. 28, and the shape of the memory cell transistor is the same as that of the first embodiment. Unlike the first embodiment, the configuration of the gate insulating film in the selection transistor portion is configured by the gate insulating film 25 of the low voltage transistor.

A circuit diagram of this embodiment is as shown in FIG. 29. Similarly to the first embodiment, select transistors (S1, S2) 50 respectively connected to both ends of memory cell transistors (M0 to M31) 52 connected in series. , 51 is represented as a MOS structure instead of MONOS.
Other configurations are the same as the circuit diagram of the first embodiment shown in FIG.

In this embodiment, since the silicon nitride film is not used for the gate insulating film of the selection transistor, the threshold voltage of the selection transistor is not changed by the stress of the gate voltage or the drain voltage during the operation of the semiconductor memory device. A highly reliable semiconductor memory device with high performance can be realized.

As the gate insulating film 25 of the selection transistor, for example, a silicon oxide film or a silicon oxynitride film of about 0.5 nm to 10 nm can be cited. However, the process steps can be reduced by using the same formation conditions as the low voltage transistor in the peripheral circuit portion. Desirable for. That is, the manufacturing method of the present embodiment applies the same manufacturing process as that of the low-voltage transistor in the peripheral circuit section without using the same manufacturing process as the memory cell transistor in the memory section in the manufacturing method in the first embodiment. This is realized.

When this process is used in a NAND flash memory, the number of manufacturing steps is not increased by making the selection transistor have the same gate insulating film structure as the low voltage transistor in the peripheral circuit portion.

In this embodiment, the semiconductor memory device having the MONOS structure has been described as an example. However, this embodiment is not limited to the semiconductor memory device having the MONOS structure, and the electrical characteristics of the gate insulating film can be improved. The present invention can be applied to all semiconductor devices having necessary miniaturized MOS transistors.

The semiconductor device according to the third embodiment of the present invention is used particularly in a memory cell using an insulating film as a charge storage layer.

FIG. 30 shows a MONOS type memory cell using a self-aligned STI which is a prototype of this embodiment. FIG. 30A shows a top view of the prototype of the present embodiment, in which the element region 111 is linearly formed in the left-right direction surrounded by the element isolation region 110. A gate electrode 112 is formed perpendicular to the longitudinal direction of the impurity region. In the element region 111, a pair of contacts 113 is provided on the left and right sides of the gate electrode 112. Further, the gate electrode is provided with a wide region at the end thereof, and a contact 114 is provided there. In this memory cell, element regions 111 on both sides of the gate electrode 112 are used.
Becomes the source diffusion layer 115 and the drain diffusion layer 116, and when data is read, the writing state and the erasing state are determined by the amount of current flowing from the source diffusion layer 115 to the drain diffusion layer 116 in the C to D direction indicated by the arrows in FIG. Is determined. Such a structure is NAND
Used in type EEPROM, NOR type EEPROM, and the like.

A cross-sectional view along the “CD” line in FIG. 30A is shown in FIG. A gate electrode 112 is formed on the semiconductor substrate 117, and a source diffusion layer 115 and a drain diffusion layer 116 are formed in the semiconductor substrate 117 on both sides thereof. The gate electrode 112 is stacked on a gate insulating film including a tunnel insulating film 118, a data retention insulating film (charge storage region) 119, and a block insulating film 120. An interlayer insulating film 121 is formed on the surfaces of the semiconductor substrate 117 and the gate electrode 112.

In addition, a cross-sectional view taken along the line “EF” in FIG. 30A is shown in FIG.
An element isolation trench 122 is provided in the semiconductor substrate 117, and an element isolation region 110 is formed therein. A gate insulating film including a tunnel insulating film 118, a data holding insulating film 119, and a block insulating film 120 is formed between the element isolation regions 110. A gate electrode 112 is formed on the block insulating film 120 so as to extend to the element isolation region 110.

In the method of manufacturing the memory cell shown in FIGS. 30B and 30C,
Since the edge of the data retention insulating film is exposed to anisotropic etching plasma during the etching process for forming the element isolation trench and the etching process of the gate electrode and the gate insulating film,
In some cases, the data holding insulating film is damaged at the edge of the element isolation region and the edge of the gate, so that the charge holding power at the edge of the data holding insulating film is deteriorated and the reliability of the memory cell is impaired.

In the case of a memory cell having the structure shown in FIG. 30, deterioration of the characteristics of the data retention insulating film at the edge of the element isolation region may be a serious problem. This is explained below.
In the cross section shown in FIG. 30B, the memory cell transistors are formed as (I), (II), (
It is divided into the area III). Here, the data holding insulating film in the regions (I) and (III) is a damaged region 123 that is damaged. Similarly, in the cross section shown in FIG. 30C, the memory cell transistor is divided into regions (IV), (V), and (VI). Here, the data holding insulating films (IV) and (VI) are damaged areas 124 which are damaged.

Here, it is assumed that the data retention insulating film traps electrons to increase the threshold value (write state). FIG. 31A shows a circuit diagram of a transistor corresponding to the cross section of FIG. 30B, FIG. 31B shows a circuit diagram of a transistor corresponding to the cross section of FIG. FIG. 31C shows the gate voltage on the horizontal axis and the drain current on the vertical axis, and shows changes in current-voltage characteristics for each state of the data retention insulating film. The circuit diagram shown in FIG. 31A shows a configuration in which three transistors (I), (II), and (III) having gates connected in common are connected in series between a source and a drain. This transistor (I), (II), (III)
Corresponds to the regions of the memory cell transistors (I), (II), and (III) in FIG. In addition, the circuit diagram shown in FIG. 31B shows a configuration in which three transistors (IV), (V), and (VI) whose gates are commonly connected are connected in parallel between the source and the drain. . The transistors (IV), (V), (VI) are shown in FIG.
Each region corresponds to the memory cell transistors (IV), (V), and (VI) in (C).

Since the charge retention characteristic is deteriorated at the edge portion of the data retention insulating film, electrons are easily desorbed. In the case of a memory cell having a structure using an insulating film as a charge storage region typified by a MONOS type memory cell, the region (I), (II), (III) or (IV), (V), (
Since the movement of charge is not performed between (VI), the threshold is lowered in the region (edge portion) from which the charge is lost compared to the central portion of the channel. Here, the cross section shown in FIG. 30B represents a channel in the direction in which the current flows. When a transistor is connected in series in the direction in which the current flows, the threshold value of any of the transistors becomes low. However, the threshold value as a whole does not change.

Here, since the regions (I), (II), and (III) are arranged in series between the source and the drain, even if the threshold values of the regions (I) and (III) are lowered, the threshold value of the region (II) Is high, no current flows between the source and the drain, and a decrease in the threshold value of the gate edge is not detected as a decrease in the threshold value of the memory cell. On the other hand, since the regions (IV), (V), and (VI) are connected in parallel between the source and the drain, a current flows between the source and the drain when the threshold values of the regions (IV) and (VI) are lowered. A threshold value decrease at the edge portion of the element isolation region is detected as a memory cell threshold value decrease. This situation is shown in FIG. That is, the gate voltage is almost the same in each region immediately after writing, but the gate voltage at the edge portions (IV) and (VI) decreases more than the central portion (V) in the writing state with time. The voltage of the erased state is approaching. That is, the charge retention characteristic of the memory cell is determined by the charge retention characteristic of the damaged part.

As described above, when the MONOS type memory cell is formed with the self-aligned STI structure, the deterioration of the data retention characteristics of the charge storage region at the edge of the element isolation region or the edge of the gate electrode is affected by the reliability of the memory cell. In particular, there is a case where deterioration of charge retention characteristics at the edges of two sides parallel to the flow direction of the current between the source and drain among the four sides defining the element region may be a problem. The present embodiment provides a method for solving the above problems.

Next, FIG. 32 shows a MONOS type memory cell using the self-aligned STI of this embodiment. FIG. 32A shows a top view of the semiconductor device of this example, and the element isolation region 13 is shown.
Surrounded by 0, the element region 131 is linearly formed in the left-right direction. This element region 13
A gate electrode 132 is formed perpendicular to the longitudinal direction of 1. The element region 131 is provided with a pair of contacts 133 on the left and right sides of the gate electrode 132. Further, the gate electrode 132 is provided with a wide region at the end thereof, and there is a gate contact 1 there.
34 is provided.

In this memory cell, the element region 131 on both sides of the gate electrode 132 is the source impurity region 13.
5. A drain impurity region 136 is formed, and at the time of data reading, the writing state and the erasing state are discriminated by the amount of current flowing from the source impurity region 135 to the drain impurity region 136 in the G to H direction indicated by the arrow in FIG. . Such a structure is a NAND type EE.
Used in PROM, NOR type EEPROM, etc.

A cross-sectional view on the “GH” line in FIG. 32A is shown in FIG. A gate electrode 132 is formed on the semiconductor substrate 137, and a source diffusion layer 135 and a drain diffusion layer 136 are formed in the semiconductor substrate 137 on both sides thereof. The gate electrode 132 includes a first gate 138 in the lower layer and a second gate 139 thereon. The gate electrode 132 is
Tunnel insulating film 140, data retention insulating film (charge storage region) 141, block insulating film 14
2 is laminated on the gate insulating film. A gate sidewall insulating film 143 is provided on the side surface of the gate electrode 132. An interlayer insulating film 144 is formed on the surfaces of the semiconductor substrate 137, the gate electrode 112, and the gate sidewall insulating film 143. Here, the data retention insulating film 1
41 is formed wider than the gate electrode 132 by the thickness of the gate sidewall insulating film 143.

FIG. 32C shows a cross-sectional view along the “I-J” line in FIG.
An element isolation groove 145 is provided in the semiconductor substrate 137, and an element isolation region 130 is formed therein. Between the element isolation regions 130, a tunnel insulating film 140, a data holding insulating film 141, a gate insulating film made of a block insulating film 142, and a first gate 138 are formed. A second gate 139 is formed on the block insulating film 142 so as to extend onto the element isolation region 130. Here, the data holding insulating film 141 is formed to be wider than the first gate 138 and protrudes into the element isolation region 130.

In this memory cell, a well, which is a low-concentration impurity region (not shown), is formed in the upper portion of the semiconductor substrate 137. A tunnel insulating film 140 is formed on the semiconductor substrate 137 from, for example, a silicon oxide film or a silicon oxynitride film having a thickness of about 1 to 15 nm. Further, on the tunnel insulating film 140, data is provided by an insulating film such as a silicon nitride film, a silicon oxynitride film, a Ta ₂ O ₅ film, a TiO ₂ film, an Al ₂ O ₃ film having a film thickness of about _{3 to 30} nm, for example. A holding film 141 is formed. Further, on the data holding film 141, a block insulating film 142 is formed of a silicon oxide film, a silicon oxynitride film or the like having a film thickness of, for example, about 1 to 15 nm. On the block insulating film 142, for example, a stack structure of polysilicon, WSi (tungsten silicide) and polysilicon, or NiSi, MOSi, TiSi, CoSi.
And a polysilicon stack structure, a metal-polysilicon stack structure, or a silicon metal compound or a metal single layer structure is formed to a thickness of 10 nm to 500 nm.

Next, the operation of the semiconductor device of this embodiment will be described. The transistors shown in FIG. 32 constitute a memory cell. The erasing operation is performed, for example, by applying a high voltage (for example, 10 to 25 V) to the semiconductor substrate with the gate electrode at 0 V and injecting holes from the semiconductor substrate into the charge storage region. Alternatively, the drain potential is negatively biased with respect to the source potential to generate hot holes accelerated in the channel, and the gate electrode is negatively biased with respect to the source potential to inject the hot holes into the charge storage region. Done in Alternatively, the source potential and drain potential are positively biased with respect to the well potential to generate a hot hole at the junction between the impurity region and the well, and the gate electrode is negatively biased with respect to the well potential to charge the hot hole. This is done by injecting into the accumulation region.

In the writing operation, for example, the semiconductor substrate is set to 0 V and a high voltage (for example, 10%) is applied to the gate electrode.
~ 25V) is applied to inject electrons from the semiconductor substrate into the charge storage region.
Alternatively, the drain potential is positively biased with respect to the source potential to generate hot electrons accelerated in the channel, and the gate electrode is positively biased with respect to the source potential to inject hot electrons into the charge storage region. Done in

In the read operation, the bit line connected to the drain contact is precharged and then floated, the voltage of the gate electrode is set to the read voltage Vref, the source line is set to 0 V, and whether the current flows through the memory cell is detected by the bit line. Is done. That is, if the threshold value Vth of the memory cell is larger than Vref, and the memory cell is turned off in the writing state, the bit line maintains the precharge potential. On the other hand, the threshold value V of the selected memory cell
If th is smaller than Vref, the memory cell is turned on, so that the potential of the bit line decreases by ΔV from the precharge potential. Data in the memory cell is read by detecting this potential change with a sense amplifier.

As shown in FIG. 32A, element regions 131 are formed on the semiconductor substrate on both sides of the gate electrode 132, and in a direction perpendicular to the gate edge ("GH line" direction) when reading data. The stored data is determined by the amount of current flowing. Here, as shown in FIG. 32B, the data retention insulating film 141 has a shape protruding from the gate electrode 132. Here, the protruding degree is about 0.5 nm to 10 nm. Here, if the degree of protrusion is small, the effect cannot be obtained, and if the degree of protrusion is too large, difficulty arises in the manufacturing process, which is inappropriate for miniaturization.

32C, the element isolation trench 145 is formed in a self-aligned manner with respect to the gate electrode 132 and the tunnel insulating film 140 and the block insulating film 142 in the gate insulating film. Here, the data retention insulating film 141 is the first gate 13 in the gate electrode 132.
8 and the semiconductor substrate 137, and both ends enter the element isolation groove 145.

Thus, in the semiconductor device of this embodiment, since the data holding insulating film protrudes from the gate electrode and / or the semiconductor substrate, the protruding portion of the data holding insulating film accumulates the charge of the memory cell transistor. It is not used as a region or a gate insulating film.

Compared with the central part, the edge of the data retention insulating film is inferior in charge retention due to processing damage, but the charge retention characteristics in this area do not affect the charge retention characteristics of the memory cell, so it is highly reliable non-volatile A semiconductor memory device can be realized. Here, in the cross section shown in FIG. 32B, the memory cell is divided into an edge portion and a central portion as regions (I), (II), and (III). Further, in the cross section shown in FIG. 32C, the memory cell is divided into regions (IV), (V), (VI
) Is divided into an edge portion and a central portion. Here, the edge portions (I), (III), (IV
), (VI) because the characteristics of the charge storage insulating film are the same as those of the central portions (II) and (V), there is no reliability deterioration due to the edge portion. In this way, the protrusion length of the protrusion portion is set to a value larger than the depth of penetration of processing damage, so that the edge portions (I), (III), (IV)
, (VI) have the same characteristics as those of the central portions (II) and (V).

Here, in particular, the direction in which the current between the source and drain flows ("GH" direction in FIG. 32A).
The data holding insulating film protrudes on two sides parallel to each other (two sides in contact with the element isolation end). This is because the regions (IV) and (VI) in FIG. 32C are arranged in parallel with the central portion (V) between the source and drain, and the threshold value drop due to charge loss in this portion is the threshold value of the entire memory cell. In particular, (IV), (VI
This is because it is necessary to prevent the charge from being lost in the portion).

Each region in the cross section shown in FIG. 32B is represented by a circuit diagram using a transistor in FIG.
However, since the characteristics of the regions (I), (II), and (III) are equal, FIG.
It is expressed by one transistor as shown in B). Further, each region in the cross section shown in FIG. 32C is represented by a circuit diagram using a transistor as shown in FIG. 33C. The characteristics of the regions (IV), (V), and (VI) are as follows. Since they are equal, they are represented by one transistor as shown in FIG.

Here, an example in which the cross section shown in FIG. 32C is enlarged is shown in FIG. First gate electrode 1
An element isolation sidewall insulating film 146 is formed between the semiconductor substrate 137 below the element 43 and the element isolation region 130. A polysilicon sidewall oxide film 147 is formed between the side surface of the first gate electrode 138 and the element isolation region 130. Further, at the end 148 where the second gate electrode 139 is in contact with the polysilicon sidewall oxide film 147 and the element isolation region 130, the second gate electrode 1
39 protrudes in the direction of the semiconductor substrate 137. Thus, the data retention insulating film 142 protrudes in the element isolation region 130 direction from the first gate 138 by the thickness of the polysilicon sidewall oxide film 147. Further, the data retention insulating film 142 protrudes from the semiconductor substrate 137 toward the element isolation region 130 by the thickness of the element isolation sidewall oxide film 146.

In this embodiment, both ends of the data retention insulating film protrude from both the gate electrode and the semiconductor substrate, but may protrude from either the gate electrode or the semiconductor substrate. That is, only one of the “IJ” cross section or the “GH” cross section of FIG. 32 is adopted,
The other may be the same as the prototype of this embodiment. In this embodiment, the data retention insulating film protrudes on all four sides defining the element region of the memory cell transistor.
It is sufficient that the data retention insulating film protrudes on at least one of the four sides, preferably on two sides parallel to the direction in which the current between the source and drain flows.

Thus, in the MONOS type nonvolatile memory cell, the data retention characteristic can be improved by forming the data retention insulating film so as to protrude from the gate electrode.

In addition, since the data retention insulating film protrudes from the gate electrode, it is not necessary to use the edge of the data retention insulating film that has been damaged by processing as the charge storage region and the gate insulation film of the transistor. Cell reliability is improved. In particular, the shape in which the data holding insulating film protrudes on two sides (two sides in contact with the end of the element isolation region) parallel to the direction in which the current between the source and drain flows (the “IJ” direction in FIG. 32C). In this case, the threshold drop can be prevented and the effect of improving the data retention characteristics is great.

According to the semiconductor device of this embodiment, if both ends of the charge storage region protrude to the gate electrode under the gate sidewall insulating film and protrude from the semiconductor substrate at the channel end, the manufacturing process to the channel portion is performed. It is possible to prevent damage from entering.

As described above, the charge storage region protrudes from the gate electrode or the substrate, so that the end portion of the insulating film that has been damaged by processing and has deteriorated charge retention characteristics is not used as the charge storage region or the gate insulating film. Therefore, the reliability of the memory cell is improved.

In the semiconductor device of the present embodiment, by arranging the end portion of the data retention insulating film, which is arranged in parallel with the direction in which the read current flows, to protrude from the gate electrode or the semiconductor substrate,
This prevents a threshold drop at the edge of the data holding insulating film from being detected as a threshold drop in the memory cell.

Even when the semiconductor device having the shape shown in FIGS. 2 and 3 in the first embodiment is used, the effect of the semiconductor device of this embodiment can be obtained.

Next, an example of a method for manufacturing the semiconductor device of this embodiment will be described with reference to FIGS.
In FIGS. 35 to 43, (A) of each figure is “I-J” in FIG. 32 (A).
The cross section on line “B” corresponds to the cross section on line “GH” in FIG.

First, after a sacrificial oxide film (not shown) is formed on the semiconductor substrate 137, channel impurities and well impurities are implanted, and the sacrificial oxide film is peeled off.

Next, as shown in FIGS. 35A and 35B, a tunnel insulating film 140 such as a silicon oxide film or a silicon oxynitride film having a thickness of about 1 to 15 nm is formed on the semiconductor substrate 137, for example.
For example, a silicon nitride film or silicon oxynitride film having a thickness of about 3 to 30 nm, Ta ₂ O ₅ , Ti
A data retention insulating film 141 is sequentially formed from an insulating film such as O ₂ or Al ₂ O ₃ . Further, the block insulating film 142 is formed by a silicon oxide film, a silicon oxynitride film, or the like having a thickness of about 1 to 15 nm, for example. Further thereon, a first gate electrode is deposited to a thickness of about 10 to 100 nm using, for example, polysilicon. Further, an insulating film such as a silicon nitride film is added to 10-20.
A mask material 150 is formed by deposition with a thickness of about 0 nm.

Next, in the step shown in FIGS. 36A and 36B, after patterning the element isolation region by photolithography, the mask material 150 and the first gate electrode 1 are processed.
38, the block insulating film 142, the data holding insulating film 141, the tunnel insulating film 140, and the semiconductor substrate 137 are processed by anisotropic etching to form the element isolation trench 151. Here, the depth of the element isolation trench to be formed is, for example, about 50 nm to 300 nm. Note that FIG.
In the cross section shown in FIG. 6B, no element isolation trench is formed.

Next, as shown in FIG. 37A, the side wall of the first gate electrode 138 is oxidized to form the gate side wall insulating film 152. The thickness of the first gate electrode 138 oxidized in this step is about 0.
. It is about 5 nm to 15 nm. This value indicates that the damage caused by processing is the data retention insulating film 14.
A value that does not enter 1 is selected. Note that oxidation is not performed in the cross section shown in FIG.

At this time, the side wall portion of the element isolation trench 151 of the semiconductor substrate 137 is also oxidized and the element isolation side wall insulating film 153 is formed, but the oxidation conditions are adjusted so that the data holding insulating film 141 is not oxidized. For example, polysilicon is used for the first gate electrode 138, and the sidewall of the element isolation trench 151 is the semiconductor substrate 137. Therefore, when single crystal silicon is used, the oxidation conditions can be set by utilizing the difference between the oxidation rates of the two. . The amount of protrusion of the data holding insulating film 141 is determined by the amount of oxidation of the side wall of the first gate electrode 138 and the amount of oxidation of the side wall of the element isolation trench 151. That is, the gate sidewall insulating film 152 is formed on the side surface of the first gate electrode 138.
The amount of protrusion of the data retention insulating film 141 to the first gate electrode 138 is determined by the amount of receding of the side surface of the first gate electrode 138. Further, the protrusion amount of the data holding insulating film 141 to the semiconductor substrate 137 is determined by the amount of retreat of the side surface of the semiconductor substrate 137 due to the formation of the element isolation sidewall insulating film 153 on the side surface of the element isolation trench 151.

The oxide film on the side wall of the element isolation trench formed here is an oxide film of single crystal silicon constituting the semiconductor substrate, and has a property of relatively high hardness. Note that the conditions may be such that only the side walls of the first gate electrode 138 or only the side walls of the element isolation trench 151 of the semiconductor substrate 137 are oxidized. Thus, as a result of the first gate electrode 138 and the semiconductor substrate 137 retreating due to oxidation, both ends of the data retention insulating film 141 are either the first gate electrode 138 or the semiconductor substrate 137, or the first gate electrode 138 and the semiconductor. The shape protrudes from both the substrate 137 and the substrate 137.

Here, by using a condition in which the data holding insulating film 141 is etched so that a forward taper is formed, the silicon oxide film can be embedded in the element isolation trench 151 in a later process more easily. The forward taper angle is preferably in the range of 60 ° to 89 ° with the upper surface of the semiconductor substrate 137 as a standard.

Next, as shown in FIG. 37A, by oxidizing the first gate electrode 138 made of polysilicon, a structure in which the first gate electrode sidewall oxide film 152 protrudes from the data holding insulating film 141 is obtained. For example, it is desirable to reduce the damage of the data retention insulating film 141 when the element isolation insulating film is embedded by HDP-SiO ₂ described later, and to form a more reliable device structure. Further, due to the oxidation of the semiconductor substrate 137, the element isolation sidewall oxide film 153 is obtained.
The structure in which the element isolation groove 151 protrudes from the data holding insulating film 141 can facilitate the embedding of the silicon oxide film in the element isolation groove 151 in a later step.

Here, both ends of the data holding insulating film 141 are 0.5 nm or more and 15 mm from the semiconductor substrate 137.
The protrusion within the range of nm or less is desirable for reliability, and the thickness of the oxide film formed on the inner wall of the element isolation region 151 is desirably formed within the range of 1 nm to 16 nm.

The method of retracting the first gate electrode 138 and the semiconductor substrate 137 with respect to the data holding insulating film 141 is not limited to oxidation, and may be etch back by wet etching or the like. Further, for example, by depositing TEOS or HTO (High Temperature Oxide) thicker than the protruding amount of the data retention insulating film 141, HDP (High Density Plasma)-
The damage of the data retention insulating film when the element isolation insulating film is embedded with SiO ₂ may be reduced. In this case, it is necessary not to etch the data retention insulating film. Wet etching or the like can also be used in combination with oxidation. Further, after depositing an insulating film such as a silicon oxide film with a thickness of, for example, about 5 to 50 nm, it is etched back by anisotropic etching to form a sidewall insulating film, and using this as a mask, the first gate insulating film and the semiconductor The element isolation groove can also be formed by etching the substrate.

Next, as shown in FIG. 38A, the element isolation trench 151 is formed, for example, by HDP-SiO 2.
After being buried by a deposition method such as a silicon oxide film such as TEOS or the like, the device isolation region 110 is formed by planarization by a CMP method. The silicon oxide film buried here has a property of relatively low hardness as compared with the oxide film of single crystal silicon.

Next, as shown in FIGS. 39A and 39B, a mask material 1 which is a stopper for CMP.
50 is removed by wet etching.

Next, as shown in FIGS. 40A and 40B, for example, a stack structure of polysilicon or WSi (tungsten silicide) and polysilicon, or NiSi, MoSi, T
From a silicon metal compound and polysilicon stack structure such as iSi and CoSi, a metal and polysilicon stack structure, a silicon metal compound and a single layer structure of a metal such as W, Al, Cu, or a single layer structure of polysilicon A second gate electrode 139 is deposited, and together with the first gate electrode 138, a gate electrode 132 of the memory cell is formed.

Next, as shown in FIG. 41, a gate pattern is formed by photolithography, and the gate electrode is etched by anisotropic etching. In FIG. 41B,
The block insulating film 142 is exposed and a gate electrode 132 is formed in part. Note that FIG.
In the cross section shown in (A), the gate electrode 132 is not etched. In this step, the data retention insulating film 141 is not etched. Here, the block insulating film 142 on the data retention insulating film 141 can be either etched or not.

Next, after performing a heat treatment for etching damage recovery as necessary, FIG.
As shown in FIG. 5, an insulating film such as a silicon oxide film is deposited to a thickness of about 5 to 50 nm, for example, and etched back by anisotropic etching to form a sidewall insulating film 143. At this time, the data holding insulating film 141 is also etched using the sidewall insulating film 143 as a mask. As a result, with respect to the gate electrode 132, the data holding insulating film 14 is equal to the film thickness of the sidewall insulating film 143.
It becomes the shape which 1 protruded. Here, since the thickness of the sidewall insulating film 143 corresponds to the deposition thickness, the thickness of the sidewall insulating film 143 is controlled by adjusting the deposited film thickness. Alternatively, the sidewall insulating film 143 may be formed not by deposition but by oxidizing the gate polycrystalline silicon.
In this case, the thickness of the sidewall insulating film 143 is adjusted by the amount of oxidation.

Next, as shown in FIG. 43B, impurities in the diffusion layer are implanted to form source and drain impurity regions 135 and 136. Further, as shown in FIGS. 43A and 43B, an interlayer insulating film 144 is deposited. Further, the contact plugs 133, 1 are formed in the interlayer insulating film 144.
34 is formed, and a nonvolatile memory cell is completed through a process of forming a metal wiring (not shown) and the like.

According to the manufacturing method of the semiconductor memory device of this embodiment, the data retention insulating film 141 forming the memory cell is defined by defining the channel width with the first gate electrode 138 and the channel length with the second gate electrode 139. Can be determined by two lithography methods.
Further, a linear pattern can be used for the two lithography. Therefore, in addition to the channel width and the channel length, it is possible to reduce the influence factors on the memory characteristics of the dimensional variation than the floating gate type nonvolatile semiconductor memory device that greatly depends on the lithography dimensions of the floating gate and the control gate. The writing voltage and erasing voltage can be further stabilized, and the reliability can be improved.

Further, the data retention insulating film 141 is not formed in the portion where the first gate electrode 138 is not formed. Therefore, for example, the data holding insulating film 14 is formed under the second gate electrode 139.
Charge injection into the data holding insulating film 141 during the electrode processing of the data holding insulating film 141 under the second gate electrode 139 or during operation does not occur when 1 is formed. Therefore, the problems of variations in breakdown voltage between channels between adjacent memory cells and current leakage caused by them do not occur.

(Modification of Example 3)
In this modification, in the semiconductor device of Example 3, the structure of the cross section shown in FIG. 32C is changed to the structure shown in FIG. Here, the lower part of the element isolation region is not formed below the data holding insulating film 141.

The manufacturing method of the semiconductor device according to the present modification differs from the third embodiment only in the cross section on the “IJ” line, in the steps shown in FIG. Since this is the same as the manufacturing method of the semiconductor device of FIG. That is, FIG.
After the step shown in FIG. 45, as shown in FIG. In the gate sidewall insulating film forming step after the element isolation trench 151 is formed, the gate sidewall insulating film 152 is formed without oxidizing the side surfaces of the element isolation trench 151.

Next, as shown in FIG. 46, the element isolation groove 151 is formed by, for example, HDP-SiO 2 or TE.
After embedding with a deposition method such as a silicon oxide film such as OS, it is planarized by CMP method,
An element isolation region 110 is formed. The silicon oxide film buried here has a property of relatively low hardness as compared with the oxide film of single crystal silicon.

Next, as shown in FIG. 47, the mask material 150 serving as a CMP stopper is removed by wet etching.

Next, as shown in FIG. 48, for example, a stack structure of polysilicon or WSi (tungsten silicide) and polysilicon, or NiSi, MoSi, TiSi, CoSi
A second structure comprising a silicon metal compound and polysilicon stack structure, a metal and polysilicon stack structure, a silicon metal compound or a single layer structure of a metal such as W, Al, or Cu, or a single layer structure of polysilicon. A gate electrode 139 is deposited, and together with the first gate electrode 138, a gate electrode 132 of the memory cell is formed.

Next, an interlayer insulating film 144 is deposited as shown in FIG. Further, the interlayer insulating film 144
A contact plug 134 is formed therein, and a nonvolatile memory cell is completed through a process of forming a metal wiring (not shown) and the like.

By not providing the element isolation side wall insulating film in this manner, the data holding insulating film 141 can protrude into only the first gate electrode 138 and not into the semiconductor substrate 137. Also in this modification, the same effect as in the third embodiment can be obtained.

FIG. 50 shows a MONO using a self-aligned STI which is a prototype of the fourth embodiment of the present invention.
An S-type memory cell is shown. FIG. 50A shows a top view of the prototype of the present embodiment. The source impurity region 1 is partially in the semiconductor substrate 117 in contact with the element isolation region 110.
55 is linearly formed in the left-right direction. A part of the source impurity region 155 has a large width, and a source contact 157 is provided. In addition, a drain impurity region 156 is formed on a part of the semiconductor substrate 117 in a horizontal direction so as to face the source impurity region 155 and in contact with the element isolation region 110. A part of the drain impurity region 156 has a large width, and a drain contact 158 is provided.

A gate electrode 112 is formed perpendicular to the longitudinal direction of the source impurity region 155 and the drain impurity region 156. The gate electrode 112 is provided with a wide region at the end thereof, and a gate contact 114 is provided there. In this memory cell, a source impurity region 155 and a drain impurity region 156 are provided immediately below the gate electrode 112, and M to N indicated by arrows in FIG. 50A from the source impurity region 155 to the drain impurity region 156 at the time of data reading. The writing state and the erasing state are discriminated based on the amount of current flowing in the direction. Such a structure is used in an AND type EEPROM, a DINOR type EEPROM, or the like.

A cross-sectional view on the “KL” line in FIG. 50A is shown in FIG. A gate electrode 112 is formed on the semiconductor substrate 117. The gate electrode 112 is stacked on a gate insulating film including a tunnel insulating film 118, a data retention insulating film (charge storage region) 119, and a block insulating film 120. An interlayer insulating film 121 is formed on the surfaces of the semiconductor substrate 117 and the gate electrode 112.

Further, a cross-sectional view on the “MN” line in FIG. 50A is shown in FIG.
An element isolation trench 122 is provided in the semiconductor substrate 117, and an element isolation region 110 is formed therein. A gate insulating film including a tunnel insulating film 118, a data holding insulating film 119, and a block insulating film 120 is formed between the element isolation regions 110. A gate electrode 112 is formed on the block insulating film 120 so as to extend to the element isolation region 110. In the semiconductor substrate 117 at the end of the tunnel insulating film 118, the element isolation trench 122 is not provided, and a source impurity region 155 and a drain impurity region 156 are provided in contact with the element isolation region 110.

In the method of manufacturing the memory cell shown in FIGS. 50B and 50C,
Since the edge of the data retention insulating film is exposed to anisotropic etching plasma during the etching process for forming the element isolation trench and the etching process of the gate electrode and the gate insulating film,
In some cases, the data holding insulating film is damaged at the edge of the element isolation region and the edge of the gate, so that the charge holding power at the edge of the data holding insulating film is deteriorated and the reliability of the memory cell is impaired.

In the case of the memory cell having the structure shown in FIG. 50, deterioration of the characteristics of the data holding insulating film at the edge of the element isolation region may be a serious problem. This is explained below.
In the cross section shown in FIG. 50B, the memory cell transistors are formed as (I), (II), (
It is divided into the area III). Here, the data holding insulating film in the regions (I) and (III) is the damaged edge region 123. Similarly, in the cross section shown in FIG. 50C, the memory cell transistors are divided into regions (IV), (V), and (VI). Here, the data holding insulating films (IV) and (VI) are damaged edge regions 124.

Here, it is assumed that the data retention insulating film traps electrons to increase the threshold value (write state). 51A shows a circuit diagram of a transistor corresponding to the cross section of FIG. 50B, FIG. 51B shows a circuit diagram of a transistor corresponding to the cross section of FIG. FIG. 51C shows the gate voltage on the horizontal axis and the drain current on the vertical axis, and shows changes in current-voltage characteristics for each state of the data retention insulating film. The circuit diagram shown in FIG. 51A shows a configuration in which three transistors (I), (II), and (III) having gates connected in common are connected in parallel between a source and a drain. This transistor (I), (II), (III)
Corresponds to the regions of the memory cell transistors (I), (II), and (III) in FIG. In addition, the circuit diagram shown in FIG. 51B shows a configuration in which three transistors (IV), (V), and (VI) whose gates are commonly connected are connected in series between the source and drain. . The transistors (IV), (V), (VI) are shown in FIG.
Each region corresponds to the memory cell transistors (IV), (V), and (VI) in (C).

Since the charge retention characteristic is deteriorated at the edge portion of the data retention insulating film, electrons are easily desorbed. In the case of a memory cell having a structure using an insulating film as a charge storage region typified by a MONOS type memory cell, the region (I), (II), (III) or (IV), (V), (
Since the movement of charge is not performed between (VI), the threshold is lowered in the region (edge portion) from which the charge is lost compared to the central portion of the channel. Here, the cross section shown in FIG. 50B represents a channel in the direction in which current flows, and when a transistor is connected in series in the direction in which this current flows, the threshold value of any transistor is lowered. However, the threshold value as a whole does not change.

Here, since the regions (IV), (V), and (VI) are arranged in series between the source and the drain, even if the threshold values of the regions (IV) and (VI) are lowered, the threshold value of the region (V) Is high, no current flows between the source and the drain, and a decrease in the threshold value of the gate edge is not detected as a decrease in the threshold value of the memory cell. On the other hand, since the regions (I), (II), and (III) are connected in parallel between the source and the drain, current flows between the source and the drain when the threshold values of the regions (I) and (III) are lowered. A threshold value decrease at the edge portion of the element isolation region is detected as a memory cell threshold value decrease. This situation is shown in FIG. That is, the gate voltage is almost the same in each region immediately after writing, but the gate voltage at the edge portions (I) and (III) decreases more than the central portion (II) in the writing state with time. The voltage of the erased state is approaching. That is, the charge retention characteristic of the memory cell is determined by the charge retention characteristic of the damaged part.

As described above, when the MONOS type memory cell is formed with the self-aligned STI structure, the deterioration of the data retention characteristics of the charge storage region at the edge of the element isolation region or the edge of the gate electrode is affected by the reliability of the memory cell. Among the four sides that define the device area,
Deterioration of charge retention characteristics at two edges parallel to the direction in which the drain-to-drain current flows can be a problem. The present embodiment provides a method for solving the above problems.

Next, FIG. 52 shows a MONOS type memory cell using the self-aligned STI of this embodiment. FIG. 52A shows a top view of the semiconductor device of this example, and the element isolation region 16 is shown.
A source impurity region 162 is linearly formed in the left-right direction in one semiconductor substrate 161 in contact with 0. A drain impurity region 163 is formed in the semiconductor substrate 161 on the other side so as to face the source impurity region 162 and in contact with the element isolation region 160. A part of the source impurity region 162 is formed wide and a source contact 164 is formed there. Further, the drain impurity region 163 is formed to have a wide width at a part thereof, and a drain contact 165 is formed there. A gate electrode 166 is formed perpendicular to the longitudinal direction of the source impurity region 162 and the drain impurity region 165.

The gate electrode 166 is provided with a wide region at the end thereof, and a gate contact 167 is provided there. In this memory cell, a part of the semiconductor substrate 161 below the gate electrode 166 becomes a source impurity region 162 and a drain impurity region 163, and an arrow in FIG. 52A moves from the source impurity region 162 to the drain impurity region 163 at the time of data reading. The writing state and the erasing state are discriminated by the amount of current flowing from Q to R indicated by. Such a structure is used in an AND type EEPROM, a DINOR type EEPROM, or the like.

A cross-sectional view along the “OP” line in FIG. 52A is shown in FIG. A gate electrode 166 is formed on the semiconductor substrate 161. This gate electrode 166 is a lower first layer.
It consists of a gate 170 and a second gate 171 thereon. The gate electrode 166 includes a tunnel insulating film 172, a data retention insulating film (charge storage region) 173, and a block insulating film 174.
Is laminated on a gate insulating film made of A gate sidewall insulating film 175 is provided on the side surface of the gate electrode 166. An interlayer insulating film 176 is formed on the surfaces of the semiconductor substrate 161, the gate electrode 166, and the gate sidewall insulating film 175. Here, the data retention insulating film 17
3 is wider than the gate electrode 166 by the thickness of the gate sidewall insulating film 175.

Further, a cross-sectional view on the “QR” line in FIG. 52A is shown in FIG.
An element isolation groove 177 is provided in the semiconductor substrate 161, and an element isolation region 160 is formed therein. Between the element isolation regions 160, a gate insulating film made of a tunnel insulating film 172, a data holding insulating film 173, and a block insulating film 174 and a first gate 170 are formed. On the block insulating film 174, a second gate 171 is formed extending to the element isolation region 160. Here, the data holding insulating film 173 and the tunnel insulating film 172 located therebelow are formed to have a width larger than that of the first gate 170, and the element isolation region 1.
It protrudes into 60.

In this memory cell, a well, which is a low concentration impurity region (not shown), is formed in the upper portion of the semiconductor substrate 161. A tunnel insulating film 172 is formed on the semiconductor substrate 161 from, for example, a silicon oxide film or a silicon oxynitride film having a thickness of about 1 to 15 nm. Further, on the tunnel insulating film 172, data is provided by an insulating film such as a silicon nitride film, a silicon oxynitride film, a Ta ₂ O ₅ film, a TiO ₂ film, an Al ₂ O ₃ film having a film thickness of about _{3 to 30} nm, for example. Holding insulating film 17
3 is formed.

Further, on this data retention insulating film 173, a block insulating film 174 is formed of a silicon oxide film, a silicon oxynitride film or the like having a film thickness of, for example, about 1 to 15 nm. On the block insulating film 174, for example, a stack structure of polysilicon or WSi (tungsten silicide) and polysilicon, a stack structure of NiSi, MOSi, TiSi, CoSi and polysilicon, or a stack structure of metal and polysilicon. Alternatively, a gate electrode 166 made of a silicon metal compound or a metal single layer structure is formed with a thickness of 10 nm to 500 nm. Here, a source impurity region 162 and a drain impurity region 163 are formed in the semiconductor substrate 161 in contact with the end of the element isolation region 160. This source impurity region 162
The drain impurity region 163 has a data retention insulating film 17 protruding from the first gate 170.
3, but not below the first gate electrode 170.

Next, the operation of the semiconductor device of this embodiment will be described. The transistors shown in FIG. 52 constitute a memory cell. The erasing operation is performed, for example, by applying a high voltage (for example, 10 to 25 V) to the semiconductor substrate with the gate electrode at 0 V and injecting holes from the semiconductor substrate into the charge storage region. Alternatively, the drain potential is negatively biased with respect to the source potential to generate hot holes accelerated in the channel, and the gate electrode is negatively biased with respect to the source potential to inject the hot holes into the charge storage region. Done in Alternatively, the source potential and drain potential are positively biased with respect to the well potential to generate a hot hole at the junction between the impurity region and the well, and the gate electrode is negatively biased with respect to the well potential to charge the hot hole. This is done by injecting into the accumulation region.

In the writing operation, for example, the semiconductor substrate is set to 0 V and a high voltage (for example, 10%) is applied to the gate electrode.
~ 25V) is applied to inject electrons from the semiconductor substrate into the charge storage region.
Alternatively, the drain potential is positively biased with respect to the source potential to generate hot electrons accelerated in the channel, and the gate electrode is positively biased with respect to the source potential to inject hot electrons into the charge storage region. Done in

In the read operation, the bit line connected to the drain contact is precharged and then floated, the voltage of the gate electrode is set to the read voltage Vref, the source line is set to 0 V, and whether the current flows through the memory cell is detected by the bit line. Is done. That is, if the threshold value Vth of the memory cell is larger than Vref, and the memory cell is turned off in the writing state, the bit line maintains the precharge potential. On the other hand, the threshold value V of the selected memory cell
If th is smaller than Vref, the memory cell is turned on, so that the potential of the bit line decreases by ΔV from the precharge potential. Data in the memory cell is read by detecting this potential change with a sense amplifier.

Here, as shown in FIG. 52B, the data retention insulating film 173 is formed of the first gate electrode 1.
The shape protrudes with respect to 70. Here, the extent of protrusion is the data retention insulating film 1.
73 is in the element isolation region 160 by about 0.5 nm to 10 nm. Here, if the degree of protrusion is small, the effect cannot be obtained, and if the degree of protrusion is too large, in the manufacturing process,
Difficulties arise and are inappropriate for miniaturization.

Further, as shown in FIG. 52C, the element isolation trench 160 is formed in a self-aligned manner with respect to the tunnel insulating film 172 and the data holding insulating film 173 in the gate insulating film. The tunnel insulating film 172 and the data holding insulating film 173 protrude from the block insulating film 174 and the first gate electrode 170 in the left-right direction. As described above, the charge storage insulating film protrudes from the gate electrode, and both ends are in the shape of the element isolation insulating film. Here, a rectangular semiconductor substrate under the control gate surrounded by two sides of the control gate in a direction parallel to the “QR” line and two sides of the diffusion layer in a direction parallel to the “OP” line The region becomes an island region.

Source and drain impurity regions 162 and 163 are formed on the semiconductor substrate 161 on both sides of the lower end of the first gate electrode 170. When reading data, the longitudinal direction of the gate ("QR"
The stored data is discriminated by the amount of current flowing in the “line direction.” Thus, in the semiconductor device of this embodiment, the data holding insulating film protrudes from the gate electrode and / or the semiconductor substrate. In addition, the protruding portion of the data holding insulating film is not used as a charge storage region or a gate insulating film of the memory cell transistor.

Compared with the central part, the edge of the data retention insulating film is inferior in charge retention due to processing damage, but the charge retention characteristics in this area do not affect the charge retention characteristics of the memory cell, so it is highly reliable non-volatile A semiconductor memory device can be realized.

Here, in the cross section shown in FIG. 52B, the memory cells are divided into regions (I), (II), (II
I) is divided into an edge portion and a central portion. Further, in the cross section shown in FIG. 52C, the memory cell is divided into an edge portion and a central portion as regions (IV), (V), and (VI). Here, since the characteristics of the charge storage insulating films of the edge portions (I), (III), (IV), and (VI) are the same as those of the central portions (II) and (V), the reliability caused by the edge portions is obtained. There is no sexual degradation. Thus, the length of the protrusion of the protrusion is set to a value larger than the depth of penetration of the processing damage, so that the characteristics of the edge portions (I), (III), (IV), and (VI) are the central portion (II ) And (V).

Here, in particular, the data retention insulating film protrudes on two sides (two sides defining the gate edge) parallel to the direction in which the current between the source and drain flows (the “QR” ′ direction in FIG. 52A). The effect of having a shape is great. This is because the regions (I) and (III) in FIG. 52B are arranged in parallel with the central portion (II) between the source and drain, and the threshold value drop due to charge loss in this portion is the threshold value of the entire memory cell. In particular, (I)
This is because it is necessary to prevent charge loss in the portion (III).

Each region in the cross section shown in FIG. 52B is represented by a circuit diagram using a transistor.
However, since the characteristics of the regions (I), (II), and (III) are equal, FIG.
It is expressed by one transistor as shown in B). Further, each region in the cross section shown in FIG. 52C is represented by a circuit diagram using a transistor as shown in FIG. 53C. The characteristics of the regions (IV), (V), and (VI) are as follows. Since they are equal, they are expressed by one transistor as shown in FIG.

In this embodiment, both ends of the data retention insulating film protrude from both the gate electrode and the semiconductor substrate, but may protrude from either the gate electrode or the semiconductor substrate. That is, only one of the “OP” cross section or the “QR” cross section of FIG. 52 is adopted,
The other may be the same as the prototype of this embodiment. In this embodiment, the data retention insulating film protrudes on all four sides defining the element region of the memory cell transistor.
It is sufficient that the data retention insulating film protrudes on at least one of the four sides, preferably on two sides parallel to the direction in which the current between the source and drain flows.

In the semiconductor device of this embodiment, the same effect as that of the semiconductor device of Embodiment 3 can be obtained. That is, since the data holding insulating film protrudes from the gate electrode and / or the semiconductor substrate, the edge portion of the data holding insulating film is not used as the charge storage region or the gate insulating film of the memory cell transistor. Compared with the central part, the edge of the data retention insulating film is inferior in charge retention due to processing damage, but the charge retention characteristics in this area do not affect the charge retention characteristics of the memory cell, so it is highly reliable non-volatile Memory can be realized.

  Next, an example of a method for manufacturing the semiconductor device of this embodiment will be described with reference to FIGS.

54 to 62, (A) of each figure is “Q-” in FIG. 52 (A).
The cross section on line R, (B) corresponds to the cross section on the “OP” line in FIG.

First, after a sacrificial oxide film (not shown) is formed on the semiconductor substrate 161, channel impurities and well impurities are implanted, and the sacrificial oxide film is peeled off.

Next, as shown in FIGS. 54A and 54B, a tunnel insulating film 172 such as a silicon oxide film or a silicon oxynitride film having a thickness of about 1 to 15 nm, for example, is formed on the semiconductor substrate 161.
For example, a silicon nitride film or silicon oxynitride film having a thickness of about 3 to 30 nm, Ta ₂ O ₅ , Ti
A data retention insulating film 173 is sequentially formed from an insulating film such as O ₂ or Al ₂ O ₃ . Further, the block insulating film 174 is formed by a silicon oxide film, a silicon oxynitride film or the like having a thickness of about 1 to 15 nm, for example. Further thereon, the first gate electrode 1 is made of, for example, polysilicon.
70 is deposited to a thickness of about 10 to 100 nm. Further, an insulating film such as a silicon nitride film is added to 10
A mask material 180 is formed by deposition with a thickness of about 200 nm.

Next, in the step shown in FIG. 55A, after patterning the element isolation region by photolithography, the mask material 180 and the first gate electrode 170 are processed by anisotropic etching. Note that etching is not performed in the cross section shown in FIG.

Next, as shown in FIG. 56A, diffusion layer impurities are implanted into the semiconductor substrate 161 using the mask material 180 as a mask to form source and drain impurity regions 162 and 163.

Next, as shown in FIG. 57A, an insulating film such as a silicon oxide film is formed, for example, at 5 to 50 nm.
After being deposited with a thickness of about, the film is etched back by anisotropic etching to form a gate sidewall insulating film 181, and using this as a mask, a block insulating film 174, a data holding insulating film 173,
The tunnel insulating film 172 and the semiconductor substrate 161 are processed by anisotropic etching to form an element isolation groove 177. Here, the depth of the element isolation trench 177 formed is about 50 nm, for example.
It is about ~ 300 nm. Note that the element isolation trench is not formed in the cross section shown in FIG. By forming the gate sidewall insulating film 181 in this way, the source and drain impurity regions 162 and 163 can be left at the channel end. The widths of the remaining source / drain impurity regions 162 and 163 can be controlled in accordance with the width of the remaining gate sidewall insulating film 181. As a result, the film thickness of the gate sidewall insulating film 181 with respect to the first gate electrode 170 is
The data retention insulating film 175 has a protruding shape.

Next, after performing heat treatment for recovery of etching damage as necessary, FIG.
As shown in FIG. 4, after the element isolation trench 177 is filled with an insulating film such as a silicon oxide film and planarized by the CMP method, the mask material 180 which is a stopper of the CMP method is removed by wet etching. In the cross section shown in FIG. 58B, the mask material 180 is removed to expose the upper surface of the first gate electrode 170.

Next, as shown in FIG. 59, for example, a stack structure of polysilicon or WSi and polysilicon, or a stack structure of NiSi, MoSi, TiSi, CoSi and polysilicon, a stack structure of metal and polysilicon, or silicon A second gate electrode 171 having a single layer structure of the above metal compound or metal is deposited, and together with the first gate electrode 170, a gate electrode 166 of the memory cell is formed.

Next, as shown in FIG. 60B, a gate pattern is formed by photolithography, and the gate electrode 166 is etched by anisotropic etching. At this time, the block insulating film 174 is slightly etched in a normal case, but the data holding insulating film 173 is not etched.
Do not etch.

If necessary, heat treatment for recovering etching damage may be performed. Further, after this step, damage recovery may be performed by oxidizing the first gate electrode in the range of 2 nm to 20 nm, for example. Note that the gate electrode 166 is not etched in the cross section shown in FIG.

Next, as shown in FIG. 61B, for example, a silicon oxide film made of TEOS or HTO or an insulating film made of silicon nitride film is deposited to a thickness of about 5 to 50 nm, for example, and anisotropic etching is performed. This is etched back to form a gate sidewall insulating film 175. At this time, the data holding insulating film 173 and the tunnel insulating film 172 are also etched using the gate sidewall insulating film 175 as a mask. As a result, with respect to the gate electrode 166, the gate sidewall insulating film 1
The data holding insulating film 173 is protruded by a thickness of 75. Note that FIG. 61 (A)
In the cross section shown in FIG. 5, the gate sidewall insulating film 175 is not formed.

Here, the sidewall insulating film 175 may be formed not by deposition but by oxidizing the gate polycrystalline silicon. In this case, the thickness of the sidewall insulating film 175 is adjusted by the amount of oxidation.

Next, as shown in FIG. 62, an interlayer insulating film 176 is deposited on the surface, and the interlayer insulating film 17
6, a contact plug 167 is formed, and a nonvolatile memory cell is completed through a process of forming a metal wiring (not shown) and the like.

Thus, according to the manufacturing method of the semiconductor device of this embodiment, since the data holding insulating film protrudes from the gate electrode, the block insulating film, the data holding insulating film, and the tunnel insulating film are provided. The reliability of the memory cell is improved because it is not necessary to use the end of the data holding insulating film that has been damaged in the etching process as the data holding insulating film and the gate insulating film of the transistor. In particular, the shape in which the data retention insulating film protrudes on two sides (two sides defining the gate edge) parallel to the direction in which the current between the source and drain flows (the “QR” line direction) in FIG. The effect of being is great.

According to the manufacturing method of the present embodiment, the same effect as in the third embodiment can be obtained. That is,
By defining the channel width with the first gate electrode and the channel length with the second gate electrode, the area of the data holding insulating film forming the memory cell can be determined by two lithography methods. Furthermore, in these two lithography, a linear pattern can be used. Therefore, the influence factors on the memory characteristics of the dimensional variation can be reduced other than the channel width and the channel length as compared with the floating gate type nonvolatile semiconductor device that largely depends on the lithography dimensions of the floating gate and the control gate. Therefore, the write voltage and erase voltage for each memory cell can be stabilized and the reliability can be improved.

Further, the data retention insulating film is not formed in the portion where the first gate electrode is not formed. Thus, for example, charge injection into the data retention insulating film during or during the processing of the data retention insulating film under the second gate electrode, which occurs when the data retention insulating film is formed under the second gate electrode Does not occur. Therefore, there is no problem of variations in breakdown voltage or current leakage between adjacent memory cells due to these charge injections.

(Modification of Example 4)
In this modification, a virtual ground array cell structure is realized as shown in FIG. FIG. 63 shows an enlarged view of the structure corresponding to the cross section shown in FIG. Here, unlike the fourth embodiment, the element isolation region 160 is not provided, and a high-concentration impurity region 185 is provided in the semiconductor substrate 161 instead.

This semiconductor device manufacturing method is the same as the semiconductor device manufacturing method according to the fourth embodiment except that an insulating film is formed from the surface of the semiconductor substrate 161 to the height of the mask material 180 instead of the step of etching the semiconductor substrate 161 shown in FIG. Embed.

Further, instead of the process shown in FIG. 61, as shown in FIG. 63, in order to improve the element isolation between the adjacent gate electrodes, for example, a P-type impurity made of boron or indium is 1
A high concentration impurity region 185 is formed by implantation in the range of 0 ¹¹ cm ⁻² to 10 ¹⁴ cm ⁻² .
At this time, since the side wall insulating film is also formed on the upper portion of the source and drain impurity region portions, by restricting the ions of the P type impurity to stop before the side wall insulating film, The drain impurity region can be limited not to be mixed with P-type impurities. The ion implantation energy of this P-type impurity is in the range of 1 eV to 100 eV. At this time, damage introduced into the data holding insulating film of the P-type impurity implanted ions can be separated by the gate electrode side wall insulating film, and a more reliable memory cell can be realized. In the virtual ground array cell having such a shape, a P plus diffusion layer or an N plus diffusion layer is formed in place of the element isolation region by embedding an insulator, and each plays a role of element isolation. Here, the N plus diffusion layer becomes a bit line or a source line and is not fixed.

This modification has the same effect as that of the fourth embodiment. Furthermore, in order to improve element isolation between adjacent gate electrodes, for example, when a p-type impurity made of boron or indium is added, It is possible to suppress the formation of the inversion layer at the edge portion, and to reduce the occurrence of problems such as variations in breakdown voltage between channels between memory cells in contact with each other and current leakage.

The structure of the semiconductor device according to Example 5 of the present invention is shown in FIG. FIG. 64A shows a top view of the semiconductor device of this embodiment, which is surrounded by the element isolation region 190 and includes the element region 1.
91 is linearly formed in the left-right direction. Perpendicular to the longitudinal direction of the element region 191,
A gate electrode 192 is formed. In the element region 191, a pair of contacts 193 is provided on the left and right sides of the gate electrode 192. In addition, the gate electrode 192 is provided with a wide region at the end thereof, and a gate contact 194 is provided there. In this memory cell, the element regions 191 on both sides of the gate electrode 192 become a source diffusion layer 195 and a drain diffusion layer 196, and at the time of data reading, S is indicated from the source diffusion layer 195 to the drain diffusion layer 196 by an arrow in FIG. The write state and the erase state are discriminated based on the amount of current flowing in the T direction from. Such a structure is a NAND type EEPROM or NOR type E.
Used in EPROM.

A cross-sectional view on the “ST” line in FIG. 64A is shown in FIG. A gate electrode 192 is formed on the semiconductor substrate 197, and a source diffusion layer 195 and a drain diffusion layer 196 are formed in the semiconductor substrate 197 on both sides thereof. The gate electrode 192 is stacked on a gate insulating film composed of a tunnel insulating film 198, a data retention insulating film (charge storage region) 199, and a block insulating film 200. An interlayer insulating film 201 is formed on the surfaces of the semiconductor substrate 197 and the gate electrode 192. Here, the block insulating film 200 is formed of the gate electrode 192.
The edge portion 202 is formed thicker than the center portion.

FIG. 64C shows a cross-sectional view on the “U-V” line in FIG.
An element isolation trench 203 is provided in the semiconductor substrate 197, and an element isolation region 190 is formed therein. Between the element isolation regions 190, a gate insulating film and a gate electrode 192 including a tunnel insulating film 198, a data holding insulating film 199, and a block insulating film 200 are formed. A gate electrode 192 is formed on the block insulating film 200 so as to extend onto the element isolation region 190. Here, the thickness of the block insulating film 200 is thicker at the edge portion 204 of the gate electrode 192 than at the central portion.

As described above, the gate insulating film thickness is increased at the edge portion of the gate electrode, which improves the read disturb characteristic. In particular, the tunnel insulating film 198 or the block insulating film 200 is characterized by being thick, and preferably the block insulating film 200.
It is desirable that the edge part of this is thick. This is because of the tunnel oxide film 19 through which charges pass.
8 and non-uniform thickness of the data retention insulating film 199 may cause variations in erasing characteristics and data retention characteristics, whereas the block insulating film 200 that does not pass charges is thickened at the edges. This is because it does not cause variation in characteristics.

Here, in the read operation of the nonvolatile memory, the read voltage Vre is applied to the gate electrode.
Although f is added, as the read operation is repeated, there is a problem in that the threshold value of the erased cell increases due to the electric field generated by Vef, and the threshold margin with the write state cell decreases. It is called disturb.

In this embodiment, since the gate insulating film is thickened at the edge portion, the electric field generated by Vref is weakened at the edge portion. For this reason, threshold fluctuation due to read disturbance is suppressed at the edge portion as compared with the channel center portion. As shown in FIGS. 64B and 64C, when the memory cell is divided into (I), (II), (III) and (IV), (V), (VI), (I ), (III), (IV), and (VI) show that the threshold fluctuation is small. These regions (I), (II), (III), (IV), (V), (VI) are defined by the penetration depth of bird's beaks.

In particular, the effect of reducing threshold fluctuations on two sides (element isolation ends) parallel to the “ST” line direction in FIG. 64A, which is the direction in which the source-drain current flows, is significant.

This will be described with reference to FIG. 65A shows a circuit diagram of a transistor corresponding to the cross section of FIG. 64B, FIG. 65B shows a circuit diagram of a transistor corresponding to the cross section of FIG. 64C, FIG. 65C shows the gate voltage on the horizontal axis and the drain current on the vertical axis, and shows changes in the current-voltage characteristics for each state of the data retention insulating film. In the circuit diagram shown in FIG. 65A, three transistors (I), (II), (II
A configuration in which I) is connected in series between the source and drain is shown. This transistor (I)
, (II), (III) are the memory cell transistors (I), (I) in FIG.
These correspond to the areas I) and (III), respectively. The transistors (I) and (III) correspond to the edge portion 202 where the block insulating film is thickened. In the circuit diagram shown in FIG. 65B, three transistors (IV), (V), (V
A configuration in which I) is connected in parallel between the source and drain is shown. This transistor (IV
), (V), (VI) are the memory cell transistors (IV), (V) in FIG.
) And (VI) respectively. The transistors (IV) and (VI) correspond to the edge portion 204 where the block insulating film is thickened.

FIG. 65C shows the drain current (Id) -gate voltage (Vg) characteristics of the memory cell. The threshold value of the memory cell in the erased state increases due to the Vref stress at the time of reading, but the threshold value fluctuation is small because the electric field is weakened at the edge portions (IV) and (VI). MO
In a memory using an insulating film as a charge storage layer such as a NOS type memory, trapped charges hardly move in the insulating film, so that the threshold values of the edge portions (IV) and (VI) are set at the central portion (
V) remains low compared to V). As shown in FIG. 65 (C), the regions (IV) and (V
), (VI) are arranged in parallel between the source and drain, the threshold of the memory cell is
It is determined by (IV) and (VI) having lower thresholds. For this reason, the threshold value fluctuation of the memory cell can be suppressed by weakening the electric field at the edge portion to suppress the threshold value fluctuation in the regions (IV) and (VI).

In the memory cell of this embodiment, a well which is a low concentration impurity region (not shown) is formed in the upper portion of the semiconductor substrate 197. For example, the film thickness is 1 nm to 15 nm on the semiconductor substrate 197.
A tunnel insulating film 198 is formed from a silicon oxide film, a silicon oxynitride film, or the like. Further, on the tunnel insulating film 198, data is provided by an insulating film such as a silicon nitride film, a silicon oxynitride film, a Ta ₂ O ₅ film, a TiO ₂ film, an Al ₂ O ₃ film having a film thickness of about ₃ nm to ₃₀ nm, for example. A holding insulating film 199 is formed.

Further, on this data retention insulating film 199, a block insulating film 200 is formed of a silicon oxide film, a silicon oxynitride film or the like having a film thickness of, for example, about 1 nm to 15 nm. On the block insulating film 200, for example, a stack structure of polysilicon or WSi (tungsten silicide) and polysilicon, a stack structure of NiSi, MOSi, TiSi, CoSi and polysilicon, or a stack structure of metal and polysilicon. Alternatively, the gate electrode 202 made of a silicon metal compound or a metal single layer structure is formed with a thickness of 10 nm to 500 nm. Here, a source impurity region 195 and a drain impurity region 196 are formed in the semiconductor substrate 197 in contact with the end of the tunnel insulating film 198.

The transistor shown in FIG. 64 constitutes a memory cell. The erase operation, write operation, and read operation are the same as in the third or fourth embodiment.

In this embodiment, by thickening the gate insulating film at the edge portion, the electric field at the time of read disturb stress is weakened at the edge portion to suppress threshold fluctuation at the edge.

That is, the threshold value of the edge portion is detected as the threshold value of the memory cell even if the threshold value at the center of the channel is increased by reducing the threshold value increase at the insulating film end portion arranged in parallel with the direction in which the read current flows. Therefore, the threshold fluctuation of the memory cell due to read disturb can be reduced.

Further, by changing the film thickness of the block insulating film through which charges do not pass, the electric field can be weakened at the edge portion without causing variations in write / erase characteristics and data retention characteristics.

Here, FIG. 66 shows an example in which the cross section of the structure of the semiconductor device configured by combining the cross section shown in FIG. 64C with the structure of the semiconductor device of Example 3 is enlarged. The gate electrode 192 is the first
An element isolation sidewall insulating film 207 is formed between the semiconductor substrate 197 below the first gate electrode 205 and the element isolation region 190, which includes the gate electrode 205 and the second gate electrode 206 thereon. A gate electrode sidewall insulating film (polysilicon sidewall insulating film) 208 is formed between the side surface of the first gate electrode 205 and the element isolation region 190. Block insulating film 200
Is formed thicker than the other portions under the end of the first gate electrode 205. The second gate electrode 206 projects toward the semiconductor substrate 197 at the end 209 where the second gate electrode 206 is in contact with the gate electrode sidewall insulating film 208 and the element isolation region 190. Thus, the data retention insulating film 199 protrudes in the direction of the element isolation region 203 by the thickness of the gate electrode sidewall insulating film 208 from the first gate electrode 205.

Next, FIG. 67 shows an example in which the cross section of the structure of the semiconductor device configured by combining the cross section shown in FIG. 64B with the structure of the semiconductor device of Example 3 is enlarged.

A tunnel insulating film 198 is formed on the semiconductor substrate 197, and a data holding insulating film 199 is formed thereon. On the data retention insulating film 199, a block insulating film 200 is formed.
And a first gate electrode 205 is formed thereon. A second gate electrode 206 is formed on the first gate electrode 205, and a gate electrode sidewall insulating film (polysilicon sidewall insulating film) 208 is formed on the sidewalls of the first gate electrode 205 and the second gate electrode 206. Yes.

Here, the total thickness of the block insulating film 200 below the end of the first gate electrode 205 and the gate electrode side wall insulating film 208 thereon is formed to be thicker than the thickness of the block insulating film 200 in other portions. A drain impurity region 196 is formed in the semiconductor substrate 197 below the end of the tunnel insulating film 198. In the region where the data retention insulating film 199 is not formed above the drain impurity region 196, the surface oxide film 210 is formed. An interlayer insulating film 201 is formed on the surface oxide film 210. Here, the tunnel insulating film 198
The data retention insulating film 199 and the block insulating film 200 protrude from the first gate electrode 205 toward the interlayer insulating film 201 by the thickness of the gate electrode sidewall insulating film 208.

In this embodiment, both ends of the block insulating film 200 (an insulating film including the region near the bottom of the polysilicon side wall oxide film 208) are near the source and drain impurity regions 195 and 196 and near the element isolation region 203. Although both are formed thick, they may be formed thick either in the vicinity of the source / drain impurity regions 195 and 196 and in the vicinity of the element isolation region 203. That is, a cross section taken along the line “ST” in FIG.
Only one of the cross-sections taken along the line may be adopted, and the other may be as in the prototype of Example 3.

Note that the effect of the semiconductor device of this embodiment can also be obtained as a semiconductor device having a shape as shown in FIGS.

Next, an example of a manufacturing method for realizing the semiconductor device of this embodiment will be described with reference to FIGS.

In FIGS. 68 to 76, (A) in each figure is “S--” in FIG. 64 (A).
The cross section on the “T” line and FIG. 64B correspond to the cross section on the “UV” line in FIG.

First, after a sacrificial oxide film (not shown) is formed on the semiconductor substrate 197, channel impurities and well impurities are implanted, and after the sacrificial oxide film is peeled off, as shown in FIG. Then, a tunnel insulating film 198 such as a silicon oxide film or a silicon oxynitride film having a thickness of about 1 to 15 nm is formed. Next, an insulating film such as a silicon nitride film, a silicon oxynitride film, a Ta ₂ O ₅ film, a TiO ₂ film, or an Al ₂ O ₃ film, which is a charge storage insulating film having a thickness of about _{3 to 30} nm, for example, 1 The first gate electrode 205 made of, for example, polysilicon is made 10 to 100 through the block insulating film 200 such as a silicon oxide film or a silicon oxynitride film of about ˜15 nm.
Deposit with a thickness of about nm. Further, an insulating film such as a silicon nitride film that becomes the mask material 211 is formed by 1
Deposited with a thickness of about 0-200 nm.

Next, as shown in FIG. 69A, after patterning the element isolation region by photolithography, the mask material 211 and the first gate electrode 205 are processed by anisotropic etching. Note that the element isolation region is not patterned in the cross section in FIG.

Next, as shown in FIG. 70A, the first polysilicon electrode 205 is oxidized to form a polysilicon sidewall oxide film 208. At this time, the oxidizing conditions are adjusted so that the oxidizing agent enters the edge of the gate electrode and the block insulating film 200 is thickened at the edge. Note that FIG.
In the cross section shown in B), the polysilicon side wall oxide film 208 is not formed.

Here, when the gate width of the memory cell is L _W , it is necessary to realize a uniform write / erase state while leaving a block insulating film that is not thickened by bird's beak.

For this reason, the entry length of the bird's beak needs to be ½ or less of L _W. In order to obtain this penetration length, it is necessary to make the oxide film thickness increment at the side wall of the gate electrode smaller than ¼ of L _W.

Therefore, when L _W is miniaturized to 0.2 μm or less, it is necessary to make the oxide film thickness increment smaller than 50 nm. On the other hand, when the side wall oxidation amount is 20 nm or less, the increment of the oxide film thickness is about 1/4 of the side wall oxidation amount. Here, side wall oxidation of 2 nm or more is necessary in order to avoid the damage region of element isolation film formation, and the increment of the oxide film thickness to be thickened at the end portion should be in the range of 0.6 nm to 50 nm. desirable.

Next, as shown in FIG. 71A, the gate insulating films 198, 199, 200 and the semiconductor substrate 197 are anisotropically etched to form element isolation trenches 203. Next, the side surface of the element isolation trench 203 is oxidized to form an element isolation side wall oxide film 207. As shown in FIG.
The polysilicon side wall oxide film 208 is formed by the oxidation of the first gate electrode 205 shown in FIG. 4B, and the data holding insulating film 199 is etched using the polysilicon side wall oxide film 208 as a mask. 208 and the data retention insulating film 199 can be aligned in a self-aligning manner. Therefore, the protrusion at the end of the data retention insulating film that receives damage when the element isolation insulating film of HDP-SiO ₂ described later is embedded can be made extremely small.
Reliability is improved.

Further, the sidewall oxide film thickness of the semiconductor region can be made much thinner than that of the polysilicon sidewall oxide film. The thickness can be set in the range of, for example, about 0 to 10 nm, and electric field concentration in the thin film on the convex portion of the semiconductor region can be prevented.

Here, by using a condition in which the data holding insulating film is etched so that a forward taper is formed, the silicon oxide film can be embedded in the element isolation trench in a later process more easily. The forward taper angle is preferably in the range of 60 ° to 89 ° with respect to the semiconductor substrate surface. In the manufacturing method, when embedding the element isolation insulating film, the gate electrode sidewall oxide film, the data retention insulating film, and the semiconductor substrate can all be formed in a forward taper, so that the embedding property of the element isolation insulating film is improved. , Improve reliability. In addition, read disturb characteristics are improved by placing bird's beaks in the block insulating film.

In this embodiment, both ends of the data retention insulating film are 0.5 nm or more from the semiconductor substrate.
The protrusion in the range of nm or less is desirable for reliability, and the thickness of the oxide film formed on the inner wall of the trench is preferably formed in the range of 1 nm to 16 nm.

  Next, if necessary, heat treatment for recovering etching damage may be performed.

Further, the element isolation trench is filled with an insulating film such as a silicon oxide film by a deposition method such as a silicon oxide film such as HDP-SiO 2 or TEOS, and planarized by a CMP method. Note that FIG.
In the process shown in FIG. 1B, no element isolation trench is formed.

Next, as shown in FIG. 72, the mask material 211 which is a stopper of the CMP method is removed by wet etching.

Next, as shown in FIG. 73, a stack structure of polysilicon or WSi (tungsten silicide) and polysilicon, a stack structure of NiSi, MoSi, TiSi, CoSi and polysilicon, or a stack structure of metal and polysilicon. Alternatively, a second gate electrode 206 made of a metal compound of silicon or a single layer structure of metal is deposited, and the first gate electrode 205 is deposited.
Together with the gate electrode 192 of the memory cell.

Next, as shown in FIG. 74B, a gate pattern is formed by photolithography, and the gate electrode 192 is etched by anisotropic etching. At this time, the block insulating film 200, the data holding insulating film 199, and the tunnel insulating film 198 are not etched. Note that the gate electrode is not etched in the cross section shown in FIG.

Next, as shown in FIG. 75B, the gate electrode 192 is oxidized. At this time, the oxidizing conditions are adjusted so that the oxidizing agent enters the edge of the gate electrode and the block insulating film 200 is thickened at the edge. Note that the gate electrode is not oxidized in the cross section shown in FIG.

Here, when the gate width of the memory cell is L _W , it is necessary to realize a uniform write / erase state while leaving a block insulating film that is not thickened by bird's beak.

For this reason, the entry length of the bird's beak needs to be ½ or less of L _W. In order to obtain this penetration length, it is necessary to make the oxide film thickness increment at the side wall of the gate electrode smaller than ¼ of L _W.

Therefore, when L _W is miniaturized to 0.2 μm or less, it is necessary to make the oxide film thickness increment smaller than 50 nm. On the other hand, when the side wall oxidation amount is 20 nm or less, the increment of the oxide film thickness is about 1/4 of the side wall oxidation amount. Here, side wall oxidation of 2 nm or more is necessary in order to avoid the damage region of the element isolation film formation, and the oxide film thickness increment to be thickened at the end is 0.6 nm to 50 nm.
It is desirable to be within the following range.

Next, as shown in FIG. 76B, the block insulating film 200, the data holding insulating film 199, and the tunnel insulating film 198 are etched using the gate sidewall insulating film 212 as a mask.

Next, diffusion layer impurity implantation, an interlayer insulating film 201 are deposited, and contact plugs 193, 19 are deposited.
4 is formed, and a nonvolatile memory cell is completed through processes such as metal wiring (not shown).

As described above, according to this embodiment, since the gate insulating film, particularly the block insulating film is thickened at the edge portion of the gate electrode, the electric field applied to the gate insulating film at the time of data reading can be reduced at the edge portion. As a result, read disturb characteristics are improved. In particular, the effect of increasing the thickness of the gate insulating film on two sides (two sides in contact with the element isolation end) parallel to the source-drain current flowing direction (ST direction) in FIG. Is big.

In this embodiment, the gate insulating film is thickened at all four edge portions defining the element region of the memory cell transistor, but at least one of the four sides, preferably the source,
It is only necessary that the gate insulating film, preferably the block insulating film, is thickened at two edge portions parallel to the direction in which the drain-to-drain current flows.

Further, according to the method for manufacturing the semiconductor memory device of the present embodiment, the same effects as those of the method for manufacturing the semiconductor device of Embodiment 3 can be obtained. Further, it is possible to provide a method for manufacturing a semiconductor device in which the threshold fluctuation of the memory cell due to read disturb is small.

FIG. 77 shows a MONOS type memory cell using self-aligned STI according to the sixth embodiment of the present invention. FIG. 77A shows a top view of the semiconductor device of this example, and shows an element isolation region 2.
15, source impurity regions 217 are linearly formed in the left-right direction in the semiconductor substrate 216 on one side. A drain impurity region 218 is formed in the semiconductor substrate 216 on the other side so as to face the source impurity region 217 and in contact with the element isolation region 215. A part of the source impurity region 217 is formed wide and a source contact 219 is formed there. Further, a part of the drain impurity region 218 is formed wide and a drain contact 220 is formed there. A gate electrode 220 is formed perpendicular to the longitudinal direction of the source impurity region 217 and the drain impurity region 218.

Further, the gate electrode 220 is provided with a wide region at an end thereof, and a contact 221 is provided there. In this memory cell, the semiconductor substrate 2 below the gate electrode 220
16 becomes a source impurity region 217 and a drain impurity region 218, and data is written from the source impurity region 217 to the drain impurity region 218 by the amount of current flowing in the Y to Z direction indicated by the arrow in FIG. The state and the erased state are discriminated.
Such a structure is used in an AND type EEPROM, a DINOR type EEPROM, or the like.

A cross-sectional view on the “W-X” line in FIG. 77 (A) is shown in FIG. 77 (B). A gate electrode 220 is formed on the semiconductor substrate 216. The gate electrode 220 is stacked on a gate insulating film composed of a tunnel insulating film 222, a data retention insulating film (charge storage region) 223, and a block insulating film 224. An interlayer insulating film 225 is formed on the surfaces of the semiconductor substrate 216 and the gate electrode 220. Here, the gate insulating film thickness is the edge portion 2 of the gate electrode.
26 is characterized by a thickening, and this improves the read disturb characteristics. In particular, the tunnel insulating film 222 or the block insulating film 224 is thick, and it is preferable that the edge of the block insulating film 224 is thick. This is because the non-uniform thickness of the tunnel oxide film 222 and the data holding insulating film 223 through which charges pass may cause variations in the erasing characteristics and data holding characteristics, whereas the block insulation in which no charges pass through. This is because even if the film 224 is thickened at the edge, it does not cause characteristic variation.

A cross-sectional view along the “YZ” line in FIG. 77 (A) is shown in FIG. 77 (C).
An element isolation groove 227 is provided in the semiconductor substrate 216, and an element isolation region 215 is formed therein. Between the element isolation regions 215, a gate insulating film and a gate electrode 220 including a tunnel insulating film 222, a data holding insulating film 223, and a block insulating film 224 are formed. Here, the gate insulating film thickness is increased at the edge portion 226 of the gate electrode, which improves the read disturb characteristic. Especially tunnel insulating film 2
22 or the block insulating film 224 is thick, and it is preferable that the edge of the block insulating film 224 is thick.

In this memory cell, a well, which is a low-concentration impurity region (not shown), is formed in the upper portion of the semiconductor substrate 216. A tunnel insulating film 222 is formed on the semiconductor substrate 216 from, for example, a silicon oxide film or a silicon oxynitride film having a thickness of about 1 to 15 nm. Further, on the tunnel insulating film 222, data is formed of an insulating film such as a silicon nitride film, a silicon oxynitride film, a Ta ₂ O ₅ film, a TiO ₂ film, or an Al ₂ O ₃ film having a thickness of about _{3 to 30} nm, for example. Holding insulating film 22
3 is formed.

Further, on the data holding insulating film 223, a block insulating film 224 is formed of a silicon oxide film, a silicon oxynitride film or the like having a film thickness of, for example, about 1 to 15 nm. On the block insulating film 224, for example, a stack structure of polysilicon or WSi (tungsten silicide) and polysilicon, a stack structure of NiSi, MOSi, TiSi, CoSi and polysilicon, or a stack structure of metal and polysilicon. Alternatively, a gate electrode 166 made of a silicon metal compound or a metal single layer structure is formed with a thickness of 10 nm to 500 nm. Here, a source impurity region 217 and a drain impurity region 218 are formed in the semiconductor substrate 216 in contact with the end of the element isolation region 227. This source impurity region 217
The drain impurity region 218 is a device isolation region 227 below the end of the tunnel insulating film 222.
Formed below.

In the read operation of the non-volatile memory, the read voltage Vref is applied to the gate electrode. As the read operation is repeated, the threshold value of the erased cell increases due to the electric field generated by Vref, and the cell is in the write state. There is a problem of read disturb in which the threshold margin decreases.

In this embodiment, the gate insulating films 222 and 2 are formed at the edge portions 226 and 228 of the gate electrode 220.
Since 24 is thickened, the electric field generated by Vref is weakened at the edge portions 226 and 228. Therefore, threshold fluctuation due to read disturb is suppressed at the edge portions 226 and 228 as compared with the channel center portion. This is because the memory cell is divided into regions (I), (II), (III) and regions (IV), (V), (VI) as shown in FIGS. It shows that the threshold fluctuations in the regions (I) and (III) and the regions (IV) and (VI) are reduced. In particular, the effect of reducing threshold fluctuations on two sides (element isolation ends) parallel to the “YZ” line direction in FIG. 77A, which is the direction in which the source-drain current flows, is significant.

This will be described with reference to FIGS. 78 (A), (B), and (C). In FIG. 78A, FIG.
) Is a circuit diagram of a transistor corresponding to the cross section of FIG. 78, FIG. 78B is a circuit diagram of a transistor corresponding to the cross section of FIG. 77C, and FIG. The vertical axis represents the drain current, and shows the change in the current-voltage characteristic for each state of the data retention insulating film. FIG.
In the circuit diagram shown in FIG. 8 (A), three transistors (I) whose gates are commonly connected,
A configuration in which (II) and (III) are connected in parallel between the source and drain is shown. The transistors (I), (II), and (III) correspond to the regions of the memory cell transistors (I), (II), and (III) in FIG. 77B, respectively. FIG. 78 (B
In the circuit diagram shown in FIG. 3, three transistors (IV), (V
), (VI) is shown in the source and drain connected in series. The transistors (IV), (V), (VI) are the memory cell transistors (IV) in FIG.
), (V), and (VI) respectively correspond to the areas.

FIG. 78C shows a drain current Id-gate voltage characteristic Vg characteristic of the memory cell. The threshold value of the memory cell in the erased state rises due to Vref stress at the time of reading, but the threshold value fluctuation is smaller than that of the central part (II) because the electric field is weakened at the edge parts (I) and (III). In a memory using an insulating film as a charge storage layer like a MONOS type memory, trapped charges hardly move in the insulating film, so that the edge portions (I), (II
The threshold of I) remains low compared to the central part (II). As shown in FIG. 78 (A), since the regions (I), (II), and (III) are arranged in parallel between the source and drain,
The threshold value of the memory cell is determined by regions (I) and (III) having lower threshold values. For this reason, it is possible to suppress the threshold fluctuation of the memory cell by weakening the electric field of the edge portion and suppressing the threshold fluctuation of (I) and (III).

The erase operation, write operation, and read operation of the semiconductor device of this embodiment are the same as those of the semiconductor device of the fourth embodiment.

  Next, an enlarged view of the cross section shown in FIG. 77C is shown in FIG.

Between the first gate electrode 230 and the element isolation region 215, a polysilicon sidewall insulating film 231 is formed.
Is formed. Further, a gate sidewall insulating film 232 is formed between the polysilicon sidewall insulating film 231 and the element isolation insulating film 215. This gate sidewall insulating film 232 is
The data retention insulating film 223 is formed to extend to the side surface. The second gate electrode 23
3 is formed on the first gate electrode 230, and the second gate electrode 23 is formed at the end 234 in contact with the polysilicon side wall oxide film 231, the gate side wall insulating film 232, and the element isolation region 215.
3 protrudes in the direction of the semiconductor substrate 216. As described above, the data retention insulating film 223 is formed by the thickness of the polysilicon sidewall oxide film 231 as compared with the first gate electrode 230, and the element isolation region 215.
Protruding in the direction. Further, the block insulating film 224 is formed under the end portion of the first gate electrode 230 so as to be thicker than other portions.

Further, the element isolation side wall insulating film 235 is connected to the tunnel insulating film 222 and the element isolation region 2
15 and the semiconductor substrate 216. Further, a drain impurity region 217 is formed below the end portion of the data retention insulating film 223.

In the structure shown in FIG. 79, the end portion of the data retention insulating film 223 is connected to the first gate electrode 230.
However, it is not always necessary to protrude from the first gate electrode 230. That is, as shown in FIGS. 77B and 77C, the sidewall insulating film is not formed on the gate electrode, and the end portion of the data holding insulating film 223 can be configured not to protrude from the gate electrode 220. . In this embodiment, the block insulating film is formed thick on all four sides below the end of the gate electrode of the memory cell transistor, but at least one of the four sides,
Preferably, the gate insulating film, preferably the block insulating film, may be formed thick at the ends of the two sides parallel to the direction in which the source-drain current flows.

As described above, according to the semiconductor device of this embodiment, since the gate insulating film, in particular, the block insulating film is thickened below the edge portion of the gate electrode, the electric field applied to the gate insulating film at the time of data reading is changed to the edge of the gate electrode. Therefore, the read disturb characteristic is improved. In particular, two sides (two sides defining the gate edge) parallel to the direction in which the current between the source and drain flows (the direction of the “YZ” line in FIG. 77A), that is, FIG. 77B is shown. The effect of increasing the thickness of the end portion of the gate insulating film in the cross section is significant.

  Next, an example of a method for manufacturing the semiconductor device of this embodiment will be described with reference to FIGS.

In FIGS. 80 to 88, (A) in each figure is “Y--” in FIG. 77 (A).
The cross section on the Z ”line, (B) corresponds to the cross section on the“ WX ”line in FIG. 77 (A).

First, after a sacrificial oxide film (not shown) is formed on the semiconductor substrate 216, channel impurities and well impurities are implanted, and the sacrificial oxide film is peeled off.

Next, as shown in FIGS. 80A and 80B, a tunnel insulating film 222 such as a silicon oxide film or a silicon oxynitride film having a thickness of about 1 to 15 nm is formed on the semiconductor substrate 216, for example.
For example, a silicon nitride film or silicon oxynitride film having a thickness of about 3 to 30 nm, Ta ₂ O ₅ , Ti
A data retention insulating film 223 is sequentially formed from an insulating film such as O ₂ or Al ₂ O ₃ . Further, the block insulating film 224 is formed by a silicon oxide film, a silicon oxynitride film or the like having a thickness of about 1 to 15 nm, for example. Further thereon, the first gate electrode 2 is made of, for example, polysilicon.
30 is deposited to a thickness of about 10 to 100 nm. Further, an insulating film such as a silicon nitride film is added to 10
A mask material 240 is formed by deposition with a thickness of about 200 nm.

Next, in the step shown in FIG. 81A, after patterning the element isolation region by photolithography, the mask material 240, the first gate electrode 230, the block insulating film 224, the data holding insulating film 223, and the tunnel are formed. The insulating film 232 is processed by anisotropic etching. Note that etching is not performed in the cross section shown in FIG.

Next, as shown in FIG. 82A, diffusion layer impurities are implanted into the semiconductor substrate 216 using the mask material 240 as a mask to form source and drain impurity regions 217 and 218. Subsequently, the first gate electrode 230 is oxidized. At this time, the oxidizing conditions are adjusted so that the oxidant enters the edge of the gate electrode and the block insulating film 224 is thickened at the edge. In this step, impurity implantation and oxidation are not performed in the cross section shown in FIG.

Here, when the gate width of the memory cell is L _W , it is necessary to realize a uniform write / erase state while leaving a block insulating film that is not thickened by bird's beak.

For this reason, the entry length of the bird's beak needs to be ½ or less of L _W. In order to obtain this penetration length, it is necessary to make the oxide film thickness increment at the side wall of the gate electrode smaller than ¼ of L _W.

Therefore, when L _W is miniaturized to 0.2 μm or less, it is necessary to make the oxide film thickness increment smaller than 50 nm. On the other hand, when the side wall oxidation amount is 20 nm or less, the increment of the oxide film thickness is about 1/4 of the side wall oxidation amount. Here, side wall oxidation of 2 nm or more is necessary in order to avoid the damage region of the element isolation film formation, and the oxide film thickness increment to be thickened at the end portion. 0.6nm to 50nm
It is desirable to be within the following range.

Next, as shown in FIG. 83A, an insulating film such as a silicon oxide film is formed to, for example, 5 to 50 nm.
After depositing to a certain thickness, etching back is performed by anisotropic etching to form a gate sidewall insulating film 242. Using this as a mask, the semiconductor substrate 261 is processed by anisotropic etching to form an element isolation trench 227. . Here, the depth of the element isolation groove 227 to be formed is, for example, about 50 nm to 300 nm. Note that the element isolation trench is not formed in the cross section shown in FIG. By forming the gate sidewall insulating film 242 in this way, the source and drain impurity regions 217 and 218 can be left at the channel end. The widths of the remaining source / drain impurity regions 217 and 218 can be controlled in accordance with the width of the remaining gate sidewall insulating film 242.

Next, after performing a heat treatment for recovering etching damage as necessary, FIG.
As shown in FIG. 2, the element isolation trench 227 is filled with an insulating film such as a silicon oxide film by a deposition method such as a silicon oxide film such as HDP-SiO2 or TEOS, and is planarized by a CMP method, and then is stopped by a CMP method stopper. A certain mask material 240 is removed by wet etching.
In the cross section shown in FIG. 84B, the mask material 240 is removed to expose the upper surface of the first gate electrode 230.

Next, as shown in FIG. 85, for example, a stack structure of polysilicon or WSi and polysilicon, a stack structure of NiSi, MoSi, TiSi, CoSi and polysilicon, a stack structure of metal and polysilicon, or silicon A second gate electrode 233 having a single layer structure of the above metal compound or metal is deposited, and together with the first gate electrode 230, the gate electrode 220 of the memory cell is formed.

Next, as shown in FIG. 86B, a gate pattern is formed by photolithography, and the gate electrode 220 is etched by anisotropic etching. At this time, the block insulating film 224 is slightly etched in a normal case, but the data holding insulating film 223 is etched.
Do not etch. Furthermore, you may perform the heat processing for an etching damage recovery as needed. In addition, after this step, for example, in the range of 2 nm to 20 nm,
Damage may be recovered by oxidizing the first gate electrode. In addition, FIG. 86 (
In the cross section shown in A), the gate electrode 220 is not etched.

Next, as shown in FIG. 87B, the gate electrode 220 is oxidized to form a gate sidewall insulating film 241. At this time, the oxidizing condition is adjusted so that the oxidizing agent enters the edge of the gate electrode 220 and the block insulating film 224 is thickened at the edge.

Here, if the gate width of the memory cell is L _W , it is necessary to leave the block insulating film 224 that is not thickened by bird's beak and realize a uniform write / erase state. For this reason, the entry length of the bird's beak needs to be ½ or less of L _W. The oxide film thickness of the block insulating film 224 for obtaining this penetration length needs to make the increment of the oxide film thickness on the side wall portion of the gate electrode 220 smaller than 1/4 of L _W.

Therefore, when L _W is miniaturized to 0.2 μm or less, it is necessary to make the oxide film thickness increment smaller than 50 nm. On the other hand, when the side wall oxidation amount is 20 nm or less, the increment of the oxide film thickness is about 1/4 of the side wall oxidation amount. Here, side wall oxidation of 2 nm or more is necessary in order to avoid the damage region of the element isolation film formation, and the oxide film thickness increment to be thickened at the end portion. 0.6nm to 50nm
It is desirable to be within the following range. Note that the gate sidewall insulating film 241 is not formed in the cross section shown in FIG.

Next, as shown in FIG. 88B, the gate electrode 220 and the gate sidewall insulating film 241 are formed.
As a mask, the block insulating film 224, the data holding insulating film 223, and the tunnel insulating film 222 on the semiconductor substrate 216 in the region other than the region below the gate electrode 220 are etched. Next, an interlayer insulating film 215 is deposited on the exposed surface, and the contact plug 22 is placed in the interlayer insulating film 215.
1 is formed, and a nonvolatile memory cell is completed through a process of forming a metal wiring (not shown) and the like.

According to the semiconductor device manufacturing method of the present embodiment, the same effects of the semiconductor device manufacturing method as in the fifth embodiment can be obtained.

(Modification of Example 6)
In this modification, a virtual ground array cell structure is realized as shown in FIG. FIG. 89 shows an enlarged view of the structure corresponding to the cross section shown in FIG. Here, unlike the sixth embodiment, the element isolation region 190 is not provided. Instead, for example, a P-type high concentration impurity region 245 is provided in the semiconductor substrate 216. A source diffusion layer 217 is formed in the semiconductor substrate 210 adjacent to the P-type high concentration impurity region 245. Also,
An interlayer insulating film 215 is formed on the P-type high concentration impurity region 245 with a silicon oxide film 246 interposed therebetween.

A tunnel insulating film 222 is formed on the semiconductor substrate 216. A data holding insulating film 223 is formed on the tunnel insulating film 222 and a part of the silicon oxide film 246 in contact with the tunnel insulating film 222. A block insulating film 224 is formed on the data retention insulating film 223. On the block insulating film 224, the first gate electrode 23 is formed.
0 and the second gate electrode 233 are stacked.

A gate electrode sidewall insulating film 232 is formed on the sidewalls of the first gate electrode 230 and the second gate electrode 233, and the gate electrode sidewall insulating film 2 is formed under the edge portion of the first gate electrode 230.
32 and the block insulating film 224 have a total thickness other than the edge portion of the block insulating film 22
4 is formed to be thicker than 4. Further, the data retention insulating film 223 is formed to protrude in the left-right direction in FIG. 89 from the edge of the first gate electrode 230.

This semiconductor device manufacturing method is the same as that of the semiconductor device manufacturing method of Embodiment 6 shown in FIG.
The step of etching the semiconductor substrate shown in FIG. 3 is not necessarily required to realize the virtual ground array cell structure, and the mask material 24 is formed from the surface of the semiconductor substrate 216.
A process of embedding an insulating film up to a height of 0 can be substituted.

Thereafter, in place of the process shown in FIG. 83A, as shown in FIG. 89, for example, boron or indium is used to improve element isolation between adjacent second gate electrodes. P-type impurities may be implanted in the range of 10 ¹¹ cm ⁻² to 10 ¹⁴ cm ⁻² . At this time, since the element isolation film or the side wall insulating film is also formed on the upper portion of the source and drain electrode portions in advance, by limiting the ions of the P-type impurity to stop at the element isolation film, The drain electrode can be limited not to be mixed with P-type impurities. The ion implantation energy of this P-type impurity is in the range of 1 eV to 100 eV. At this time, damage introduced into the charge storage film of the P-type impurity implanted ions can be separated by the gate electrode side wall insulating film, and a more reliable memory cell can be realized.

In the virtual ground array cell having such a shape, a P plus diffusion layer or an N plus diffusion layer is formed in place of the element isolation region by embedding an insulator, and each plays a role of element isolation. Here, the N plus diffusion layer becomes a bit line or a source line and is not fixed.

This modification has the same effect as that of the sixth embodiment. Further, in order to improve element isolation between adjacent gate electrodes, for example, when a P-type impurity made of boron or indium is added, It is possible to suppress the formation of the inversion layer at the edge portion, and to reduce the occurrence of problems such as variations in breakdown voltage between channels between memory cells in contact with each other and current leakage.

90 and 91 show the structure of the semiconductor device according to Example 7 of the present invention. The present embodiment is a memory cell having the characteristics of the third and fifth embodiments, and is a type of typical nonvolatile memory device, NAN.
A D-type EEPROM is configured.

Here, FIG. 90A shows an equivalent circuit diagram of the NAND type EEPROM, and FIG. 90B shows a plan view of the memory cell. Here, in the NAND type EEPROM, the memory is connected between the source line contact and the bit line contact via the source selection transistor S1 in which the SSL signal line is input to the gate and the source selection transistor S2 in which the GSL signal line is input to the gate. Cell transistors M0 to M15 are arranged in series to constitute one NAND memory cell block. The gate electrode (control gate) of each memory cell transistor is connected to data selection lines (word lines) WL0 to WL15. A well potential is applied to the back gate of each of the memory cell transistors M0 to M15.

In addition, as shown in FIG. 90B, a plurality of bit lines BL are arranged in a straight line parallel to each other at regular intervals in the vertical direction in the figure. A plurality of word lines are arranged below the bit lines in parallel to each other perpendicular to the bit lines BL. Each word line WL0-WL
15, an element isolation region 250 is formed outside the bit line, and the source / drain region 251 is insulated and isolated. A bit line contact 252 is formed in the source / drain region 251 adjacent to the SSL signal line of the bit line BL. An SL contact 253 to which a ground potential is applied is connected to the source / drain region 251 adjacent to the GSL signal line of the bit line BL.

Further, FIG. 91A shows a cross-sectional view of the memory cell in the row direction when cut in parallel to the word line (a cross-sectional view along the “III-IV” line in FIG. 90B), and FIG. ) Shows a cross-sectional view of the memory cell in the column direction ("I-I" in FIG. 90B) when cut perpendicular to the word line.
Sectional view on line I ”).

In FIG. 90, the number of memory cell transistors in one NAND block is 16, and the selection transistor has a MOS structure different from that of the memory cell. The number is not limited to 16, and the selection transistor may have the same MONOS structure as the memory cell. The structure shown in FIG. 90 is a combination of the structures of the semiconductor devices of the third and fifth embodiments.

As shown in FIG. 91A, in this memory cell, an N-type well 256 is formed on a semiconductor substrate 255, and a P-type well 257 is formed on the N-type well 256. An element isolation groove 258 is provided in the P-type well 257, and an insulating material is buried in the element isolation groove 258 to form a plurality of element isolation regions 259. On the P-type well 257 between the plurality of element isolation regions 259, a tunnel insulating film 260 is formed of, for example, a silicon oxide film or a silicon oxynitride film having a thickness of about 1 to 15 nm. further,
On this tunnel insulating film 260, a data retention film such as a silicon nitride film, a silicon oxynitride film, a Ta ₂ O ₅ film, a TiO ₂ film, an Al ₂ O ₃ film or the like having a film thickness of about _{3 to 30} nm, for example. 261
Is formed.

Further, on the data holding film 261, a block insulating film 262 is formed of a silicon oxide film, a silicon oxynitride film or the like having a film thickness of, for example, about 1 to 15 nm.

On the block insulating film 262, for example, a stack structure of polysilicon, WSi (tungsten silicide) and polysilicon, or NiSi, MOSi, TiSi, Co
A first gate electrode 263 and a second gate electrode 264 made of a stack structure of Si and polysilicon, a stack structure of metal and polysilicon, or a single layer structure of a metal compound or metal of silicon
A word line WL having a laminated structure of 10 nm to 500 nm is formed. A first interlayer insulating film 265 is formed on the second gate electrode 264. A plurality of bit lines BL are formed above the first interlayer insulating film 265. A second interlayer insulating film 266 is formed on the bit line BL and the first interlayer insulating film 265.

Here, the data holding insulating film 261 is formed with its end protruding into the element isolation region 259. Further, the block insulating film 262 is formed to be thicker at the end portion in contact with the element isolation region 259 than at other portions.

Here, the protruding length of the data holding insulating film 261 and the degree of thickening of the block insulating film are the same as in the third and fifth embodiments described above.

In the cross section shown in FIG. 91 (B), the memory cell transistor has a P-type well 25.
7 are formed on a plurality of tunnel insulating films 260 separated from each other, a data holding insulating film 261 thereon, and a block insulating film 262 thereon. Here, a gate electrode sidewall insulating film 267 is formed around the gate electrode. This gate electrode side wall insulating film 2
The block insulating film 262 is formed to be narrower than the tunnel insulating film 260 and the data holding insulating film 261 by the width of 67. A source / drain region 251 is formed near the upper surface in the P-type well 257 between the gate electrodes.

The selection transistor S1 at one end of the memory cell column is formed on the gate insulating film 268 provided on the P-type well 257 with a stacked structure of the first gate electrode 269 and the second gate electrode 270, and around it. A gate sidewall insulating film 271 is formed. Gate insulating film 268
Is formed under the edge of the first gate electrode 269 so that its thickness is thicker than the thickness of other portions. The width of the selection transistor S1 is formed larger than the width of the memory cell transistor. A bit line contact 252 is connected to the source / drain region 251 in the P-type well 257 at the end of the selection transistor S1. This bit line contact 2
52 is provided in the first interlayer insulating film 265 and connected to the bit line BL.

The selection transistor S2 at the other end of the memory cell column is formed on the P-type well 257 in the same manner as the selection transistor S1. P-type well 25 at the end of this select transistor S2
A source line contact 253 is connected to the source / drain region 251 in FIG.
The source line contact 253 is provided in the first interlayer insulating film 265 and is connected to the source line 272 provided in the first interlayer insulating film 265.

Next, the operation of the semiconductor device of this embodiment will be described. The erasing operation is performed, for example, by applying a high voltage (for example, 10 to 25 V) to the semiconductor substrate with the gate electrode at 0 V and injecting holes from the semiconductor substrate into the charge storage region. Alternatively, the drain potential is negatively biased with respect to the source potential to generate hot holes accelerated in the channel, and the gate electrode is negatively biased with respect to the source potential to inject the hot holes into the charge storage region. Done in Alternatively, the source potential and drain potential are positively biased with respect to the well potential to generate a hot hole at the junction between the impurity region and the well, and the gate electrode is negatively biased with respect to the well potential to charge the hot hole. This is done by injecting into the accumulation region.

In the writing operation, for example, the semiconductor substrate is set to 0 V and a high voltage (for example, 10%) is applied to the gate electrode.
˜25V) is applied, the charge is transferred from the semiconductor substrate through the tunnel insulating film, and electrons are injected into the charge storage region. Alternatively, the drain potential is positively biased with respect to the source potential to generate hot electrons accelerated in the channel, and the gate electrode is positively biased with respect to the source potential to inject hot electrons into the charge storage region. Done in

In the read operation, the bit line connected to the drain contact is precharged and then floated, and the voltage of the gate electrode of the memory cell selected for reading is set to the read voltage Vref and the source line is set to 0 V. This is done by detecting this with a bit line. The voltage of the control gate of the memory cell that is not selected for reading is defined as a non-selected reading voltage Vread. The gate voltages of the selection transistors S1 and S2 are set to the power supply voltage Vc.
c, the source line is set to 0V. This is done by detecting whether or not a current flows through the memory cell selected for reading by the bit line BL. That is, as shown in FIG. 92, Vref is applied to the gate of the selected memory cell M2 to be read, and Vread is applied to the gates of the other non-read memory cells M0, M1, M3 to M15. Select gate S
Vdd is applied to the gates of 1 and S2.

That is, if the threshold value Vth of the memory cell is larger than Vref, and the memory cell is turned off in the writing state, the bit line maintains the precharge potential. On the other hand, if the threshold value Vth of the selected memory cell is smaller than Vref, the memory cell is turned on, so that the potential of the bit line is lowered by ΔV from the precharge potential.

Data in the memory cell is read by detecting this potential change with a sense amplifier. By changing the amount of charge in the charge storage insulating film, the threshold voltage of the memory cell changes, and data can be read by detecting this.

Here, Vref is an intermediate voltage between the threshold value in the write state and the threshold value in the erase state.
ad is a voltage higher than the threshold value of the write state, and Vdd is a voltage higher than the threshold value of the selection transistor.

In reading from the NAND-type EEPROM, the voltage Vread higher than the write threshold is applied to the read unselected word line as described above. Therefore, compared with the case where the voltage Vref as described in the fifth and sixth embodiments is used, read is performed. Threshold fluctuation due to disturbance is large.

In contrast, in the semiconductor device of this embodiment, since the block insulating film is thickened under the edge portion of the gate electrode, the electric field due to Vread is weakened at the edge portion, and the increase in the erase threshold is small. When the data holding insulating film is used as the charge storage region, the charge does not move through the data holding insulating film. Therefore, even if the threshold value at the center of the channel rises due to read disturb, the threshold value at the edge portion remains low. In particular, since the threshold value at two sides parallel to the direction in which the read current flows, that is, at the element isolation end is kept low, the threshold value of the memory cell can be kept low, so that the problem of an increase in erase threshold due to Vread stress can be solved. .

In the present embodiment, both ends of the data holding insulating film protrude from the end of the element isolation region and the edge of the gate electrode. For this reason, both ends of the data retention insulating film whose charge retention characteristics have deteriorated due to damage during processing are not used as a charge storage region or a gate insulating film of a transistor, improving the reliability of the memory cell. To do. In particular, since the data retention insulating film protrudes at two sides parallel to the direction in which the read current flows, that is, at the element isolation end, a threshold decrease due to charge loss at the edge of the gate electrode is detected as a threshold decrease of the memory cell. Can solve the problem.

Furthermore, in the semiconductor device of this embodiment, since the data holding insulating film is not shared between adjacent memory cells, the exchange of charges occurs between the memory cells by moving the charges through the insulating film.
The problem that the threshold value of the memory cell fluctuates is solved.

As described above, the example in which the memory cell having the characteristics of the first and third embodiments is applied to the NAND-type EEPROM has been described, but the scope of application is not limited to this. That is, a memory cell having the characteristics of Embodiments 3 to 6 may be used, or a memory cell having only a part of the characteristics of Embodiments 3 to 6 may be used.

(Modification of Example 7)
The EEPROM to which this embodiment is applied is not limited to the NAND type.

That is, the equivalent circuit diagram shown in FIG. 93A, which is the present modification, and an AND type EEPROM showing the potential in the read operation state may be used. That is, the drains of the memory cell transistors M0 to M15 constituting one memory cell are commonly connected to the drain of the selection transistor S1 whose source is connected to the bit line BL. The sources of the memory cell transistors M0 to M15 are connected in common to each other, and the selection transistor S2
Connected to the drain. The source of the selection transistor S2 is the common source line Sou
connected to rce. Here, at the time of reading, Vref is input to the gate of the memory cell transistor M2 selected for reading, and the other memory cell transistors M0, M
1, Vread is input to the gates of M3 to M15. Select transistor S1, S2
Vdd is input to the gates of the two.

Further, the NOR type EEPR showing the equivalent circuit diagram and the reading operation shown in FIG.
OM may be sufficient. The drain of the memory cell transistor M1 is connected to the first bit line BL1. The drain of the memory cell transistor M2 is connected to the source of the memory cell transistor M1, and the drain of the memory cell transistor M3 is connected to the source of the memory cell transistor M2. A source potential VSL is input to the source of the memory cell transistor M3. The drain of the memory cell transistor M4 is connected to the adjacent bit line BL2. The source of the memory cell transistor M4 is connected to the drain of the memory cell transistor M5, and the source of the memory cell transistor M5 is connected to the drain of the memory cell transistor M6 and the bit line BL2. A source potential VSL is input to the source of the memory cell transistor M6.

Here, the Vref potential is applied to the gate of the selected memory cell transistor M2 selected for reading and the memory cell transistor M5 connected to the adjacent bit line, and the source of the selected memory cell transistor M2 selected for reading is The selected bit line BL1 is connected. The VSL potential is applied to the sources of the memory cell transistors M1 and M4. Further, Vre is connected to the gates of the memory cell transistors M1, M3, M4 and M6.
An ad potential is applied.

Although not shown, the present invention can also be applied to other types of EEPROM such as DINOR type.
An EEPROM having a virtual ground array structure may be used. In the case of the AND type, the semiconductor device having the structure of Example 4 or 6 is applied. In the case of the NOR type, the semiconductor device having the structure of Example 3 or 5 is applied. In the virtual ground array type semiconductor device, the semiconductor devices of Examples 3 to 6 are applied.

In any type of EEPROM, both ends of the data holding insulating film protrude from the gate electrode and / or the semiconductor substrate, thereby solving the deterioration of the data holding characteristics at the edge of the gate electrode. In addition, since both ends of the data holding insulating film protrude particularly on two sides parallel to the direction in which the read current flows, the problem that a threshold value decrease at the edge of the gate electrode is detected as a memory cell threshold value is solved. That is, since the data holding insulating film damaged during the manufacturing process does not exist in the channel region, the threshold value can be prevented from being lowered and the data holding characteristics can be improved.

Further, the gate insulating film, preferably the block insulating film disposed between the data holding insulating film and the gate electrode is thickened at the edge of the gate electrode, thereby changing the threshold due to the gate voltage stress during data reading. Can be suppressed at the edge portion of the gate electrode. In particular, since the gate insulating film, preferably the block insulating film, is thickened on two sides parallel to the direction in which the read current flows, the threshold fluctuation suppression at the edge portion of the gate electrode is suppressed as the threshold fluctuation of the memory cell. As a result, the read disturb characteristic of the memory cell is improved. In particular, it is possible to prevent the threshold value from increasing when a weak electric field is applied.

Here, the protruding length of the data retention insulating film and the degree of thickening of the block insulating film are the same as those in the fourth and sixth embodiments described above.

Further, by cutting the data holding insulating film between adjacent memory cells, it is possible to prevent threshold fluctuation due to charge exchange between the memory cells.

In the above-described Examples 3 to 6, an example in which a contact electrode is formed for each transistor is shown for easy understanding, but a contact electrode is not formed for each transistor as in this example. For example, it can be configured by connecting in series or in parallel by a gate electrode or a drain electrode.

The present invention can be configured as described in the following supplementary notes.
(Supplementary Note 1) A step of forming a first gate insulating film on a semiconductor substrate of a peripheral circuit unit having a high voltage transistor region and a low voltage transistor region and a memory unit, and a low voltage transistor region of the peripheral circuit unit and the memory unit Removing the first gate insulating film, forming a second gate insulating film comprising a multilayer film including a silicon nitride film on the entire surface, and forming the memory section and the peripheral circuit section after forming the second gate insulating film. Forming a trench groove in the semiconductor substrate, burying an insulator in the trench groove to form a shallow trench isolation region, and silicon nitride in the second gate insulating film of the peripheral circuit portion After removing the membrane
Forming a low voltage transistor gate insulating film and a high voltage transistor gate insulating film in the peripheral circuit section by thermal oxidation; and the gate insulating film, low voltage transistor gate insulating film and high voltage transistor gate insulating film in the memory section, And a step of forming a gate electrode on the shallow trench isolation region.

(Supplementary Note 2) In the step of forming the gate electrode, a plurality of gate electrodes in the memory portion and a plurality of gate electrodes in the peripheral circuit portion are simultaneously formed, and after the step of forming the gate electrode, the peripheral circuit portion Introducing a first conductivity type impurity into the first number of gate electrodes, introducing a second conductivity type impurity into the second number of gate electrodes of the peripheral circuit portion, and a first of the memory portion. The method of manufacturing a semiconductor device according to claim 1, further comprising: introducing a first conductivity type impurity into the number of gate electrodes; and introducing a second conductivity type impurity into the second number of gate electrodes of the memory section. Method.

(Supplementary Note 3) Forming a first gate insulating film on a semiconductor substrate of a memory portion having a memory cell transistor region and a select transistor region, and a peripheral circuit portion having a low voltage transistor region and a high breakdown voltage transistor region, and the peripheral circuit A step of removing the first gate insulating film of the memory portion, a step of forming a second gate insulating film made of a multilayer film including a silicon nitride film, and a step of forming the second gate insulating film A step of forming a trench groove in the semiconductor substrate of the memory portion and the peripheral circuit portion later, a step of filling an insulator in the trench groove to form a shallow trench isolation region, and a select transistor region of the memory portion And removing the silicon nitride film from the second gate insulating film of the peripheral circuit portion, and then thermally oxidizing the periphery. A step of forming a low voltage transistor gate insulating film and a high voltage transistor gate insulating film in the side circuit portion; a gate insulating film of the memory cell transistor; a gate insulating film of the selection transistor; a low voltage transistor gate insulating film; And a step of forming a gate electrode on the insulating region and the shallow trench isolation region.

(Supplementary Note 4) A semiconductor substrate, a first conductivity type element region having substantially four sides formed in the semiconductor substrate, and a first conductivity type formed on two opposite sides of the element region, respectively. A source electrode and a drain electrode of reverse conductivity type, a first gate insulating film provided on the element region, and provided on the first gate insulating film, capable of storing data and electrically And a charge storage region having two ends on two sides where a source electrode and a drain electrode are not formed, and the source on the lower surface provided on the charge storage region. The distance between two opposing sides where the electrode and the drain electrode are not formed is 2 on the two sides where the source electrode and the drain electrode are not formed on the upper surface of the charge storage region.
A semiconductor device comprising: at least one gate electrode formed smaller than a distance between two ends.

(Supplementary Note 5) The distance between the two opposite sides where the source electrode and the drain electrode are not formed on the lower surface of the gate electrode is 10 nm to 100 than the distance between the two ends of the charge storage region.
The semiconductor device according to appendix 4, which is small in the range of nm.

(Supplementary Note 6) The distance between the two ends of the charge storage region is larger than the distance between two sides of the element region where the source electrode and the drain electrode are not formed on the surface facing the first gate insulating film. The semiconductor device according to appendix 4, which is long.

(Supplementary Note 7) The distance between the two ends of the charge storage region is larger than the distance between the two sides of the element region where the source electrode and the drain electrode are not formed on the surface facing the first gate insulating film. The semiconductor device according to appendix 4, which is long in a range of 1 nm to 30 nm.

(Supplementary Note 8) A semiconductor substrate, a first conductivity type element region having substantially four sides formed in the semiconductor substrate, a first gate insulating film provided on the element region, and the semiconductor substrate A source electrode and a drain electrode having a conductivity type opposite to that of the first conductivity type formed therein and the first gate insulating film are provided, and can store data and can be electrically written and erased. An insulating film having two ends on two opposite sides, wherein at least the source electrode and the drain electrode are in a conductive state, a direction in which a current flows on the element formation region is a first direction, and the semiconductor If the direction perpendicular to the first direction on the substrate surface is the second direction, the upper surface is provided with a charge storage region having two ends in the second direction, and on the charge storage region, The second on the lower surface At least one gate electrode formed so that a length of two sides in the direction of the first electrode is shorter than a distance between two ends of the charge storage region in the second direction on the upper surface of the charge storage region; Connected to the source electrode and drain electrode,
A semiconductor device comprising: at least two current terminals for detecting a data storage state of the charge storage region depending on whether it is in a conductive state or a cut-off state.

(Supplementary Note 9) The length of two sides in the second direction of the gate electrode on the surface facing the charge storage region is 10 nm longer than the length of the two ends of the charge storage region in the second direction. 9. The semiconductor device according to appendix 8, which is short in a range of 100 nm to 100 nm.

(Supplementary Note 10) The length of the two ends of the charge storage region in the second direction is such that the length of the device region in the second direction is the surface of the device region facing the first gate insulating film. Item 9. The semiconductor device according to appendix 8, which is longer than the length.

(Supplementary Note 11) The length of the two ends of the charge storage region in the second direction is such that the length of the device region in the second direction is the surface of the device region facing the first gate insulating film. Item 9. The semiconductor device according to appendix 8, which is longer in a range of 1 nm to 30 nm than the length.

(Supplementary Note 12) The gate electrode includes a lower conductor formed of a rectangular region having two sides substantially parallel to the first direction and two sides substantially parallel to the second direction; 12. The semiconductor device according to any one of appendices 4 to 11, further comprising: an upper conductor that shares one of two opposing sides of the lower conductor and electrically connects the lower conductors in a plurality of adjacent gate electrodes.

(Additional remark 13) It further comprises the side wall insulating film formed in the side wall part of the said gate electrode, and
When the side of the side wall insulating film that is in contact with the gate electrode is a first side surface, the end of the charge storage insulating film is located on the surface facing the gate electrode so that the gate electrode is closer than the first side surface. 13. The semiconductor device according to any one of appendices 4 to 12, wherein the semiconductor device is formed up to a non-formed side.

(Supplementary note 14) The supplementary note 4 to 13, further comprising a second gate insulating film provided on the charge storage region, wherein the gate electrode is formed on the second gate insulating film. Semiconductor device.

(Supplementary Note 15) A semiconductor substrate, a first conductivity type element region having substantially four sides formed in the semiconductor substrate, a first gate insulating film provided on the element region, A charge storage region which is provided on one gate insulating film and is made of an insulating film capable of storing data and electrically writable and erasable and having two ends on two opposite sides; At least one gate electrode provided on the region, a source electrode and a drain electrode having a conductivity type opposite to the first conductivity type provided in the semiconductor substrate, and provided on the source electrode and the drain electrode, respectively. By the conduction state and the cutoff state between the source electrode and the drain electrode,
A current terminal that detects a storage state of the charge storage region, and is disposed between the charge storage region and the gate electrode, and at least the current terminal is in a conductive state, and a direction in which a current flows over the element region is a first direction. When the direction perpendicular to the first direction on the semiconductor substrate surface is the second direction, the charge in the second direction is lower than that below the center of the gate electrode on the surface facing the charge storage region. A second gate insulating film that is thick below the end of the gate electrode on the surface facing the storage region, and the thickness of the first gate insulating film is below the center of the gate electrode on the surface facing the charge storage region; In comparison, a semiconductor device that is thick under the edge of the gate electrode on the surface facing the charge storage region.

(Supplementary Note 16) The gate electrode has at least two layers of stacked conductor regions, each of which is a lower conductor and an upper conductor in the stacking direction, and the lower conductor is substantially in the first direction. Formed in a rectangular region having two sides parallel to each other and two sides substantially parallel to the second direction, and the upper conductor shares one of the two opposite sides of the lower conductor. The semiconductor device according to appendix 15, wherein a plurality of adjacent lower conductors are electrically connected.

(Supplementary Note 17) The gate electrode is disposed adjacent to at least a part of the gate electrode,
Additional remarks 4 to 16 further comprising an element isolation region having an element isolation groove formed in a self-aligned manner with respect to at least one of the first gate insulating film, the charge storage insulating film, and the second gate insulating film. Any one of the semiconductor devices.

(Supplementary note 18) The semiconductor device according to any one of supplementary notes 4 to 17, wherein a plurality of the gate electrodes are arranged on the semiconductor substrate, and the charge storage layers are separated between the adjacent gate electrodes.

(Additional remark 19) Additional remarks 4 thru | or 1 further equipped with the element isolation area | region which is arrange | positioned adjacent to at least one part of the said 1st gate electrode, and has the high concentration impurity region provided in the said semiconductor substrate.
The semiconductor device according to any one of 6 and 18.

FIG. 3 is a cross-sectional view in the row direction illustrating the configuration of the memory unit according to the first embodiment of the invention. FIG. 3 is a cross-sectional view in the row direction showing the configuration of the prototype memory unit according to the first embodiment of the invention. FIG. 3 is an enlarged view of a shallow trench element isolation region edge portion in the row direction of the prototype memory portion according to the first embodiment of the invention. FIG. 5 is a voltage-current characteristic diagram in a writing state for each region of the prototype memory cell transistor according to the first embodiment of the invention. FIG. 4 is a voltage-current characteristic diagram in a write state of the prototype memory cell transistor according to the first embodiment of the invention. FIG. 5 is a voltage-current characteristic diagram in a write / erase state of the prototype memory cell transistor according to the first embodiment of the invention. Sectional drawing of the row direction of the high voltage transistor which concerns on Example 1 of this invention. Sectional drawing of the low direction of the low voltage transistor which concerns on Example 1 of this invention. FIG. 2 is a plan view illustrating a configuration of a memory unit according to the first embodiment of the invention. FIG. 3 is a cross-sectional view in the column direction of the memory unit according to the first embodiment of the invention. FIG. 3 is a circuit diagram illustrating a NAND string of the memory unit according to the first embodiment of the invention. (A) is sectional drawing of the row direction showing 1 process of the manufacturing method of the memory cell transistor and selection transistor which concern on Example 1 of this invention, (b) is the low voltage which concerns on Example 1 of this invention FIG. 4C is a cross-sectional view in the row direction showing one step of the method for manufacturing a transistor, and FIG. 4C is a cross-sectional view in the row direction showing one step in the method for manufacturing the high voltage transistor according to Example 1 of the present invention. (A) is sectional drawing of the row direction showing 1 process of the manufacturing method of the memory cell transistor and selection transistor which concern on Example 1 of this invention, (b) is the low voltage which concerns on Example 1 of this invention FIG. 4C is a cross-sectional view in the row direction showing one step of the method for manufacturing a transistor, and FIG. 4C is a cross-sectional view in the row direction showing one step in the method for manufacturing the high voltage transistor according to Example 1 of the present invention. (A) is sectional drawing of the row direction showing 1 process of the manufacturing method of the memory cell transistor and selection transistor which concern on Example 1 of this invention, (b) is the low voltage which concerns on Example 1 of this invention FIG. 4C is a cross-sectional view in the row direction showing one step of the method for manufacturing a transistor, and FIG. 4C is a cross-sectional view in the row direction showing one step in the method for manufacturing the high voltage transistor according to Example 1 of the present invention. (A) is sectional drawing of the row direction showing 1 process of the manufacturing method of the memory cell transistor and selection transistor which concern on Example 1 of this invention, (b) is the low voltage which concerns on Example 1 of this invention FIG. 4C is a cross-sectional view in the row direction showing one step of the method for manufacturing a transistor, and FIG. 4C is a cross-sectional view in the row direction showing one step in the method for manufacturing the high voltage transistor according to Example 1 of the present invention. (A) is sectional drawing of the row direction showing 1 process of the manufacturing method of the memory cell transistor and selection transistor which concern on Example 1 of this invention, (b) is the low voltage which concerns on Example 1 of this invention FIG. 4C is a cross-sectional view in the row direction showing one step of the method for manufacturing a transistor, and FIG. 4C is a cross-sectional view in the row direction showing one step in the method for manufacturing the high voltage transistor according to Example 1 of the present invention. (A) is sectional drawing of the row direction showing 1 process of the manufacturing method of the memory cell transistor and selection transistor which concern on Example 1 of this invention, (b) is the low voltage which concerns on Example 1 of this invention FIG. 4C is a cross-sectional view in the row direction showing one step of the method for manufacturing a transistor, and FIG. 4C is a cross-sectional view in the row direction showing one step in the method for manufacturing the high voltage transistor according to Example 1 of the present invention. (A) is sectional drawing of the row direction showing 1 process of the manufacturing method of the memory cell transistor and selection transistor which concern on Example 1 of this invention, (b) is the low voltage which concerns on Example 1 of this invention FIG. 4C is a cross-sectional view in the row direction showing one step of the method for manufacturing a transistor, and FIG. 4C is a cross-sectional view in the row direction showing one step in the method for manufacturing the high voltage transistor according to Example 1 of the present invention. (A) is sectional drawing of the row direction showing 1 process of the manufacturing method of the memory cell transistor and selection transistor which concern on Example 1 of this invention, (b) is the low voltage which concerns on Example 1 of this invention FIG. 4C is a cross-sectional view in the row direction showing one step of the method for manufacturing a transistor, and FIG. 4C is a cross-sectional view in the row direction showing one step in the method for manufacturing the high voltage transistor according to Example 1 of the present invention. (A) is sectional drawing of the row direction showing 1 process of the manufacturing method of the memory cell transistor and selection transistor which concern on Example 1 of this invention, (b) is the low voltage which concerns on Example 1 of this invention FIG. 4C is a cross-sectional view in the row direction showing one step of the method for manufacturing a transistor, and FIG. 4C is a cross-sectional view in the row direction showing one step in the method for manufacturing the high voltage transistor according to Example 1 of the present invention. (A) is sectional drawing of the row direction showing 1 process of the manufacturing method of the memory cell transistor and selection transistor which concern on Example 1 of this invention, (b) is the low voltage which concerns on Example 1 of this invention FIG. 4C is a cross-sectional view in the row direction showing one step of the method for manufacturing a transistor, and FIG. 4C is a cross-sectional view in the row direction showing one step in the method for manufacturing the high voltage transistor according to Example 1 of the present invention. (A) is sectional drawing of the row direction showing 1 process of the manufacturing method of the memory cell transistor and selection transistor which concern on Example 1 of this invention, (b) is the low voltage which concerns on Example 1 of this invention FIG. 4C is a cross-sectional view in the row direction showing one step of the method for manufacturing a transistor, and FIG. 4C is a cross-sectional view in the row direction showing one step in the method for manufacturing the high voltage transistor according to Example 1 of the present invention. (A) is sectional drawing of the row direction showing 1 process of the manufacturing method of the memory cell transistor and selection transistor which concern on Example 1 of this invention, (b) is the low voltage which concerns on Example 1 of this invention FIG. 4C is a cross-sectional view in the row direction showing one step of the method for manufacturing a transistor, and FIG. 4C is a cross-sectional view in the row direction showing one step in the method for manufacturing the high voltage transistor according to Example 1 of the present invention. (A) is sectional drawing of the row direction showing 1 process of the manufacturing method of the memory cell transistor and selection transistor which concern on Example 1 of this invention, (b) is the low voltage which concerns on Example 1 of this invention FIG. 4C is a cross-sectional view in the row direction showing one step of the method for manufacturing a transistor, and FIG. 4C is a cross-sectional view in the row direction showing one step in the method for manufacturing the high voltage transistor according to Example 1 of the present invention. (A) is sectional drawing of the row direction showing 1 process of the manufacturing method of the memory cell transistor and selection transistor which concern on Example 1 of this invention, (b) is the low voltage which concerns on Example 1 of this invention FIG. 4C is a cross-sectional view in the row direction showing one step of the method for manufacturing a transistor, and FIG. 4C is a cross-sectional view in the row direction showing one step in the method for manufacturing the high voltage transistor according to Example 1 of the present invention. (A) is sectional drawing of the row direction showing 1 process of the manufacturing method of the memory cell transistor and selection transistor which concern on Example 1 of this invention, (b) is the low voltage which concerns on Example 1 of this invention FIG. 4C is a cross-sectional view in the row direction showing one step of the method for manufacturing a transistor, and FIG. 4C is a cross-sectional view in the row direction showing one step in the method for manufacturing the high voltage transistor according to Example 1 of the present invention. (A) is sectional drawing of the row direction showing 1 process of the manufacturing method of the memory cell transistor and selection transistor which concern on Example 1 of this invention, (b) is the low voltage which concerns on Example 1 of this invention FIG. 4C is a cross-sectional view in the row direction showing one step of the method for manufacturing a transistor, and FIG. 4C is a cross-sectional view in the row direction showing one step in the method for manufacturing the high voltage transistor according to Example 1 of the present invention. Sectional drawing of the column direction showing the structure of the memory part which concerns on Example 2 of this invention. FIG. 6 is a circuit diagram illustrating a NAND string of a memory unit according to Example 2 of the invention. FIG. 30A is a top view of a prototype semiconductor device according to the third embodiment of the present invention, and FIG. 30B shows “C” in FIG. 30A showing the prototype semiconductor device according to the third embodiment of the present invention. FIG. 30C is a cross-sectional view taken along the line “E-F” in FIG. 30A, which represents a prototype semiconductor device according to Example 3 of the present invention. (A) is an equivalent circuit diagram corresponding to the cross section in FIG. 30 (B) corresponding to the prototype semiconductor device according to the third embodiment of the present invention, and (B) is a prototype according to the third embodiment of the present invention. FIG. 30C is an equivalent circuit diagram corresponding to the cross section in FIG. 30C corresponding to the semiconductor device of FIG. 30, and FIG. 30C shows the drain current and gate voltage characteristics of the semiconductor device corresponding to the prototype according to Example 3 of the present invention. FIG. (A) is a top view of the semiconductor device according to the third embodiment of the present invention, and (B) is on the “GH” line in FIG. 32 (A) showing the semiconductor device according to the third embodiment of the present invention. FIG. 32C is a sectional view taken along the line “I-J” in FIG. 32A showing the semiconductor device according to Example 3 of the invention. (A) is an equivalent circuit diagram corresponding to the cross section in FIG. 32 (B) corresponding to Example 3 of the present invention, and (B) is in FIG. 32 (C) corresponding to Example 3 of the present invention. FIG. 33 is an equivalent circuit diagram corresponding to a cross section, FIG. 33C is an equivalent circuit diagram showing a simplified version of FIG. 33A, and FIG. 13D is an equivalent circuit diagram showing a simplified version of FIG. It is. FIG. 33 is an enlarged cross-sectional view of a part of FIG. 32C, which is a cross-sectional view of a semiconductor device according to Example 3 of the invention. (A) is sectional drawing which represents 1 process of the manufacturing method of the semiconductor device which concerns on Example 3 of this invention corresponding to the cross section on the "IJ" line of FIG. 32, (B) is this FIG. 33 is a cross-sectional view showing one process of a manufacturing method of a semiconductor device according to Example 3 of the invention corresponding to the cross section on the “GH” line of FIG. 32. (A) is sectional drawing which represents 1 process of the manufacturing method of the semiconductor device which concerns on Example 3 of this invention corresponding to the cross section on the "IJ" line of FIG. 32, (B) is this FIG. 33 is a cross-sectional view showing one process of a manufacturing method of a semiconductor device according to Example 3 of the invention corresponding to the cross section on the “GH” line of FIG. 32. (A) is sectional drawing which represents 1 process of the manufacturing method of the semiconductor device which concerns on Example 3 of this invention corresponding to the cross section on the "IJ" line of FIG. 32, (B) is this FIG. 33 is a cross-sectional view showing one process of a manufacturing method of a semiconductor device according to Example 3 of the invention corresponding to the cross section on the “GH” line of FIG. 32. (A) is sectional drawing which represents 1 process of the manufacturing method of the semiconductor device which concerns on Example 3 of this invention corresponding to the cross section on the "IJ" line of FIG. 32, (B) is this FIG. 33 is a cross-sectional view showing one process of a manufacturing method of a semiconductor device according to Example 3 of the invention corresponding to the cross section on the “GH” line of FIG. 32. (A) is sectional drawing which represents 1 process of the manufacturing method of the semiconductor device which concerns on Example 3 of this invention corresponding to the cross section on the "IJ" line of FIG. 32, (B) is this FIG. 33 is a cross-sectional view showing one process of a manufacturing method of a semiconductor device according to Example 3 of the invention corresponding to the cross section on the “GH” line of FIG. 32. (A) is sectional drawing which represents 1 process of the manufacturing method of the semiconductor device which concerns on Example 3 of this invention corresponding to the cross section on the "IJ" line of FIG. 32, (B) is this FIG. 33 is a cross-sectional view showing one process of a manufacturing method of a semiconductor device according to Example 3 of the invention corresponding to the cross section on the “GH” line of FIG. 32. (A) is sectional drawing which represents 1 process of the manufacturing method of the semiconductor device which concerns on Example 3 of this invention corresponding to the cross section on the "IJ" line of FIG. 32, (B) is this FIG. 33 is a cross-sectional view showing one process of a manufacturing method of a semiconductor device according to Example 3 of the invention corresponding to the cross section on the “GH” line of FIG. 32. (A) is sectional drawing which represents 1 process of the manufacturing method of the semiconductor device which concerns on Example 3 of this invention corresponding to the cross section on the "IJ" line of FIG. 32, (B) is this FIG. 33 is a cross-sectional view showing one process of a manufacturing method of a semiconductor device according to Example 3 of the invention corresponding to the cross section on the “GH” line of FIG. 32. (A) is sectional drawing which represents 1 process of the manufacturing method of the semiconductor device which concerns on Example 3 of this invention corresponding to the cross section on the "IJ" line of FIG. 32, (B) is this FIG. 33 is a cross-sectional view showing one process of a manufacturing method of a semiconductor device according to Example 3 of the invention corresponding to the cross section on the “GH” line of FIG. 32. Sectional drawing showing the semiconductor device in the modification of Example 3 of this invention corresponded to a part of cross section on the "IJ" line | wire in FIG. 32 (A). FIG. 33 is a cross-sectional view showing one process of a manufacturing method of a semiconductor device according to a modification of Example 3 of the invention corresponding to a cross section on the “IJ” line of FIG. 32; FIG. 33 is a cross-sectional view showing one process of a manufacturing method of a semiconductor device according to a modification of Example 3 of the invention corresponding to a cross section on the “IJ” line of FIG. 32; FIG. 33 is a cross-sectional view showing one process of a manufacturing method of a semiconductor device according to a modification of Example 3 of the invention corresponding to a cross section on the “IJ” line of FIG. 32; FIG. 33 is a cross-sectional view showing one process of a manufacturing method of a semiconductor device according to a modification of Example 3 of the invention corresponding to a cross section on the “IJ” line of FIG. 32; FIG. 33 is a cross-sectional view showing one process of a manufacturing method of a semiconductor device according to a modification of Example 3 of the invention corresponding to a cross section on the “IJ” line of FIG. 32; (A) is a top view of the prototype semiconductor device according to the fourth embodiment of the present invention, and (B) is “K” in FIG. 50 (A) showing the prototype semiconductor device according to the fourth embodiment of the present invention. FIG. 5C is a cross-sectional view taken along the line “MN” in FIG. 50A, which represents the prototype semiconductor device according to the fourth embodiment of the present invention. (A) is an equivalent circuit diagram corresponding to the cross section in FIG. 50 (B) corresponding to the prototype semiconductor device according to the fourth embodiment of the present invention, and (B) is a prototype according to the fourth embodiment of the present invention. FIG. 50C is an equivalent circuit diagram corresponding to the cross section in FIG. 50C corresponding to the semiconductor device of FIG. 50, and FIG. 10C is a diagram illustrating the drain current and gate voltage characteristics of the prototype semiconductor device according to Example 4 of the present invention. is there. (A) is a top view of a semiconductor device according to Embodiment 4 of the present invention, and (B) is an “OP” line in FIG. 52 (A) showing the semiconductor device according to Embodiment 4 of the present invention. FIG. 52C is a sectional view taken along the line “QR” in FIG. 52A showing the semiconductor device according to Example 4 of the invention. (A) is an equivalent circuit diagram corresponding to the cross section in FIG. 52 (B) corresponding to Example 4 of the present invention, and (B) is an equivalent circuit diagram showing a simplified form of FIG. 53 (A). FIG. 52C is an equivalent circuit diagram corresponding to the cross section in FIG. 52C corresponding to the fourth embodiment of the present invention. FIG. 53D is an equivalent circuit diagram schematically showing FIG. 53C. It is. (A) is sectional drawing which represents 1 process of the manufacturing method of the semiconductor device based on Example 4 of this invention corresponding to the cross section on the "QR" line of FIG. 52, (B) is this FIG. 53 is a cross-sectional view showing one process of a manufacturing method of a semiconductor device according to Example 4 of the invention corresponding to the cross section on the “OP” line of FIG. 52. (A) is sectional drawing which represents 1 process of the manufacturing method of the semiconductor device based on Example 4 of this invention corresponding to the cross section on the "QR" line of FIG. 52, (B) is this FIG. 53 is a cross-sectional view showing one process of a manufacturing method of a semiconductor device according to Example 4 of the invention corresponding to the cross section on the “OP” line of FIG. 52. (A) is sectional drawing which represents 1 process of the manufacturing method of the semiconductor device based on Example 4 of this invention corresponding to the cross section on the "QR" line of FIG. 52, (B) is this FIG. 53 is a cross-sectional view showing one process of a manufacturing method of a semiconductor device according to Example 4 of the invention corresponding to the cross section on the “OP” line of FIG. 52. (A) is sectional drawing which represents 1 process of the manufacturing method of the semiconductor device based on Example 4 of this invention corresponding to the cross section on the "QR" line of FIG. 52, (B) is this FIG. 33 is a cross-sectional view showing one process of a manufacturing method of a semiconductor device according to Example 4 of the invention corresponding to the cross section along the “OP” line in FIG. 32. (A) is sectional drawing which represents 1 process of the manufacturing method of the semiconductor device based on Example 4 of this invention corresponding to the cross section on the "QR" line of FIG. 52, (B) is this FIG. 53 is a cross-sectional view showing one process of a manufacturing method of a semiconductor device according to Example 4 of the invention corresponding to the cross section on the “OP” line of FIG. 52. (A) is sectional drawing which represents 1 process of the manufacturing method of the semiconductor device based on Example 4 of this invention corresponding to the cross section on the "QR" line of FIG. 52, (B) is this FIG. 53 is a cross-sectional view showing one process of a manufacturing method of a semiconductor device according to Example 4 of the invention corresponding to the cross section on the “OP” line of FIG. 52. (A) is sectional drawing which represents 1 process of the manufacturing method of the semiconductor device based on Example 4 of this invention corresponding to the cross section on the "QR" line of FIG. 52, (B) is this FIG. 53 is a cross-sectional view showing one process of a manufacturing method of a semiconductor device according to Example 4 of the invention corresponding to the cross section on the “OP” line of FIG. 52. (A) is sectional drawing which represents 1 process of the manufacturing method of the semiconductor device based on Example 4 of this invention corresponding to the cross section on the "QR" line of FIG. 52, (B) is this FIG. 33 is a cross-sectional view showing one process of a manufacturing method of a semiconductor device according to Example 4 of the invention corresponding to the cross section along the “OP” line in FIG. 32. (A) is sectional drawing which represents 1 process of the manufacturing method of the semiconductor device based on Example 4 of this invention corresponding to the cross section on the "QR" line of FIG. 52, (B) is this FIG. 53 is a cross-sectional view showing one process of a manufacturing method of a semiconductor device according to Example 4 of the invention corresponding to the cross section on the “OP” line of FIG. 52. FIG. 52 is a cross-sectional view showing a semiconductor device according to a modification of Example 4 of the present invention, which corresponds to a part of a cross section on the “QR” line in FIG. (A) is a top view of a semiconductor device according to Embodiment 5 of the present invention, and (B) is an “ST” line in FIG. 64 (A) showing the semiconductor device according to Embodiment 5 of the present invention. FIG. 6C is a sectional view taken along the line “UV” in FIG. 64A showing the semiconductor device according to the fifth embodiment of the present invention. (A) is an equivalent circuit diagram corresponding to the cross section in FIG. 64 (B) corresponding to Example 5 of the present invention, and (B) is in FIG. 64 (C) corresponding to Example 5 of the present invention. FIG. 9C is an equivalent circuit diagram corresponding to a cross section, and FIG. 10C is a diagram illustrating drain current and gate voltage characteristics of the semiconductor device according to Example 5 of the present invention. FIG. 64 is an enlarged cross-sectional view of a part of FIG. 64C, which is a cross-sectional view of the semiconductor device according to the fifth embodiment of the present invention. FIG. 64 is an enlarged cross-sectional view of a part of FIG. 64B, which is a cross-sectional view of the semiconductor device according to the fifth embodiment of the present invention. (A) is sectional drawing which represents 1 process of the manufacturing method of the semiconductor device which concerns on Example 5 of this invention corresponding to the cross section on the "ST" line of FIG. 64, (B) is this FIG. 67 is a cross-sectional view showing one process of a manufacturing method of a semiconductor device according to Example 5 of the invention corresponding to the cross section on the “UV” line of FIG. 64. (A) is sectional drawing which represents 1 process of the manufacturing method of the semiconductor device which concerns on Example 5 of this invention corresponding to the cross section on the "ST" line of FIG. 64, (B) is this FIG. 67 is a cross-sectional view showing one process of a manufacturing method of a semiconductor device according to Example 5 of the invention corresponding to the cross section on the “UV” line of FIG. 64. (A) is sectional drawing which represents 1 process of the manufacturing method of the semiconductor device which concerns on Example 5 of this invention corresponding to the cross section on the "ST" line of FIG. 64, (B) is this FIG. 67 is a cross-sectional view showing one process of a manufacturing method of a semiconductor device according to Example 5 of the invention corresponding to the cross section on the “UV” line of FIG. 64. (A) is sectional drawing which represents 1 process of the manufacturing method of the semiconductor device which concerns on Example 5 of this invention corresponding to the cross section on the "ST" line of FIG. 64, (B) is this FIG. 67 is a cross-sectional view showing one process of a manufacturing method of a semiconductor device according to Example 5 of the invention corresponding to the cross section on the “UV” line of FIG. 64. (A) is sectional drawing which represents 1 process of the manufacturing method of the semiconductor device which concerns on Example 5 of this invention corresponding to the cross section on the "ST" line of FIG. 64, (B) is this FIG. 67 is a cross-sectional view showing one process of a manufacturing method of a semiconductor device according to Example 5 of the invention corresponding to the cross section on the “UV” line of FIG. 64. (A) is sectional drawing which represents 1 process of the manufacturing method of the semiconductor device which concerns on Example 5 of this invention corresponding to the cross section on the "ST" line of FIG. 64, (B) is this FIG. 67 is a cross-sectional view showing one process of a manufacturing method of a semiconductor device according to Example 5 of the invention corresponding to the cross section on the “UV” line of FIG. 64. (A) is sectional drawing which represents 1 process of the manufacturing method of the semiconductor device which concerns on Example 5 of this invention corresponding to the cross section on the "ST" line of FIG. 64, (B) is this FIG. 67 is a cross-sectional view showing one process of a manufacturing method of a semiconductor device according to Example 5 of the invention corresponding to the cross section on the “UV” line of FIG. 64. (A) is sectional drawing which represents 1 process of the manufacturing method of the semiconductor device which concerns on Example 5 of this invention corresponding to the cross section on the "ST" line of FIG. 64, (B) is this FIG. 67 is a cross-sectional view showing one process of a manufacturing method of a semiconductor device according to Example 5 of the invention corresponding to the cross section on the “UV” line of FIG. 64. (A) is sectional drawing which represents 1 process of the manufacturing method of the semiconductor device which concerns on Example 5 of this invention corresponding to the cross section on the "ST" line of FIG. 64, (B) is this FIG. 67 is a cross-sectional view showing one process of a manufacturing method of a semiconductor device according to Example 5 of the invention corresponding to the cross section on the “UV” line of FIG. 64. (A) is a top view of a semiconductor device according to Embodiment 6 of the present invention, and (B) is a “WX” line in FIG. 77 (A) showing the semiconductor device according to Embodiment 6 of the present invention. (C) is a sectional view taken along the line “YZ” in FIG. 77 (A) showing the semiconductor device according to Example 6 of the present invention. (A) is an equivalent circuit diagram corresponding to the cross section in FIG. 77 (B) corresponding to Example 6 of the present invention, and (B) is in FIG. 77 (C) corresponding to Example 6 of the present invention. FIG. 9C is an equivalent circuit diagram corresponding to a cross section, and FIG. 10C is a diagram illustrating drain current and gate voltage characteristics of the semiconductor device according to Example 6 of the present invention. FIG. 78 is an enlarged cross-sectional view of a part of FIG. 78C, which is a cross-sectional view of a semiconductor device according to Example 6 of the invention. (A) is sectional drawing which represents 1 process of the manufacturing method of the semiconductor device based on Example 6 of this invention corresponding to the cross section on the "YZ" line of FIG. 77, (B) is this FIG. 78 is a cross-sectional view showing one process of a manufacturing method of a semiconductor device according to Example 6 of the invention corresponding to the cross section along the “WX” line in FIG. 77. (A) is sectional drawing which represents 1 process of the manufacturing method of the semiconductor device based on Example 6 of this invention corresponding to the cross section on the "YZ" line of FIG. 77, (B) is this FIG. 78 is a cross-sectional view showing one process of a manufacturing method of a semiconductor device according to Example 6 of the invention corresponding to the cross section along the “WX” line in FIG. 77. (A) is sectional drawing which represents 1 process of the manufacturing method of the semiconductor device based on Example 6 of this invention corresponding to the cross section on the "YZ" line of FIG. 77, (B) is this FIG. 78 is a cross-sectional view showing one process of a manufacturing method of a semiconductor device according to Example 6 of the invention corresponding to the cross section along the “WX” line in FIG. 77. (A) is sectional drawing which represents 1 process of the manufacturing method of the semiconductor device based on Example 6 of this invention corresponding to the cross section on the "YZ" line of FIG. 77, (B) is this FIG. 78 is a cross-sectional view showing one process of a manufacturing method of a semiconductor device according to Example 6 of the invention corresponding to the cross section along the “WX” line in FIG. 77. (A) is sectional drawing which represents 1 process of the manufacturing method of the semiconductor device based on Example 6 of this invention corresponding to the cross section on the "YZ" line of FIG. 77, (B) is this FIG. 78 is a cross-sectional view showing one process of a manufacturing method of a semiconductor device according to Example 6 of the invention corresponding to the cross section along the “WX” line in FIG. 77. (A) is sectional drawing which represents 1 process of the manufacturing method of the semiconductor device based on Example 6 of this invention corresponding to the cross section on the "YZ" line of FIG. 77, (B) is this FIG. 78 is a cross-sectional view showing one process of a manufacturing method of a semiconductor device according to Example 6 of the invention corresponding to the cross section along the “WX” line in FIG. 77. (A) is sectional drawing which represents 1 process of the manufacturing method of the semiconductor device based on Example 6 of this invention corresponding to the cross section on the "YZ" line of FIG. 77, (B) is this FIG. 78 is a cross-sectional view showing one process of a manufacturing method of a semiconductor device according to Example 6 of the invention corresponding to the cross section along the “WX” line in FIG. 77. (A) is sectional drawing which represents 1 process of the manufacturing method of the semiconductor device based on Example 6 of this invention corresponding to the cross section on the "YZ" line of FIG. 77, (B) is this FIG. 78 is a cross-sectional view showing one process of a manufacturing method of a semiconductor device according to Example 6 of the invention corresponding to the cross section along the “WX” line in FIG. 77. (A) is sectional drawing which represents 1 process of the manufacturing method of the semiconductor device based on Example 6 of this invention corresponding to the cross section on the "YZ" line of FIG. 77, (B) is this FIG. 78 is a cross-sectional view showing one process of a manufacturing method of a semiconductor device according to Example 6 of the invention corresponding to the cross section along the “WX” line in FIG. 77. FIG. 77 is a cross-sectional view showing a semiconductor device in a modification of Example 6 of the present invention corresponding to a part of a cross section on the “YZ” line in FIG. 77 (A). (A) is a circuit diagram showing one memory cell of the semiconductor device according to the seventh embodiment of the present invention, and (B) is a top view showing the memory cell structure of the semiconductor device according to the seventh embodiment of the present invention. It is. FIG. 90A is a cross-sectional view corresponding to a cross section taken along line “III-IV” in FIG. 90B, in the semiconductor device according to the seventh embodiment of the present invention, and FIG. FIG. 90 is a cross-sectional view corresponding to a cross section taken along line “I-II” in FIG. FIG. 10 is a circuit diagram illustrating a read state of one memory cell of a semiconductor device according to a seventh embodiment of the present invention. (A) is a circuit diagram showing a read state of one memory cell of an AND-type EEPROM in a semiconductor device of a modification of the seventh embodiment of the present invention, and (B) is a circuit diagram of the seventh embodiment of the present invention. FIG. 11 is a circuit diagram showing a read state of one memory cell of a NOR type EEPROM in a semiconductor device of a modification example. FIG. 6 is a cross-sectional view of a MONOS (metal-silicon oxide film-silicon nitride film-silicon oxide film-semiconductor) memory cell by shallow trench isolation formed by a conventional selective thermal oxidation method.

Explanation of symbols

1, 117, 137, 161, 197, 216, 255 Semiconductor substrate (well)
2, 13, 21, 26 Shallow trench isolation region 3, 10, 118, 140, 172, 198, 222, 260 Tunnel insulating film 4, 11 Charge storage layer 5, 12, 120, 142, 174, 200, 224, 262 Block insulating film 6, 112, 132, 166, 192, 220 Gate electrode 7 Bird's beak part 8, 9 Protruding part 14, 22, 27, 138, 170, 205, 230, 263, 269 First gate electrode 15, 23, 28, 139, 171, 206, 233, 264, 270 Second gate electrode 16, 24, 29 Gate cap insulating film 17 Interlayer film 18, 43 Bit line 19 Protective film 20, 25, 268 Gate insulating film 30, 251 Drain regions 31, 32 Barrier insulating film 40 Data selection line (word line)
41 Bit line selection signal line (SSL)
42 Common source line selection signal line (GSL)
44 bit line contact 45 source line contact 46 bit line lead contact 47 bit line lead wiring 48 source line wiring 50, 51 selection transistor 52 memory cell transistor 55, 66, 72, 73 resist 56 stopper film 57, 150, 180, 211, 240 Mask material 58, 59, 60 Element isolation trench (trench trench)
61, 71 Silicon oxide films 62, 63, 64 Element isolation insulating film (filling material)
65, 67 Recess 68, 69, 70 Gate electrode material 110, 130, 160, 190, 215, 250, 258 Element isolation region 111, 131, 191 Element region 113, 133, 193, 219 Contact 114, 134, 167, 194 221 Gate contacts 115, 135, 155, 162, 195, 217 Source impurity regions 116, 136, 156, 163, 196, 218 Drain impurity regions 119, 141, 173, 199, 223, 261 Data retention insulating films 121, 144 176, 201, 225 Interlayer insulating film 122, 145, 151, 177, 203, 227, 259 Element isolation groove 123, 124, 202, 204, 226, 228 Edge region 143, 175, 181, 241, 242, 267, 271 Gate sidewall insulation Films 146, 207, 235 Element isolation side wall oxide films 147, 208 Polysilicon side wall oxide films 148, 209, 234 Edge 152 First gate electrode side wall oxide film 153 Element isolation side wall insulating films 157, 164 Source contacts 158, 165 Drain contact 185, 245 P-type high concentration regions 210, 246 Silicon oxide film 212 Post oxide film 232 Polysilicon sidewall insulating film 252 Bit line contact 253 SL contact 256 N well 257 P well 265 First interlayer insulating film 266 Second interlayer insulating film 272 Source wire

Claims (5)

A semiconductor substrate;
An element region formed in the semiconductor substrate;
A first gate insulating film provided on the element region;
At least one gate electrode;
An element isolation region formed on the semiconductor substrate in contact with at least a portion of the gate electrode;
A charge storage region provided on the first gate insulating film, having an insulating film capable of storing data and electrically writable and erasable, and having an end portion located in the element isolation region;
And the end of the charge storage region is 0.5 nm to 15 nm in the element isolation region.
A semiconductor device that has entered in a range of. A semiconductor substrate;
A first conductivity type element region having substantially four sides formed in the semiconductor substrate;
A first gate insulating film provided on the element region;
A charge storage region provided on the first gate insulating film, having an insulating film capable of storing data and electrically writable and erasable;
At least one gate electrode provided on the charge storage region;
A source electrode and a drain electrode of a conductivity type opposite to the first conductivity type, each formed on two opposing sides of the element region;
The charge is disposed between the charge storage region and the gate electrode, and on the two sides where the source electrode and the drain electrode are not formed, as compared with the lower part of the gate electrode at the surface facing the charge storage region. A second gate insulating film formed thick below the edge of the gate electrode on the surface facing the storage region;
And the second gate insulating film has a thickness on two sides where the source electrode and the drain electrode are not formed, as compared with a lower portion of the gate electrode at a surface facing the charge storage region. A semiconductor device, wherein the semiconductor device is formed thicker in the range of 0.6 nm to 50 nm below the edge of the gate electrode on the surface facing the storage region. The semiconductor device according to claim 2, wherein a distance between two sides of the gate electrode where the source electrode and the drain electrode are formed is 0.2 μm or less. A semiconductor substrate;
A first conductivity type element region having substantially four sides formed in the semiconductor substrate;
A first gate insulating film provided on the element region;
A charge storage region provided on the first gate insulating film, made of an insulating film capable of storing data and electrically writable and erasable, and having two ends on two opposite sides;
At least one gate electrode provided on the charge storage region;
A source electrode and a drain electrode having a conductivity type opposite to the first conductivity type provided in the semiconductor substrate;
Provided on each of the source electrode and the drain electrode;
A current terminal for detecting a storage state of the charge accumulation region according to a conduction state and a cutoff state between the source electrode and the drain electrode;
The first electrode is disposed between the charge storage region and the gate electrode, and at least between the current terminals is in a conducting state. The first direction is a direction in which current flows in the element region, and the first direction is orthogonal to the first direction on the semiconductor substrate. Assuming that the direction is the second direction, in the second direction, 0. 0 below the end of the gate electrode on the surface facing the charge storage region as compared to below the center of the gate electrode on the surface facing the charge storage region. A second gate insulating film thick in the range of 6 nm to 50 nm;
A semiconductor device comprising: The semiconductor device according to claim 4, wherein a distance between two sides of the gate electrode in the second direction is 0.2 μm or less.

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