JP2000286349A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent a short circuit from occurring due to etching residues of a conducive layer and a projection from being formed at the edge of a trench. SOLUTION: A trench is cut on the surface of a silicon substrate 1 provided with a channel region so as to isolate the channel region, and the trench is filled up with an insulating film to form a trench element isolation insulating film 2. A control gate 3 is formed on the channel region through the intermediary of an ONO film 5 as a charge storage layer, crossing the trench at right angles. Diffused layers 4 are formed on each side of the control gate 3 on the silicon substrate 1 through ion implantation to serve as a source region and a drain region for the formation of a memory transistor, and thus a MONOS- type semiconductor nonvolatile memory device is fabricated.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a semiconductor device suitable for application to a semiconductor nonvolatile memory device having a charge storage layer between a gate electrode and a channel region of a MIS transistor. It is.

[0002]

2. Description of the Related Art An EEPROM (Electrically Erasable) which is an electrically rewritable semiconductor nonvolatile memory device.
and Programmable Read Only Memory) is a DRAM (Dyna
The memory area per bit can be theoretically minimized as compared with other semiconductor memory devices such as a mic random access memory), and is expected as a large-capacity semiconductor memory device. Investigations are actively being conducted as alternatives to magnetic storage devices. As this EEPROM, a floating gate type, MNOS (Metal-Nitride-Oxide-Semi-
conductor) type or MONOS (Metal-Oxide-Nitrid)
e-Oxide-Semiconductor) type, TEXTUREDPOLY
Structures having various features such as molds have been developed.

A description will be given of a method of manufacturing an example of a floating gate type semiconductor nonvolatile memory device which is one of EEPROMs. First, as shown in FIG. 13, for example, LOCOS (Local Oxidat
An element isolation insulating film 102 made of silicon oxide is formed by an ion of silicon method.

[0004] Next, as shown in FIG. 14, ion implantation is performed to form a well 103 in the active region separated by the element isolation insulating film 102, and then ion implantation for adjusting the threshold voltage of the transistor is performed. Do.

Next, as shown in FIG. 15, a gate insulating film (tunnel insulating film) 104 made of silicon oxide is formed on the surface of the active region separated by the element isolation insulating film 102 by, for example, a thermal oxidation method.

[0006] Next, as shown in FIG.
A polycrystalline silicon film 105 is deposited as a layer for forming a floating gate by a (Chemical Vapor Deposition) method. Next, a resist pattern (not shown) having the same width as the floating gate in the channel width direction of the transistor is formed on the polycrystalline silicon film 105 by a photolithography process. As a polycrystalline silicon film 105
Is patterned by, for example, a reactive ion etching (RIE) method.

[0007] Next, as shown in FIG.
According to the method, an ONO (Oxide-Nitride-Oxide) film or the like which is a stacked insulating film of an oxide film-nitride film-oxide film is formed on the entire surface so as to cover the polycrystalline silicon film 105 patterned as described above. Intermediate insulating film (coupling insulating film)
106 is formed.

Next, after depositing a polycrystalline silicon film as a layer for forming a control gate on the intermediate insulating film 106 by, for example, a CVD method, the polycrystalline silicon film is doped with impurities by ion implantation or the like to reduce the polycrystalline silicon film. Resistance.
Next, a resist pattern (not shown) having a predetermined shape corresponding to the control gate is formed on the polycrystalline silicon film by a photolithography process, and the polycrystalline silicon film is formed using the resist pattern as a mask, for example, by RIE. By patterning by etching with the control gate 10 as shown in FIG.
7 is formed. At this time, by performing etching subsequent to the etching processing of the control gate 107, the intermediate insulating film 106 and the polycrystalline silicon film 105 are processed in a self-aligned manner with respect to the control gate 107, and the floating gate 108 is formed. Next, an n-type or p-type impurity is ion-implanted using the control gate 107 as a mask to form a diffusion layer 109 used as a source region and a drain region in a self-aligned manner with respect to the control gate 107. Next, formation of an interlayer insulating film 110, formation of a contact hole reaching the diffusion layer 109 in the interlayer insulating film 110,
09 to form electrodes 111 and 112 to be connected to
A semiconductor nonvolatile memory device having a memory cell structure as shown in FIG. 18 is manufactured.

In the semiconductor nonvolatile memory device shown in FIG. 18, a memory transistor is a field-effect transistor having a floating gate 108 surrounded by an insulating film between a control gate 107 and a channel region in a silicon substrate 101, that is, a memory transistor. It is composed of MIS transistors. In this memory transistor, the floating gate 108 has a function of retaining charges therein, and the gate insulating film 104 and the intermediate insulating film 106 have a function of confining charges inside the floating gate 108. In this memory transistor, the control gate 107, the silicon substrate 101 or the diffusion layer 1 as a source region and a drain region
When an appropriate voltage is applied to the semiconductor substrate 101 or the like, a Fowler-Nordheim type tunnel current is generated, charges are injected from the silicon substrate 101 to the floating gate 108 through the gate insulating film 104, or the silicon substrate 101 Charge is released.

As described above, the floating gate 108
When electric charges are accumulated therein, an electric field is generated by the accumulated electric charges, so that the threshold voltage of the transistor changes. For example, assuming that the memory transistor is an n-channel type, charge is accumulated in the floating gate 108, so that the threshold voltage shifts in the positive direction. When reading data, a read voltage set to a predetermined value is applied to the control gate 107. However, if the threshold voltage is shifted in the positive direction, even if the read voltage is applied, the source region and the drain region No channel current flows between them. On the other hand, when the charge in the floating gate 108 is discharged, a channel current flows between the source region and the drain region of the transistor due to the application of the read voltage. Data can be stored in such a manner that "flow" or "no flow" of the channel current corresponds to "0" or "1".

When the memory cell having the above structure is integrated, a NOR type circuit configuration as shown in an equivalent circuit diagram of FIG. 19 is obtained. In FIG. 19, four memory transistors MT11, MT12, MT21, and MT22 are provided, and the memory transistors MT11 and MT21 are connected to a word line (control gate) WL1.
The memory transistors MT12 and MT22 are connected to the word line (control gate) WL2. The source and drain regions of the memory transistors MT11, MT12, MT21, MT22 are respectively connected to bit lines BL.
1a, BL1b, BL2a, and BL2b.

In the NOR type semiconductor nonvolatile memory device shown in FIG. 19, for example, a memory transistor MT1
To read the data of 1, a read voltage (positive voltage if the transistor is an n-channel type) is applied to the word line WL1, and the current flowing between the bit lines BL1a and BL1b is detected to be "0" or The data of "1" is determined.

FIG. 20 shows an equivalent circuit diagram of a NAND type semiconductor nonvolatile memory device in which a plurality of memory transistors are connected in series to the above NOR type semiconductor nonvolatile memory device. As shown in FIG. 20, memory transistors MT1 to MT8 controlled by control gates CG1 to CG8 are connected in series to form a memory string. Select transistors ST1 and ST2 for selecting the memory string, which are controlled by select gates SG1 and SG2, respectively, are connected to both ends of the memory string. The drain region of one select transistor ST1 is connected to bit line BL, and the other select transistor ST2
Are connected to the source line S. Although eight memory transistors are connected in FIG. 20, the number is not limited in principle.

Normally, in the above-mentioned NAND type semiconductor nonvolatile memory device, data is erased collectively in block units. Specifically, a voltage (hereinafter, referred to as _Vpp ) sufficient for erasing is applied to all word lines (control gates) of the block to be erased, and a positive voltage is applied to the source line S to block. Charge is injected into the floating gates of all the memory transistors in the memory transistor, and the data is erased by setting the memory transistors to an enhancement type (normally-off type).

When writing data to a memory transistor of a desired cell, the word line of the memory transistor is fixed to 0 V, and the word lines of the memory transistors of all other cells are set to a voltage at which the transistor is conducted. (Hereinafter, referred to as _Vcc ). Next, writing is performed by applying a voltage corresponding to data “0” or “1” to be written to the bit line BL. For example, when the data to be written is “1”, the voltage V
By applying _pp , charges are discharged from the floating gate. As a result, this memory transistor becomes a depletion type (normally on type). On the other hand, when the data to be written is “0”, the voltage V
_{Apply pp} / 2. At this time, since the charge is not discharged from the floating gate or injected into the floating gate, the memory transistor holds the enhancement type (normally-off type) which is the state at the time of erasing.

When reading data, the word line of the memory transistor of the cell to be read is fixed to 0 V, and the voltage _Vcc is applied to the word lines of the memory transistors of all other cells. When a positive voltage is applied to the source line S, all the memory transistors other than the cell to be read are in a conductive state. Therefore, a bit is determined depending on whether the memory transistor of the cell to be read is a normally-on type or a normally-off type. It is determined whether a current flows or does not flow in the line BL. "0" or "1" indicates that this current "flows" or "does not flow"
The data can be read in correspondence with.

In the above-described floating gate type semiconductor nonvolatile memory device, the LOCOS method is conventionally used for element isolation. However, as the element is miniaturized, a trench is used for element isolation due to a bird's beak problem. Has begun to be considered.

However, in the conventional method for forming the trench element isolation region, a projection is formed as a by-product at the interface between the upper portion of the trench and the active region and the channel region due to a problem of the formation process. Due to the concentration of the electric field, the writing / erasing characteristics vary.

In the above-mentioned conventional floating gate type semiconductor nonvolatile memory device, a structure in which the floating gate and the element isolation region are aligned in a self-aligning manner and no projection is formed at the end of the upper surface of the trench (hereinafter, referred to as a "structure").
SA-STI (Self-aligned Shallow Trench Isolatio
n) (referred to as a cell structure) and a method for forming the same.
No. 17948.

A floating gate type NAND type semiconductor nonvolatile memory device having the SA-STI cell structure will be described. FIG. 21 is a plan view thereof. FIG.
As shown in FIG. 7, an active region is formed by being separated by a trench element isolation insulating film 202 formed in a silicon substrate 201. In a region where the active region intersects with the control gate 203 serving as a word line, a floating gate 204 surrounded by, for example, an insulating film is formed as a charge storage layer between the control gate 203 and the channel region of the silicon substrate 201. ing. In the silicon substrate 201 on both sides of the control gate 203, diffusion layers 205 used as a source region and a drain region are formed. A bit line (not shown) is formed above the control gate 203 in a direction perpendicular to the control gate 203.
It is connected to the diffusion layer 205 at a bit contact (not shown).

FIGS. 22 and 23 are cross-sectional views taken along lines AA 'and BB' in FIG. 21, respectively. As shown in FIGS. 22 and 23, a gate insulating film (tunnel insulating film) 206 made of, for example, a thin silicon oxide is formed on the active region of the silicon substrate 201 separated by the trench isolation insulating film 202. Floating gate 204 made of, for example, polycrystalline silicon is formed on the upper layer.
An intermediate insulating film 207 made of an NO film is formed. A control gate 203 made of, for example, polycrystalline silicon doped with an impurity is formed on the intermediate insulating film 207. An interlayer insulating film 208 made of, for example, silicon oxide is formed on the upper layer of the control gate 203, and a bit line (not shown) made of, for example, aluminum is formed on the upper layer.

In the semiconductor nonvolatile memory device having the structure shown in FIGS. 21, 22 and 23, the memory transistor is composed of a control gate 203 and a silicon substrate 20.
1 is a field effect transistor having a floating gate 204 surrounded by an insulating film between itself and a channel region, that is, an MIS transistor. Each memory transistor is connected in a NAND type to form a NAND type string.

In the floating gate type semiconductor nonvolatile memory device having the above SA-STI cell structure, when electric charges are accumulated in the floating gate 204, the threshold voltage of the transistor changes due to the electric field due to the accumulated electric charges. The data can be stored by the change. Theoretically, the minimum cell area is 4F
2 (here, F is the minimum feature size), so that the cell area can be reduced, the capacity can be increased, and the chip cost and bit cost can be reduced.

A method of manufacturing a floating gate type semiconductor nonvolatile memory device having the SA-STI cell structure will be described. First, a description will be given with reference to a cross-sectional view corresponding to a cross section taken along line AA ′ of FIG. As shown in FIG. 24, a LOCOS (not shown) for separating a peripheral element region and a memory cell region on a silicon substrate 201 is provided.
After forming an element isolation insulating film and further performing ion implantation for adjusting the threshold voltage of the transistor or forming a well or the like (not shown), for example, 7 to 8 is performed by a thermal oxidation method.
Gate insulating film 2 made of silicon oxide having a thickness of about nm
No. 06 is formed thereon, and a polycrystalline silicon film 209 is deposited thereon in a thickness of 300 to 400 nm by, for example, a CVD method to form a layer for forming a floating gate.

Next, as shown in FIG. 25, a resist pattern 210 having the same shape as the floating gate in the channel width direction of the transistor is formed on the polycrystalline silicon film 209 for forming the floating gate by a photolithography process. Is formed, using the resist pattern 210 as a mask, the polycrystalline silicon film 207 is etched and patterned by, for example, RIE.

Next, as shown in FIG. 26, etching by RIE is successively performed using the resist pattern 210 as a mask to form a trench 211 in self-alignment with the active region of the silicon substrate 201.

Next, after removing the resist pattern 210, as shown in FIG. 27, the insulating film 21 made of silicon oxide is entirely formed by, for example, a CVD method or a bias-applied electron cyclotron resonance (ECR) plasma CVD method.
2 is deposited to a thickness of 700 to 1000 nm to fill the trench 211.

Next, as shown in FIG.
The insulating film 212 is etched by a method or the like to form the trench isolation insulating film 202 embedded in the trench 211 in a self-aligned manner with the active region of the silicon substrate 201.

Next, as shown in FIG.
An intermediate insulating film 207 is formed by forming an ONO film or the like on the entire surface by a method or a thermal oxidation method.

Next, FIG. 30 (plan view) and FIG. 31 (FIG. 30)
30 (a cross-sectional view along the line AA ′) and FIG. 32 (FIG. 30).
(A cross-sectional view taken along the line BB ′), a polycrystalline silicon film 213 is deposited to a thickness of 300 to 400 nm on the intermediate insulating film 207 by, for example, a CVD method to form a control gate forming layer. To form Hereinafter, B in FIG.
Description will be made with reference to a cross-sectional view corresponding to a cross section taken along line -B '.

As shown in FIG. 33, the polycrystalline silicon film 2
On resist 13, a resist pattern 214 having a shape corresponding to the control gate is formed by a photolithography process.

Next, as shown in FIG. 34, etching such as RIE is performed using the resist pattern 214 as a mask to form a control gate 203 and an intermediate insulating film 207 made of polycrystalline silicon doped with impurities.
And floating gate 2 made of polycrystalline silicon
04 is formed in a self-aligned manner. At this time, as shown in FIG. 21, the floating gate 204 is left only in the region where the control gate 203 and the active region of the silicon substrate 201 intersect, and has a shape separated for each memory cell.

Next, as shown in FIG. 35, an n-type or p-type impurity is ion-implanted at a dose of, for example, 5 × 10 ¹³ / cm ^{2 using} the control gate 203 as a mask, so that both sides of the control gate 203 are formed. A diffusion layer 205 as a source region and a drain region is formed in a portion of the silicon substrate 201 in a self-aligned manner.

Next, after removing the resist pattern 214, as shown in FIG. 23, silicon oxide such as phosphorus silicate glass (PSG) or BPSG (boron phosphorus silicate glass) is deposited by, for example, a CVD method to form an interlayer insulating film. Form 208. Thus, FIG. 21 and FIG.
2 and FIG. 23 are manufactured. Although illustration is omitted, thereafter, for example, the interlayer insulating film 2
A desired semiconductor non-volatile memory device is obtained by forming an opening of a bit contact reaching the diffusion layer 205 to the layer 08, forming an upper layer wiring such as a bit line, and forming a peripheral circuit.

[0035]

By the way, in the manufacture of the above-mentioned conventional semiconductor nonvolatile memory device having the SA-STI cell structure, the patterned polycrystalline silicon film 2 is formed.
In order to form a trench element isolation insulating film 202 on both sides of the semiconductor device 09 (FIG. 28), a process of forming a control gate 203 and a floating gate 204 (FIG. 3)
In 4), as shown in FIG. 36, a portion of the polycrystalline silicon film 20 surrounded by the trench isolation insulating film 202 and not opposed to the channel region with the gate insulating film 206 interposed therebetween.
9 needs to be removed.

However, in practice, it is very difficult to remove only the polycrystalline silicon film 209 in the structure surrounded by the trench element isolation insulating film 202 in this manner, and etching residue tends to occur. . In particular, in such a structure, portions where etching residue is likely to occur are shown in FIG.
As shown in FIG. 5, the portion is considered to be along the trench side wall. However, if such an etching residue of the polycrystalline silicon film 209 occurs, adjacent floating gates 204 are short-circuited to each other, and Becomes

In particular, when the scaling of the device progresses and the opening surrounded by the trench side wall is reduced,
Further difficulties are expected due to problems such as the microloading effect in the etching apparatus and the efficiency of exhausting the etched molecules.

Therefore, the object of the present invention is to provide a conventional S
Semiconductor device capable of preventing short circuit due to residual etching of conductive layer as in the method for forming an A-STI cell structure and occurrence of protrusion at the trench end as in the conventional method for forming a trench element isolation region, and manufacturing thereof It is to provide a method.

[0039]

In order to solve the above problems, a semiconductor device according to a first aspect of the present invention is provided on a semiconductor substrate having a channel region and a semiconductor substrate so as to separate the channel region. A first insulating film for element isolation buried in the groove, a control gate provided on the channel region via the second insulating film via the second insulating film, and a semiconductor substrate on both sides of the control gate In which a memory transistor is constituted by a control gate, a source region and a drain region.

According to a second aspect of the present invention, there is provided a semiconductor substrate having a channel region, and a first insulating film for element isolation embedded in a first groove provided in the semiconductor substrate so as to separate the channel region. And a control gate provided on the channel region so as to intersect the first groove via the second insulating film, and a source region and a drain region provided on the semiconductor substrate on both sides of the control gate. A method of manufacturing a semiconductor device, comprising: a memory transistor including a control gate, a source region, and a drain region, comprising: forming a first trench in a semiconductor substrate so as to separate a channel region; Forming a first insulating film on the semiconductor substrate so as to fill the groove, and intersecting the first groove by patterning the first insulating film. Forming a second groove extending in a direction extending in a direction to expose a channel region, forming a second insulating film on at least a channel region inside the second groove, and forming a second insulating film on the semiconductor substrate. Depositing a conductive material so as to fill the second groove, forming a control gate inside the second groove by etching back the conductive material at least until the first insulating film is exposed,
Etching back the insulating film substantially to the vicinity of the surface of the semiconductor substrate, and forming a source region and a drain region by introducing impurities into the semiconductor substrate on both sides of the control gate. .

In the present invention, the second insulating film has a charge storage function. The second insulating film is typically composed of a multilayer insulating film. Specifically, for example, a stacked film (ONO) film of an oxide film, a nitride film, and an oxide film, or a film of an oxide film and a nitride film is formed. It is a laminated film (NO) film. When this multilayer insulating film is used as a charge storage layer, charges are held in charge traps in the multilayer insulating film.

In the present invention, typically, the groove or the first groove provided in the semiconductor substrate and the control gate are formed to extend in directions perpendicular to each other.

In the present invention, preferably, a plurality of memory transistors are connected in series to form a NAND type memory string. This NAND type circuit configuration is advantageous for high integration of semiconductor nonvolatile memory devices and miniaturization of elements.

According to the present invention, the second
Is formed in a self-aligned manner with the groove or the first groove and the control gate provided in the semiconductor substrate.

In the present invention, the semiconductor device may be various semiconductor devices partially including a semiconductor nonvolatile memory unit, in addition to the semiconductor nonvolatile memory device.

In the semiconductor nonvolatile memory device according to the present invention, the memory transistor has the second insulating film as a charge storage layer between the control gate and the channel region in the semiconductor substrate. In this memory transistor, when an appropriate voltage is applied to the control gate, the semiconductor substrate or the source region and the drain region, a Fowler-Nordheim tunnel current is generated,
Charge is injected into the second insulating film as a charge storage layer.
When charges are stored in the second insulating film in this manner, an electric field is generated by the stored charges, so that the threshold voltage of the transistor changes. This change allows data to be stored.

According to the present invention configured as described above, as in the conventional method of forming the SA-STI cell structure, the channel region is opposed to the channel region surrounded by the trench isolation insulating film via the gate insulating film. Since there is no step of removing the conductive layer at a portion where the conductive layer is not to be formed, the problem of the remaining etching of the conductive layer does not occur. Also, there is no occurrence of a protrusion at the trench end as in the conventional method of forming a trench element isolation region.

[0048]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings. In all the drawings of the embodiments, the same or corresponding portions are denoted by the same reference numerals.

The semiconductor nonvolatile memory device according to this embodiment is a MONOS type semiconductor nonvolatile memory device having an SA-STI cell structure. FIG. 1 is a plan view thereof.

As shown in FIG. 1, in the semiconductor nonvolatile memory device according to this embodiment, an active region is formed by being separated by a trench isolation insulating film 2 made of, for example, an SiO ₂ film formed on a silicon substrate 1. Have been. In a region where the active region intersects with the control gate 3 serving as a word line, an O as a charge storage layer is provided between the control gate 3 and the channel region of the silicon substrate 1.
An NO film is formed. Control gate 3
A diffusion layer 4 used as a source region and a drain region is formed in the silicon substrate 1 on both sides. A bit line (not shown) is formed above the control gate 3 in a direction orthogonal to the control gate 3, and is connected to the diffusion layer 4 at a bit contact (not shown). The ONO film serving as the charge storage layer may be present on the entire surface of the diffusion layer 4 and the trench isolation insulating film 2 used as the source region and the drain region without any problem. This is only a portion where the control gate 3 and the channel region intersect.

FIG. 2 is a cross-sectional view taken along the line AA 'of the plan view of FIG. 1, and FIG. 3 is a cross-sectional view taken along the line BB' of the plan view of FIG. As shown in FIGS. 2 and 3, an ONO film 5 is formed as a charge storage layer on the active region of the silicon substrate 1 separated by the trench isolation insulating film 2.
A control gate 3 made of, for example, polycrystalline silicon doped with an impurity is formed on the NO film 5.
An interlayer insulating film 6 made of, for example, silicon oxide is formed on the control gate 3, and a bit line (not shown) made of, for example, aluminum is formed thereon.

In the semiconductor nonvolatile memory device having the structure shown in FIGS. 1, 2 and 3, the memory transistor has an ONO film 5 as a charge storage layer between control gate 3 and a channel region in silicon substrate 1. Field effect transistor, that is, a MIS transistor. Each memory transistor is connected in a NAND type to form a NAND type string.

In the MONOS type semiconductor nonvolatile memory device, the ONO film 5 has a function of retaining charges in the film. When an appropriate voltage is applied to the control gate 3 and the silicon substrate 1 or the diffusion layer 4 as a source region and a drain region, a Fowler-Nordheim type tunnel current is generated, and the ONO film 5
When the electric charge is injected into the ONO film 5 and the electric charge is thus accumulated in the ONO film 5, an electric field is generated by the accumulated electric charge, so that the threshold voltage of the transistor changes. This change allows data to be stored. For example, data can be written by accumulating electrons in the ONO film 5, and data can be erased by accumulating holes in the ONO film 5.

The MONOS nonvolatile semiconductor memory device according to this embodiment can have, for example, a NAND circuit configuration as shown in an equivalent circuit diagram of FIG. Here, the selection transistors ST1, ST2 in FIG.
Are formed between a source contact or a bit contact and a NAND string of memory transistors.

Next, a method of manufacturing the semiconductor nonvolatile memory device according to the embodiment having the above-described configuration will be described. First, a description will be given with reference to a cross-sectional view corresponding to a cross section taken along line AA ′ of FIG. As shown in FIG. 4, a LOCOS element isolation insulating film (not shown) for separating a peripheral element region and a memory cell region is formed on a silicon substrate 1, and further, a threshold voltage of a transistor is adjusted or a well or the like is omitted. Is performed, a buffer layer 7 made of, for example, silicon oxide having a thickness of about 10 to 30 nm is formed on the surface of the silicon substrate 1 by, for example, a thermal oxidation method.

Next, as shown in FIG. 5, a resist pattern 8 having a shape corresponding to the element isolation region by STI is formed on the buffer layer 7 by a photolithography process, and the buffer layer is The trench 9 is formed by etching the silicon substrate 7 and the silicon substrate 1 by, for example, the RIE method.

Next, as shown in FIG. 6, after removing the resist pattern 8 and subsequently removing the buffer layer 7 by wet etching or the like, the entire surface is made of silicon oxide by, for example, a CVD method or a bias ECR plasma CVD method. An insulating film 10 is deposited to a thickness of, for example, 700 to 1000 nm to fill the trench 9. At this time, the insulating film 10 may be deposited after a silicon oxide film having a thickness of about 5 to 20 nm is formed on the surface of the trench 9 and the surface of the silicon substrate 1 by a thermal oxidation method or the like.

Next, the continuation of the process shown in FIG.
A description will be given with reference to a cross-sectional view corresponding to a cross section taken along line -B '. That is, as shown in FIG. 7, a resist pattern 11 having a shape in which a portion corresponding to a control gate formation region is opened is formed on the insulating film 10 by a photolithography process, and the resist pattern 11 is used as a mask, for example, by an RIE method. By etching the insulating film 10 by, for example, the groove 12 orthogonal to the trench 9 is formed. Note that the depth of the groove 12 is a depth to the surface of the silicon substrate 1.

Next, after the resist pattern 11 is removed, as shown in FIG. 8, an ONO film 5 as a charge storage layer is formed on the entire surface by, for example, a CVD method or a thermal oxidation method. The thickness of the ONO film 5 is not particularly limited, but is, for example, about 8 to 20 nm in terms of an oxide film.

Next, as shown in FIG. 9, a polycrystalline silicon film 13 is formed on the ONO film 5 by, for example, a CVD method.
After the polycrystalline silicon film 13 is deposited with a thickness of 0 to 200 nm, the polycrystalline silicon film 13 is doped with impurities to reduce the resistance, and a layer for forming a control gate is formed.

Next, as shown in FIG. 10, the control gate 3 is buried in the trench 12 by performing etch-back using an etching method such as RIE until at least the ONO film 5 is exposed. To form

Next, as shown in FIG. 11, the ONO film 5 and the insulating film 10 deposited on the entire surface of the silicon
For example, etch back is performed by using the RIE method or the like. This etch back may be performed up to the surface of the silicon substrate 1 or may be performed until the insulating film 10 has a thickness of, for example, about several nm to several tens nm. Thus, the trench isolation insulating film 2 buried in the trench 9 formed in the silicon substrate 1 is formed. In the formation of the trench element isolation insulating film 2, it is possible to prevent the formation of the protrusion at the trench end as in the conventional trench element isolation.

Next, as shown in FIG. 12, an n-type or p-type impurity is ion-implanted into the silicon substrate 1 using the control gate 3 as a mask, so that portions of the silicon substrate 1 on both sides of the control gate 3 are formed. Then, a diffusion layer 5 as a source region and a drain region is formed in a self-aligned manner. For example, when an n-channel MOS transistor is used as a memory transistor, an n-type impurity such as phosphorus is ion-implanted at a dose of 5 × 10 ¹³ / cm ² .

Next, PSG or BP is formed by, for example, the CVD method.
An interlayer insulating film 6 is formed by depositing silicon oxide such as SG on the entire surface. Thus, FIGS. 1, 2 and 3
1 is manufactured. Although illustration is omitted, after that, for example, an opening of a bit contact reaching the diffusion layer 5 to the interlayer insulating film 6, formation of an upper layer wiring such as a bit line, and formation of a peripheral circuit are performed. A semiconductor nonvolatile memory device is obtained.

As described above, according to this embodiment,
Since there is no step of etching the conductive layer on the trench side wall as in the above-described conventional method for forming the SA-STI cell structure, there is no problem of the etching residue of the conductive layer on the trench side wall, and therefore, this etching residue does not occur. This eliminates the problem of failure due to. Further, it is possible to prevent the formation of the protrusion at the trench end as in the conventional trench element isolation. Also, the MONO according to this embodiment
The S-type semiconductor nonvolatile memory device has a very simple structure and a very simple manufacturing process. In addition, the power supply voltage can be reduced to, for example, about 7 to 8 V, and the lifetime is 2 to 2 times that of the floating gate type semiconductor nonvolatile memory device.
About three digits longer. Furthermore, since the element isolation is performed by the trench element isolation insulating film 2 in which the first insulating film is embedded in the groove provided in the plate, the cell area can be reduced more than the element isolation by the LOCOS element isolation insulating film. It is possible to increase the integration density of the memory cells.

As described above, one embodiment of the present invention has been specifically described. However, the present invention is not limited to the above embodiment, and various modifications based on the technical idea of the present invention are possible. .

For example, the numerical values, structures, materials, processes, and the like described in the above-described embodiment are merely examples, and different numerical values, structures, materials, processes, and the like may be used as needed.

More specifically, in the above-described embodiment, the control gate 3 is constituted by a single layer of a polycrystalline silicon film. However, if necessary, for example, a laminate of a polycrystalline silicon film and a metal silicide film may be used. It may be a multilayer structure with a film. In the above-described embodiment, the ONO film 5 is used as the charge storage layer. However, for example, an NO film may be used as the charge storage layer. The structure of the memory transistor is different from that used in the above-described embodiment, for example, an LDD (Lightly Doped Drain).
Various structures such as a structure can be adopted.

In the above-described embodiment, the NA
Although the ND type semiconductor nonvolatile memory device has been described,
Depending on the arrangement of source contacts, bit contacts, trench element isolation and wiring, NAND type, N
Either the OR type may be used, and the DINOR type may be used. Further, the injection of charges into the charge storage layer may be any of data writing and data erasing.

More specifically, for example, a NOR type circuit configuration as shown in an equivalent circuit diagram of FIG. 19 can be adopted. This NOR-type circuit configuration includes, for example, a diffusion layer 4 as a source region and a drain region formed between two memory transistors formed on the right and left sides in FIG. 3 and shared by both transistors. Can be realized by forming them so as not to be shared by both transistors.

[0071]

As described above, according to the present invention, short-circuiting due to the residual etching of the conductive layer as in the conventional method for forming the SA-STI cell structure and the conventional method for forming the trench element isolation region are not required. It is possible to prevent the formation of a projection at the end of the trench.

[Brief description of the drawings]

FIG. 1 is a plan view showing a MONOS type semiconductor nonvolatile memory device according to an embodiment of the present invention.

FIG. 2 is a sectional view taken along the line AA ′ of FIG.

FIG. 3 is a sectional view taken along the line BB ′ of FIG. 1;

FIG. 4 is a cross-sectional view for explaining the method of manufacturing the MONOS type semiconductor nonvolatile memory device according to one embodiment of the present invention.

FIG. 5 is a cross-sectional view for explaining the method of manufacturing the MONOS type semiconductor nonvolatile memory device according to one embodiment of the present invention.

FIG. 6 is a cross-sectional view for explaining the method of manufacturing the MONOS type semiconductor nonvolatile memory device according to one embodiment of the present invention.

FIG. 7 is a cross-sectional view for explaining the method for manufacturing the MONOS type semiconductor nonvolatile memory device according to one embodiment of the present invention.

FIG. 8 is a cross-sectional view for explaining the method for manufacturing the MONOS type semiconductor nonvolatile memory device according to one embodiment of the present invention.

FIG. 9 is a cross-sectional view for explaining the method of manufacturing the MONOS type semiconductor nonvolatile memory device according to one embodiment of the present invention.

FIG. 10 is a cross-sectional view for explaining the method of manufacturing the MONOS type semiconductor nonvolatile memory device according to one embodiment of the present invention.

FIG. 11 is a cross-sectional view for explaining the method for manufacturing the MONOS type semiconductor nonvolatile memory device according to one embodiment of the present invention.

FIG. 12 is a cross-sectional view for explaining the method for manufacturing the MONOS type nonvolatile semiconductor memory device according to one embodiment of the present invention.

FIG. 13 is a cross-sectional view for explaining a method of manufacturing a conventional floating gate type semiconductor nonvolatile memory device.

FIG. 14 is a cross-sectional view for explaining a method of manufacturing a conventional floating gate semiconductor nonvolatile memory device.

FIG. 15 is a cross-sectional view for explaining a method of manufacturing a conventional floating gate type semiconductor nonvolatile memory device.

FIG. 16 is a cross-sectional view for explaining a method of manufacturing a conventional floating gate type semiconductor nonvolatile memory device.

FIG. 17 is a cross-sectional view for explaining a method of manufacturing a conventional floating gate type semiconductor nonvolatile memory device.

FIG. 18 is a cross-sectional view for explaining a method of manufacturing a conventional floating gate semiconductor nonvolatile memory device.

FIG. 19 is an equivalent circuit diagram showing a semiconductor nonvolatile memory device having a NOR type circuit configuration.

FIG. 20 is an equivalent circuit diagram showing a semiconductor nonvolatile memory device having a NAND circuit configuration.

FIG. 21 is a plan view showing a conventional floating gate type semiconductor nonvolatile memory device having an SA-STI cell structure.

FIG. 22 is a sectional view taken along line AA ′ of FIG. 21;

FIG. 23 is a sectional view taken along the line BB ′ in FIG. 21;

FIG. 24 is a cross-sectional view for explaining a method of manufacturing a floating gate type semiconductor nonvolatile memory device having a conventional SA-STI cell structure.

FIG. 25 is a cross-sectional view for explaining a method of manufacturing a floating gate type semiconductor nonvolatile memory device having a conventional SA-STI cell structure.

FIG. 26 is a cross-sectional view for explaining a method of manufacturing a conventional floating gate type semiconductor nonvolatile memory device having an SA-STI cell structure.

FIG. 27 is a cross-sectional view for explaining a method of manufacturing a conventional floating gate type semiconductor nonvolatile memory device having an SA-STI cell structure.

FIG. 28 is a cross-sectional view for explaining a method of manufacturing a floating gate type semiconductor nonvolatile memory device having a conventional SA-STI cell structure.

FIG. 29 is a cross-sectional view for explaining a method of manufacturing a floating gate type semiconductor nonvolatile memory device having a conventional SA-STI cell structure.

FIG. 30 is a plan view for explaining a method of manufacturing a floating gate type semiconductor nonvolatile memory device having a conventional SA-STI cell structure.

FIG. 31 is a cross-sectional view for explaining a method of manufacturing a conventional floating gate semiconductor nonvolatile memory device having an SA-STI cell structure.

FIG. 32 is a cross-sectional view for explaining a method of manufacturing a floating gate type semiconductor nonvolatile memory device having a conventional SA-STI cell structure.

FIG. 33 is a cross-sectional view for explaining a method of manufacturing a floating gate type semiconductor nonvolatile memory device having a conventional SA-STI cell structure.

FIG. 34 is a cross-sectional view for explaining a method of manufacturing a conventional floating gate type semiconductor nonvolatile memory device having an SA-STI cell structure.

FIG. 35 is a cross-sectional view for explaining a method of manufacturing a floating gate type semiconductor nonvolatile memory device having a conventional SA-STI cell structure.

FIG. 36 is a perspective view for explaining a problem of a method of manufacturing a floating gate type semiconductor nonvolatile memory device having a conventional SA-STI cell structure.

FIG. 37 is a perspective view for explaining a problem of a method of manufacturing a floating gate type semiconductor nonvolatile memory device having a conventional SA-STI cell structure.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Silicon substrate, 2 ... Trench isolation insulating film, 3 ... Control gate, 4 ... Diffusion layer, 5
... ONO film, 6 ... interlayer insulating film, 9 ... trench, 13 ... polycrystalline silicon film

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5F001 AA14 AB02 AC02 AD12 AD53 AG03 AG07 5F048 AA07 AA09 AB01 AC01 BA01 BB05 BB15 BG01 BG11 5F083 EP22 EP43 EP76 EP77 ER03 ER14 ER21 ER30 GA27 JA05 NA01 PR03 PR21 PR29 PR39

Claims (16)

[Claims] A semiconductor substrate having a channel region; a first insulating film for element isolation embedded in a groove provided in the semiconductor substrate so as to separate the channel region; A control gate provided so as to intersect with the trench through the insulating film of 2, and a source region and a drain region provided on the semiconductor substrate on both sides of the control gate; A semiconductor device, wherein a memory transistor is constituted by the source region and the drain region. 2. The semiconductor device according to claim 1, wherein said second insulating film has a charge storage function. 3. The semiconductor device according to claim 2, wherein said second insulating film comprises a multilayer insulating film. 4. The semiconductor device according to claim 3, wherein said multilayer insulating film is a laminated film of an oxide film, a nitride film and an oxide film. 5. The semiconductor device according to claim 3, wherein said multilayer insulating film is a laminated film of an oxide film and a nitride film. 6. The semiconductor device according to claim 1, wherein said groove and said control gate extend in directions orthogonal to each other. 7. The semiconductor device according to claim 1, wherein a plurality of said memory transistors are connected in series to form a NAND memory string. 8. The semiconductor device according to claim 1, wherein said semiconductor device is a semiconductor nonvolatile memory device. 9. A semiconductor substrate having a channel region, a first insulating film for element isolation embedded in a first groove provided in the semiconductor substrate so as to separate the channel region, and the channel region A control gate provided on the semiconductor substrate so as to intersect the first groove with a second insulating film interposed therebetween; and a source region and a drain region provided on the semiconductor substrate on both sides of the control gate. A method of manufacturing a semiconductor device in which a memory transistor is constituted by the control gate, the source region, and the drain region, wherein the first groove is formed in the semiconductor substrate so as to separate the channel region. Forming the first insulating film on the semiconductor substrate so as to fill the first groove; and forming the first insulating film on the semiconductor substrate. Forming a second groove intersecting the first groove by patterning a film to expose the channel region; and forming the second insulating layer on at least the channel region inside the second groove. A step of forming a film; a step of depositing a conductive material on the semiconductor substrate on which the second insulating film is formed so as to fill the second groove; and a step of applying the conductive material to at least the first insulating film. Forming the control gate in the second groove by etching back until the semiconductor substrate is exposed; etching back the first insulating film almost to the vicinity of the surface of the semiconductor substrate; Forming the source region and the drain region by introducing impurities into the semiconductor substrate on both sides of the semiconductor substrate. Method of manufacturing a semiconductor device that. 10. The method according to claim 9, wherein the second insulating film has a charge storage function. 11. The method according to claim 10, wherein said second insulating film comprises a multilayer insulating film. 12. The method according to claim 11, wherein the multilayer insulating film is a laminated film of an oxide film, a nitride film, and an oxide film. 13. The method according to claim 11, wherein said multilayer insulating film is a laminated film of an oxide film and a nitride film. 14. The method according to claim 9, wherein said first groove and said control gate extend in directions orthogonal to each other. 15. The method according to claim 9, wherein the second insulating film on the channel region is formed in a self-aligned manner with the first trench and the control gate. 16. The method according to claim 9, wherein said semiconductor device is a semiconductor nonvolatile memory device.