JP2004241698A - Nonvolatile semiconductor memory device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide the nonvolatile semiconductor memory device of a laminated gate insulating film structure which can surely protect an oxide aluminum trap insulating film. <P>SOLUTION: The nonvolatile semiconductor memory device has a semiconductor substrate, a laminated gate insulating film formed on the semiconductor substrate, a gate electrode formed on the laminated gate insulating film, and a pair of impurity diffusion regions formed in a position holding the gate electrode therebetween in a semiconductor substrate surface. The laminated gate insulating film has the four-layer structure of a tunnel insulating film, an oxide aluminum trap insulating film, a top insulating film, and a cover insulating film protecting the oxide aluminum trap insulating film and the top insulating film in order from the semiconductor substrate side. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a nonvolatile semiconductor memory device having a stacked gate insulating film composed of a tunnel insulating film, a trap insulating film, and a block insulating film on a semiconductor substrate. The present invention relates to a MOAOS (Metal Oxide Aluminum Oxide Semiconductor) type nonvolatile semiconductor memory device using an aluminum oxide-based insulating film and a method for manufacturing the same.
[0002]
[Prior art]
A flash memory is known as a nonvolatile semiconductor memory. In a flash memory, in addition to writing and erasing a memory capacity (charge) at an arbitrary address, batch erasing is also possible, and the contents of the memory can be maintained even when the power is turned off.
[0003]
As a structure of the flash memory, a double gate structure including a control gate and a floating gate has been conventionally used. However, since it is difficult to achieve miniaturization and mounting on a logic with a double-gate structure, a single-gate nonvolatile semiconductor memory that stores data by trapping charges in a gate insulating film has been proposed (for example, see Patent Reference 1).
[0004]
A single-gate nonvolatile semiconductor memory is referred to as a MONOS (Metal Oxide Nitride Oxide Semiconductor) type or a SONOS (Poly-Silicon Oxide Nitride Semiconductor type memory) from a stacked structure in which a gate insulating film is formed under a control gate. ing.
[0005]
FIG. 1A shows a memory cell configuration of a general MONOS or SONOS type flash memory. A silicon oxide film (SiO 2) is formed on the semiconductor substrate 110. ₂ ) 112a, silicon nitride film (SiN) 112b, silicon oxide film (SiO ₂ ) 112c, and the control gate electrode 113 is located on the stacked gate insulating film 112 having the ONO structure.
[0006]
The SiN film 112b is called a trap layer because it traps electric charges, ₂ The film 112a is called a tunnel insulating film because electrons tunnel during data programming and erasing. Upper SiO ₂ The film 112c prevents leakage of electrons from the SiN trap film 112b to the gate electrode 113 and injection of holes other than when erasing from the gate electrode 113 to the SiN trap film 112b, and is called a top insulating film or a block insulating film.
[0007]
By controlling the writing voltage to the control gate electrode 113 and the application of the voltage pulse to the second diffusion region 111b, or controlling the writing voltage to the control gate electrode 113 and the application of the voltage pulse to the first diffusion region 111a, ₂ At the interface between the SiN films 112b sandwiched between the films 112a and 112c, charges are discretized and trapped in either the second diffusion region 111b or the first diffusion region 111a. That is, a memory function of two bits is realized by one cell.
[0008]
Further, based on the above-described MONOS structure, a MONOS-type nonvolatile semiconductor memory capable of multi-value writing exceeding four values has been proposed by changing the trapping state of charges discretely accumulated in the gate insulating film 112. (For example, see Patent Document 2).
[0009]
However, the charge holding ability of the silicon nitride (SiN) film cannot be said to be sufficient, and it cannot be said that data reliability is sufficiently ensured, especially when miniaturization proceeds. Therefore, Japanese Patent Application No. 2002-264252 filed by the same applicant as the present patent application proposes a method in which an aluminum oxide-based material is used as a trap insulating film instead of a silicon nitride film.
[0010]
FIG. 1B shows a configuration example of a MOAOS type memory cell using an alumina film as a trap insulating film. On the silicon substrate 140, a laminated gate insulating film 145 having an OAO structure composed of a silicon oxide film 142, an alumina film 143, and a silicon oxide film 144 is located. A word line 146 functioning as a control gate electrode is located on 145. On both sides of the control gate electrode (or word line) 146, sidewalls (sidewall spacers) 147 are provided.
[0011]
Alumina or aluminum oxide (Al ₂ O ₃ In (2), electric charges are trapped deeper and the storage retention characteristics are higher than those of a silicon nitride (SiN) film which is a conventional trap insulating film. Also, the erasing operation is faster than that of the silicon nitride film.
[0012]
[Patent Document 1]
JP 2001-358237 A
[0013]
[Patent Document 2]
JP 2001-93995 A
[0014]
[Problems to be solved by the invention]
However, aluminum oxide (Al ₂ O ₃ ) Has poor acid resistance, and has a problem that it is eroded in a wet process using an acidic cleaning solution in a memory cell manufacturing process. For example, as shown in FIGS. 2A to 2D, a silicon oxide film (SiO ₂ ) 142, aluminum oxide (Al ₂ O ₃ ) Film 143, silicon oxide film (SiO ₂ ) A word line 146 as a control gate electrode is patterned on an OAO type laminated gate insulating film 145 composed of a film 144, and the whole is formed of SiO. ₂ In the case where the sidewall 147 is formed by being covered with the film 147a and then etched back, the uppermost silicon oxide film (top insulating film) of the laminated gate insulating film 145 is also etched, and aluminum oxide (Al ₂ O ₃ ) The surface is exposed.
[0015]
Normally, after the formation of the sidewalls 147 by the etch back, cleaning with an acidic cleaning liquid is performed. ₂ O ₃ The film 143 is etched. As a result, as shown in FIG. ₂ O ₃ Both sides of the membrane 143 are eroded, creating grooves 149.
[0016]
When the trap insulating film is eroded from both sides, the charges to be discretely trapped on the source side and the drain side are mixed and do not function as a multi-valued memory, but also the reliability of storage retention is impaired.
[0017]
It is conceivable to replace the top insulating film with a nitride-based thin film instead of a silicon oxide film. However, the nitride-based film has a lower density than the oxide-based film, and there is a concern about leakage. Further, in order to suppress diffusion of ions into the gate insulating film at the time of ion implantation for forming the source / drain, it is preferable that the top insulating film is an oxide film type.
[0018]
Therefore, the present invention provides a nonvolatile semiconductor memory using an aluminum oxide-based trap insulating film having a high memory retention capability, based on an OAO structure and a trap layer edge film (Al). ₂ O ₃ It is an object of the present invention to provide a nonvolatile semiconductor memory having high performance and high reliability while avoiding etching damage to the film and erosion due to cleaning. It is another object of the present invention to provide a method for manufacturing such a nonvolatile semiconductor memory.
[0019]
[Means for Solving the Problems]
In order to achieve the above object, according to the present invention, a fourth cover insulating film having a lower etching selectivity than a sidewall (sidewall spacer or sidewall insulating film) is inserted into the uppermost layer of the stacked gate insulating film including the OAO structure. By doing so, the aluminum oxide-based trapping insulating film is reliably protected from etching damage at the time of forming the side wall insulating film and erosion due to subsequent cleaning.
[0020]
Specifically, according to the first aspect of the present invention, a nonvolatile semiconductor memory device includes a semiconductor substrate, a stacked gate insulating film formed on the semiconductor substrate, and a gate electrode formed on the stacked gate insulating film. A pair of impurity diffusion regions formed at positions sandwiching the gate electrode on the surface of the semiconductor substrate, wherein the laminated gate insulating film includes, in order from the semiconductor substrate side, a tunnel insulating film, an aluminum oxide-based trap insulating film, It has a four-layer structure of an insulating film and a cover insulating film for protecting an aluminum oxide-based trap insulating film and a top insulating film.
[0021]
This nonvolatile semiconductor memory device further includes a side wall insulating film located on a side wall of the gate electrode, and the cover insulating film is formed of a material having a lower etching rate than the side wall insulating film.
[0022]
The sidewall is desirably a silicon oxide film from the viewpoint of denseness and prevention of an increase in fringe capacitance of the gate electrode. The fourth cover insulating film is a silicon nitride (SiN) film having a lower etching rate than the silicon oxide film. In this case, the laminated gate insulating film has a four-layer structure of a silicon oxide film, an aluminum oxide film, a silicon oxide film, and a silicon nitride film in this order from the substrate side.
[0023]
According to a second aspect of the present invention, there is provided a method for manufacturing a nonvolatile semiconductor device capable of reliably protecting an aluminum oxide-based film as a trap insulating film from process damage. This manufacturing method includes the following steps.
(A) forming, on a silicon substrate, a tunnel insulating film, an aluminum oxide-based trap insulating film, a top insulating film, and a cover insulating film sequentially to form a four-layer laminated gate insulating film;
(B) forming a gate electrode of a predetermined shape on the laminated gate insulating film;
(C) A sidewall insulating film is formed on both sides of the gate electrode using an insulating material having a high etching selectivity with respect to the cover insulating film.
[0024]
The step of forming the gate electrode includes a step of depositing a gate electrode material on the laminated gate insulating film and processing the gate electrode material until the surface of the cover insulating film is exposed.
[0025]
In the step of forming the stacked gate insulating film, it is preferable that the forming temperature of at least one of the top insulating film and the cover insulating film is higher than the forming temperature of the aluminum oxide-based trap insulating film. In this case, even if individual annealing is not performed after the formation of the aluminum oxide-based trap insulating film, the aluminum oxide is baked at the formation temperature of the top insulating film or the cover insulating film, and the number of steps can be reduced. Other configurations and features of the present invention will become more apparent from the detailed description given below with reference to the drawings.
[0026]
BEST MODE FOR CARRYING OUT THE INVENTION
FIG. 3 is a diagram schematically illustrating a configuration of a flash memory cell included in the nonvolatile semiconductor memory device according to the embodiment of the present invention.
[0027]
In this flash memory cell, a silicon oxide film (SiO ₂ 2.) Aluminum oxide film (Al ₂ O ₃ 3) Silicon oxide film (SiO ₂ ) 4 and a stacked gate insulating film 7 composed of four layers of a silicon nitride film (SiN) 5. In the active region partitioned by the element isolation layer 9 such as a LOCOS oxide film, the gate electrode 6 functioning as a word line is provided on the laminated gate insulating film 7. Side walls 8 are located on both sides of the gate electrode 6.
[0028]
In the example of FIG. 3, the sidewall 8 is made of, for example, a silicon oxide film. As a fourth insulating film of the laminated gate insulating film 7, a silicon nitride film (SiN) 5 having an etching selectivity lower than that of the silicon oxide film is used. Is selected.
[0029]
Among the stacked gate insulating films 7, the silicon oxide film 2 located on the silicon substrate 1 functions as a tunnel insulating film, and charges are tunneled by an applied voltage when programming and erasing a memory cell. The aluminum oxide film 3 on the silicon oxide film 2 has a deeper trapping order than the silicon nitride film, and has a higher retention of trapped charges. The silicon oxide film on the aluminum oxide film 3 is a top insulating film for preventing leakage of electrons and injection of holes.
[0030]
The OAO structure in which the aluminum oxide film 3 serving as a trap insulating film is sandwiched between silicon oxide films is important for preventing leakage of charges trapped in the aluminum oxide. In order to protect the OAO structure, the silicon nitride film 5 as the uppermost cover insulating film only needs to have a thickness that does not significantly affect an increase in applied voltage and can protect the lower OAO structure. For example, when the thickness of the silicon oxide film 2 as the tunnel insulating film is 7 nm, the thickness of the aluminum oxide film 3 as the trap insulating film is 10 nm, and the thickness of the silicon oxide film 4 as the top insulating film is 10 nm, The thickness of the silicon nitride film 5 is 6 nm.
[0031]
FIG. 4 is a plan view of a flash memory cell array including a memory cell having the four-layered gate insulating film shown in FIG. 3, and FIG. 5 is an equivalent circuit diagram of the memory cell array. The memory cell region 20 is located at the intersection of the word line 6 and the bit line 11, and the source and drain of the memory cell are connected to two adjacent bit lines 11, respectively.
[0032]
The bit lines (BL1 to BL5) 11 are connected to a sense amplifier 31, and the word lines (WL1 to WL8) are connected to a word line driver 32. The sense amplifier 31 and the word line driver 32 are controlled by the control circuit 30, and access a desired memory cell by selecting the word line 6 and the bit line 11 by the control circuit. The control circuit 30 is controlled by an external CPU 33. A RAM 34 is connected to the CPU 33, and the RAM 34 temporarily stores data to be written to the memory cells.
[0033]
6 to 9 are cross-sectional views taken along line AA ', line BB', line CC ', and line DD' in the plan view of FIG. 4, respectively. AA ′ cross-sectional view of FIG. 6 shows the structure of the control gate electrode 6 and the stacked gate insulating film 7 located between two adjacent bit lines 11 in the active region. The control gate electrode 6 becomes the word line 6 as it is.
[0034]
A cross-sectional view taken along the line BB ′ of FIG. 7 shows the structure of the word line 6 and the stacked gate insulating film 7 located below the bit line 11 in the active region. The bit line 11 is connected to one of the high-concentration source / drain regions 16b via a plug 18 penetrating the interlayer insulating film 15.
[0035]
The cross-sectional view taken along the line CC ′ of FIG. 8 shows an inactive region that separates and independents each memory cell in a direction along the bit line 11. 9 shows a cross-sectional structure in a direction along the word line 6 in the active region.
[0036]
In such a memory cell write operation, a write voltage is applied to the control gate electrode 6, a positive voltage pulse is applied to one source / drain region 16 via the bit line 11 and the plug 18, and the other source / drain Region 16 'is set to 0V. As a result, charges (hot electrons) tunnel from the vicinity of the source / drain regions 16 to the tunnel insulating film 2, and the charges are discretely trapped on the region 16 a side of the aluminum oxide film 3 below the control gate electrode 6. You.
[0037]
Further, by applying a write voltage to the control gate electrode 6, setting one of the source / drain regions 16 to 0V, and applying a positive voltage pulse to the other source / drain region 16 ', the aluminum oxide film 3 has a region 16a The charges are trapped discretely on the 'side.
[0038]
Erasing is performed collectively by neutralizing the charges discretely trapped in the aluminum oxide film 3 by injecting holes. That is, with respect to the charges trapped in the region 16a, an erase voltage is applied to all of the word lines of the selected block, that is, the control gate electrode 6, and all of the one source / drain region 16, and the other source / drain region 16 is charged. By setting the drain region 16 ′ to be floating, a hot hole is generated and injected into the aluminum oxide film 3. With respect to the charges trapped in the region 16a ', an erase voltage is applied to all of the word lines of the selected block, that is, the control gate electrode 6, and all of the other source / drain regions 16'. By making the drain region 16 floating, hot holes are generated on the side of the other source / drain 16 ′ to erase all at once.
[0039]
At the time of reading, a predetermined gate voltage is applied to a word line (control gate electrode) 6 connected to the selected memory cell, a positive read voltage is applied to one source / drain region 16, and the other source / drain 16 is applied. 'By setting the region to 0 V, the current flowing through the memory cell is compared with the reference current to determine the presence or absence of charges on the region 16a. Further, a predetermined gate voltage is applied to the selected word line 6, a positive read voltage is applied to the other source / drain region 16 ', and one of the source / drain 16 is set to 0V, so that the memory cell is The flowing current is detected and compared with the reference current to determine the presence or absence of charges on the side of the region 16a '.
[0040]
FIG. 10 shows a process of manufacturing the nonvolatile semiconductor memory according to the embodiment of the present invention.
[0041]
First, as shown in FIG. 10A, a local element isolation region 9 is formed on, for example, a p-type silicon substrate 1 by, for example, a LOCOS method, and an active region is determined. A silicon oxide film 2 as a tunnel insulating film, an aluminum oxide film 3 as a trap insulating film, a silicon oxide film 4 as a top insulating film, and a silicon nitride film 5 as a cover insulating film are sequentially formed on the entire surface of the substrate. I do. These four layers constitute the laminated gate insulating film 7.
[0042]
The silicon oxide film 2 as a tunnel insulating film is formed, for example, by exposing the silicon substrate 1 to an oxidizing atmosphere at a high temperature of about 1000 ° C. to a thickness of about 7 nm. The aluminum oxide film 3 as a trap insulating film is formed to a thickness of about 10 nm by, for example, an ALCVD (Atomic Layer Chemical Vapor Deposition) method. Al (CH ₃ ) ₃ And ozone (O ₃ ) Are supplied alternately. The aluminum oxide film can be formed by MOCVD or PVD.
[0043]
The silicon oxide film 4 as the top insulating film is formed, for example, by mono-silane (SiH) by LPCVD (Low Pressure Chemical Vapor Deposition). ₄ ) And N ₂ O is reacted to form a film having a thickness of about 10 nm. The top insulating film 4 may be formed by a CVD method using a TEOS material, an MOCVD method, or a plasma CVD method. Silicon oxide film 4 insulates charges trapped in aluminum oxide film 3.
[0044]
The silicon nitride film 5 as the cover insulating film is formed to a thickness of about 6 nm by plasma CVD, low pressure CVD, MOCVD, or the like, using purified ammonia as a reaction gas. This silicon nitride film 5 prevents the lower aluminum oxide film 3 from being eroded in a cleaning step after forming a sidewall in a later step.
[0045]
When aluminum oxide 3 as a trap insulating film is formed at, for example, 300 ° C. to 500 ° C., it is desirable to form silicon oxide film 4 and silicon nitride film 5 at about 800 ° C. Thus, the annealing treatment of the aluminum oxide film 3 can be performed at the time of forming the upper insulating film 4 and the cover insulating film 5 without performing the single annealing treatment on the aluminum oxide 3.
[0046]
When the annealing process is performed at about 900 ° C. after the formation of the aluminum oxide film 3, the subsequent silicon oxide film 4 and silicon nitride film 5 are formed at a low temperature that does not impair the denseness of the film, for example, at about 700 ° C. Can be formed.
[0047]
Next, as shown in FIG. 10B, a word line 6 as a gate electrode is formed in an active region defined by the element isolation region 9. After depositing polysilicon or amorphous silicon on the entire surface, patterning is performed into a predetermined word line shape by photolithography. By dry etching when forming the word line 6, the silicon nitride film 5 having a high selectivity with respect to polysilicon functions as a stopper. After patterning, self-aligned low-concentration n-type impurity diffusion regions 16a and 16a 'are formed using the word line (gate electrode) 6 as a mask. As a dopant, for example, As, an acceleration voltage of about 10 KeV, and a dose of 1.5 × 10 ¹⁴ cm ^-2 And a dopant is implanted into the silicon substrate 1 via the laminated gate insulating film 7 and diffused by a subsequent heat treatment.
[0048]
Next, as shown in FIG. 10C, a silicon oxide film 8a is deposited so as to cover the gate electrode (word line) 6 and the entire surface of the substrate.
[0049]
Next, as shown in FIG. 10D, the oxide film 8a is etched back to leave sidewalls 8 on both sides of the gate electrode (word line) 6. When performing anisotropic etching by dry processing, the silicon nitride film 5 located on the uppermost layer of the laminated gate insulating film 7 has a higher dry etching resistance than the silicon oxide film, and functions as a hard mask. As a result, sidewall 8 can be formed without exposing lower silicon oxide film 4 and aluminum oxide film 3. After the formation of the sidewalls 8, the substrate is cleaned with an acidic cleaning solution. Also in this cleaning step, erosion is prevented because the aluminum oxide is protected without being exposed. Therefore, the reliability as a trap insulating film for charge storage is not impaired.
[0050]
Further, using the side wall 8 as a mask, an acceleration voltage of 30 KeV and a dose of 1 × 10 ^Fifteen cm ^-2 Then, an n-type dopant is implanted into the silicon substrate 1 via the laminated gate insulating film 7 to form high-concentration impurity diffusion regions 16b and 16b '.
[0051]
Subsequently, although not shown, an interlayer insulating film is deposited on the front surface to cover the word lines 6 and the side walls 8 to form holes reaching the source / drain regions, and the inside of the holes is formed via an adhesion layer such as TiN. Embed with conductive material. Then, after the surface is flattened by CMP or the like, the entire surface is covered with a conductive material, and patterned into a predetermined shape by photolithography to form a bit line 11 (see FIG. 7).
[0052]
According to such a manufacturing process, the aluminum oxide film serving as the trap insulating film can be protected from etching damage and erosion due to cleaning without exposing the aluminum oxide film. As a result, the charges can be reliably trapped discretely on the source side and the drain side, and the reliability of the operation as the nonvolatile memory can be ensured.
[0053]
In the embodiment, the silicon nitride film is used as the cover insulating film (the fourth insulating film). However, the present invention is not limited to this example as long as the etching selectivity with the sidewall is large. For example, an oxynitride film may be used. It is possible.
[0054]
Further, the forming method, film thickness, and the like of each film constituting the stacked gate insulating film are not limited to the examples described in the embodiment, and can be appropriately changed within a range that does not cause a significant increase in applied voltage. For example, the silicon nitride film as the cover insulating film can be adjusted in a range of 2 nm to 10 nm according to the thickness of the lower layer as long as the thickness can protect the aluminum oxide system from etching damage and cleaning damage.
[0055]
Aluminum oxide based insulating film as a trap insulating film is made of alumina (Al ₂ O ₃ However, for example, AlHfO, AlZrO, AlTaO, ZrAlO, etc. may be used.
[0056]
Finally, with regard to the above description, the following supplementary notes are disclosed.
(Supplementary Note 1) A semiconductor substrate, a stacked gate insulating film formed on the semiconductor substrate, a gate electrode formed on the stacked gate insulating film, and a pair of impurities formed at positions sandwiching the gate electrode on the surface of the semiconductor substrate. A diffusion region, and the laminated gate insulating film includes, in order from the semiconductor substrate side, a tunnel insulating film, an aluminum oxide-based trap insulating film, a top insulating film, and the aluminum oxide-based trap insulating film and a top insulating film. A nonvolatile semiconductor memory device having a four-layer structure of a cover insulating film for protecting the semiconductor device.
(Supplementary Note 2) The supplementary note 1, further comprising a side wall insulating film located on a side wall of the gate electrode, wherein the cover insulating film is formed of a material having a lower etching rate with respect to the side wall insulating film. Nonvolatile semiconductor memory device.
(Supplementary Note 3) The nonvolatile semiconductor memory device according to supplementary note 1, wherein the cover insulating film is a silicon nitride film.
(Supplementary Note 4) The nonvolatile semiconductor memory device according to supplementary note 2, wherein the side wall is a silicon oxide film, and the cover insulating film is a silicon nitride film.
(Supplementary Note 5) The nonvolatile semiconductor memory device according to Supplementary Note 1, wherein the thickness of the cover insulating film is 2 nm to 10 nm.
(Supplementary Note 6) A step of sequentially forming a tunnel insulating film, an aluminum oxide-based trap insulating film, a top insulating film, and a cover insulating film on a silicon substrate to form a four-layer laminated gate insulating film;
Forming a gate electrode of a predetermined shape on the laminated gate insulating film;
Forming a sidewall insulating film on both sides of the gate electrode with an insulating material having a large etching selectivity with respect to the cover insulating film;
A method for manufacturing a nonvolatile semiconductor memory device, comprising:
(Supplementary Note 7) The step of forming the gate electrode includes a step of depositing a gate electrode material on the laminated gate insulating film and processing the gate electrode material until the surface of the cover insulating film is exposed. 7. The method for manufacturing a nonvolatile semiconductor memory device according to supplementary note 6.
(Supplementary Note 8) In the step of forming the laminated gate insulating film, a forming temperature of at least one of the top insulating film and the cover insulating film is higher than a forming temperature of the aluminum oxide-based trap insulating film. Item 4. The method for manufacturing a nonvolatile semiconductor memory device according to Item 3.
(Supplementary Note 9) The method for manufacturing a nonvolatile semiconductor memory device according to supplementary note 6, wherein the cover insulating film is a silicon nitride film, and the sidewall insulating film is a silicon oxide film.
[0057]
【The invention's effect】
As described above, according to the present invention, in a nonvolatile semiconductor memory including an OAO structure in which an aluminum oxide film is used as a trap insulating film, damage or erosion of the aluminum oxide film is prevented, and high reliability of operation is maintained. It becomes possible to do.
[Brief description of the drawings]
FIG. 1 shows a configuration example of a single-gate nonvolatile memory cell. FIG. 1A shows a structure of a general MONOS memory cell, and FIG. 1B shows a newly proposed MOAOS memory. It is a figure showing the structure of a cell.
FIG. 2 is a diagram showing a manufacturing process of the MOAOS memory cell shown in FIG.
FIG. 3 is a diagram showing a configuration example of a flash memory cell having a four-layer stacked gate insulating film structure according to an embodiment of the present invention.
FIG. 4 is a plan view of a memory cell array using the flash memory cells having the configuration shown in FIG. 3;
FIG. 5 is a block diagram including an equalization circuit diagram of the flash memory cell array of FIG. 4;
FIG. 6 is a sectional view taken along the line AA ′ of FIG. 4;
FIG. 7 is a sectional view taken along the line BB ′ of FIG. 4;
FIG. 8 is a sectional view taken along line CC ′ of FIG. 4;
FIG. 9 is a sectional view taken along line DD ′ of FIG. 4;
FIG. 10 is a diagram showing a manufacturing process of a flash memory having a four-layer laminated gate insulating film structure according to the embodiment of the present invention.
[Explanation of symbols]
1 semiconductor substrate (silicon substrate)
2 Tunnel insulating film (silicon oxide film)
3 Trap insulating film (aluminum oxide film)
4 Top insulating film (silicon oxide film)
5 Cover insulating film (silicon nitride film)
6 Gate electrode (word line)
7 Stacked gate insulation structure
8 Side wall (side wall insulating film)
9 Device isolation area
10 Flash memory cell array
11 bit line
15 Interlayer insulation film
16 Source / drain regions
16a Low concentration impurity diffusion region
16b High concentration impurity diffusion region
18 plug

Claims (5)

A semiconductor substrate;
A stacked gate insulating film formed on the semiconductor substrate,
A gate electrode formed on the laminated gate insulating film;
A pair of impurity diffusion regions formed on the surface of the semiconductor substrate so as to sandwich the gate electrode, wherein the laminated gate insulating film includes, in order from the semiconductor substrate side, a tunnel insulating film and an aluminum oxide-based trap insulating film. A non-volatile semiconductor memory device having a four-layer structure of: a top insulating film; and a cover insulating film for protecting the aluminum oxide-based trap insulating film and the top insulating film. 2. The non-volatile memory according to claim 1, further comprising a side wall insulating film located on a side wall of the gate electrode, wherein the cover insulating film is formed of a material having a lower etching rate than the side wall insulating film. Semiconductor storage device. Forming a tunnel insulating film, an aluminum oxide-based trap insulating film, a top insulating film, and a cover insulating film on a silicon substrate sequentially to form a four-layer laminated gate insulating film;
Forming a gate electrode of a predetermined shape on the laminated gate insulating film;
Forming a sidewall insulating film on both sides of the gate electrode with an insulating material having a large etching selectivity with respect to the cover insulating film;
A method for manufacturing a nonvolatile semiconductor memory device, comprising: 4. The method according to claim 3, wherein the step of forming the gate electrode includes a step of depositing a gate electrode material on the laminated gate insulating film and processing the gate electrode material until the surface of the cover insulating film is exposed. 3. The method for manufacturing a nonvolatile semiconductor memory device according to 1. 4. The step of forming the stacked gate insulating film, wherein a forming temperature of at least one of the top insulating film and the cover insulating film is higher than a forming temperature of the aluminum oxide-based trap insulating film. Manufacturing method of a nonvolatile semiconductor memory device of the present invention.

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