JP2007103764A - Semiconductor memory device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor memory device that enables a memory window to be enlarged. <P>SOLUTION: This semiconductor memory device has a gate electrode 105 mounted on a semiconductor layer 101 having a first conductivity type via an insulating layer 102, two diffusion areas (106, 107) having a second conductivity type which is the reverse of the first conductivity type on the top surface of the above semiconductor layer corresponding to both sides of the above gate electrode, a charge storage film 103 with a function for storing the charges placed oppositely on the above semiconductor layer via the above gate electrode and insulating film 104, and two areas (108 and 109) having lower impurity densities in comparison with those in areas (111 and 112) except the gate electrode, on the gate electrode side of the diffusion areas. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor memory device and a method for manufacturing the semiconductor memory device, and is particularly suitable for a semiconductor memory device that can be electrically written and erased and a method for manufacturing the semiconductor memory device.

A further increase in capacity of the semiconductor memory device is desired.
As an increase in capacity, there is a multilevel memory that stores information of a plurality of bits in one cell. An example of the multi-level memory is NROM (Nitride-containing programmable read-only memory) described in Patent Document 1 (Japanese Patent Laid-Open No. 2001-156189).

  FIG. 10 is a schematic cross-sectional view of a memory cell 9000 constituting a conventional NROM cut along the channel direction. The outline of how to form the NROM according to the formation of the NMOSFET is shown below, and the schematic structure of the NROM is shown.

  The NROM includes a p-type semiconductor substrate 9001, a first oxide film 9002 formed on the p-type semiconductor substrate 9001, a nitride film 9003 formed on the first oxide film 9002, and the nitride film It has a second oxide film 9004 formed on 9003 and a gate electrode 9005 formed on the second oxide film 9004.

  In general, a silicon substrate is used as the semiconductor substrate 9001, a silicon oxide film is used as the first oxide film 9002 and the second oxide film 9004, a silicon nitride film is used as the nitride film 9003, and a polysilicon film is used as the gate electrode 9005. .

  Further, an n-type diffusion region 9006 is formed on the left side of the paper surface and an n-type diffusion region 9007 is formed on the right side of the paper surface at locations corresponding to both sides of the gate electrode 9005 in the semiconductor substrate 9001. By applying a positive voltage to the gate electrode 9005 in a state where a potential difference is provided between the n-type diffusion region 9006 and the n-type diffusion region 9007, the diffusion region 9006 is connected to the diffusion region 9006 via a channel formed under the gate electrode. A current is allowed to flow between the diffusion regions 9007.

  The NROM is a quaternary nonvolatile memory with 2 bits per cell. That is, the NROM can accumulate electrons independently in the portion near the diffusion region 9006 and the portion near the diffusion region 9007 in the nitride film 9003. As a method for injecting (accumulating) electrons into the nitride film, hot electron injection is usually used. Therefore, electrons are independently accumulated in either the nitride film in the vicinity of the diffusion region 9006 or in the vicinity of the diffusion region 9007. be able to. Then, by swapping the source and drain, the side on which electrons are stored can be switched to the opposite side. Therefore, the portion for accumulating charges in the nitride film can be separated into left and right. The accumulated electrons increase the channel resistance during reading. By detecting the change in the current value, stored (accumulated) information can be read. This read operation can also be read independently like writing.

As described above, a single memory cell having a plurality of bits can be created and operated.
JP 2001-156189 A

  However, one of the most important issues of a semiconductor memory device having a plurality of bits in one cell is memory window degradation. Here, the memory window is the difference between the read current at the time of writing and the read current at the time of erasing.

  In consideration of the reliability of the entire memory, when there is a variation in read current among a plurality of memory cells in one chip, it is necessary to consider the total variation, so the memory window is further narrowed. . In addition, in a device having a region where charges are accumulated on the left and right, such as NROM, it becomes difficult to distinguish left and right charges due to miniaturization. That is, the memory window may become narrow due to miniaturization. This issue becomes a more serious problem at the mass production stage. That is, in order to mass-produce a large-capacity semiconductor memory device, that is, a semiconductor memory device having a large number of memory cells, for example, 1 Gb memory of 1 billion, a change in read current due to variations of individual memory cells is allowed. The memory window must be designed to do this.

  In the case of a semiconductor memory device such as an NROM that stores 2-bit information on the left and right sides, the problem of interference between the left and right information must also be considered. In other words, since charges are held separately (separated) on the left and right sides of the nitride film, when reading information on one side, so-called inter-bit interference occurs that interferes with the other information and degrades the read current. . Specifically, when reading the write information on the right side, the read current is deteriorated (increased) when the left side is erased compared to when the left side is written. When reading the erase information, a phenomenon occurs in which the read current deteriorates (decreases) when the left side is written compared to when the left side is erased. Therefore, in the case of a memory device with two bits on the left and right, considering the deterioration of the read current due to interference between these bits, the difference between the read current for writing and erasing on one side when the left and right information are different is narrowed. However, the most severe difference between the write and erase current values must be designed to ensure sufficient reliability as a memory window. In addition, when considered at the mass production level, it is necessary to design the memory window sufficiently large so that it can be read even if the total variation of the memory cells is taken into consideration.

  Accordingly, an object of the present invention is to widen the memory window of memory cells constituting a semiconductor memory device.

In order to solve the above problems, a semiconductor memory device according to the present invention provides:
A gate electrode disposed on the semiconductor layer having the first conductivity type via an insulating film;
A diffusion region having a second conductivity type opposite to the first conductivity type on the semiconductor layer corresponding to both sides of the gate electrode;
A charge storage film having a function of storing charges disposed on the semiconductor layer so as to face the gate electrode through an insulating film;
A region having a lower impurity concentration than the impurity concentration in a region other than the gate electrode side is provided on the gate electrode side of the diffusion region.

  By using the semiconductor memory device having the above structure, the memory window of the semiconductor memory device can be widened. By doing so, the reading operation can be performed satisfactorily, so that the reading speed can be increased. Furthermore, when the semiconductor memory device is a left / right 2-bit device, it is possible to suppress memory window degradation due to inter-bit interference of 2 bits per cell and memory window degradation when mass-producing semiconductor memory devices.

The semiconductor memory device according to one embodiment
The charge storage film can store charges locally.

  By using the semiconductor memory device configured as described above, it is possible to form a left and right 2-bit device in a device having a charge storage film on the entire gate by accumulating injected charges locally in the charge storage film. In addition, since the injected charge in the charge storage film is difficult to move, the steepness on the drain side of the electric field distribution of the channel after pseudo inversion is easily maintained, so that the writing efficiency is good.

The semiconductor memory device according to one embodiment
On the semiconductor layer, a first insulating film, the charge storage film, and a second insulating film are arranged in order from the bottom,
The gate electrode is formed on the second insulating film.

  By using the semiconductor memory device having the above-described configuration, the charge storage film is located immediately below the gate as well as having the same effect as that of the semiconductor memory device having the above-described configuration, thereby contributing to the expansion of the memory window extremely effectively. Further, when the charge storage film extends directly under the gate, the width of the pseudo inversion layer can be set to be extremely long, which contributes to the expansion of the memory window more effectively.

The semiconductor memory device according to one embodiment
The impurity concentration of the semiconductor layer between the diffusion regions has at least a portion higher than a low impurity concentration existing on the gate electrode side of the diffusion region.

  By using the semiconductor memory device having the above-described configuration, not only has the same effect as the semiconductor memory device having the above-described configuration, but also the generation efficiency of hot carriers is increased, so that the writing speed is improved.

The semiconductor memory device according to one embodiment
A counter region having a first conductivity type higher than a low impurity concentration existing on the gate electrode side of the diffusion region is provided between the diffusion regions.

  By using the semiconductor memory device having the above-described configuration, not only has the same effect as the semiconductor memory device having the above-described configuration, but also the generation efficiency of hot carriers is increased, so that the writing speed is improved. Further, since the impurity concentration on the substrate side in the bottom junction of the diffusion region can be lowered, the junction capacitance at the junction surface is reduced, and the operation speed is improved.

The semiconductor memory device according to one embodiment
The diffusion region has a junction depth shallower than that of a region other than the gate electrode side on the gate electrode side.

  By using the semiconductor memory device having the above structure, the junction depth of the portion where the pseudo inversion layer is formed can be formed shallow, so that a current similar to so-called punch-through (current that cannot be controlled by the electric field from the gate) can be suppressed, and the memory Contributes to window enlargement. That is, when the junction depth is deep, even if the diffusion region near the surface of the semiconductor layer is pseudo-inverted by forming a pseudo inversion layer near the surface of the semiconductor layer by the stored accumulated charge, Although the phenomenon that the current does not sufficiently invert and current flows from that portion occurs, it can be suppressed by reducing the junction depth. In this case, it is necessary to make the junction depth shallower than the depth that can be pseudo-inverted. For example, a junction depth of 100 nm or less, preferably 20 nm or less is effective. On the other hand, if it is too shallow, the current driving force before writing decreases, so that it is 5 nm or more, preferably 10 nm or more.

The semiconductor memory device according to one embodiment
A first insulating film, a charge storage film, and a second insulating film are disposed in order from the bottom on the semiconductor layer having the first conductivity type, and a gate electrode is formed on the second insulating film, on both sides of the gate electrode. In a semiconductor memory device including a memory cell having a diffusion region having a second conductivity type opposite to the first conductivity type above the corresponding semiconductor layer,
The effective channel length can be changed in accordance with the amount of charges held in the charge storage film.

  By using the semiconductor memory device having the above structure, the memory window of the semiconductor memory device can be widened. By doing so, the reading operation can be performed satisfactorily, so that the reading speed can be increased. Furthermore, when the semiconductor memory device is a left / right 2-bit device, it is possible to suppress memory window degradation due to inter-bit interference of 2 bits per cell and memory window degradation when mass-producing semiconductor memory devices.

  The memory window of the semiconductor memory device can be widened. By doing so, the reading operation can be performed satisfactorily, so that the reading speed can be increased.

  Furthermore, when the semiconductor memory device is a left / right 2-bit device, it is possible to suppress memory window degradation due to inter-bit interference of 2 bits per cell and memory window degradation when mass-producing semiconductor memory devices.

  Hereinafter, the present invention will be described in detail with reference to the drawings.

(First embodiment)
FIG. 1 is a schematic cross-sectional view of a memory cell 100 constituting a semiconductor memory device according to an embodiment of the present invention, taken along the channel direction. In this memory cell 100, a gate electrode 105 disposed on a semiconductor layer 101 having a first conductivity type via an insulating film (referred to as a first insulating film in this embodiment) 102, and on both sides of the gate electrode 105 A diffusion region (106 and 107) having a second conductivity type opposite to the first conductivity type is provided on the corresponding semiconductor layer 101. On the semiconductor layer 101, a charge storage film 103 having a function of storing charges, which is disposed so as to face the gate electrode 105 and an insulating film (referred to as a second insulating film in this embodiment) 104, and Have Further, on the semiconductor layer 101 side, the diffusion regions (106 and 107) are formed on the gate electrode side region, which has a lower impurity concentration (108 than the impurity concentration on regions other than the gate electrode side (111 and 112)). And 109) to form a semiconductor device.

  In the present application, for the sake of convenience and simplicity, the relatively low concentration diffusion regions (108 and 109) on the gate electrode side are referred to as the low concentration diffusion region, and the relatively high concentration diffusion regions (111 on the other side than the gate electrode side). And 112) may be referred to as a high concentration diffusion region.

  In FIG. 1, the charge storage film 103 extends under the gate electrode and is formed in a film shape over the semiconductor layer 101. However, the charge storage film 103 may be divided in the middle, and is not under the gate electrode. It may be beside the electrode or may be only under the gate electrode. That is, the diffusion region has the above-described configuration, and the effect of the present invention is achieved.

  By having the above characteristic structure, the position of the accumulated charge can be effectively changed for the reasons described later. Therefore, the amount of the source / drain current can be effectively changed in accordance with the amount of accumulated charge as compared with the memory cell not having the above characteristic configuration. In other words, it can be said that the source / drain resistance can be effectively changed. As a result, the memory window can be enlarged. Furthermore, since the amount of charge that can be stored can be dramatically increased, the memory window can be further expanded.

-Outline of conduction levels according to accumulated charge-
Next, according to the configuration of the present embodiment, the memory window is enlarged by moving the injection position of the write charge, but the principle can be explained from various aspects, but one of them will be explained. .

  2 to 4 are diagrams for explaining that the write charge injection position moves. These will be described in order.

  FIG. 2A is a schematic cross-sectional view of a memory cell in a state where there is no injected charge at the moment when a write voltage is applied. For example, the applied voltage is 6 V for the gate electrode, 0 V for one diffusion region 106 (for convenience, here, the left diffusion region; the same applies hereinafter), 6 V for the other diffusion region 107, and 0 V for the semiconductor layer 101. It shall be applied.

  FIG. 3A is a schematic cross-sectional view of the memory cell at the stage where writing is started and electrons of a certain level are injected. The schematically injected electrons are indicated by circles. Although not injected in a row in the horizontal direction as shown in the drawing, it is shown in a horizontal row in order to schematically show that the position where electrons are injected moves in the horizontal direction. The applied voltage is the same as in the case of FIG.

  FIG. 4A is a schematic cross-sectional view of the memory cell in a state where more electrons are injected by further writing from the state shown in FIG. The applied voltage is the same as in the case of FIG.

  2 (b), FIG. 3 (b), and FIG. 4 (b) show the corresponding memory cells (FIG. 2 (a), FIG. 3 (a), and FIG. It is a schematic diagram explaining the lowest level (hereinafter simply referred to as a conduction level) of a conduction band in the vicinity of the interface between the semiconductor layer 101 and the first insulating film 102 in a)). The vertical axis in the figure indicates the energy of electrons, and the horizontal direction is the horizontal position in the corresponding memory cell. The diagram shows the conduction level in the semiconductor layer near the interface between the semiconductor layer of the memory cell and the first insulating film. Since this is a schematic diagram for explanation, there are some differences from reality.

  First, as shown in FIGS. 2A and 2B, when a write voltage is applied, the conduction level at the lower portion of the gate electrode 105 is lowered by the gate voltage to form a channel. . In this state, the conduction level of the channel is lower than the conduction level of the diffusion region 106 and electrons flow from the diffusion region 106 in the channel direction, that is, the transistor is turned on. Further, a reverse bias is applied in the vicinity of the junction between the diffusion region 107 and the channel. Here, since a sufficiently large voltage is applied to the diffusion region 107 for writing, the conduction level in the vicinity of the junction between the diffusion region 107 and the channel has a very steep slope. That is, a high electric field is applied. Due to the high electric field, electrons flowing from the diffusion region 106 into the channel are accelerated and become hot electrons having high energy. Then, hot electrons having energy that jumps over the barrier of the first insulating film 102 are injected into the charge storage film 103. Here, hot electrons are formed in the vicinity of a portion where a high electric field is applied (portion shown by a double-headed arrow in FIG. 2B), and the generated hot electrons are pulled by the gate voltage and charged. It is injected into the storage film 103. Therefore, it is considered that the portion where electrons are injected in the charge storage film 103 is a portion in the vicinity of the portion where a high electric field is applied.

  Next, as shown in FIGS. 3A and 3B, a memory cell in a state where writing is started and a certain level of electrons is injected will be described.

  FIG. 3A schematically shows a state where electrons are injected. FIG. 3B schematically shows that the conduction level is raised by the electrons. That is, as described above, electrons injected in the vicinity of the portion where the high electric field is applied to the charge storage film 103 acts as if a negative voltage is applied by itself, so Raise the rank. By doing so, the conduction level which is the state of FIG. 2B shown in the dotted line in the figure becomes a state shown in the solid line. Along with this, a portion where a high electric field is applied (portion indicated by a double-ended arrow on a solid line) also moves to the right. Along with this, the portion where the electrons are injected in the charge storage film 103 is considered to be a portion near the portion where the high electric field is applied, so the portion where the electrons are injected also moves in the right direction in the drawing. From the above, the PN junction between the diffusion region 107 and the semiconductor layer 101 is substantially moved to the right side, that is, the low concentration diffusion region 109 is depleted or reversed. It can be said that it became such a state. Such a state is said to be pseudo-inverted for convenience. In FIG. 3A, in order to schematically represent the pseudo-inversion state, the portion located under the electrons in the low-concentration diffusion region 109 is illustrated as pseudo-inverted and disappeared.

  Next, as shown in FIGS. 4A and 4B, a memory cell in a state where more electrons are injected by further writing will be described.

  FIG. 4A shows a state where electrons are injected, as in FIG. As a result of further writing, it is shown that electrons are injected toward the right side of the drawing. Accordingly, as shown in FIG. 3A, the low-concentration diffusion region 109 located under the electrons is pseudo-inverted and disappears. As shown in FIG. 4 (b), as in FIG. 3 (b), the portion to which a high electric field is applied (the portion shown by the double-ended arrow of the solid line) further spreads to the right side, and electrons that become hot electrons It can be seen that occurs more extensively. As a result, the position where electrons are injected to the right side becomes wide. However, the reason for the pseudo inversion is that the diffusion region is formed at a sufficiently low concentration. Even if electrons are injected above the high concentration diffusion region 112, the region does not cause the pseudo inversion. Therefore, the electron injection region does not move further to the right. That is, the electron injection range can be limited by the diffusion region formed at a high concentration to the extent that pseudo inversion does not occur.

In the above description, the applied voltage is the same from (a) in FIG. 2 to (a) in FIG. 4. In this case, the write time elapses from (a) in FIG. 2 to (a) in FIG. Explained. That is, by changing the writing time, the writing state can be changed from the writing state of FIG. 2A to the writing state of FIG. 30C. However, the writing state can be changed from (a) in FIG. 2 to (a) in FIG. 4 by changing the applied voltage itself regardless of the passage of time. That is, in the state where electrons are not injected as shown in FIG. 2A, all the nodes are set to 0V or a voltage not to be written, and in the state of FIG. 3A, the gate electrode 105 and the right diffusion region 107 are applied to the right side. 4V is applied or voltage is applied to the lowest level at which writing is possible. In the state of FIG. 4A, 6V is applied to the gate electrode 105 and the right diffusion region 107, or writing can be performed without any problem. The write state can be changed by setting the voltage application state to a certain extent.

  That is, the write voltage is the same, the write level can be changed by changing the write time, and the write level can be changed by changing the write voltage with the same write time. If a sufficient memory window can be obtained at each write level, multi-leveling can be performed for each write level. As described above, in the present invention, the memory window can be dramatically expanded as compared with the prior art, so that multi-leveling for each write level is relatively easy.

―Description of operation―
Next, an operation method of this embodiment, that is, a writing, erasing and reading method will be described. Although an n-type device is described here, it goes without saying that it can be operated as a p-type device if the conductivity type of the impurity and the bias are reversed.

  The writing, erasing and reading operations of the semiconductor memory device of this embodiment may be basically performed in accordance with the documents described in the background art and the writing, erasing and reading methods normally used in this technology. That is, for example, when writing is performed, a positive write voltage such as 6V is applied to the diffusion region 107 shown in FIG. 1, a positive write voltage such as 6V is applied to the gate electrode, and the semiconductor layer 101 and the diffusion region 106 are set to 0V. At this time, an inversion layer is formed under the gate electrode, and electrons flow from the diffusion region 106 to 107. However, when a constant high voltage determined by a device such as 6 V is applied to the diffusion region 107, the electrons increase in the vicinity of the diffusion region 107. Accelerated by the electric field, hot electrons are generated. A part of this hot electron is pulled by the electric field of the gate electrode 105 and moves to the gate electrode side, and is trapped in the charge storage film 103. This accumulated charge is trapped in the charge accumulation film 103 at a portion extending under the gate electrode 105 near the diffusion region 107. As described above, the pseudo-inversion of the low-concentration diffusion region 109 moves the position of the injected electrons in the charge storage film 103 toward the right side of the drawing.

  The reading of this charge (charge accumulated on the diffusion region 107 side by the write operation) is also performed in accordance with the background art and publicly known techniques. This time, the diffusion region 107 is set to 0V, and a positive read voltage such as 2V is applied to the diffusion region 106. Further, when a positive read voltage such as 3 V is applied to the gate electrode 105, electrons flow from the diffusion region 107 to the diffusion region 106. Depending on the amount of accumulated charges, the magnitude of the flow of electrons is also affected by the potential. That is, the amount of accumulated charge can be read as the magnitude of the read current, and this can be used as information storage. Further, as already described, the read current can be further changed by increasing the number of injected electrons by moving the electron injection position and by increasing the pseudo effective channel length by pseudo inversion, so that the memory window is very large. Memory cells can be provided.

  On the other hand, when writing, when a positive voltage is applied to the diffusion region 106 and 0 V is applied to the diffusion region 107 contrary to the above, the gate electrode 105 lower portion on the left side of the page, that is, near the diffusion region 106, contrary to the above. Charges are trapped in the charge storage film 103 in the vicinity of the vicinity.

  This left-side charge readout is detected as the magnitude of the current flowing between the diffusion regions 106 to 107 by applying 0V to the diffusion region 106, a positive voltage of 2V to the diffusion region 107, and a positive voltage of 3V to the gate electrode, for example. The In this case, the amount of charge accumulated on the left side greatly affects the magnitude of the current, but the amount of charge accumulated on the right side does not significantly affect the magnitude of the current. The background art describes that the inversion layer in the vicinity is pinched off by the positive voltage applied to the diffusion region 107 on the right side of the drawing when reading. However, this explanation is an explanation from one side. Specifically, the electric field in the vicinity of the PN junction to which the reverse bias is applied is a high electric field, and the conduction level is raised by the stored electrons. However, it is possible to explain that the high electric field cannot be canceled, and it is not the drain side potential gap but the source side potential that has a dominant influence on the transistor threshold voltage. The explanation of a gap can also be used.

  Conversely, when reading the right charge amount, by applying a positive voltage to the left diffusion region 106, the left charge amount is ignored and the right charge amount information is reflected mainly in the current amount.

  In other words, according to the above-described method, by reversing the reading directions, the presence / absence of accumulated charge on the left side and the presence / absence of accumulated charge on the right side can be taken out individually, and 2-bit information is stored in one device. be able to.

  In the case of erasing, as in the background art, for example, when a negative erasing voltage such as −6 V is applied to the gate electrode 105 and a positive erasing voltage such as 6 V is applied to the right diffusion region 107 and the semiconductor layer 101 is set to 0 V, charge accumulation is performed. The electrons accumulated on the right side of the film can be erased. At this time, some electrons flow from the valence band of the semiconductor layer to the conduction band of the diffusion region 107 by interband tunneling, and are further accelerated by an electric field to collide with silicon atoms in the semiconductor layer 101 to cause hot holes and hot electrons. Generate a pair. A part of the hot hole is pulled by the electric field of the gate electrode 105 and enters the charge storage film 103 to cancel the stored charge. As a result, only the charge accumulated on the right side can be erased. In the case of erasing the left accumulated charge, a positive voltage is applied to the left diffusion region 106.

  In the case of erasure, as in the case of writing, the region where the hot hole / hot electron pair is generated moves to the right side as electrons are written due to the above-described pseudo long channel, The written electrons can be erased sequentially from the right side.

  From the above, it can be seen that, unlike the prior art, there are the following effects. That is, in a conventional memory cell, it is considered that electrons and holes that are not canceled remain in the write / erase cycle, but the injection position of electrons and holes can be moved as in the present invention, that is, injection. In a memory cell in which the absolute number of charged charges can be dramatically increased compared to the prior art, even if electrons and holes that are not canceled remain, they are canceled and positive. The number is very small compared to the number of holes, and moreover, it extends over a portion that hardly affects the read current at both ends of the charge storage portion. Therefore, in the memory cell of the present invention, it is possible to suppress deterioration in reliability in the write / erase cycle due to uncancelled electrons and holes, or deterioration in reliability related to retention.

-Detailed explanation of each part-
As described above, the diffusion regions (106 and 107) are regions having the second conductivity type formed on the semiconductor layer 101 corresponding to both sides of the gate electrode 105. In the diffusion regions (106 and 107), the diffusion regions (108 and 109) having a lower impurity concentration than the regions (111 and 112) other than the gate electrode side on the gate electrode side, and other than the gate electrode side There are relatively high concentration diffusion regions (111 and 112).

  Generally, a diffusion region structure of a MOSFET (transistor) device having a low concentration diffusion region inside such a high concentration diffusion region is sometimes referred to as LDD (lightly doped drain) or the like. However, the LDD used in the transistor and the low-concentration diffusion region of the present application require completely different effects, and therefore there are differences in configuration. This will be described below.

  In general, the reason why LDD is used in a MOSFET is to suppress the short channel effect that occurs with the miniaturization of elements. That is, this is a technique for suppressing deterioration typified by current variations that occur when the channel length is shortened.

  Therefore, the impurity concentration of the LDD region aims at relaxing the electric field at the PN junction between the diffusion region and the channel region. On the other hand, the larger the electric field at the PN junction between the diffusion region and the channel region of the present application, the better. This is because HCI (hot carrier injection) is used to inject charges into the charge storage section. Therefore, increasing the impurity concentration of the semiconductor layer or forming a counter region contributes to improvement in performance. However, general LDD is not preferable because the effect of LDD is reduced.

  In addition, since the purpose is different from that of LDD, the difference in configuration is raised.

  LDD is more effective as it is shallower for miniaturization, but the low-concentration diffusion region of this application is effective if it is shallow enough to form a pseudo inversion layer. There is a difference in the range of playing. In the low concentration diffusion region of the present application, for example, a junction depth of 100 nm or less, preferably 20 nm or less is effective. On the other hand, if it is too shallow, the current driving force before writing is lowered, so that it is 5 nm or more, preferably 10 nm or more.

  For miniaturization, it is desirable to design the LDD with the smallest possible overlap width with the gate electrode. However, the low-concentration diffusion region of this application is designed to have the largest possible overlap width. Is desirable. This is because the width of the pseudo inversion region is increased and the amount of stored charge can be increased. It is known that the lateral diffusion of the normal diffusion layer is about 60% of the depth in terms of the size. Furthermore, the device which suppresses the horizontal direction diffusion is made | formed for miniaturization. On the other hand, in the low concentration diffusion region of the present application, the lateral diffusion (that is, the lateral entry width from the implantation mask when forming the gate electrode or the low concentration diffusion region) should be 70% or more of the depth. It is desirable to form using oblique implantation. Of course, if the approach width is long and both sides are in contact with each other, the channel disappears, which is inconvenient, so it is necessary to limit the length to less than half of the gate length at the maximum.

  Furthermore, since the LDD has a low impurity concentration, it usually becomes a parasitic resistance in the MOSFET. Therefore, it is desirable that the offset width between the gate electrode and the n + diffusion layer is as narrow as possible. However, in the present application, due to the characteristics of the semiconductor memory element, priority is given to the enlargement of the memory window, so that the offset width between the gate electrode and the high-concentration diffusion region (but needs to face the charge storage film) is wide. May be. For example, the offset width may be 2 nm or more, more preferably 5 nm or more. However, if it is too wide, the driving current will be extremely lowered, which is inconvenient. Therefore, this offset width may be designed within a maximum range of 40 nm. More desirably, the design is made in the range of 25 nm.

  When the semiconductor memory device and the logic normal transistor are mixedly mounted as in the present embodiment, the low-concentration diffusion region can naturally be used as the LDD of the normal transistor. However, it is necessary to consider the optimum device scaling considering each characteristic, and in this case, the optimum scale may be different from the case of the semiconductor memory device alone.

-Explanation of effects-
By having the above structure, the position of accumulated charges can be effectively changed. Therefore, the amount of the source / drain current can be effectively changed in accordance with the amount of accumulated charge as compared with the memory cell not having the above characteristic configuration. Thereby, the memory window can be widened. In other words, it can be said that the source / drain resistance can be effectively changed in accordance with the amount of accumulated charge.

  In this semiconductor memory device, the impurity concentration in the diffusion region is preferably in the following range. That is, the impurity concentration in the main diffusion region is preferably 1E17 or more and 5E20 or less. The reason is that at 1E17 or higher, the drive current does not deteriorate due to the parasitic resistance, so that high-speed reading can be realized. Moreover, if it is 5E20 or less, it can be formed by a normal transistor manufacturing process, so cost deterioration can be prevented.

The impurity concentration in the low-concentration diffusion region is very preferably about 2 × 10 ¹⁶ cm ⁻³ or more and about 4 × 10 ¹⁸ cm ⁻³ or less. The reason is that it can be formed thinner than the impurity concentration of the diffusion region that is normally used, so that the effect of pseudo inversion when electrons are accumulated in the charge storage film becomes significant, and the read current is greatly changed. Because it will be possible. On the other hand, if it is too thin, the reading current when electrons are not accumulated is reduced, which is not good. Therefore, the above range is most desirable. Furthermore, 1 × 10 ¹⁴ cm ⁻³ to 1 × 10 ²⁰ cm ⁻³ is preferable. This is because the impurity concentration must be higher than the impurity concentration of the semiconductor layer in the vicinity of the low concentration diffusion region, and must be adjusted to be lower than that of the high concentration diffusion region. is there.

  It should be noted that the low-concentration diffusion region and the high-concentration diffusion region are not only clearly demarcated as shown in the figure, but are merely illustrated in this manner for convenience in the present application. In other words, as described in FIG. 1 above, the gate electrode side is configured to have a region having an impurity concentration lower than that of the region other than the gate electrode side (even if there is no clear boundary). The effects of the present invention can be achieved. That is, it may be a case where it cannot be clearly distinguished due to a gradual change in density, or it may be a case where there is a part having the above configuration.

  For example, as in the memory cell shown in FIG. 8, in the diffusion region on the gate electrode side, the vicinity of the semiconductor layer surface (shallow portion) is a low concentration diffusion region, but the region away from the semiconductor layer surface (deep portion). Otherwise, it is included in the above configuration, and of course the same effect as described above can be obtained. More specifically, in the diffusion region on the gate electrode side, the vicinity of the surface of the semiconductor layer (shallow portion) has a lower concentration than the region other than the gate electrode side, but the portion away from the surface of the semiconductor layer (deep portion) ) Is the same when the concentration is high. On the contrary, the vicinity of the semiconductor layer surface (shallow portion) has a higher concentration than the region other than the gate electrode side, but the portion away from the semiconductor layer surface (deep portion) has a low concentration. Sometimes it doesn't mean that it doesn't work immediately.

  In the present application, for the sake of simplicity, a low concentration diffusion region is similarly formed from a shallow portion to a deep portion on the gate electrode side, and has a clear boundary, and the portion other than the gate electrode side has a uniform high concentration diffusion region. Although the description will be made with reference to the drawings as formed, the above-described various aspects of the structure are included.

  Here, illustration of element isolation regions, interlayer insulating films, wirings (electrodes, contact plugs), etc. provided on the semiconductor layer is omitted, but a known technique is used unless otherwise specified. That's fine.

  In general, an impurity diffusion region in which impurities are diffused and activated is used as the diffusion region.

  However, this region may be partially made of a material that promotes electrical conduction because it is necessary to establish electrical connection with wiring or the like. The material that promotes electrical conduction is a substance composed of a metal such as metal or silicide and a semiconductor and other substances that promote electrical conduction. Therefore, the diffusion region may be made of a material that conducts electricity. Note that in the case of designing for the purpose of miniaturization and low power consumption, a structure having a region made of a material that promotes electrical conduction is preferable because the performance is improved.

  Although the diffusion region is illustrated as being entirely covered with the first insulating film, the charge storage film, and the second insulating film, it is not necessary to be completely covered with these films. In other words, the charge storage film only needs to be disposed so as to cover a region where normal charge can be stored, that is, a region where charges are injected, and need not be disposed over the entire diffusion region.

  Note that all the drawings are only schematic explanatory diagrams, and unless otherwise specified, the dimensions (dimension ratios) of the drawings are not accurate with respect to size, film thickness, shape, and other design matters.

There are several reasons why the source / drain current amount can be effectively changed as follows. (A) The absolute amount of accumulated charge can be increased effectively. That is, since the accumulated charge density depends on the physical properties of the charge accumulation film, such as the trap density, the amount of charge that can be accumulated in a certain region naturally has a limit value. However, by effectively changing the position where charges are accumulated, the region where charges can be accumulated can be effectively expanded, so that the absolute amount of accumulated charges can be effectively increased. (B) The effective channel length can be changed effectively. That is, when electrons are accumulated in the charge storage film on the drain side, for example, on the diffusion region 107 side in FIG. 1, the low concentration diffusion region 109, which is a relatively low concentration diffusion region below the stored electrons, The conduction level which is the energy level at the bottom of the conduction band is pushed up. In other words, the channel / drain pn junction surface on the drain side has been pseudo-moved to the drain side, so that it can be considered that an inversion layer has been effectively formed. Therefore, the pseudo effective channel length becomes long, and the amount of source / drain current can be reduced. A schematic relational expression between the pseudo effective channel length Lquasi and the source / drain current Id is shown and described below.
The source / drain current Id is expressed by the following equation (degradation equation of the channel) by depletion approximation in a general MOS transistor.

  Here, W is the gate width, μ is the mobility of electrons (holes), C is the gate insulating film capacitance, Vg is the gate voltage, Vt is the threshold voltage, and Vd is the drain voltage. Since this phenomenon is a peculiar phenomenon in a general MOS transistor, various explanations can be given, but here, it will be explained as follows. That is, in formula (1), W, μ, C, Vg, and Vd are constant for simplicity. Here, C mainly indicates the capacitance per unit area between the gate electrode under the gate electrode and the channel. The accumulation of electrons on the drain side of the charge storage film changes the capacitance at the drain end. However, since C is the average value of the entire channel, it is considered that the change in the capacitance at the drain end has little effect on the average of the entire channel, and is considered constant. Further, Vth is considered to be constant because it is a value mainly related to the source-side source / channel junction. From the above, Id = const / Lquasi is derived from the above (1). Therefore, the current value Id decreases as the pseudo effective channel length Lquasi increases. In other words, the reason why the source / drain current value decreases due to the accumulation of electrons is thought to be because the effective channel length Leff increases.

-Production method-
Next, a method for manufacturing the semiconductor memory device of the first embodiment will be described with reference to FIG. Although an n-channel type memory cell is described here, it goes without saying that it can be applied to a p-channel type memory cell by appropriately changing the impurity type.

  First, as shown in FIG. 5A, on a silicon substrate 1101 having a p-type conductivity type, a first insulating film 1102 (currently a pre-processed film that is merely formed on the entire surface, The desired first insulating film can be finally obtained by processing the film, but the word “film used for” is not added in consideration of simplicity of explanation and understanding. There are some differences in the shape and film thickness from the finally obtained film (this is the same for all the following films), and the charge storage film 1103 and the second insulating film 1104 are formed in order. To do. Then, a gate electrode 1105 is formed over the second insulating film 1104. Although a silicon substrate having a general element isolation region is used as the semiconductor layer 101 here, a silicon-germanium substrate or the like may be used, or a semiconductor layer (eg, a silicon layer) provided over a glass substrate is used. Any other material that can turn on / off the channel according to the gate voltage may be used.

  Here, the first insulating film 1102 was obtained by thermally oxidizing the surface of the semiconductor layer 101. The film thickness is preferably about 1 nm to 10 nm, and is 5 nm here. In addition to the thermal oxide film, the film material may be a CVD oxide film, a high dielectric material film, a radical oxidized oxide film, or the like, or a combination thereof. A silicon nitride film is used as the charge storage insulating film 1103, but other materials such as aluminum oxide and hafnium oxide may be used, or an insulating film containing a plurality of fine dots capable of storing charge (silicon oxide film) Etc.), or a combination of these films. In this embodiment using a silicon nitride film, the film thickness is 1 nm to 15 nm, for example, 5 nm. In particular, when the film is thinned, there is an advantage that the stored charge is suppressed by suppressing the lateral diffusion of the accumulated charge. Here, the second insulating film 1104 is a CVD oxide film and has a thickness of 8 nm, for example. Here, in addition to the CVD oxide film, the surface of the silicon nitride film can be thermally oxidized to obtain an oxide film, or a high dielectric material film can be used. A combination of these films may be used. When the silicon nitride film surface is thermally oxidized, a part of the surface of the silicon nitride film is consumed as an oxide film. Therefore, the consumption by oxidation is reduced so that a silicon nitride film having a desired film thickness remains finally. An overlaid silicon nitride film is formed. Polysilicon is used for the gate electrode 1105. All the films described above can be formed by a known thermal oxidation method or CVD method.

  Next, as shown in FIG. 5B, the gate electrode 1105 is formed by processing the gate electrode 1105 into a desired shape using a known lithography and dry etching process. In the present embodiment, the dry etching here may be performed by stopping the etching with the second insulating film 1104 and leaving a film below this.

Next, in order to form the low concentration diffusion regions (1108 and 1109), arsenic ions are implanted with an implantation energy of about 15 keV and an implantation amount of about 1 × 10 ¹⁴ cm ⁻² .

  Here, the implantation energy should be freely adjusted so that the extension diffusion regions 1108 and 1109 have a desired junction depth, and the lower limit and the upper limit are technically feasible without any trouble in operating as a MOS transistor. As long as it can be adjusted freely. However, it may be in the range of about 5 keV to about 50 keV, and is most preferably implanted in the range of about 10 keV to 20 keV. The reason is that by implanting with this energy, a junction depth of about 10 nm to 50 nm can be formed, so that it can be formed shallower than the junction depth of the diffusion region that is normally used. This is because the effect of pseudo inversion due to accumulation becomes remarkable, and the read current can be changed greatly. On the other hand, if it is too shallow, the read current when electrons are not accumulated is reduced, which is not good.

  Further, it is preferable to increase the width of the low-concentration diffusion region by performing an oblique implantation of about 30 to 60 degrees during the implantation so that the above-described effects can be obtained.

The injection amount may be an appropriate amount in the range of about 1 × 10 ^{12 to} 5 × 10 ¹⁶ cm ⁻² , and the injection amount is in the range of about 2 × 10 ¹³ cm ⁻² to 4 × 10 ¹⁴ cm ^−2. This is most desirable. The reason is that, if the implantation amount is within this range, the impurity concentration can be formed to about 2 × 10 ¹⁶ cm ⁻³ to 4 × 10 ¹⁸ cm ⁻³ , so that it is thinner than the impurity concentration of the diffusion region normally used. This is because, since it can be formed, the effect of pseudo inversion when electrons are stored in the charge storage film becomes remarkable, and the read current can be changed greatly. On the other hand, if it is too thin, the reading current when electrons are not accumulated is reduced, which is not good. Therefore, the above range is most desirable. However, this implantation amount must be such that the impurity concentration formed by this implantation is higher than the impurity concentration of the semiconductor layer in the vicinity of the implantation region, and is thinner than the diffusion region formed later. It is necessary to adjust to.

  Further, although this step is not essential and is not shown, the second insulating film 1104 other than just below the gate electrode 105 may be removed by wet etching after the above step. Since the surface of the second insulating film 1104 other than directly under the gate electrode 105 may be damaged by plasma of etching species or damage due to implantation during gate etching, the gate can be improved in improving the reliability as a memory device. It is preferable to remove the second insulating film 1104 other than directly under the electrode 105.

  Next, as shown in FIG. 5C, sidewall spacers 1120 and 1121 made of an insulator having a thickness of about 70 nm are formed on the side surface of the gate electrode. Since the later high concentration diffusion region can be offset from the gate electrode by this side wall spacer, the thickness of the side wall spacer may be adjusted so that the offset amount becomes appropriate. If the offset amount is too small, the width of the low concentration diffusion region is narrowed and the width of the charge injection region is narrowed, so that the memory window is narrowed. On the other hand, if the offset amount is too large, it becomes difficult for the gate electrode to pull the charge effectively at the time of writing, the injection efficiency is deteriorated, and the write / erase speed at that portion is deteriorated. The film thickness may be about 20 nm to 200 nm.

  This can be done by forming an insulating film such as a silicon oxide film on the entire surface of the substrate by CVD and then forming it by etch back, or by thermally oxidizing the surface of the gate electrode. You can also get In particular, the latter method is simple and has the advantage of reducing the manufacturing cost, and the latter method is adopted here.

Next, a diffusion region forming step is performed. In the diffusion region forming step in the present embodiment, the first insulating film 1102 and the charge storage film 1103 remaining on the silicon layer surface are used as they are as an injection protection film, and a CVD oxide film or the like is further formed thereon. It may be deposited to adjust the implantation protective film thickness. Further, after removing the charge storage film 1103 exposed on the surface and the first insulating film 1102 therebelow, a new implantation protective film may be formed by thermal oxidation or deposition of a CVD oxide film. After that, for example, arsenic ions whose energy is controlled to 50 keV are implanted at an area density of 5 × 10 ¹⁵ cm ⁻² , and the surface of the semiconductor layer 101 and the gate electrode 105 are doped with arsenic ions that are n-type impurities. To do. At this time, the gate electrode 1105 and the side wall spacers 1120 and 1121 function as an implantation mask. Thereafter, annealing (for example, RTA treatment at 1050 ° C. for 10 seconds) is performed in a nitrogen atmosphere, and an activation process of the implanted ions is performed.

  In this way, as shown in FIG. 5C, the n-type diffusion region 1106 as an example of the second conductivity type is formed in the silicon substrate 1101 so as to be substantially bilaterally symmetric about the gate electrode 1105 on the paper surface. An n-type diffusion region 1107 is formed. During this annealing, arsenic ions enter the lower part of the side wall spacers (1120 and 1121) due to the lateral diffusion of arsenic ions in the silicon, and a part of the high concentration diffusion regions (1111 and 1112) are side wall spacers (106). And 107) are extended downward, and a part of the low-concentration diffusion regions (1108 and 1109) extend below the gate electrode 1105. By appropriately setting the annealing conditions, the end of the high concentration diffusion region (1111 and 1112) (the junction with the p-type of the silicon substrate) is positioned under the side wall spacer (1120 and 1121), and the high concentration diffusion is performed. Low-concentration diffusion regions (1108 and 1109) can be left between the regions (1111 and 1112) and the gate electrode 1105.

Note that a halo implantation step may be performed before the annealing step. In this case, before or after the arsenic ion implantation step, boron, which is a p-type impurity whose energy is set to 20 to 60 keV, is implanted at a dose smaller than the arsenic dose (for example, when forming a high concentration diffusion region). (If the area density is about 1 × 10 ¹³ to 1 × 10 ¹⁴ cm ⁻² ), implantation is performed at an angle of 15 ° to 45 ° with respect to the vertical direction, and an implantation mask (gate electrode or sidewall spacer) Then, boron is implanted into the lower portion of the substrate and then annealed to form a halo region having a high concentration of p-type impurity boron (not shown) in the vicinity of the end of each diffusion region. By forming the halo region, it is possible to provide a semiconductor device in which excessive diffusion of each diffusion region is suppressed and the shape of each diffusion region is stable. In addition, since the electric field applied to the PN junction between the diffusion region and the halo region when a write voltage or the like is applied can be increased, the write / erase efficiency can be improved and the speed can be improved.

By the above steps, the p-type region which is the first conductivity type was originally the entire silicon substrate 1101, but the first region is obtained by forming the diffusion regions (1106 and 1107) in the silicon substrate 1101. Of course, the p-type region which is a conductive type is reduced to a non-diffusion region where the diffusion regions (1106 and 1107) in the silicon substrate 1101 are not formed.

The device structure of the first embodiment is obtained through the above steps. Here, if necessary, the insulating film above the gate electrode 1105 and the charge storage film 1103 exposed on the surface may be removed by etching.

(Second Embodiment)
FIG. 6 is a schematic cross-sectional view of the memory cell 200 constituting the semiconductor memory device which is an embodiment of the semiconductor memory device of the present invention, cut along the channel direction. Since the memory cell 200 is the same as the memory cell 100 shown in the first embodiment except for the configuration of the characteristic part described later, the description of the same part will be omitted here, and only the characteristic part will be described. That is, the memory cell 200 is characterized by having at least a portion where the impurity concentration of the semiconductor layer 213 between the diffusion region 106 and the diffusion region 107 is higher than the impurity concentration of the semiconductor layer 101.

  According to the semiconductor memory device having the above characteristics, the potential gradient of the PN junction between the drain and the channel becomes steep and hot carriers are likely to be generated. Therefore, the write / erase speed is increased. For the same reason, writing at a lower voltage is possible, and a reduction in voltage can be achieved.

  As an example of the actual structure, as shown in FIG. 6, a reverse conductivity type region 214 having a conductivity type opposite to that of the diffusion region may be formed.

As an example of the manufacturing method, it is formed by performing ion implantation that forms a conductivity type opposite to that of the diffusion region in the step before forming the gate electrode 1105 in FIG. 5B described in the first embodiment. For example, boron ions may be implanted with an implantation energy of 40 keV and an implantation amount of about 1 × 10 ¹³ cm ⁻² .

  Here, the amount of implantation is not particularly limited as long as a reverse conductivity type region having an appropriate concentration can be formed in the vicinity of the junction on the gate side of the diffusion region (106 and 107). Note that the appropriate impurity concentration may be higher than the impurity concentration of the semiconductor layer 101 and thinner than the low concentration diffusion regions (108 and 109). Further, even if it has a darker portion than the low concentration diffusion region, it is good as long as the vicinity of the junction of the low concentration diffusion region has a lower concentration than the low concentration diffusion region and a desired low concentration diffusion region shape can be formed.

  The design of the implantation energy is the same. That is, the implantation energy is not limited as long as the reverse conductivity type region having an appropriate concentration can be formed in the vicinity of the junction on the gate side of the diffusion region (106 and 107). Note that the appropriate impurity concentration is most preferably higher than the impurity concentration of the semiconductor layer 101 and thinner than the low concentration diffusion regions 108 and 109. Further, even if it has a darker portion than the low concentration diffusion region, it is good as long as the vicinity of the junction of the low concentration diffusion region has a lower concentration than the low concentration diffusion region and a desired low concentration diffusion region shape can be formed.

  Note that the wording “having at least a portion” is added to indicate that the above structure does not mean that the impurity concentration of the entire region between the diffusion region 106 and the diffusion region 107 is high. In addition, it is clear from the following technical common sense that the overall impurity concentration may not be high. That is, the semiconductor layer 213 between the diffusion region 106 and the diffusion region 107 includes a region closest to the interface with the first insulating film 102. In the region closest to the interface, the concentration changes by an order of magnitude depending on both the material constituting the interface and the substance that becomes an impurity. Therefore, the impurity concentration in the region closest to the interface does not affect the effect of the present embodiment. Therefore, the impurity concentration in the region closest to the interface deviates from the above concentration condition. Even if it is, it is included in this embodiment.

Needless to say, the effects of the first embodiment can also be achieved.

(Third embodiment)
FIG. 7 is a schematic cross-sectional view of a memory cell 300 constituting a semiconductor memory device according to an embodiment of the present invention, cut along the channel direction. The memory cell 300 is the same as the memory cell 100 shown in the first embodiment except for the configuration of the characteristic portion described later. Therefore, the description of the same configuration is omitted here, and only the characteristic portion is described. . That is, the memory cell 300 is characterized in that it has a counter region 314 between the diffusion region 106 and the diffusion region 107, which is higher in impurity concentration than the semiconductor layer 101 and has a conductivity type opposite to that of the diffusion region.

  The present embodiment can be said to be very similar to the second embodiment in that a certain impurity concentration between the diffusion regions is a structural requirement. However, the difference from the configuration of the second embodiment is that the counter region is As shown in the figure, it does not exist so much around the lower part of the high concentration diffusion region. That is, in the configuration of the second embodiment, in order to increase the impurity concentration of the constant region 213 between the diffusion regions, the impurity concentration of the semiconductor layer 101 near the region 213 is also increased. Therefore, since the impurity concentration of the semiconductor layer under the diffusion region (106 and 107) also becomes high, the PN junction capacitance in that portion increases. Further, since the region 213 has an impurity concentration between the diffusion region 106 and the diffusion region 107 that is almost uniformly set to a high concentration, it is difficult to adjust the threshold voltage as a MOS transistor. This embodiment solves these problems. That is, by setting the desired region between the diffusion region 106 and the diffusion region 107 to a constant high concentration, the junction capacitance of the PN junction under the diffusion region 106 and the diffusion region 107 can be reduced, so that high-speed operation ( Writing, erasing, reading, and so on) are possible, and the threshold voltage as a MOS transistor can be easily adjusted, so that a highly functional semiconductor memory device can be provided.

  Here, the counter region 314 may be arranged in any manner between the diffusion region 106 and the diffusion region 107, and may be arranged so as to be separated into right and left as shown in the figure. In some cases, they are placed between them. The shape does not necessarily have to be symmetrical.

  The manufacturing method having the above configuration is, for example, as follows.

After the formation up to the gate electrode 1105 of FIG. 5B shown in the first embodiment, the energy is 20 before or after the arsenic ion implantation step for forming the low concentration diffusion regions (1108 and 1109). Boron, which is a p-type impurity set to ˜60 keV, with a dose smaller than the dose of arsenic (for example, about 1 × 10 ¹³ to 1 × 10 ¹⁴ cm ⁻² when implanted at the time of forming a high concentration diffusion region) By implanting at an angle between 45 ° and 70 ° with respect to the vertical direction and implanting boron into the lower portion of the implantation mask (gate electrode and sidewall spacer), and then annealing. A counter region having a high boron concentration is formed near the end of each diffusion region. By forming the counter region, it is possible to provide a semiconductor device in which excessive diffusion of each diffusion region is suppressed and the shape of each diffusion region is stable. In addition, since the electric field applied to the PN junction between the diffusion region and the counter region when a write voltage or the like is applied can be increased, the write / erase efficiency can be improved and the speed can be improved.

  Needless to say, the effects of the first embodiment and the second embodiment can be similarly achieved.

(Fourth embodiment)
FIG. 8 is a schematic cross-sectional view of the memory cell 400 constituting the semiconductor memory device according to the embodiment of the present invention cut along the channel direction. Since this memory cell 400 is the same as the memory cell 100 shown in the first embodiment except for the configuration of the characteristic part described later, only the characteristic part will be described here. That is, the memory cell 400 has low concentration diffusion regions (408 and 409) having a shallow junction depth compared to the junction depth of the high concentration diffusion regions (111 and 112) on the gate electrode side of the diffusion region. Features.

  By having this characteristic structure, the memory window can be widened. That is, when the junction depth is not a constant shallow depth as in this configuration, even if the diffusion region near the semiconductor layer surface is pseudo-inverted by the accumulated charge, the deep diffusion region is not sufficiently pseudo-inverted, May cause current to flow. However, this phenomenon can be suppressed by setting a certain shallow junction depth. Therefore, since the source / drain current can be effectively reduced when electrons are accumulated, the memory window can be widened and the read reliability can be increased. For example, a junction depth of 100 nm or less, preferably 20 nm or less is effective. On the other hand, if it is too shallow, the current driving force before writing is lowered, so that it is 5 nm or more, preferably 10 nm or more.

(Fifth embodiment)
FIG. 9 is a schematic cross-sectional view of a memory cell 1300 constituting a semiconductor memory device according to an embodiment of the present invention, taken along the channel direction. The memory cell 1300 is the same as the memory cell 100 shown in the first embodiment except for the configuration of the characteristic part described below. Therefore, the description is omitted here, and only the characteristic part is described. That is, the memory cell 1300 is characterized in that the charge storage film 1303 is on the side wall portion of the gate electrode 1305 and may be sandwiched between the insulating film 1302 and the insulating film 1304. Therefore, the charge storage film is separated on the left and right sides of the gate electrode, and there is no difficulty in 2-bit separation due to the closeness of the stored charge, so that the 2-bit separation can be easily performed, and the gate insulating film 1320 is formed thin. Therefore, it is superior to the above device in that it can be easily miniaturized. The merits resulting from the above characteristic structure are described in Japanese Patent No. 3683895 which is patented for the similar characteristic structure. That is, the effect produced by the characteristic structure described in Japanese Patent No. 3683895 naturally occurs also in this embodiment. In addition, in the present invention, the effects obtained in the above-described embodiment can be obtained as much as possible in terms of configuration.

  In this embodiment, since the width of the charge storage film is limited, the following unique configuration can be defined. That is, since the low concentration diffusion region (1309 and 1308) is located under the charge storage film, it has a pseudo-inversion effect. Therefore, the low concentration diffusion region extends under the charge storage film as much as possible. It is desirable to do.

  Further, it is desirable that the low concentration diffusion regions (1309 and 1308) and the low concentration diffusion region which is not pseudo-inverted are offset when they are offset from the gate electrode. Naturally, it is desirable that the high concentration diffusion regions (1311 and 1312), that is, the entire diffusion regions (1306 and 1307) are offset from the gate electrode.

1 is a schematic cross-sectional view showing a semiconductor memory device according to a first embodiment of the present invention. It is a figure explaining the outline | summary of the conduction level according to a stored charge. It is a figure explaining the outline | summary of the conduction level according to a stored charge. It is a figure explaining the outline | summary of the conduction level according to a stored charge. It is a schematic sectional drawing which shows the manufacturing method of 1st Embodiment of this invention. It is a schematic sectional drawing which shows the semiconductor memory device of 2nd Embodiment of this invention. It is a schematic sectional drawing which shows the semiconductor memory device of 3rd Embodiment of this invention. It is a schematic sectional drawing which shows the semiconductor memory device of 4th Embodiment of this invention. It is a schematic sectional drawing which shows the semiconductor memory device of 5th Embodiment of this invention. 1 is a diagram showing a conventional semiconductor memory device.

Explanation of symbols

100, 200, 300, 400 Memory cell 101 Semiconductor layer 102 First insulating film 103 Charge storage film 104 Second insulating film 105 Gate electrode 106, 107 Diffusion region 108, 109 Low concentration diffusion region 111, 112 High concentration diffusion region 213 Diffusion Semiconductor layer between region 106 and diffusion region 107 214 Reverse conductivity type region 314 Counter region

Claims (11)

A gate electrode disposed on the semiconductor layer having the first conductivity type via an insulating film;
A diffusion region having a second conductivity type opposite to the first conductivity type on the semiconductor layer corresponding to both sides of the gate electrode;
A charge storage film having a function of storing charges disposed on the semiconductor layer so as to face the gate electrode with an insulating film interposed therebetween;
A semiconductor memory device comprising: a region having a lower impurity concentration than that of a region other than the gate electrode side on the gate electrode side of the diffusion region. The semiconductor memory device according to claim 1,
A semiconductor memory device characterized in that the charge storage film can locally store charges. The semiconductor memory device according to claim 1,
On the semiconductor layer, a first insulating film, the charge storage film, and a second insulating film are arranged in order from the bottom,
A semiconductor memory device, wherein the gate electrode is formed on the second insulating film. The semiconductor memory device according to claim 1,
The semiconductor memory device according to claim 1, wherein the impurity concentration of the semiconductor layer between the diffusion regions has at least a portion higher than a low impurity concentration existing on the gate electrode side of the diffusion region. The semiconductor memory device according to claim 1,
A semiconductor memory device having a counter region having a first conductivity type higher than a low impurity concentration existing on the gate electrode side of the diffusion region between the diffusion regions. The semiconductor memory device according to claim 1,
A semiconductor memory device having a junction depth shallower than that of a region other than the gate electrode side on the gate electrode side of the diffusion region. The semiconductor memory device according to claim 1,
A semiconductor memory device, wherein the amount of current flowing from the one diffusion region to the other diffusion region can be changed in accordance with the amount of charge held in the charge storage film. The semiconductor memory device according to claim 1,
A semiconductor memory device characterized in that an effective channel length can be changed in accordance with the amount of charges held in the charge storage film. The semiconductor memory device according to claim 1,
A semiconductor memory device, wherein a junction depth of a region having a lower impurity concentration than that of a region other than the gate electrode side existing on the gate electrode side of the diffusion region is 5 nm or more and 100 nm or less. The semiconductor memory device according to claim 1,
The overlap width between the gate electrode and the region having a low impurity concentration compared to the impurity concentration in the region other than the gate electrode side existing on the gate electrode side of the diffusion region is 70% or more of the junction depth of the region, A semiconductor memory device characterized by being less than half of the electrode length. The semiconductor memory device according to claim 1,
The offset width between the gate electrode and a region having a relatively high impurity concentration other than the gate electrode side of the diffusion region in the semiconductor layer facing the charge storage film via an insulating film is 2 nm or more and 40 nm or less. There is provided a semiconductor memory device.

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