KR102032221B1 - Capacitorless 1t dram cell device using tunneling field effect transistor, fabrication method thereof and memory array using the same - Google Patents
Capacitorless 1t dram cell device using tunneling field effect transistor, fabrication method thereof and memory array using the same Download PDFInfo
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- KR102032221B1 KR102032221B1 KR1020150157129A KR20150157129A KR102032221B1 KR 102032221 B1 KR102032221 B1 KR 102032221B1 KR 1020150157129 A KR1020150157129 A KR 1020150157129A KR 20150157129 A KR20150157129 A KR 20150157129A KR 102032221 B1 KR102032221 B1 KR 102032221B1
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Abstract
The present invention forms a lower source region with an impurity of a type opposite to that of the source region and the same type as the drain region in the lower portion of the source region, and a potential well is formed under the body region between the lower source region and the drain region. The present invention provides a 1T DRAM cell device using a tunneling field effect transistor, which has a potential well in a body region like a 1T DRAM cell device using a structure, and can be operated like a TFET, a method of manufacturing the same, and a memory array using the same.
Description
The present invention relates to a semiconductor memory device, and more particularly, to a 1T DRAM cell device using a tunneling field effect transistor without a capacitor, a method of manufacturing the same, and a memory array using the same.
Currently, a commercial DRAM (DRAM) is composed of a cell device that records one bit of information using one transistor and one capacitor (1T / 1C), and there is a difficulty in minimizing the capacitor as well as the transistor during the miniaturization process. High integration has been limited.
Therefore, recently, researches on 1T DRAMs in which a cell capable of storing one bit of information with only one transistor without a capacitor have been actively conducted. Compared with the existing 1T / 1C DRAM cells, the 1T DRAM cell has the advantage of being easy to be miniaturized, fast operating speed, and easy to integrate into the CMOS process, thereby reducing the production cost.
In the conventional 1T DRAM cell device, as shown in FIG. 1, sources /
However, since the conventional DRAM cell device as shown in FIG. 1 uses the structure and operating principle of the MOSFET, there is a fundamental limitation in further minimizing the DRAM cell. As the temperature increases, the read current and the leakage current in the idle state increase very much. Because of this, there is a limit that stable operation is difficult.
Meanwhile, in the field of logic devices, as shown in FIG. 2, a tunneling field effect transistor (TFET) having an asymmetric structure in which the
The present inventor has received Korean Patent No. 10-1085155 for the first time suggesting that the TFET can be used as a 1T DRAM cell device away from the switching device.
However, the patent allows a potential well to be formed in the body by inserting the isolation semiconductor region between the source or drain region and the body region, thereby requiring a new formation of the isolation semiconductor region. In addition, when the respective regions are stacked vertically, one cell element occupies an area of 4F 2 , and thus high integration is possible, but a manufacturing process is not easy.
Accordingly, the present invention proposes a structure using a lower portion of the body as a potential well by doping with impurities of the same type as the drain region in the lower portion of the source region according to a conventional TFET manufacturing process, thereby having a structure of TFET instead of the conventional MOSFET. 1T DRAM cell device using tunneling field effect transistor that overcomes limitations of MOSFET reduction by replacing 1T DRAM cell device, operates at lower voltage than MOSFET, and enables stable operation even at high temperature by band-to-band tunneling. It is an object of the present invention to provide a manufacturing method and a memory array using the same.
In order to achieve the above object, the 1T DRAM cell device according to the present invention comprises: a source region and a drain region formed by being doped with impurities of opposite types to a semiconductor substrate at a predetermined distance; A body region in which a channel is formed between the source region and the drain region; A gate formed on the body region with a gate insulating layer interposed therebetween; A lower source region formed below the source region opposite to the source region and doped with impurities of the same type as the drain region; A bottom insulating film formed under the lower source region, the body region and the drain region; And a potential well formed to be electrically isolated from the lower portion of the body region between the lower source region and the drain region.
The source region is a P-type impurity high concentration doping layer (P + region), the lower source region and the drain region are an N-type impurity high concentration doping layer (N + region), and the body region is P doped at a lower concentration than the source region. It may be a type impurity low concentration doping layer (P region), or may be formed by being doped with impurities having opposite conductivity types, respectively.
The potential well may be electrically isolated by side insulating films formed on both sides of the body region and the drain region or by side insulating films formed on both sides of the source region, the lower source region, the body region, and the drain region. Can be.
The semiconductor substrate may be a silicon-on-insulator (SOI) substrate, and the bottom insulating layer may be a buried oxide layer of the SOI substrate.
The gate may have a shape of one of a finFET, a triple-gate, and a gate-all-around (GAA).
A method of manufacturing a 1T DRAM cell device according to the present invention includes a first step of defining an active region by etching a semiconductor substrate and forming a side insulating film; Forming a gate insulating film on the active region; Forming a gate on the gate insulating film; A fourth step of forming a drain region by forming an ion implantation shielding layer on the gate insulating layer and the gate, and then opening only one side of the gate to form an implant region having an impurity having a first conductivity type; And forming an ion implantation shielding layer on the gate insulating layer and the gate, and then opening only the other side of the gate to form an impurity implantation having the first conductivity type, the second conductivity type opposite to the lower source region and the first conductivity type. And a fifth step of forming source regions with different implantation energies by impurity implantation.
The semiconductor substrate is a silicon-on-insulator (SOI) substrate, and the etching of the semiconductor substrate and the formation of the side insulating layer in the first step are performed in the fifth step except for the lower source region and the source region. It can be formed to be electrically isolated from the.
In the memory array according to the present invention, a plurality of 1T DRAM cell elements are arranged, wherein the semiconductor substrate is a silicon-on-insulator (SOI) substrate, the bottom insulating film is a buried oxide film of the SOI substrate, A back bias contact and a back bias line are formed on one side to apply a voltage to the lower silicon layer of the SOI substrate, and the potential well of each 1T DRAM cell device is controlled through the back bias line.
In the memory array according to the present invention, a gate of each of the 1T DRAM cell elements arranged in a column direction is formed of a word line, and a drain region of each of the 1T DRAM cell elements arranged in a row direction is connected to the word line through a contact plug. The source region of each of the 1T DRAM cell elements connected to a vertical bit line is formed as a common source line in parallel with the word line in a column direction.
The lower source region of each of the 1T DRAM cell elements may be formed as an integral conductive line in parallel with the word line in the column direction, thereby controlling the potential well of each of the 1T DRAM cell elements.
The present invention forms a lower source region with an impurity of a type opposite to that of the source region and the same type as the drain region in the lower portion of the source region, and a potential well is formed under the body region between the lower source region and the drain region. By having a potential well in the body region like a 1T DRAM cell device using a structure, the operation can be performed like a TFET, overcoming the limitations of the cell shrinkage of the MOSFET, and operating at a lower voltage than the MOSFET. Band tunneling enables the realization of a 1T DRAM cell device capable of stable operation even at high temperatures. The manufacturing process can also use a conventional TFET process and can simplify array wiring.
1 is a cross-sectional view showing the structure of a 1T DRAM cell device using a conventional MOSFET.
2 is a cross-sectional view illustrating a structure of a conventional tunneling field effect transistor (TFET).
3 is a cross-sectional view illustrating a structure of a 1T DRAM cell device according to an embodiment of the present invention.
4 is a cross-sectional view illustrating a case in which impurity conductivity types of a source region, a lower source region, a body region, and a drain region are reversed in the embodiment of FIG. 3.
FIG. 5 is an electrical characteristic diagram comparing the concentration of holes (holes) accumulated in the potential well according to the information storage state in the embodiment of FIG. 3.
6 is an electrical characteristic diagram comparing potentials of a substrate according to concentrations of holes accumulated in a potential well according to an information storage state in the embodiment of FIG. 3.
7 is an electrical characteristic diagram comparing energy band diagrams of a channel surface according to an information storage state in the embodiment of FIG. 3.
FIG. 8 is an electrical characteristic diagram comparing band-to-band tunneling ratio of electrons on a channel surface according to an information storage state in the embodiment of FIG. 3.
9 is an electrical characteristic diagram comparing retention characteristics according to an information storage state in the embodiment of FIG. 3.
10 to 14 are cross-sectional views illustrating a process of manufacturing a 1T DRAM cell device according to the embodiment of FIG. 3.
FIG. 15 is a layout illustrating an example of a memory array in which a 1T DRAM cell device is a unit cell according to the exemplary embodiment of FIG. 3.
FIG. 16 is a cross-sectional view illustrating the array cut along the line AA ′ in FIG. 15.
FIG. 17 is a cross-sectional view illustrating the array cut vertically along the line BB ′ in FIG. 15.
FIG. 18 is a cross-sectional view illustrating the array cut along the line CC ′ in FIG. 15.
19 is a cross-sectional view illustrating the array cut along the line DD ′ in FIG. 15.
Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention.
1T DRAM cell device according to an embodiment of the present invention, as shown in Figure 3, the
The core technical idea of the present invention is to form the
3, the
The embodiment of FIG. 4 reverses the conductivity of each region in the embodiment of FIG. 3 so that the source region 20 'is an N-type impurity high concentration doping layer (N + region), and the lower source region 10' and the drain region. 40 'is a P-type impurity high concentration doping layer (P + region), and the body region 30' is formed of an N-type impurity low concentration doping layer (N region) doped at a lower concentration than the source region 20 '. It can also be implemented as a 1T DRAM cell device operating as a channel TFET.
In each of the embodiments described herein, including the embodiments of FIGS. 3 and 4, the
Thus, in the embodiments of FIGS. 3 and 4, the
3 and 4, the
When the
The bottom insulating
The
FIG. 18 is a cross-sectional view of an array, which is vertically cut along a line CC ′ of FIG. 15, as described below. FIG. 15 is a unit cell of a 1T DRAM cell device according to the embodiment of FIG. 3. This is a layout showing an example of a memory array referred to as A).
FIG. 16 is a cross-sectional view of the array vertically cut along the AA ′ line in FIG. 15, FIG. 17 is a cross-sectional view of the array vertically cut along the BB ′ line in FIG. 15, and FIG. 19. A cross-sectional view of the array showing vertical cut along line DD 'at 15.
Referring to FIG. 16, it can be seen that the unit cell A of the memory array has a structure according to the embodiment of the above-described 1T DRAM cell device.
15 to 19, both side surfaces of the
The
According to an embodiment of the memory array described below, the
In this case, the
The
Referring to FIGS. 15 and 16, the memory array including the 1T DRAM cell device as the unit cell A according to the embodiment of FIG. 3 is a word line of the
The memory array may be formed on one SOI substrate, and as described above, the buried
In this case, the
When the
In the embodiment of FIG. 16, since the
15 to 19, both side surfaces of the
Although not shown in the drawings, an embodiment of another memory array including the 1T DRAM cell device of the present invention as the unit cell A, as described above, the
In the latter embodiment, the
3 and 16, the basic operation principle of the 1T DRAM cell device of the present invention will be briefly described.
The basic operation principle is to change the electric potential of the channel surface in accordance with the amount of charge stored in the isolated
<Write '1' action>
When a negative voltage (eg, -3.0 V) is applied to the
<Hold operation>
It is to retain holes before the read (read) or write '0' operation after the holes are trapped in the
<Read operation>
This is to check whether holes are stored in the
<Write '0' action>
Since the holes stored in the
After storing the information of '0' and '1' by the above method, and comparing the states of each cell during the read operation, there is a difference in the electrical characteristics as shown in FIGS. That is, as shown in FIG. 5, when the information of '1' is stored, a lot of holes are accumulated in the
As a result, as shown in FIG. 7, the potential of the channel surface increases together under the influence of the positive charge stored in the
Next, referring to FIGS. 10 to 14, a method of manufacturing the 1T DRAM cell device according to the exemplary embodiment of FIG. 3 will be briefly described.
First, as shown in FIG. 10, the semiconductor substrate is etched and a side insulating film (not shown) is formed to define the active region 31 (first step). In this case, the
Next, as shown in FIG. 11, a
Next, after forming an ion implantation shielding layer (not shown) on the
Subsequently, as shown in FIG. 13, an ion implantation shielding layer (not shown) is formed on the
The fourth step and the fifth step may be performed in reverse order. In the fifth step, the order of forming the
The rest of the process is according to the manufacturing method of the 1T DRAM cell device of the MOSFET, so the description thereof will be omitted.
1: bottom silicon layer of SOI substrate 2: bottom insulating film (burying oxide film)
3: semiconductor substrate (top silicon layer of SOI substrate) 10, 10 ': bottom source region
20, 20 ':
31:
40, 40 ': drain region 50: gate insulating film
60: gate (word line) 82, 84, 86: contact plug
90: insulating film 100: source line
120: back bias line 200: bit line
Claims (14)
A body region in which a channel is formed between the source region and the drain region;
A gate formed on the body region with a gate insulating layer interposed therebetween;
A lower source region formed below the source region opposite to the source region and doped with impurities of the same type as the drain region;
A bottom insulating film formed under the lower source region, the body region and the drain region; And
A potential well formed to be electrically isolated from a lower portion of the body region between the lower source region and the drain region,
The potential well is electrically isolated from the lower source region and the drain region by a pn junction, but is formed of an impurity of the same type as the source region and electrically connected thereto.
And the lower source region is formed of an integral conductive line to be electrically connected to cells arranged in one direction to control the potential well by voltage application.
The source region is a P-type impurity high concentration doping layer (P + region),
The lower source region and the drain region are N-type impurity high concentration doping layer (N + region),
And the body region is a P-type impurity low concentration doping layer (P region) doped at a lower concentration than the source region.
The source region is an N-type impurity high concentration doping layer (N + region),
The lower source region and the drain region are P-type impurity high concentration doping layer (P + region),
And the body region is an N-type impurity low concentration doping layer (N region) doped at a lower concentration than the source region.
And the potential well is electrically isolated by side insulating films formed on both sides of the body region and the drain region.
The semiconductor substrate is a silicon-on-insulator (SOI) substrate,
And the bottom insulating film is a buried oxide film of the SOI substrate.
And the gate has a shape of one of finFET, triple-gate and gate-all-around (GAA).
Forming a gate insulating film on the active region;
Forming a gate on the gate insulating film;
A fourth step of forming a drain region by forming an ion implantation shielding layer on the gate insulating layer and the gate, and then opening only one side of the gate to form a drain region by impurity implantation having a first conductivity type opposite to the active region; And
After forming an ion implantation shielding layer on the gate insulating film and the gate, only the other side of the gate is opened, and impurity implantation having the first conductivity type is opposite to the lower source region and the first conductivity type and is the same as the active region. And a fifth step of forming source regions with different implantation energies by impurity implantation having a second conductivity type.
Forming a gate insulating film on the active region;
Forming a gate on the gate insulating film;
A fourth step of forming a drain region by forming an ion implantation shielding layer on the gate insulating layer and the gate, and then opening only one side of the gate to form a drain region by impurity implantation having a first conductivity type opposite to the active region; And
After forming an ion implantation shielding layer on the gate insulating film and the gate, only the other side of the gate is opened, and impurity implantation having the first conductivity type is opposite to the lower source region and the first conductivity type and is the same as the active region. A fifth step of forming source regions with different implantation energies by impurity implantation having a second conductivity type,
The semiconductor substrate is a silicon-on-insulator (SOI) substrate,
The etching of the semiconductor substrate and the formation of the side insulating layer in the first step may be performed to electrically isolate the neighboring cell except for the lower source region and the source region in the fifth step. Manufacturing method.
The gates of each of the 1T DRAM cell elements arranged in the column direction are formed of word lines,
The drain region of each of the 1T DRAM cell elements arranged in a row direction is connected to a bit line perpendicular to the word line through a contact plug,
And the source region of each of the 1T DRAM cell elements is formed as a common source line in parallel with the word line in a column direction.
And a lower source region of each of the 1T DRAM cell elements is formed as an integral conductive line in parallel with the word line in a column direction.
And a potential well of each of the 1T DRAM cell elements through the conductive line.
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US7719054B2 (en) * | 2006-05-31 | 2010-05-18 | Advanced Analogic Technologies, Inc. | High-voltage lateral DMOS device |
KR101286704B1 (en) * | 2011-09-15 | 2013-07-16 | 서강대학교산학협력단 | Transistor having fixed charge layer in box and fabrication method thereof |
KR101576267B1 (en) * | 2013-12-12 | 2015-12-09 | 서강대학교산학협력단 | Esaki Tunneling Assisted Tunnel Field-Effect Transistor |
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