KR20090039111A - Manufacturing method of one transistor type dram - Google Patents

Abstract

A manufacturing method of one transistor type DRAM is provided to prevent surface damage of a drain by forming a contact plug contacted with a metal wiring of an island shape formed on a top of a drain of a transistor. A gate(112) is formed on a top of an active region of a silicone layer(104). A gate spacer(114) is formed on both side walls of the gate. A source region(116a) and a drain region(116b) are formed inside an active region of both sides of a gate by performing a source/drain ion injection process. An LDD region(118) is formed inside an active region of both sides of the gate by performing an LDD(Lightly Doped Drain) ion injection process. An insulation film(120) is formed on a top of a whole surface. A first contact hole is formed by selectively etching the insulation film. A material film for a metal wiring is formed on a top of the insulation film including the first contact hole. Metal wirings(124a,124b) contacted in the source region and the drain region are formed by selectively etching the material film for the metal wiring. An insulation film(126) is formed on a top of the whole surface. A second contact hole is formed by selectively etching the insulation film. A contact plug(130) is formed by filling a conductive film on the second contact hole. A bit line(132) is formed on the contact plug and the insulation film.

Description

Manufacturing method of 1-transistor type DRAM {MANUFACTURING METHOD OF ONE TRANSISTOR TYPE DRAM}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a 1-transistor type DRAM. In particular, in a 1-transistor type DRAM structure, two transistors share one source and a bit line passes over an active region, thereby reducing cell size. It is a technology that can.

A typical device for a semiconductor memory device is DRAM. In general, a DRAM is composed of one transistor and one capacitor to form one unit cell.

Digital data 1 (= high) or 0 (= low) is stored in the capacitor, and in order to maintain the level of data stored in the capacitor normally, the DRAM has a predetermined time interval and refreshes the data recharging operation. refresh). The DRAM having such a unit cell has been developed to a synchronous semiconductor memory device called a DDR series (DDR (Double Data Rate SDRAM) series).

However, as DRAM density increases to Giga level, the chip area will have to be increased. This will be a burden for the system, which is advantageous as the size of the chip becomes smaller.

In particular, the capacitor constituting the unit cell forms a height of the lower electrode of 2 μm or more in order to increase the capacitance of the capacitor, and uses a high dielectric constant material. As a result, there is a difficulty in patterning the capacitor and the leakage current is increased.

In addition, the conventional unit cell structure has a limitation in that the DRAM device has a structure of 6F2 or less because the bit line is disposed to pass over the device isolation layer instead of the upper portion of the active region.

The present invention has the following object.

First, the 1-transistor DRAM can be implemented to simplify the process and reduce the chip height by eliminating the capacitor process.

Secondly, two transistors share one source, and the bit line can be arranged to pass over the active region, thereby reducing the cell size.

Third, an island-type metal wiring is formed on the drain of the transistor, and a contact plug for connecting the island-type metal wiring is formed to connect the drain and the bit line to lower the height of the contact plug to facilitate the process. The purpose is to prevent surface damage.

A method of manufacturing a 1-transistor type DRAM according to the present invention includes forming first and second gates over an active region of a substrate; Forming a common source region in an active region between the first and second gates, and forming a drain region in an active region outside the first and second gates; Forming first and second metal interconnections over the structure, the first and second metal interconnects respectively connecting to the common source and drain regions; And forming a bit line connected to the second metal wire on the second metal wire.

The present invention provides the following effects.

First, the 1-transistor DRAM can be implemented to simplify the process and reduce the chip height by eliminating the capacitor process.

Second, the two transistors share a single source, and the bit line is arranged to pass over the active region, thereby reducing the cell size.

Third, an island-type metal wiring is formed on the drain of the transistor, and a contact plug for connecting the island-type metal wiring is formed to connect the drain and the bit line to lower the height of the contact plug to facilitate the process. Provides the effect of preventing surface damage.

In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range

Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention.

1A to 1F are cross-sectional views illustrating a method of manufacturing a 1-transistor type DRAM according to a first embodiment of the present invention.

As shown in FIG. 1A, a silicon on insulator (SOI) wafer 106 is formed of a stacked structure of a silicon substrate 100, an insulating film 102, and a silicon layer 104. In the silicon layer 104 of the SOI wafer 106, an isolation layer 110 defining an active region 108 is formed to contact the insulating layer 102. Here, the insulating film 102 is preferably formed of an oxide film.

Next, a gate 112 is formed over the active region of the silicon layer 104. Next, gate spacers 114 are formed on both sidewalls of the gate 112. Here, the gate 112 is formed in a direction perpendicular to the SOI wafer 106, and two gates 112 are preferably formed on one active region 108.

As shown in FIG. 1B, a source / drain ion implantation process is performed to form a source region 116a and a drain region 116b in the active region 108 at both sides of the gate 112.

Here, the source / drain ion implantation process is preferably performed using any one selected from N-type impurities such as phosphorus (P), arsenic (As), and combinations thereof. The source region 116a is preferably formed in the active region 108 between the two gates 112, and the drain region 116b is formed in the edge portion of the active region 108.

Next, an LDD (Lightly Doped Drain) ion implantation process is performed to form the LDD region 118 in the active region 108 on both sides of the gate 112.

Here, the LDD ion implantation process is preferably performed by giving a tilt so that the LDD region 118 is formed on both sides of the source / drain regions 116a and 116b. In addition, the LDD ion implantation process may be performed using the same impurities as the source / drain ion implantation process or using other impurities, but using an impurity concentration and ion implantation energy lower than that of the source / drain ion implantation process. .

As shown in FIG. 1C, an insulating film 120 is formed over the entire surface. Next, the insulating layer 120 is selectively etched to form first contact holes 122 exposing the source / drain regions 116a and 116b.

Here, after the insulating film 120 is formed, the planarization process for the insulating film 120 may be further performed. In this case, the planarization process may be preferably performed by chemical mechanical polishing (CMP).

As shown in FIG. 1D, a material film (not shown) for metal wiring is formed on the insulating layer 120 including the first contact hole 122. Next, the material film for metal wiring is selectively etched to form the metal wiring 124a connected to the source region 116a, and at the same time, the metal wiring 124b connected to the drain region 116b is formed.

Here, the metal wires 124a are formed to connect the source regions 116a between the two gates 112 to each other, and preferably formed in a line shape in a direction parallel to the gates 112. . In addition, the ground voltage VSS is applied to the metal line 124a so that a current path is formed from the source region 116a to the drain region 116b during the transistor operation.

The metal wire 124b serves as a contact plug for connecting the bit line and the drain region 116b to be formed in a subsequent process, and is preferably formed in an island form on the drain region 116b. . Here, the metal wiring 124b is preferably formed in a rectangular or square shape.

In addition, the metal wire 124b serves as a buffer. That is, when the bit line and the drain region 116b to be formed in a subsequent process as in the prior art are directly connected with one contact plug, the height of the insulating layer to be etched is high, so that the line width decreases toward the bottom of the contact hole, and the drain region 116b. ) Surface damage is added.

However, when the metal wiring 124b is formed first and the contact plugs are connected to the metal wiring 124b as the second embodiment to connect the bit line and the drain region 116b, the height of the insulating layer to be etched. The low width ensures the line width of the contact hole. Therefore, the contact plug can be formed large, and the contact resistance is reduced. Accordingly, it is possible to increase the current flow of the transistor to improve the operation speed of the device.

As shown in FIG. 1E, an insulating film 126 is formed over the entire surface. Next, the insulating layer 126 is selectively etched to form a second contact hole 128 exposing the metal wiring 124b. Here, in the etching process for forming the second contact hole 128, the metal wiring 124b serves as a buffer to prevent damage to the surface of the drain region 116b, and the height of the insulating layer to be etched is low. Line width can be secured.

Next, as shown in FIG. 1F, a contact plug 130 is formed by filling a conductive film in the second contact hole 128. Next, the bit line 132 is formed on the contact plug 130 and the insulating layer 126. Here, the bit line 132 may be formed of any one selected from a material having a low resistance, such as aluminum, copper, tungsten, and a combination thereof, in order to increase the sensing margin.

As described above, the DRAM cell implemented in the SOI wafer 106 may have a threshold voltage of a transistor depending on the degree of trapping of holes in the floating body 134 corresponding to the channel region under the gate 112. Vt) is changed. When the threshold voltage Vt changes, the amount of current flowing from the source region 116a to the drain region 116b varies.

For example, when holes are trapped in the floating body 134, the threshold voltage Vt of the transistor is lowered. Then, the amount of current flowing from the source region 116a to the drain region 116b is increased to enter the data " 1 " storage state.

On the other hand, when the holes stored in the floating body 134 are released, the threshold voltage Vt of the transistor is increased. Then, the amount of current flowing from the source region 116a to the drain region 116b is reduced to enter the data " 0 " storage state.

This operation is performed by the voltage applied to the source / drain regions 116a and 116b. In other words, when the ground voltage VSS is applied to the source region 116a and a positive voltage is applied to the drain region 116b, holes are captured in the floating body 134 by an electric field. When a ground voltage VSS is applied to the source region 116a and a negative voltage is applied to the drain region 116b, a forward bias is formed between the drain region 116b and the floating body 134 to release holes. Will be.

Meanwhile, the amount of current flowing from the source region 116a to the drain region 116b varies according to the voltage level applied to the bit line 132 during the read operation.

For example, when a voltage having a level lower than the threshold voltage Vt of the transistor is applied to the bit line 132, holes are trapped in the floating body 134, thereby lowering the electric field. At this time, a voltage having a level lower than the positive voltage is applied to the drain region 116b.

As a result, electrons move from the source region 116a to the drain region 116b to increase the amount of current. Then, the voltage of the bit line 132 drops to a level lower than that of the reference voltage and data "0" is read.

On the other hand, when a voltage having a level higher than the threshold voltage Vt of the transistor is applied to the bit line 132, the electric field becomes high. As a result, the amount of current flowing from the source region 116a to the drain region 116b is reduced. Then, the voltage of the bit line 132 becomes higher than the reference voltage, and data "1" is read.

 2A to 2E are cross-sectional views illustrating a method of manufacturing a 1-transistor type DRAM according to a second embodiment of the present invention.

As shown in FIG. 2A, the silicon on insulator (SOI) wafer 206 has a stacked structure of a semiconductor substrate 200, an insulating film 202, and a silicon layer 104. In the silicon layer 204 of the SOI wafer 206, the device isolation layer 210 defining the active region 208 is formed to contact the insulating layer 202. Here, the insulating film 202 is preferably formed of an oxide film.

Next, a gate 212 is formed over the active region of the silicon layer 204. Next, gate spacers 214 are formed on both side walls of the gate 212. Here, the gate 212 is formed in a direction perpendicular to the SOI wafer 206, and it is preferable to form two gates 212 on one active region 208.

A source / drain ion implantation process is then performed to form the source region 216a and the drain region 216b in the active region 208 on both sides of the gate 212.

Here, the source / drain ion implantation process is preferably performed using any one of N-type impurities such as phosphorus (P), arsenic (As), and a combination thereof. The source region 216a is preferably formed in the active region 208 between the two gates 212, and the drain region 216b is formed in the edge portion of the active region 208.

Next, an LDD (Lightly Doped Drain) ion implantation process is performed to form the LDD region 218 in the active region on both sides of the gate 212.

Here, the LDD ion implantation process is preferably performed by giving a tilt so that the LDD region 218 is formed on both sides of the source / drain regions 216a and 216b. In addition, the LDD ion implantation process may be performed using the same impurities as the source / drain ion implantation process or using other impurities, but using an impurity concentration and ion implantation energy lower than that of the source / drain ion implantation process. .

Next, an insulating film 220 is formed over the entire surface. Next, the insulating layer 220 is selectively etched to form first contact holes 222 exposing the source / drain regions 216a and 216b.

Here, after the insulating film 220 is formed, the planarization process for the insulating film 220 may be further performed. In this case, the planarization process may be preferably performed by chemical mechanical polishing (CMP) method.

As shown in FIG. 2B, a first contact plug 224 is formed by filling a conductive film in the first contact hole 222.

Here, the first contact plug 224 may be formed of any one selected from tungsten, aluminum, copper, polysilicon, and a combination thereof. In addition, silicon may be formed in the first contact hole 222 by a selective epitaxial growth process. In this case, the selective epitaxial growth process may use a vapor phase epitaxial growth method, a liquid phase epitaxial growth method, and a molecular epitaxial growth method, and among these, it is preferable to use a vapor phase epitaxial growth method.

As shown in FIG. 2C, metal wires 226a and 226b are formed on the first contact plug 224.

Here, the metal lines 226a are formed to connect the source regions 216a between the two gates 212 to each other. The metal lines 226a may be formed in a line shape in a direction parallel to the gates 212. In addition, the ground voltage VSS is preferably applied to the metal line 226a so that a current path is formed from the source region 216a to the drain region 216b during the transistor operation.

In addition, the metal wiring 226b serves as a contact plug for connecting the bit line to be formed in the subsequent process and the drain region 216b, and is preferably formed in an island shape only on the drain region 216b. Here, the metal wiring 226b is preferably formed in a rectangular or square shape.

Meanwhile, the metal wire 226a and the metal wire 226b may be separated and formed in a separate process. This is because when the process margin is insufficient, when the metal wires 226a and 226b are formed at the same time, the edge portions of the metal wires 226b may be excessively etched to reduce the size of the metal wires 226b.

As shown in FIG. 2D, an insulating film 228 is formed over the entire surface. Next, the insulating layer 228 is selectively etched to form a second contact hole 230 exposing the metal wiring 226b.

Here, during the etching process for forming the second contact hole 230, the metal wiring 226b serves as a buffer to prevent surface damage from being applied to the drain region 216b, and the height of the insulating layer to be etched is low. Line width can be secured.

Next, as shown in FIG. 2E, a second contact plug 232 is formed by filling a conductive film in the second contact hole 230. Next, a bit line 234 is formed on the second contact plug 232 and the insulating layer 228. Here, the bit line 234 may be formed of any one selected from a material having a low resistance such as aluminum, copper, tungsten, and a combination thereof to increase the sensing margin.

1A to 1F are cross-sectional views illustrating a method of manufacturing a 1-transistor type DRAM according to a first embodiment of the present invention.

 2A to 2E are cross-sectional views illustrating a method of manufacturing a 1-transistor type DRAM according to a second embodiment of the present invention.

Claims (15)

Forming first and second gates over the active region of the substrate; Forming a common source region in the active region between the first and second gates, and forming a drain region in the active region outside the first and second gates; Forming first and second metal interconnections on the structure to connect with the common source and drain regions, respectively; And Forming a bit line on the second metal wire to connect with the second metal wire Method of manufacturing a 1-transistor type DRAM comprising a. The method of claim 1, wherein the substrate has an SOI structure including a silicon substrate, an insulating film, and a silicon layer. The method of claim 1, further comprising forming gate spacers on both sidewalls of the first and second gates after forming the first and second gates, respectively. . 2. The method of claim 1, wherein the source and drain regions comprise LDD regions. The method of claim 4, wherein the LDD region forming process is performed by a gradient ion implantation process. The method of claim 1, wherein the forming of the first and second metal wires is performed. Forming a first insulating film over the entire surface; Etching the first insulating layer to form a first contact hole exposing the common source and drain regions; Forming a first material film for metallization on the first insulating film including the first contact hole; And Selectively etching the first material layer for the metallization to form the first and second metallizations Method of manufacturing a 1-transistor type DRAM comprising a. The method of claim 1, wherein the forming of the first and second metal wires is performed. Forming a second insulating film over the entire surface; Etching the second insulating layer to form a second contact hole exposing the common source and drain regions; Filling a second conductive hole in the second contact hole to form a first contact plug; Forming a second material film for metal wiring on the second insulating film; And Selectively etching the second material layer for metal wiring to form the first and second metal wirings Method of manufacturing a 1-transistor type DRAM comprising a. The method of claim 7, wherein the first contact plug is formed of any one of tungsten, aluminum, copper, polysilicon, and a combination thereof. 8. The method of claim 7, wherein the first contact plug is formed by an epitaxial growth process. 10. The method of claim 9, wherein the epitaxial growth process is performed by a vapor phase epitaxial growth method. The method of claim 1, wherein the first metal wiring is formed in a line shape in a direction parallel to the first and second gates. 12. The method of claim 11, wherein the second metal wiring is formed in an island shape. 13. The method of claim 12, wherein the island shape is rectangular or square. The method of claim 1, wherein the bit line is formed above the active region in a direction perpendicular to the first and second gates. The method of claim 1, wherein the bit line is connected to the second metal wiring through a second contact plug.

Images