KR101147523B1 - 1t dram device having split gate structure and dram array using the same - Google Patents

Abstract

The present invention relates to a semiconductor memory device and a memory array using the same, and more particularly, to a 1T DRAM device having a split gate structure with one transistor without a capacitor and a DRAM array using the same.

Description

1T DRAM device having split gate structure and DRAM array using the same {1T DRAM DEVICE HAVING SPLIT GATE STRUCTURE AND DRAM ARRAY USING THE SAME}

The present invention relates to a semiconductor memory device and a memory array using the same, and more particularly, to a 1T DRAM device having a split gate structure with one transistor without a capacitor and a DRAM array using the same.

A conventional DRAM device (DRAM device or DRAM memory cell) has a structure of 1T / 1C composed of one transistor and one capacitor, which is complicated to form a capacitor and embeds a memory chip together with other devices. There is a limit to forming chips and high integration.

Thus, in order to solve the problem of the 1T / 1C DRAM device, a 1T DRAM device having a transistor structure without a capacitor has been recently developed (Korean Patent Nos. 10-0860744 and 10-0945508, and Korean Patent Publication No. 10-2008-A). 0064001).

The 1T DRAM device stores the excess holes generated by impact ionization in the floating body as is known, and uses the data that the threshold voltage and the current level of the transistor vary according to the amount of holes stored in the floating body. Will be recorded or read.

By the way, although the 1T DRAM device does not need to make a capacitor, there is an advantage that the process is simple and the integration can be easily improved. However, the reason why the 1T / 1C DRAM device cannot be replaced is that there is a problem in hole retention characteristics. .

That is, the 1T DRAM device has a problem in that the holes stored in the floating body disappear due to recombination with time, and thus the hole retention time is shortened.

FIG. 1 is a view illustrating a problem of the 1T DRAM device, and FIG. 1 (a) shows the source 3 and the drain 4 at both sides for forming the floating body 2 on the buried oxide film 1. Example 5 shows a structure of a conventional 1T DRAM device, which is formed (reference numeral 5 denotes a junction region of a depletion layer formed between a source / drain and a body) and a gate 7 is formed between the gate insulating film 6 on an active region. 1 (b) is an energy band diagram for intuitively showing a problem of inflow and outflow (recombination) of holes caused by the application of a voltage (bias) to the gate 7 of FIG.

In FIG. 1 (a), when a large negative bias is applied to the gate 7 to hold a hole stored in the floating body 2, as shown in FIG. 1 (b), the GIDL ( The excess holes are introduced into the floating body by the gate induced drain leakage current, and as a result, as shown in FIG. 2, the retention time of the data '0' is reduced.

On the contrary, if the negative bias applied to the gate at the time of holding is reduced to prevent the generation of the GIDL current, as shown in FIG. 1 (b), the ability of the gate to hold a hole decreases. As a result, as shown in FIG. There is a problem that the retention time of data '1' is reduced by recombination.

Therefore, the conventional 1T DRAM device has a problem that it is impossible to find an optimal hold bias condition that can structurally improve the retention time of the data '1' and the data '0' state.

Accordingly, the present invention has a center gate and a split gate structure with side gates on one side or both sides of the center gate and the center gate to solve the problems of the conventional 1T DRAM device. It is an object of the present invention to provide a 1T DRAM device having a split gate structure capable of separately controlling energy bands of respective portions by allowing different biases to be applied to side gates.

In addition, the present invention solves the problem of forming a contact between the center gate and the side gate for each DRAM device, and can improve the integration characteristics as well as device characteristics, and can be manufactured as a bulk substrate instead of an SOI substrate. Another object is to provide a 1T DRAM device and a DRAM array using the same.

In order to achieve the above object, the 1T DRAM device having a split gate structure according to the present invention comprises an electrically isolated semiconductor body; Source and drain formed on both sides of the semiconductor body; A center gate formed on the semiconductor body with a gate insulating film interposed therebetween; And one or two side gates formed on the semiconductor body with a separation insulating film interposed between one or both sides of the center gate.

In addition, each side gate has at least one end formed on a depletion junction region formed between the source and the semiconductor body or between the drain and the semiconductor body. do.

The semiconductor body has a vertical pillar shape, the source and the drain are formed on both sides of the pillar, and the center gate and each side gate are formed on at least one side surface of the pillar between the isolation insulating layers. The first side gate / center gate / the second side gate, the first side gate / center gate or the center gate / the second side gate in the vertical stacking in the order characterized in that formed.

In addition, the pillar has a horizontal cross section having a rectangular or circular shape, and the center gate and each side gate are formed to surround the sides of the pillar, which is another feature of the 1T DRAM device having a split gate structure according to the present invention.

The pillar may be formed by vertically etching a first type bulk silicon substrate, and the source and drain may be doped with a second type impurity doped and diffused on top of the first type bulk silicon substrate and the pillar, respectively. And a 1T DRAM device having a split gate structure according to the present invention.

Meanwhile, the DRAM array according to the present invention is a DRAM array using a 1T DRAM element having a vertically stacked first side gate / center gate / second side gate structure, each of which is specified in a first direction and a second direction on a semiconductor substrate. And a plurality of 1T DRAM elements spaced apart from each other, wherein the first side gate / center gate / second side gate of each of the devices is shared with neighboring devices in the first direction, respectively, and the drain of each of the devices. Is electrically connected to a drain of a neighboring device through a bit line formed in the second direction, and a source of each device is electrically connected to a source of a neighboring device through a common source line formed on the semiconductor substrate. .

The first side gate and the second side gate may be connected to a side word line, and the center gate may be connected to a center word line.

The present invention has a split gate structure having one or two side gates on one side or both sides separately from the center gate, so that different biases can be applied and energy bands of the respective portions can be controlled separately. The retention time of the data '0' as well as the retention time can be improved simultaneously.

In particular, by forming the electrically isolated semiconductor body and source / drain in a columnar structure, and forming the first side gate / center gate / second side gate in a vertical stack, contacting the center gate and side gate in each word line unit It is possible to improve the degree of integration, extend the channel length vertically, and also improve the device characteristics according to the GAA structure, and in some cases, it is possible to produce a bulk substrate instead of an SOI substrate. have.

FIG. 1 is a cross-sectional view (a) illustrating a structure of a conventional 1T DRAM device and an energy band diagram (b) for intuitively showing a problem of inflow and outflow (recombination) of a hole according to voltage application of a gate when held.
FIG. 2 is a diagram illustrating that when the hold in the structure of FIG. 1 increases, a retention time of data '0' is reduced when a negative bias is increased in a gate.
FIG. 3 is a diagram illustrating that the retention time of data '1' is reduced when the negative bias applied to the gate during the structure of FIG. 1 is reduced.
4 is a cross-sectional view (a) conceptually illustrating the structure of the 1T DRAM device of the present invention and by applying different voltages to the center gate and the side gate at the time of holding, thereby increasing the barrier to increase the retention time of the data '1'. The energy band diagram (b) conceptually shows that the retention time of the data '0' can be improved by increasing the energy gap of the junction and increasing the energy gap of the junction.
FIG. 5 is a simulation showing that the retention time of data '1' is secured for 3 seconds or more at room temperature when -3.6V and -1.4V are respectively applied to the center gate and the side gate during hold in the structure of FIG. 4 (a). The result is also.
FIG. 6 is a simulation result showing that a retention time of a data '0' much longer than that of FIG. 1 (a) can be secured even when held at a high temperature (85 ° C.) during the structure of FIG. 4 (a).
7 is a simulation result diagram showing an energy band according to the structure of FIG.
8 is a simulation result diagram showing an energy band according to the structure of FIG.
FIG. 9 is a simulation result diagram for comparing sensing margins of those having a 20 nm underlap structure in FIGS. 1 (a) (Conventional), 4 (a) (Proposed) and FIG. 1 (a). to be.
10 is an exemplary perspective view for conceptually showing a structure of a DRAM array according to the present invention.
11 to 18 are cross-sectional views illustrating a process step of manufacturing a DRAM device having a pillar structure connected to a bit line in FIG. 10.
19 to 21 are cross-sectional views conceptually illustrating a structure of each embodiment in which one or two side gates are vertically stacked around a center gate.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

Embodiments Regarding DRAM Elements

First, an embodiment of a 1T DRAM device according to the present invention includes a semiconductor body 2 electrically isolated in a planar type, as shown in FIG. Source (3) and drain (4) formed on both sides of the semiconductor body; A center gate 7 formed on the semiconductor body 2 with a gate insulating film 6 interposed therebetween; One or two side gates 9 may be formed on the semiconductor body 2 with the isolation insulating layer 8 therebetween on one side or both sides of the center gate.

Here, the semiconductor body 2 is preferably formed in a single crystal silicon layer on the buried oxide film 1 in an SOI substrate, in which case the buried oxide film 1 is below, and field regions (not shown) on both sides of the channel direction are shown below. And between the source 3 / drain 4 and the semiconductor body 2 is surrounded by a depletion junction region 5 to be electrically isolated.

In addition, the two side gates 9 are disposed between the source 3 and the semiconductor body 2 and between the drain 4 and the semiconductor body 2, respectively, as shown in FIG. 4A. At least one end is preferably formed on the formed depletion junction region 5 to suppress the GIDL current caused by the side gate.

In this configuration, different voltages can be applied to the center gate 7 and the side gate 9 at the time of charge holding to the semiconductor body 2, as shown in FIG. 4B. In addition, it is possible to improve the retention time of the data '1' by increasing the height of the energy barrier to the source 3 or the drain 4, as well as to increase the energy gap of the junction portion and to suppress the data '0' by suppressing the GIDL current. It also has the advantage of improving retention time.

This was verified using a Silvaco tool simulation program, and the results are shown in FIGS. 5 to 9.

FIG. 5 shows that the device of the structure of FIG. 1 (a), which is used as a control, applies -2.2V to the gate 7 during the hold, and the device of the structure of FIG. In this example, the change in retention time of the data '1' is given by a difference of -2.2V to 0.3V. In this embodiment, -3.6V and -1.4V are applied to the center gate 7 and the side gate 9, respectively. When applied, it can be seen that the retention time of the data '1' for 3 seconds or more at room temperature is secured.

In addition, it can be seen from FIG. 6 that the holding time of the data '0' much longer than the structure of FIG. 1 (a) can be secured even when held in the structure of FIG.

7 shows an energy band according to the structure of FIG. 1 (a) and FIG. 8 shows an energy band according to the structure of FIG. 4 (a). By applying different biases to the side gates, it can be seen that the energy bands of each part can be modified and controlled separately.

Meanwhile, FIG. 9 is a sensing margin of the structure of FIG. 1 (a), the structure of FIG. 4 (a), and the 20 nm underlap structure of FIG. 1 (a). The simulation result is also compared. According to this, when using the underlap structure to suppress the GIDL current to improve the retention time, there is a disadvantage that the sensing margin is sharply reduced, while the structure according to the present embodiment is the same as the underlap structure It can be seen that there is no decrease in sensing margin.

Another embodiment of the 1T DRAM device of the present invention having the above electrical characteristics includes a semiconductor body 12 electrically isolated in a pillar type as shown in FIG. 18 or 19; A source 20 and a drain 19 formed on both sides of the semiconductor body; A center gate 50 formed on the semiconductor body 12 with a gate insulating film 30 interposed therebetween; Two side gates 40 and 60 formed on the semiconductor body 12 may be formed on both sides of the center gate with the insulating insulating layers 32 and 34 interposed therebetween.

Here, the semiconductor body 12 has a vertical pillar shape, and the source 20 and the drain 19 are formed on both sides of the pillar.

The center gate 50 and the two side gates 40 and 60 may be formed to surround side surfaces of the pillar, as shown in FIG. 18 or 19, but at least one side such as one side or both sides thereof. The isolation insulating layers 32 and 34 may be vertically stacked on the first side gate 40, the center gate 50, and the second side gate 60.

When the center gate 50 and the two side gates 40 and 60 are formed to surround the side of the pillar, as shown in FIG. 18 or 19 (GAA structure), the pillar has a horizontal cross section rectangular. Or round is preferred.

As described above, the first side gate 40 / center gate 50 / the second side gate 60 are vertically enclosed in the column-shaped semiconductor body 12 in a gate-all-around (GAA) structure. When stacked and formed there are four advantages.

First, as will be described later, the center gate and the side gate can be contacted for each word line unit. In the previous embodiment, the problem of inhibiting integration is fundamentally avoided due to the contact between the center gate and the side gate for each DRAM element. Will be solved.

Second, since the semiconductor body 12 is formed vertically, the channel length can be made large, thereby shortening the short channel effect and the like.

Third, it is possible to take advantage of the improvement of device characteristics according to the GAA structure.

Fourth, there is an advantage that can be manufactured as a bulk substrate instead of expensive SOI substrate.

FIG. 19 illustrates the main part of FIG. 18, wherein the first type (eg, p-type) bulk silicon substrate 10 is vertically etched to form a semiconductor pillar, and then the first type bulk silicon substrate on which the pillar is formed. 20 and the upper end 19 of the pillar are doped and diffused with a second type (eg, n-type) impurity to form a source and a drain.

Accordingly, the columnar first semiconductor body 12 is electrically depleted on the upper and lower sides of the column with the depletion junction region of the second type source 20 and the drain 19 and surrounded by the gate insulating film 30 on the side. By being isolated, it serves as a charge (eg hole) storage node.

Also in this embodiment in the form of the pillar, as in the previous embodiment, the two side gates 40 and 60 are respectively between the source 20 and the semiconductor body 12 and the drain 19. At least one end is preferably formed on the depletion junction region (not shown) formed between the semiconductor body 12 and the semiconductor body 12 to suppress the GIDL current caused by the side gate.

Another embodiment of the 1T DRAM device according to the present invention is shown in FIG. 20 instead of the vertically stacked 'first side gate 40 / center gate 50 / second side gate 60' in the above embodiment. Similarly, the vertically stacked 'first side gate 40 / center gate 50' structure or the vertically stacked 'center gate 50 / second side gate 60' structure as shown in FIG. It may be formed.

As described above, one side gate is removed from the vertically stacked 'first side gate 40 / center gate 50 / second side gate 60' configuration and the depletion junction of the portion is underlapped. When created, it is disadvantageous to improve retention time compared to using three gates, but has the advantage of simplifying the process.

In FIG. 21, reference numeral 31 is an insulating film filled in place of the first side gate 40, and although not shown in FIG. 20, the second side gate 60 is filled with an insulating film. Since other configurations are the same as in the above embodiment, repeated description is omitted.

Embodiment of DRAM Array

On the other hand, a DRAM array using the pillar-shaped DRAM element, in particular, a device having a first side gate / center gate / second side gate structure stacked vertically, is basically a semiconductor substrate (as shown in FIGS. 10 and 18). The plurality of 1T DRAM elements (eg, the pillar structure elements illustrated in FIG. 10) formed at a specific distance from each other in a first direction (eg, x-axis direction) and a second direction (eg, y-axis direction) in FIG. 10. The first side gate 40 / center gate 50 / second side gate 60 of each device is shared with neighboring devices in the first direction, respectively, and drain of each device. 19 is electrically connected to a drain of a neighboring device through a bit line 90 formed in the second direction, and a source of each device is connected through a common source line 20 formed on the semiconductor substrate 10. Neighboring devices Su are electrically connected.

The first side gate 40 and the second side gate 60 shared by the plurality of 1T DRAM elements formed in the first direction may be contact plugs 42 and 62 as shown in FIG. 10. It is connected to one side word line 70 through, and the center gate 50 is connected to the center word line 80 through a contact plug 52.

By the configuration as described above, the problem of having to contact the center gate and the side gate for each conventional device is solved, and there is an advantage of improving the degree of integration.

In FIG. 10, two center word lines 80 and two side word lines 70 are formed in the first direction and four bit lines 90 are formed in the second direction. However, this is omitted for convenience of understanding the present embodiment. It should be understood that this is shown briefly.

That is, the center word line 80 and the side word line 70 are vertically spaced apart in parallel in the second direction in units of the first side gate 40, the center gate 50, and the second side gate 60. By the number of stacked blocks, and the bit line 90 is parallel in the first direction between the contact plug 52 of each center word line 80 and the contact plugs 42 and 62 of the side word line 70. Spaced apart and may be formed in plurality.

In FIG. 10, reference numeral 20 denotes a common source line. As shown in FIG. 18, the reference numeral 20 may be integrally formed with the source of each device. That is, all DRAM devices according to the present exemplary embodiment may be integrally connected through the common source line 20 formed on the semiconductor substrate 10.

In addition, since the features (advantages) of the present embodiment according to the structure of each DRAM element are the same as those mentioned in the embodiment of the DRAM element, repeated description is omitted.

11 to 18, a manufacturing method of the array according to the present embodiment will be briefly described with reference to the device.

First, as shown in FIG. 11, the etching mask 14 is formed on the first type semiconductor substrate 10 using a silicon nitride film or the like, and is etched based on the etching mask 14 to form a plurality of pillars 12 (first step).

Next, as shown in FIG. 12, the second type impurity doping layer 21 is formed on the etched semiconductor substrate 10 by performing ion implantation perpendicularly to the entire surface of the substrate (second step).

Next, as illustrated in FIG. 13, a thermal oxidation process is performed to form the gate insulating film 30 on the exposed semiconductor surface (third step). In this case, the second type impurity doping layer 21 doped in the second step is diffused under the plurality of pillars 12 to form a source or a common source line 20 of each device. Of course, a separate thermal process may be performed before the thermal oxidation process for forming the gate insulating layer 30 to form a source or a common source line 20 of each device under the plurality of pillars 12.

Thereafter, as shown in FIG. 14, the conductive material 41 is deposited on the entire surface of the substrate (fourth step). The conductive material 41 may be a metal as well as a doped semiconductor material (eg, polysilicon, amorphous silicon, etc.).

Subsequently, as shown in FIG. 15, the conductive material 41 is etched using an etch back after performing a substrate front planarization process (eg, a CMP process) to form a first side gate 40 (fifth) step). In this case, when the silicon nitride film is used as the etching mask 14, the silicon nitride film 14 serves as an etch stopper during the CMP process.

Next, as shown in FIG. 16, a separation insulating layer 32 is formed on the first side gate 40 (sixth step). At this time, the gate insulating film 30 exposed on the first side gate 40 may be removed and a thermal oxidation process may be performed again to form the isolation insulating film 32 together with the gate insulating film.

Thereafter, as shown in FIG. 17, the fourth to sixth steps are repeated to form the center gate 50, the isolation insulating layer 34, and the second side gate 60 (seventh step).

Next, as shown in FIG. 18, the etching mask 14 is removed and an ion implantation process is performed to form the drain 19 of each device on the first type semiconductor body 12 using a second type impurity doped layer. (Step 8).

After that, the interlayer insulating film is deposited and planarized on the entire surface of the substrate, and then a plurality of contact holes are formed to form a bit line 90 connected to the drain 19 of each device, each first side gate 40, and each second side. If the side word line 70 connected to the gate 60 and the center word line 80 connected to each center gate 50 are formed, a DRAM array having a structure as shown in FIG. 10 may be manufactured.

1: investment oxide 2, 12: semiconductor body
3, 20: source 4, 19: drain
5: depletion junction region 6, 30: gate insulating film
7, 50: center gate 8, 31, 32, 34: isolation insulating film
9, 40, 60: side gate 10: semiconductor substrate
14: etch mask 42, 52, 62: contact plug
70: side word line 80: center word line
90: bitline

Claims (7)

An electrically isolated semiconductor body;
Source and drain formed on both sides of the semiconductor body;
A center gate formed on the semiconductor body with a gate insulating film interposed therebetween;
1T DRAM device having a split gate structure, comprising one or two side gates formed on the semiconductor body with a separation insulating layer interposed between one or both sides of the center gate.
The method of claim 1,
And each side gate has at least one end formed on a depletion junction region formed between the source and the semiconductor body or between the drain and the semiconductor body.
The method according to claim 1 or 2,
The semiconductor body has a vertical columnar shape,
The source and drain are formed on both sides of the pillar,
The center gate and each side gate may include a first side gate / center gate / second side gate, a first side gate / center gate, or a center gate / second, with the isolation insulating layer therebetween on at least one side of the pillar. A 1T DRAM device having a split gate structure, which is formed by vertically stacking side gates.
The method of claim 3, wherein
The pillar has a square or circular horizontal cross section,
The center gate and each side gate is 1T DRAM device having a split gate structure characterized in that it is formed surrounding the side of the pillar.
The method of claim 4, wherein
The pillar is formed by vertically etching a type 1 bulk silicon substrate,
The source and drain of the 1T DRAM device having a split gate structure, characterized in that the first type bulk silicon substrate having the pillars formed thereon and a second type impurity doped and diffused on each of the upper ends of the pillars.
A DRAM array using a 1T DRAM device having a first side gate / center gate / second side gate structure of claim 4,
Comprising a plurality of the 1T DRAM devices formed on the semiconductor substrate spaced apart in a first distance and a second direction, respectively,
Each of the first side gate / center gate / second side gate of each device is shared with neighboring devices in the first direction,
The drain of each device is electrically connected to the drain of the neighboring device through a bit line formed in the second direction,
And the source of each device is electrically connected to a source of a neighboring device through a common source line formed on the semiconductor substrate.
The method according to claim 6,
The first side gate and the second side gate are connected to a side word line,
And the center gate is connected to a center word line.

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