KR101286704B1 - Transistor having fixed charge layer in box and fabrication method thereof - Google Patents

Abstract

The present invention provides a transistor for forming a fixed charge layer by injecting impurities which generate a positive charge or a negative charge into an embedded insulating film such as a buried oxide film of an SOI substrate, thereby controlling a threshold voltage and a method of manufacturing the same .

Description

TECHNICAL FIELD [0001] The present invention relates to a transistor having a fixed charge layer in an embedded insulating film and a method of manufacturing the transistor.

The present invention relates to a semiconductor device, and relates to a transistor having various threshold voltages in the same substrate and a method of manufacturing the same.

The threshold voltage determines whether the transistor is to be channeled, i.e., determines the on / off state of the device, which requires transistors with various threshold voltages depending on the circuit design.

Up to now, the threshold voltage of a transistor can be controlled by injecting ions such as boron into the active region where a channel is to be formed when the transistor is formed on a bulk substrate, or by injecting impurities into the gate insulating film Non-Patent Documents 1 and 2), attempts have been made to achieve this by changing the gate material and controlling the work function of the gate material.

However, MOSFETs and TFETs implemented in SOI (Silicon-On-Insulator) substrates often have very low doping of silicon on buried insulating films (BOX) Adjusting the voltage is very difficult.

Further, the thickness of the gate insulating film becomes thinner to the order of several nm, and it becomes increasingly difficult to accurately place the impurity in this portion. That is, in order to place the impurity in the thin gate insulating film, ion implantation must be performed with a low energy, so that the beam current is low and not only the process time is prolonged, but the injected ions are not located only in the gate insulating film.

However, if the threshold voltage of the transistors manufactured on the SOI substrate is adjusted by the gate material work function, the process becomes very complicated because the gate material needs to be different in the number of the gate electrodes to obtain the threshold voltage on one substrate. There is no guarantee that there is a gate material having a work function.

1, in order to control the threshold voltage of the transistors formed on the SOI substrate, the impurity concentration of the silicon layer 100 under the buried oxide layers 122 and 124 is higher than the channel regions 145 and 147, A high concentration impurity doping layer 162 and a high concentration impurity doping layer 164 are formed and the threshold voltage between the transistors is adjusted by the difference in impurity concentration between the impurity doping layers 162 and 164 (see Patent Document 1).

However, according to Patent Document 1, the impurities are passed through the buried oxide films 122 and 124 to form the impurity doping layers 162 and 164 in the region of the lower silicon 100, which is difficult in the process of making the ion implantation energy excessively large .

The impurities forming the impurity doping layers 162 and 164 in Patent Document 1 are B and BF _{2 in} the case of the n-type MISFET, and As, P and the like in the case of the p-type MISFET. In order to increase the concentration of electrons or holes that are more carriers than the channel regions 145 and 147 and to affect the threshold voltage by using an acceptor capable of receiving a donor or an electron, that is, a hole, The isolation insulating film 130 must be deeply formed so as to electrically isolate the both-side impurity doping layers 162 and 164 from each other so as to prevent migration of a large number of carriers between the transistors.

Patent Document 1: Japanese Unexamined Patent Application Publication No. 2007-180402, July 12, 2007.

Non-Patent Document 1: J. T. Watt, B. J. Fishbein, and J. D. Plummer, "A low-temperature NMOS technology with Cesium-implanted load devices", Electron Devices, IEEE Transactions on Electron Devices, Vol. 34, pp. 28-38, 1987 Non-Patent Document 2: H. P. Zappe, S. Aronowitz, and C. Hu, "Oxide implantation for threshold voltage control", Solid-State Electronics, Vol. 33, pp. 1447-1453, 1990.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems of the prior art, and it is an object of the present invention to provide a method of manufacturing an SOI substrate in which an impurity which generates positive or negative charges is injected into an embedded insulating film, And to provide a transistor for controlling the threshold voltage and a method of manufacturing the same.

In order to achieve the above object, a transistor according to the present invention includes an embedded insulating film; A source region and a drain region formed on the upper semiconductor layer on the islanding insulating film so as to be spaced apart from each other with a channel region therebetween; A gate insulating film formed on the channel region; And a gate formed on the gate insulating film, wherein the buried insulating film has a first fixed charge layer into which a first impurity for generating a positive charge or a negative charge is injected, and the source region and the drain region And conductive types are formed opposite to each other.

Another characteristic of the transistor according to the present invention is that the gate insulating film also has a second fixed charge layer into which a second impurity for generating a positive charge or a negative charge is injected.

A method of manufacturing a transistor according to the present invention includes: a first step of defining at least one active region in which an element is to be formed in an upper semiconductor layer of a semiconductor substrate having an embedded insulating film and forming an insulating film for isolation between elements; A second step of forming an impurity implantation mask so as to open only a part of the active region defined as the isolation insulating film and to cover the remaining portion and implant a dopant to form a fixed charge layer on the buried insulating film under the open active region; A third step of forming a gate insulating film on the upper semiconductor layer constituting the active region after removing the impurity implantation preventing mask; A fourth step of depositing a gate material on the gate insulating film and etching the gate material to form a gate; And a fifth step of forming a source region and a drain region by an ion implantation process, wherein the fifth step alternately shields the source region and the drain region with a third impurity implantation mask, Is formed.

Another method of manufacturing a transistor according to the present invention comprises the steps of: defining an active region in which an element is to be formed in an upper semiconductor layer of a semiconductor substrate having an embedded insulating film and forming an insulating film for isolation between elements; A second step of forming a gate insulating layer on the upper semiconductor layer exposed between the isolation insulating films; The gate insulating film and the buried insulating film located on the upper and lower sides of the upper semiconductor layer of the open active region by injecting impurities with different energy and forming the impurity injection preventing mask so as to open only a part of the active region defined as the isolation insulating film, A third step of forming a fixed charge layer; A fourth step of removing the impurity implantation mask, depositing a gate material on the entire surface of the substrate, and etching the gate material to form a gate; And a fifth step of forming a source region and a drain region by an ion implantation process, wherein the fifth step alternately shields the source region and the drain region with a third impurity implantation mask, Is formed.

The transistor according to the present invention is capable of easily and variously controlling the threshold voltage through the formation of a fixed charge layer by injecting an impurity which generates a positive charge or a negative charge into the buried insulating film such as the buried oxide film of the SOI substrate .

In the method of manufacturing a transistor according to the present invention, only one active region is opened with a mask for preventing impurities from being injected into one substrate, and the impurity implantation process is repeatedly performed by varying at least one of the dose amount, kind, Thereby, transistors having various threshold voltages can be manufactured simultaneously at the same time.

In addition, the transistor and the manufacturing method thereof according to the present invention are characterized in that in the SOI substrate, the buried insulating film is thick and the silicon layer (SOI film) is provided on the upper portion. Impurity ion implantation for forming the fixed charge layer in the buried insulating film, It is possible to shorten the process time with a high beam current. Thus, the impurity ions thus injected are located in the buried insulating film instead of the upper silicon layer (SOI film), so that the fixed charge layer can be easily formed.

1 is a cross-sectional view of a structure manufactured by the conventional patent document 1.
FIGS. 2 to 8 are process cross-sectional views illustrating that a transistor having different threshold voltages can be manufactured on the same substrate by forming fixed charge layers on the buried insulating film by varying the dose amount of impurities according to an embodiment of the present invention .
FIGS. 9 and 10 are process cross-sectional views illustrating that transistors having different threshold voltages can be fabricated on the same substrate by forming fixed charge layers on the buried insulating film by different kinds of impurities according to another embodiment of the present invention.
FIGS. 11 to 13 are process cross-sectional views showing that a source region and a drain region are formed so that the TFETs having different threshold voltages can be simultaneously formed on one substrate by forming the source region and the drain region such that the conductivity types are opposite to each other .
FIGS. 14 to 17 are process cross-sectional views showing that a fixed charge layer can be easily formed by following the same process for a gate insulating film according to still another embodiment of the present invention.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

[The first Example ]

As shown in FIG. 8, the first embodiment of the transistor structure according to the present invention basically comprises an embedded insulating film 20; Source regions (42, 46) and drain regions (44, 48) spaced apart from each other with a channel region (45, 47) therebetween in the upper semiconductor layer on the islanding insulating film; A gate insulating film (72, 74) formed on the channel region; And a gate (82, 84) formed on the gate insulating film. The first and second fixed charge layers (62, 62) are formed in the buried insulating film (20), in which a first impurity for generating a positive charge or a negative charge is injected, 64).

In FIG. 8, reference numeral 10 denotes a lower semiconductor layer, and reference numeral 30 denotes an active region in which an element is to be formed in the upper semiconductor layer and an isolation insulating film for element-to-element isolation.

FIG. 8 illustrates two transistor structures according to the present embodiment with an isolating insulation film 30 interposed therebetween, but the present invention is not limited thereto. The two transistors shown in FIG. 8 show only differences in concentration of the first impurity in the first fixed charge layers (62, 64) formed in the buried insulating film (20).

The threshold voltage of the transistor can be adjusted according to the first impurity concentration of the first fixed charge layers 62 and 64 formed in the buried insulating film 20.

The buried insulating film 20 may have any shape as long as it is buried under the semiconductor layer constituting the source / drain region and the channel region, and may be a buried oxide film (silicon oxide film) of the SOI substrate, for example.

The first impurity may be an element and an ion which are injected into the buried insulating film 20 and react with the surrounding buried insulating film material to generate a positive charge or a negative charge.

The first fixed charge layers 62 and 64 are formed in the buried insulating film 20 because the injected first impurity affects the threshold voltage of the transistor by the banded charge and the first impurity is injected into the buried insulating film 20 The electrons and holes emitted from the first impurity hardly move and remain around the atoms constituting the buried insulating film.

Therefore, as in the case of the conventional patent document 1, there is an advantage that the isolation insulating film 30 is extended to form the impurity doped layer, that is, the first fixed charge layers 62 and 64, so that it is not necessary to separate them.

The charge amount of the first fixed charge layer (62, 64) affecting the threshold voltage of the transistor depends on the concentration of the first impurity implanted into the material of the buried insulating film (20), the kind, the implantation energy and the implantation direction Can be determined. This is because the first impurity implanted reacts with the material of the buried insulating film 20 to emit or receive electrons and to have a positive charge or a negative charge.

The first fixed charge layers 62 and 64 are buried in contact with the upper semiconductor layer in which the source regions 42 and 46 and the drain regions 44 and 48 and the channel regions 45 and 47 are formed, It is preferable that the insulating film 20 is formed at a portion of the insulating film 20 so that the influence on the channel can be increased. However, as described above, the insulating film 20 may be formed deep within the insulating film 20 depending on the implantation energy of the first impurity .

The embodiment shown in FIG. 10 is the same as the embodiment shown in FIG. 8 except that the first fixed charge layers 62 and 65 have different first impurities.

Thus, by differentiating the types of the first impurities constituting the first fixed charge layers 62 and 65 from those of the neighboring transistors, transistors having various threshold voltages can be realized on one substrate.

8 and 10 are all MOSFET structures having the same conductivity type (for example, n + in both the source and drain regions) of the source regions 42 and 46 and the drain regions 44 and 48, Likewise, a TFET can also be realized by forming the source regions 42 and 46 and the drain regions 44a and 48a in opposite conductivity types (for example, the source region is n + and the drain region is p +).

That is, the TFET, which is a tunneling field effect transistor, also has the first fixed charge layers 62 and 64, into which the first impurity for generating the positive or negative charge is injected into the buried insulating film 20, The device can be formed on one substrate.

[The second Example ]

The second embodiment of the transistor structure of the present invention is the same as the first embodiment of the transistor structure as shown in Fig. 17, except that the gate insulating films 72 and 74 are formed with a positive charge or negative charge And the second fixed charge layer (61, 63) into which the second impurity is implanted.

The second fixed charge layers 61 and 63 are further formed to more effectively control the threshold voltage of the transistor.

The charge amount of the second fixed charge layers 61 and 63 affecting the threshold voltage of the transistor is set such that the amount of charge of the second impurity injected into the gate insulating films 72 and 74 The type, the implantation energy, and the direction of implantation (angle).

Specifically, the buried insulating film 20 and the gate insulating films 72 and 74 may be a silicon oxide film, and the upper semiconductor layer may be an SOI film, that is, a single crystal silicon layer.

The first impurity and the second impurity respectively react with the material of the buried insulating film 20 and the gate insulating film 72 to form a positive charge or a negative charge and may be different materials, It is preferable to use a material because the manufacturing process can be simplified.

In addition, the description of the constitution has been fully described in the first embodiment of the transistor structure, and repeated description will be omitted.

[The first related to a method for manufacturing a transistor Example ]

Next, a first embodiment of a method of manufacturing a transistor according to the present invention will be described with reference to FIGS. 2 to 8. FIG.

First, as shown in FIG. 2, one or more active regions 41 and 43 to be formed in an upper semiconductor layer of a semiconductor substrate such as an SOI substrate having an embedded insulating film 20 are defined and an isolation insulating film 30 (Step 1).

At this time, the isolation insulating film 30 may be formed up to the buried insulating film 20 or a part of the upper part of the buried insulating film 20 by a known STI process or the like, and the buried insulating film 20 may be formed to reach the lower silicon layer There is no need.

3, an impurity injection preventing mask 52 is formed so as to open only a part 41 of the active region defined by the isolation insulating film 30 and to cover the remaining portion 43, A fixed charge layer 62 is formed on the buried insulating film 20 under the region 41 (second step).

Here, the impurity implantation may selectively determine at least one of the dose amount, type, implantation energy, and implantation direction (angle) of the impurity to obtain a desired threshold voltage.

4, a second impurity injection preventing mask 54 is formed so as to cover the other portion 43 of the active region and cover the remaining portion 41, as shown in FIG. 4, after removing the impurity implantation- (Step 2-1) of forming a second fixed charge layer (64) on the embedded insulating film (20) below the active region (43) by injecting a second impurity. .

At this time, impurities injected every time the step 2-1 is repeated are injected with different doses selected from the dose amount, type, implantation energy and injection direction (angle), and various threshold voltages are applied to one substrate It is preferable to form the transistor having the transistor.

FIG. 9 and FIG. 10 show that the impurities to be implanted can be changed with each repetition of Step 2-1.

5, gate insulating films 72 and 74 are formed on the upper semiconductor layers 41 and 43 forming the active region after removing the impurity injection preventing masks 52 and 54 (third step) .

Here, the gate insulating films 72 and 74 may be formed by a known thermal oxidation process or the like.

6, a gate material 80 is deposited on the gate insulating films 72 and 74 and the gate material 80 is etched to form gates 82 and 84 as shown in FIG. 7 Step 4).

Here, the gate material 80 may be a doped silicon-based material.

Next, as shown in FIG. 7, source regions 42 and 46 and drain regions 44 and 48 are formed by an ion implantation process (fifth step).

7, the source regions 42 and 46 and the drain regions 44 and 48 may be formed in a MOSFET structure by one ion implantation process. However, as shown in FIGS. 11 and 12, And the drain region are alternately covered with the third impurity injection preventing mask 91, 92, 93, 94, and impurities having different conductivity types are injected thereinto to form the TFET structure as shown in FIG. 13 .

Although not shown in the accompanying drawings, a sacrificial insulating film (not shown) is formed on the upper semiconductor layers 41 and 43 exposed immediately before the impurity is implanted in each of the steps of the second and the second stages, And removing the sacrificial insulating layer after the impurity is implanted.

By doing so, it is possible to prevent the surface damage of the active region when the impurity is implanted.

[The second concerning the manufacturing method of the transistor Example ]

Next, a second embodiment of a method of manufacturing a transistor according to the present invention will be described with reference to FIGS. 14 to 17. FIG.

First, as shown in FIG. 14, active regions 41 and 43 are formed in an upper semiconductor layer of a semiconductor substrate such as an SOI substrate having an embedded insulating film 20, and an isolation insulating film 30 for isolating elements is defined And then gate insulating films 72 and 74 are formed on the upper semiconductor layers 41 and 43 exposed between the isolation insulating films 30 (step 2).

Here, the gate insulating films 72 and 74 may be formed through a known thermal oxidation process or the like. Since the gate insulating films 72 and 74 are formed and the impurity implantation process is performed in the next process, A sacrificial insulating film forming process is not required.

15, the impurity injection preventing mask 52 is formed so as to open only a part 41 of the active region defined by the isolation insulating film 30 and to cover the remaining part 43, The fixed charge layers 61 and 62 are formed in the gate insulating film 72 and the buried insulating film 20 located on both upper and lower sides of the upper semiconductor layer of the open active region 41 in the third step.

Here, the impurity implantation may be performed by selecting at least one of the dose amount, type, implantation energy, and implantation direction (angle) of the impurity and implanting appropriate impurities into the fixed charge layers 61 and 62 respectively to obtain a desired threshold voltage .

In particular, it is necessary to adjust the impurity implantation energy so that the fixed charge layer 61 is also formed in the gate insulating film 72. [

By doing so, the fixed charge layer 61 can be formed not only in the embedded insulation film 20 but also in the gate insulation film 72 in this step, so that the fixed charge due to the upper and lower sides of the channel region 41 The layers 61 and 62 can more easily control the threshold voltage.

16, a second impurity injection preventing mask 54 is formed so as to open the other portion 43 of the active region and cover the remaining portion 41, as shown in FIG. 16, after removing the impurity implantation preventing mask 52. Next, Forming the fixed charge layers 63 and 65 in the gate insulating film 74 and the buried insulating film 20 located on both upper and lower sides of the open active region 43 by injecting the second impurity Step) can be repeated one or more times.

At this time, impurities injected every time the step 3-1 is repeated are injected with different doses selected from the dose amount, type, implantation energy and injection direction (angle), and various threshold voltages are applied to one substrate It is preferable to form the transistor having the transistor.

17, a gate material is deposited on the entire surface of the substrate after the removal of the impurity injection preventing masks 52 and 54, and etching is performed to form gates 82 and 84 (step 4) Source regions 42 and 46 and drain regions 44 and 48 are formed (fifth step).

7, the source regions 42 and 46 and the drain regions 44 and 48 may be formed in a MOSFET structure by one ion implantation process. However, as shown in FIGS. 11 and 12, And the drain region are alternately covered with the third impurity injection preventing mask 91, 92, 93, 94, and impurities having different conductivity types are injected thereinto to form the TFET structure as shown in FIG. 13 .

10: Lower semiconductor layer
20:
30: Isolation insulating film
42, 46: source region
45, 47: channel region
44, 44a, 48, 48a: drain region
61, 63: a second fixed charge layer
62, 64, 65: a first fixed charge layer
72, 74: gate insulating film
82, 84: Gate
91, 92, 93, 94: mask for preventing impurity injection

Claims (14)

Buried insulating film;
A source region and a drain region formed on the upper semiconductor layer on the islanding insulating film so as to be spaced apart from each other with a channel region therebetween;
A gate insulating film formed on the channel region; And
And a gate formed on the gate insulating film,
Wherein the embedded insulating film has a first fixed charge layer into which a first impurity for generating a positive charge or a negative charge is injected,
Wherein the source region and the drain region are formed in opposite conductivity types.
The method according to claim 1,
Wherein the first fixed charge layer is formed on a portion of the buried insulating film in contact with the upper semiconductor layer.
delete 3. The method according to claim 1 or 2,
Wherein the gate insulating film has a second fixed charge layer into which a second impurity for generating a positive charge or a negative charge is injected.
5. The method of claim 4,
The buried insulating film and the gate insulating film are silicon oxide films,
The upper semiconductor layer is a silicon layer,
Wherein the first impurity and the second impurity react with the silicon oxide film with the same material to generate the same amount of charge or negative charge.
A first step of defining at least one active region in which an element is to be formed in an upper semiconductor layer of a semiconductor substrate having an embedded insulating film and forming an isolation insulating film for element isolation;
A second step of forming an impurity implantation mask so as to open only a part of the active region defined as the isolation insulating film and to cover the remaining portion and implant a dopant to form a fixed charge layer on the buried insulating film under the open active region;
A third step of forming a gate insulating film on the upper semiconductor layer constituting the active region after removing the impurity implantation preventing mask;
A fourth step of depositing a gate material on the gate insulating film and etching the gate material to form a gate; And
And a fifth step of forming a source region and a drain region by an ion implantation process,
Wherein the fifth step comprises forming the source region and the drain region in a third impurity implantation mask alternately and injecting different impurities.
The method according to claim 6,
A second impurity implantation mask is formed between the second and third steps to remove the impurity implantation mask and open another portion of the active region to cover the remaining portion, and a second impurity is implanted And a second step of forming a second fixed charge layer in an embedded insulating film below the open active region is repeatedly performed at least once.
8. The method of claim 7,
The impurity implanted in the second step and the impurity implanted each time it is repeated in the second step are implanted in at least one selected from the group consisting of dose, kind, implantation energy and implantation direction. Gt;
9. The method of claim 8,
A sacrificial insulating film is formed on the upper semiconductor layer exposed immediately before the impurity is implanted in each of the steps of the second step and the second step, and after the impurity is implanted, the sacrificial insulating film is removed Wherein the step of forming the transistor further comprises the steps of:
delete A first step of defining an active region in which an element is to be formed in an upper semiconductor layer of a semiconductor substrate having an embedded insulating film and forming an isolation insulating film for element isolation;
A second step of forming a gate insulating layer on the upper semiconductor layer exposed between the isolation insulating films;
The gate insulating film and the buried insulating film located on the upper and lower sides of the upper semiconductor layer of the open active region by injecting impurities with different energy and forming the impurity injection preventing mask so as to open only a part of the active region defined as the isolation insulating film, A third step of forming a fixed charge layer;
A fourth step of removing the impurity implantation mask, depositing a gate material on the entire surface of the substrate, and etching the gate material to form a gate; And
And a fifth step of forming a source region and a drain region by an ion implantation process,
Wherein the fifth step comprises forming the source region and the drain region in a third impurity implantation mask alternately and injecting different impurities.
12. The method of claim 11,
Removing the impurity implantation mask between the third step and the fourth step, forming a second impurity implantation mask so as to open another portion of the active region and cover the remaining portion, Wherein the impurity is implanted to form a fixed charge layer in each of the gate insulating film and the buried insulating film located above and below the upper semiconductor layer in the open active region.
13. The method of claim 12,
The impurity implanted in the third step and the impurity implanted each time it is repeated in the step 3-1 are implanted in at least one selected from the group consisting of dose, kind, implantation energy and implantation direction. Gt;
delete

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