KR101093148B1 - Semiconductor device and method for fabricating the same - Google Patents

Abstract

The present invention is to provide a semiconductor device and a method of manufacturing the same that can prevent the leakage current in the off state, in particular, GIDL (Gate Induced Drain Leakge) current generation, the semiconductor device of the present invention comprises a gate on the substrate; An organic semiconductor pattern interposed between the substrate and the gate; A junction region formed on both sides of the gate and partially overlapping the organic semiconductor pattern; And a junction pattern in contact with the organic semiconductor pattern sidewall on the junction region. According to the present invention, the organic semiconductor pattern is provided to effectively prevent leakage current in an off state. .

GIDL, Leakage Current, Organic Semiconductor, Inorganic Semiconductor, Threshold Voltage

Description

Semiconductor device and manufacturing method therefor {SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a manufacturing technique of a semiconductor device, and more particularly, to a semiconductor device capable of preventing generation of gate induced drain leakage (GIDL) and a method of manufacturing the same.

As the integration degree of the semiconductor device increases, the channel length also becomes very short at the same time, and as the channel length decreases, the operating characteristics of the semiconductor device gradually deteriorate.

1 is a cross-sectional view showing a semiconductor device according to the prior art.

Referring to FIG. 1, a method of manufacturing a semiconductor device according to the related art is described. A threshold voltage adjusting layer 19 is formed to adjust a threshold voltage by implanting impurities into a substrate 11. Subsequently, a gate 16 having a structure in which the gate insulating layer 12, the gate electrode 13, and the gate hard mask layer 14 are stacked on the substrate 11 is formed, and then spacers 17 are formed on both side walls of the gate 16. ). Subsequently, the junction region 18 is formed in the substrate 11 on both sides of the gate 16. At this time, since the junction region 18 is formed through impurity ion implantation and heat treatment, the gate 16 and a portion of the junction region 18 overlap each other.

However, the semiconductor device according to the related art has a problem that a gate induced drain leak (GIDL) current occurs in a region where the gate 16 and the junction region 18 overlap with each other (see reference numeral 'A'). have. Specifically, the semiconductor device having the above-described structure has the gate 16 by the bias applied to the junction region 18 in the off state in which the semiconductor device is not operated, that is, the bias is not applied to the gate 16. ) And a GIDL current is generated in a region where the junction region 18 overlaps, resulting in deterioration of off characteristics of the semiconductor device.

In addition, as the size of the semiconductor device decreases, the impurity doping concentration of the threshold voltage adjusting layer 19 is increased to maintain the threshold voltage, and thus the deterioration of off characteristics of the semiconductor device due to the GIDL current is intensified.

The present invention has been proposed to solve the above problems of the prior art, and an object thereof is to provide a semiconductor device and a method of manufacturing the same, which can prevent generation of GIDL current.

According to one aspect of the present invention, a semiconductor device includes: a gate on a substrate; An organic semiconductor pattern interposed between the substrate and the gate; A junction region formed on both sides of the gate and partially overlapping the organic semiconductor pattern; And a junction pattern in contact with the organic semiconductor pattern sidewall on the junction region.

The organic semiconductor pattern may be interposed between the substrate and both edges of the gate, and an interface between the organic semiconductor pattern and the junction pattern may be aligned with the gate sidewall.

The substrate and the organic semiconductor pattern may have a complementary conductivity type, and the organic semiconductor pattern and the junction region may have the same conductivity type.

The organic semiconductor pattern may include pentacene (Pentacene) or phthalocyanine (Phthalocyanine) having a conductive type, and may include a perylene diimide derivative having a conductive type of N.

In addition, a threshold voltage control layer formed on the substrate under the gate; And it may further include a spacer formed on both side walls of the gate. In this case, the bonding pattern may be interposed between the spacer and the substrate.

According to an aspect of the present invention, a method of manufacturing a semiconductor device includes: forming a bonding pattern on a substrate; Forming an organic semiconductor pattern between the bonding patterns; Forming a gate on the substrate to cover the organic semiconductor pattern; And forming a junction region on the substrate under the junction pattern on both sides of the gate to partially overlap the organic semiconductor pattern.

The method may further include forming a threshold voltage control layer on the substrate before forming the junction pattern.

The method may further include forming spacers on both side walls of the gate before forming the junction region; And etching the bonding pattern using the spacer as an etch barrier. ,

The forming of the organic semiconductor pattern may include forming one sidewall to be bonded to the sidewall of the junction pattern, and forming the organic semiconductor pattern to be positioned between the edges of the substrate and the gate.

The forming of the gate may include forming the gate sidewall and an interface between the organic semiconductor pattern and the junction pattern to be aligned with each other.

The substrate and the organic semiconductor pattern may be formed to have complementary conductivity types, and the organic semiconductor pattern and the junction region may be formed to have the same conductivity type.

The organic semiconductor pattern may include pentacene (Pentacene) or phthalocyanine (Phthalocyanine) having a conductive type, and may include a perylene diimide derivative having a conductive type of N.

The present invention based on the above-described problem solving means has an effect of effectively preventing the leakage current, in particular the generation of the GIDL current, even when a bias is applied to the junction region in the off state. In addition, even if the impurity doping concentration of the threshold voltage control layer is increased in order to control the threshold voltage of the semiconductor device, there is an effect of preventing the generation of the GIDL current.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings, in order to facilitate a person skilled in the art to easily carry out the technical idea of the present invention.

First, the electrical characteristics of the organic semiconductor will be described with reference to FIG. 2, which shows a capacitance change according to the voltage of the organic semiconductor.

As shown in FIG. 2, the structure of the device for evaluating the electrical properties of the organic semiconductor is deposited on a high concentration doped silicon semiconductor and then deposited on the P-type organic semiconductor pentacene (Pentacene) and deposited thereon A metal electrode Au was deposited.

'Cmax' represents the capacitance of the oxide film as the capacitance value measured when the thermal oxide film is placed on the device structure without organic semiconductor, that is, on the n ++ / p ++ Si and the metal electrode is deposited thereon. Next, the electrical characteristics of the organic semiconductor in the device structure on which the organic semiconductor is deposited will be described. When the positive bias is applied to n + / p ++ Si, the capacitance of the device is very small. This is because the organic semiconductor on the oxide film serves as another insulating film, the thickness of the insulating film between the two electrodes becomes thick, so that the capacitance appears small. Next, applying a negative bias to n + / p ++ Si increases the measured capacitance to the same as the oxide capacitance, which causes the positive charge in the organic semiconductor to move towards the oxide layer by the negative bias applied to n + / p ++ Si. The positive charge thus accumulated acts as an electrode opposite to n + / p ++ Si of the oxide film, so that the capacitance of the organic semiconductor is lost and only the oxide film capacitance is measured. The positive charge thus formed acts as a channel, and the formation of the channel by the organic semiconductor upon application of a negative bias means that the pentacene used as the organic semiconductor has P-type semiconductor characteristics.

The present invention to be described below with reference to the above-described characteristics of the organic semiconductor provides a semiconductor device and a method of manufacturing the same that can prevent the deterioration (off) characteristics of the semiconductor device due to the generation of GIDL (Gate Induced Drain Leakge) current. To this end, the present invention is characterized in that the organic semiconductor pattern is inserted between the edges of both sides of the gate where the GIDL current is generated and the substrate.

3 is a cross-sectional view illustrating a semiconductor device in accordance with an embodiment of the present invention.

As shown in FIG. 3, a semiconductor device according to an embodiment of the present invention includes a gate 28 on a substrate 21, an organic semiconductor pattern 23 interposed between the substrate 21, and a gate 28. (28) a junction region 30 formed on both substrates 21 and partially overlapping with the organic semiconductor pattern 23, and a junction pattern 22A on the junction region 30 in contact with sidewalls of the organic semiconductor pattern 23. .

The organic semiconductor pattern 23 serves as a channel in a state where a bias is applied to the gate 28, that is, an on state, and a junction in a state in which the bias is not applied to the gate 28, that is, in an off state. It serves as a blocking film to prevent the occurrence of leakage current (eg, GIDL current) due to the bias applied to the region 30. The organic semiconductor pattern 23 performing the above-described role may be formed of a perylene diimide derivative having a conductivity type of N and a pentacene (Pentacene) or phthalocyanine (Phthalocyanine) having a conductivity of P type. Can be. For reference, the organic semiconductor is not determined by the type of impurities doped differently from the inorganic semiconductor such as silicon, and the P-type or the organic semiconductor layer may be formed according to the conductivity of the carrier according to the structure of the molecules and the molecular structure of the molecules. It can be divided into N type.

Here, the principle that the organic semiconductor pattern 23 can prevent the generation of the GIDL current due to the bias applied to the junction region 30 in the off state in which the bias is not applied to the gate 28 is that the organic semiconductor is energy from the outside. This is because it has insulation characteristics in a state where no voltage or electric field is applied. That is, in the off state where the bias is not applied to the gate 28, the organic semiconductor pattern 23 acts as an insulating film (or a blocking film), so that the capacitance between the gate 28 and the junction region 30 becomes small, and Since the field size is reduced, generation of a GIDL current having a large field dependency between the gate 28 and the junction region 30 can be prevented.

On the contrary, when the organic semiconductor pattern 23 is turned on with the bias applied to the gate 28, an inversion rayer is formed on the substrate 21 under the gate 28, and the organic semiconductor overlaps the gate 28. In the pattern 23, carriers are concentrated on the surface of the organic semiconductor pattern 23 in contact with the gate 28 in response to a bias applied to the gate 38 to form the same conductive path as that of the inversion layer, that is, a channel. Operation is possible.

In addition, as shown in the drawing, the organic semiconductor pattern 23 may have a structure overlapping a part of both edges of the gate 28, or a structure overlapping the entire gate 28. In this case, since the charge mobility of the inorganic semiconductor, for example, silicon (or silicon doped with impurities) is superior to that of the organic semiconductor, the organic semiconductor pattern 23 is shown in terms of the operating speed of the semiconductor device. It is preferable to form the gate 28 so as to have a structure overlapping with a part of both edges.

In addition, the organic semiconductor pattern 23 preferably has the same conductivity type as the junction region 30, and preferably has a conductivity type complementary to the substrate 21. For example, in the case of NMOS, the organic semiconductor pattern 23 and the junction region 30 are preferably N-type, and the substrate 21 is P-type. In the case of PMOS, the organic semiconductor pattern 23 and the junction region 30 are preferably P-type, and the substrate 21 is N-type.

The bonding pattern 22A in contact with the sidewall of the organic semiconductor pattern 23 serves to connect the bonding region 30 and the organic semiconductor pattern 23, that is, the extended bonding region 30. Therefore, the bonding pattern 22A is formed of a conductive material, and a silicon film, a metallic film, or the like may be used as the conductive material.

Here, when the bias is applied to the gate 28 and the distribution of the charge in the organic semiconductor pattern 23 is examined, the charge moves to the interface contacting the gate 28, that is, the upper region of the organic semiconductor pattern 23. At the same time as the channel is formed, the interface which is in contact with the junction region 30, that is, the lower region of the organic semiconductor pattern 23, has a state in which there is no charge such as a kind of depletion region (ie, an insulation state). As a result, the semiconductor device cannot operate normally because the organic semiconductor pattern 23 serving as the channel and the junction region 23 are electrically separated (or insulated). This can be solved by providing a bonding pattern 22A in contact with the sidewall of the organic semiconductor pattern 23.

The gate 28 may be a stacked structure in which the gate insulating layer 24, the first gate electrode 25, the second gate electrode 26, and the gate hard mask layer 27 are sequentially stacked. In this case, the gate insulating film 24 and the gate hard mask film may be formed of any single film selected from the group consisting of an oxide film, a nitride film, and an oxynitride film, or a stacked film in which they are stacked. The first gate electrode 25 may be formed of a silicon film, and the second gate electrode 26 may be formed of a metallic film.

Here, the sidewalls of the gate 28 are preferably formed to be aligned with the interface between the junction pattern 22A and the organic semiconductor pattern 23. This allows the entire organic semiconductor pattern 23 to act as a channel due to the bias applied to the gate 28, and at the same time prevents the gate insulating film 24 from remaining on the junction pattern 22A, thereby increasing the parasitic capacitance. For sake.

In addition, the semiconductor device according to the embodiment may further include a threshold voltage regulating layer 31 formed on the substrate 21 under the gate 28 and spacers 29 formed on both sidewalls of the gate 28. . In this case, the bonding pattern 22A may have a shape interposed between the spacer 29 and the substrate 21.

The semiconductor device according to the embodiment of the present invention having the above-described structure includes the organic semiconductor pattern 23 so that leakage current, in particular, GIDL current is generated even when a bias is applied to the junction region 30 in the off state. It can prevent. In addition, even if the impurity doping concentration of the threshold voltage adjusting layer 31 is increased to adjust the threshold voltage of the semiconductor device, it is possible to prevent the GIDL current from occurring.

4A through 4E are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

As shown in FIG. 4A, the threshold voltage adjusting layer 31 for controlling the threshold voltage is formed by implanting impurities into the entire surface of the substrate 21.

Next, the bonding pattern 22 is formed on the substrate 21. In this case, the junction pattern 22 serves to connect the junction region to be formed on the substrate and the organic semiconductor pattern through a subsequent process and at the same time serves as a junction for the organic semiconductor pattern. Accordingly, the bonding pattern 22 is positioned on the region where the substrate 21 is to be bonded, and the bonding pattern 22 is not positioned on the region to be gated of the substrate 21.

The bonding pattern 22 may be formed through a series of processes of forming a conductive film on the substrate 21 and then patterning the conductive film so that the conductive film does not remain on the substrate 21 in the gate predetermined region. In this case, the bonding pattern 22 may be formed of a silicon film, a metal film, or the like, which is a conductive material.

As shown in FIG. 4B, the organic semiconductor pattern 23 is formed between the junction patterns 22 so that the sidewalls contact the sidewalls of the junction pattern 22. In this case, the organic semiconductor pattern 23 may be positioned on the substrate 21 in the predetermined region of the gate and may be formed such that one sidewall of the organic semiconductor pattern 23 is in contact with the sidewall of the bonding pattern 22. .

The organic semiconductor pattern 23 may be formed on the entire surface of the gate predetermined area, or may be formed on the substrate 21 at both edges of the gate predetermined area.

Here, the organic semiconductor pattern 23 serves to prevent the GIDL current from being generated in the off state and acts as a channel in the on state. Therefore, the organic semiconductor pattern 23 is preferably formed to have a conductivity type complementary to the substrate 21. For example, in the case of NMOS, the substrate 21 may be P, the organic semiconductor pattern 23 may be N-type, and in the case of PMOS, the substrate 21 may be N-type and the organic semiconductor pattern 23 may be P-type.

As the organic semiconductor pattern 23, a perylene diimide derivative having an N-type conductivity and a pentacene (Pentacene) or a phthalocyanine (Phthalocyanine) having a conductivity type P may be used.

As shown in FIG. 4C, the gate 28 is formed on the substrate 21 so that both edges cover (or overlap) the organic semiconductor pattern 23. In this case, the sidewalls of the gate 28 may be formed to be aligned with the interface between the junction pattern 22 and the organic semiconductor pattern 23. This allows the entire organic semiconductor pattern 23 to act as a channel due to a bias applied to the gate 28, and at the same time prevents the gate insulating layer 24 from remaining on the junction pattern 22 to increase the parasitic capacitance. For sake.

The gate 28 may be formed as a stacked structure in which the gate insulating layer 24, the first gate electrode 25, the second gate electrode 26, and the gate hard mask layer 27 are sequentially stacked. In this case, the gate insulating film 24 and the gate hard mask film may be formed of any single film selected from the group consisting of an oxide film, a nitride film, and an oxynitride film, or a stacked film in which they are stacked. The first gate electrode 25 may be formed of a silicon film, and the second gate electrode 26 may be formed of a metallic film.

As shown in FIG. 4D, a spacer insulating film (not shown) is formed along the surface of the structure including the gate 28, and then an entire surface etching process, for example, an etchback is performed, on both side walls of the gate 28. While forming the spacer 29, the junction pattern 22 is etched to expose the substrate 21 on both sides of the gate 28. Hereinafter, the reference numeral of the etched bonding pattern 22 is changed to '22A' and described.

Here, the reason for exposing the substrate 21 by partially etching the bonding pattern 22A while forming the spacer 29 is to facilitate the subsequent bonding region forming process. If the substrate 21 is not exposed by partially etching the junction pattern 22A, the difficulty of the impurity ion implantation process for forming subsequent junction regions may increase, which may reduce the characteristics and productivity of the semiconductor device. .

As shown in FIG. 4E, the junction region 30 is formed in the substrate 21 on both sides of the gate 28. In this case, the junction region 30 may be formed by implanting impurity ions and heat treatment, and the junction region 30 may be formed of the junction pattern 22A, the organic semiconductor pattern 23, and the gate due to diffusion of impurities implanted during the heat treatment process. It may have a structure in which part 28 and some or all overlap.

The junction region 30 is preferably formed to have the same conductivity type as the substrate 21 and the organic semiconductor pattern 23. For example, in the case of NMOS, the junction region 30 and the organic semiconductor pattern 23 may be N-type, and the substrate 21 may be P-type. In the case of PMOS, the junction region 30 and the organic semiconductor pattern 23 may be P-type. The substrate 21 may be N-type.

The semiconductor device according to the embodiment of the present invention formed through the above-described process includes an organic semiconductor pattern 23, so that a leakage current, in particular, a GIDL current is generated even when a bias is applied to the junction region 30 in an off state. Can be effectively prevented. In addition, even if the impurity doping concentration of the threshold voltage adjusting layer 31 is increased to adjust the threshold voltage of the semiconductor device, it is possible to prevent the GIDL current from occurring.

Although the technical spirit of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will appreciate that various embodiments within the scope of the technical idea of the present invention are possible.

1 is a cross-sectional view showing a semiconductor device according to the prior art.

Figure 2 is a graph for explaining the electrical properties of the organic semiconductor.

3 is a cross-sectional view illustrating a semiconductor device in accordance with an embodiment of the present invention.

4A through 4E are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

* Description of symbols on the main parts of the drawings *

21: substrate 22, 22A: bonding pattern

23 organic semiconductor pattern 24 gate insulating film

25: first gate electrode 26: second gate electrode

27: gate hard mask film 28: gate

29 spacer 30 junction area

31: threshold voltage control layer

Claims (19)

A gate on the substrate; An organic semiconductor pattern interposed between the substrate and the gate; A junction region formed on both sides of the gate and partially overlapping the organic semiconductor pattern; And A junction pattern in contact with a sidewall of the organic semiconductor pattern on the junction region A semiconductor device comprising a. The method of claim 1, The organic semiconductor pattern is disposed on the substrate and is interposed between the substrate and edges on both sides of the gate. The method of claim 1, And a boundary surface between the organic semiconductor pattern and the junction pattern and the gate sidewall. The method of claim 1, And the substrate and the organic semiconductor pattern have a conductivity type complementary to each other. The method according to claim 1 or 4, And the organic semiconductor pattern and the junction region have the same conductivity type. The method of claim 1, The organic semiconductor pattern includes a pentacene (Pentacene) and phthalocyanine (Phthalocyanine) of the conductivity type. The method of claim 1, The organic semiconductor pattern includes a perylene diimide derivative having a conductivity type of N type. The method of claim 1, A threshold voltage control layer formed on the substrate under the gate; And Spacers formed on both sidewalls of the gate The semiconductor device further comprising. The method of claim 8, The bonding pattern is a semiconductor device interposed between the spacer and the substrate. Forming a bonding pattern on the substrate; Forming an organic semiconductor pattern between the bonding patterns; Forming a gate on the substrate to cover the organic semiconductor pattern; And Forming a junction region on the substrate under the junction pattern on both sides of the gate to partially overlap the organic semiconductor pattern Semiconductor device manufacturing method comprising a. The method of claim 10, And forming a threshold voltage control layer on the substrate before forming the junction pattern. The method according to claim 10 or 11, wherein Before forming the junction region Forming spacers on both sidewalls of the gate; And Etching the bonding pattern using the spacer as an etch barrier A semiconductor device manufacturing method further comprising. The method of claim 10, Forming the organic semiconductor pattern, A semiconductor device manufacturing method, wherein any one sidewall is formed to be bonded to the sidewall of the junction pattern. The method of claim 10, And the organic semiconductor pattern is formed between the substrate and edges on both sides of the gate. The method of claim 10, Forming the gate, And forming a boundary surface between the gate sidewall and the organic semiconductor pattern and the junction pattern to be aligned with each other. The method of claim 10, And the substrate and the organic semiconductor pattern are formed to have a complementary conductivity type. The method according to claim 10 or 16, And the organic semiconductor pattern and the junction region are formed to have the same conductivity type as each other. The method of claim 10, The organic semiconductor pattern is a semiconductor device manufacturing method comprising a pentacene (Pentacene), phthalocyanine (Phthalocyanine) of the conductivity type. The method of claim 10, The organic semiconductor pattern is a semiconductor device manufacturing method comprising a perylene diimide derivative of the conductivity type N-type.

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