KR19990051079A - Manufacturing Method of Power Device Using Insulating Film Inclined Etching - Google Patents
Manufacturing Method of Power Device Using Insulating Film Inclined Etching Download PDFInfo
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- KR19990051079A KR19990051079A KR1019970070318A KR19970070318A KR19990051079A KR 19990051079 A KR19990051079 A KR 19990051079A KR 1019970070318 A KR1019970070318 A KR 1019970070318A KR 19970070318 A KR19970070318 A KR 19970070318A KR 19990051079 A KR19990051079 A KR 19990051079A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 19
- 238000005530 etching Methods 0.000 title claims description 7
- 238000000034 method Methods 0.000 claims abstract description 28
- 238000001039 wet etching Methods 0.000 claims abstract description 11
- 239000010408 film Substances 0.000 claims description 83
- 229920002120 photoresistant polymer Polymers 0.000 claims description 8
- 239000012535 impurity Substances 0.000 claims description 7
- 238000000206 photolithography Methods 0.000 claims description 6
- 150000002500 ions Chemical class 0.000 claims description 5
- 230000000873 masking effect Effects 0.000 claims description 5
- 239000010409 thin film Substances 0.000 claims description 5
- 239000000758 substrate Substances 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims 1
- 230000005684 electric field Effects 0.000 abstract description 5
- 239000011229 interlayer Substances 0.000 abstract description 5
- 238000009413 insulation Methods 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 15
- 230000015556 catabolic process Effects 0.000 description 9
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 9
- 229920005591 polysilicon Polymers 0.000 description 7
- 238000009792 diffusion process Methods 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 239000012212 insulator Substances 0.000 description 3
- 150000004767 nitrides Chemical class 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 230000001737 promoting effect Effects 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
본 발명은 고전압 전력소자로서 표류영역(drift region)내에 있는 게이트 확장영역(gate extended region, 도 1의 'Le' 영역)의 절연막을 경사형 구조로 하는 LDMOS(lateral double diffused MOS) 소자 제작공정에 대한 것이다. 일반적으로 LDMOS를 이용하여 구동 IC를 제작할 경우 게이트 산화막은 p채널 LDMOS의 경우 두꺼운 반면에, n채널 LDMOS는 얇은 산화막을 갖는다. 따라서 신뢰성 측면에서 얇은 산화막을 갖는 n채널 LDMOS의 경우, n 표류영역내에 있는 게이트 확장영역의 산화막은 소자동작시 높은 전계에 의해 게이트 산화막의 파괴가 쉽게 일어난다. 본 발명에서는 이러한 종래의 고전압 전력소자의 문제점을 해결하기 위해 n채널 LDMOS의 게이트 확장영역에서의 얇은 게이트 산화막위에 저온 산화막을 증착하여 습식식각으로 절연막을 경사지게 함으로서 고전계에 의한 게이트 확장영역의 절연 파괴특성을 개선하였다. 아울러 층간절연막의 단차를 줄이고 p채널 LDMOS 공정과 함께 제작할 수 있는 고전압 전력소자 제조공정법을 제시하였다.The present invention relates to a process for fabricating a lateral double diffused MOS (LDMOS) device having an insulated structure of an insulating film of a gate extended region (“Le” region of FIG. 1) in a drift region as a high voltage power device. It is about. In general, when the driving IC is manufactured using LDMOS, the gate oxide film is thicker than the p-channel LDMOS, whereas the n-channel LDMOS has a thin oxide film. Therefore, in the case of n-channel LDMOS having a thin oxide film in terms of reliability, the oxide film of the gate extension region in the n-drift region easily breaks the gate oxide film due to a high electric field during device operation. In the present invention, in order to solve the problem of the conventional high voltage power device, the low-temperature oxide film is deposited on the thin gate oxide film in the gate extension region of the n-channel LDMOS to insulate the insulating film by wet etching, thereby destroying the insulation of the gate extension region by the high electric field. Improved properties. In addition, a method of fabricating a high voltage power device capable of reducing the step difference between interlayer insulating films and fabricating with a p-channel LDMOS process is presented.
Description
본 발명은 PDP 및 FED의 구동 IC에 사용될수 있는 고전압 전력소자로서 표류영역(drift region)내에 있는 게이트 확장영역의 절연막 경사식각공정을 사용하여 제작한 LDMOS(lateral double diffused MOS) 소자 제조공정에 관한 것이다.The present invention relates to a process for fabricating a lateral double diffused MOS (LDMOS) device fabricated using an insulator etch process of an insulating film of a gate extension region in a drift region as a high voltage power device that can be used in driving ICs of PDP and FED. will be.
LDMOS는 100V용 전력구동 IC에 적용할 때에, 게이트 산화막은 p채널 LDMOS의 경우 약 1500∼3000Å 두께로 두꺼운 반면에 n채널 LDMOS는 약 200∼300Å 두께로 얇은 산화막을 갖는다. 따라서 얇은 산화막을 갖는 n채널 LDMOS는 게이트 확장영역의 산화막이 소자동작시 높은 전계에 의해 절연 파괴가 쉽게 일어나며, 소자의 신뢰성은 급격히 저하된다.When the LDMOS is applied to a 100V power driving IC, the gate oxide film is thick with a thickness of about 1500 to 3000 mW for the p-channel LDMOS, while the n-channel LDMOS has a thin oxide film about 200 to 300 mW. Therefore, in the n-channel LDMOS having a thin oxide film, dielectric breakdown occurs easily due to a high electric field when the oxide film in the gate extension region is operated, and the reliability of the device is drastically reduced.
도 1은 종래의 제조공정으로 제작된 고전압용 LDMOS의 단면도를 나타낸 것이다.1 is a cross-sectional view of a high voltage LDMOS fabricated by a conventional manufacturing process.
100V용 전력 구동 IC의 경우, 게이트 절연막은 p채널 LDMOS를 위해 고온산화막을 약 1500∼3000Å 두께로 성장시킨 다음 사진전사공정을 이용하여 n채널 LDMOS에 성장된 두꺼운 산화막을 제거시킨 다음, 약 200∼300Å 두께의 얇은 산화막을 성장시킨후 다결정실리콘으로 게이트 패턴을 형성시킨다. 따라서 n채널 LDMOS는 n 표류영역내에 있는 게이트 확장영역(Le 영역)의 산화막에서 고전계가 인가될 때에 절연파괴가 쉽게 일어나는 취약한 부분으로 남게 된다.In the case of the 100V power driving IC, the gate insulating film is a high temperature oxide film grown to a thickness of about 1500 to 3000Å for the p-channel LDMOS, and then a thick oxide film grown on the n-channel LDMOS is removed using a photolithography process, and then about 200 to A 300 Å thick thin oxide film is grown, and then a gate pattern is formed of polysilicon. Therefore, the n-channel LDMOS remains a fragile portion where insulation breakdown occurs easily when a high field is applied to the oxide film of the gate extension region (Le region) in the n-drift region.
이와같이 종래에는 n 채널 LDMOS의 게이트 확장영역은 채널영역의 절연막 두께와 동일하게 하였다. 그리고 다결정실리콘의 게이트 패턴은 게이트 채널영역 및 게이트 확장영역, n표류영역내의 필드산화막의 일부영역까지 포함한다. 여기서 n채널 LDMOS의 게이트 확장영역은 고전계가 인가될 때에 신뢰성 측면에서 절연파괴가 일어나는 취약한 부분으로 남게 된다. 그리고 n채널 및 p채널 LDMOS를 동시에 제작할 때에 서로 다른 게이트 산화막 두께로 인해 공정상에서 층간 절연막의 단차가 매우 큰 단점이 있다.As described above, the gate extension region of the n-channel LDMOS is made equal to the thickness of the insulating layer of the channel region. The gate pattern of the polysilicon includes the gate channel region, the gate extension region, and even a partial region of the field oxide film in the n-drift region. Here, the gate extension region of the n-channel LDMOS remains a weak part in which dielectric breakdown occurs in terms of reliability when a high field is applied. In addition, when the n-channel and p-channel LDMOS are simultaneously manufactured, there are disadvantages in that the step difference between the interlayer insulating layers is very large due to different gate oxide thicknesses.
본 발명의 목적은 n채널 및 p채널 LDMOS를 제작하는 제조공정법으로서 n채널 LDMOS의 게이트 확장영역의 절연막을 경사형 구조로 함으로서, 종래의 소자공정으로 제작된 전력소자가 갖는 게이트 확장영역에서의 고전압에 의한 절연 파괴현상을 개선하여 궁극적으로 소자의 신뢰성을 개선하기 위함이다.SUMMARY OF THE INVENTION An object of the present invention is to fabricate an n-channel and p-channel LDMOS, in which the insulating film of the gate extension region of the n-channel LDMOS is inclined to form a high voltage in the gate extension region of a power device manufactured by a conventional device process. This is to improve the dielectric breakdown phenomenon and ultimately improve the reliability of the device.
본 발명에서는 n채널 LDMOS의 게이트 확장영역의 산화막위에 저온 절연막을 증착하여 습식식각으로 경사지게 함으로서 게이트 확장영역내에서의 절연파괴특성을 개선시켰으며, 동시에 층간절연막의 단차를 줄이고 p채널 LDMOS공정과 함께 제작할수 있는 고전압 전력소자 제조방법을 제공한다.In the present invention, a low-temperature insulating film is deposited on the oxide film of the gate extension region of the n-channel LDMOS to be inclined by wet etching, thereby improving the dielectric breakdown characteristics in the gate extension region, and at the same time reducing the step difference between the interlayer dielectric layers and the p-channel LDMOS process. It provides a high voltage power device manufacturing method that can be manufactured.
본 발명은 n 채널 LDMOS에서 n표류영역내의 게이트 확장영역상의 절연막을 경사지게하는 것이 중요한 기술적 과제이다. 이를 구현하기 위해 도 2에서 제시한 바와 같이 저온절연막을 증착하여 습식식각으로 게이트 확장영역의 절연막을 경사지게 식각을 한후, n 채널 LDMOS의 채널영역에 200∼300Å 두께의 게이트 산화막을 형성하여 다결정실리콘으로 게이트 패턴을 형성시키는 것이 중요한 공정기술과제이다.In the present invention, it is an important technical problem to incline the insulating film on the gate extension region in the n-drift region in the n-channel LDMOS. To implement this, as shown in FIG. 2, a low-temperature insulating film is deposited to wet-etch the insulating film of the gate extension region by wet etching, and then a gate oxide film having a thickness of 200 to 300 에 is formed in the channel region of the n-channel LDMOS to form polycrystalline silicon. Forming a gate pattern is an important process technology challenge.
도 1은 종래의 제조공정에 의해 제작된 전력소자의 단면도.1 is a cross-sectional view of a power device manufactured by a conventional manufacturing process.
도 2는 본 발명에 의한 절연막 경사식각을 이용하여 제작된 전력소자의 단면도.2 is a cross-sectional view of a power device fabricated using an insulator etched in accordance with the present invention.
도 3의 (a) 내지 (g)는 본 발명에서 제시된 절연막 경사식각을 이용한 전력소자의 제조 공정 순서도.Figure 3 (a) to (g) is a flow chart of the manufacturing process of the power device using the insulating film gradient etching presented in the present invention.
＜도면의 주요부분에 대한 부호의 설명＞<Description of the code | symbol about the principal part of drawing>
1 : p형 실리콘기판(p type silicon substrate)1: p type silicon substrate
2 : p 에피층(p epitaxial layer)2: p epitaxial layer
3 : 깊은 n웰 영역(deep n well region)3: deep n well region
4 : p 표류영역(p drift region)4: p drift region
5 : n 표류영역(n drift region)5: n drift region
6 : n웰영역(n well region)6: n well region
7 : p웰영역(p well region)7: p well region
8 : 완충 산화막(Buffer oxide layer)8: buffer oxide layer
9 : 질화막(Silicon nitride layer)9: silicon nitride layer
10 : 필드 산화막(Field oxide layer)10: Field oxide layer
11, 11a : 1차 게이트 산화막(1stgate oxide layer)11, 11a: 1 st gate oxide layer
12 : 게이트 저온 절연막(Gate low temperature insulator layer)12: Gate low temperature insulator layer
13 : 2차 게이트 산화막(2ndgate oxide layer)13: the second gate oxide film (gate oxide layer 2 nd)
14 : 감광막(Photoresister)14: Photoresister
15 : 다결정실리콘 게이트 패턴(Polysilicon gate pattern)15 polysilicon gate pattern
16, 16a, 16b : p+확산영역(p+diffused region)16, 16a, 16b: p + diffusion region (p + diffused region)
17, 17a, 17b : n+확산영역(n+diffused region)17, 17a, 17b: n + diffusion region (n + diffused region)
18 : 층간 절연막(Interlayer dielectrics)18: interlayer dielectrics
19 : 소오스 전극(Source electrode)19 source electrode
20 : 게이트 전극(Gate electrode)20: Gate electrode
21 : 드레인 전극(Drain electrode)21: drain electrode
도 2는 본 발명에 의한 n채널 LDMOS에서 게이트 확장영역의 절연막을 습식식각으로 경사지게한 소자의 단면도를 나타낸 것이다.2 is a cross-sectional view of a device in which an insulating film of a gate extension region is inclined by wet etching in an n-channel LDMOS according to the present invention.
본 발명에서는 먼저 p채널 LDMOS에 약 300∼1000Å 두께의 1차 게이트 산화막(11)을 형성시킨 다음 약 1000∼3000Å 두께의 게이트 절연막(12)을 증착시킨다.In the present invention, a first gate oxide film 11 having a thickness of about 300 to 1000 Å is formed on a p-channel LDMOS, and then a gate insulating film 12 having a thickness of about 1000 to 3,000 Å is deposited.
이어서 사진전사공정을 이용하여 p채널 LDMOS영역과 n채널 게이트 확장영역의 절연막(12) 및 필드 산화막(10)의 일부영역을 감광막으로 마스킹 한 다음, 습식식각법을 이용하여 n채널 LDMOS 영역의 게이트 저온 절연막(12)을 경사지게 식각한다.Subsequently, a portion of the insulating layer 12 and the field oxide layer 10 of the p-channel LDMOS region and the n-channel gate extension region is masked with a photoresist using a photolithography process, and then the gate of the n-channel LDMOS region is wet-etched. The low temperature insulating film 12 is etched obliquely.
이후 n채널 LDMOS에 200∼300Å 두께의 2차 게이트 산화막(13)을 형성한후 다결정실리콘으로 게이트 패턴을 형성시킨 구조이다.After that, a second gate oxide film 13 having a thickness of 200 to 300 에 is formed on the n-channel LDMOS, and a gate pattern is formed of polysilicon.
따라서 본 발명으로 제작된 고전압 전력소자는 n채널 LDMOS에서 게이트 확장영역의 절연막을 경사지게 함으로써 고전계에 의한 절연파괴를 방지하여 소자의 신뢰성을 높일수 있다. 또한 경사진 절연막을 얻기 위해 저온절연막 증착 및 습식식각법을 사용함으로서 종래의 제조공정으로 제작된 소자구조보다 층간 단차를 줄일수 있다.Therefore, the high voltage power device manufactured according to the present invention can increase the reliability of the device by preventing the dielectric breakdown caused by the high electric field by inclining the insulating film of the gate extension region in the n-channel LDMOS. In addition, by using the low temperature insulating film deposition and wet etching method to obtain the inclined insulating film, it is possible to reduce the step difference between the device structure manufactured by the conventional manufacturing process.
본 발명에서는 도 2에서 제시한 바와 같이, n 채널 LDMOS의 경우 다결정실리콘으로 이루어진 게이트 영역은, 채널영역의 얇은 게이트 산화막과 n표류영역에서의 게이트 확산영역(도 2의 'Le ' 영역)의 얇은 산화막 및 경사형 절연막구조, 그리고 n표류영역내에서의 필드산화막위의 저온 절연막의 일부분까지를 포함한다.In the present invention, as shown in FIG. 2, in the case of n-channel LDMOS, a gate region made of polysilicon is formed by a thin gate oxide film of a channel region and a thin gate diffusion region ('Le' region of FIG. 2) in an n-drift region. Up to a part of the low-temperature insulating film on the field oxide film in the n-drift region.
아울러 p채널 LDMOS의 경우 다결정실리콘의 게이트 영역은 게이트 채널영역 및 게이트 확장영역에서의 고온산화막과 저온 절연층으로, 그리고 p표류영역내에서의 필드산화막위의 저온 절연막의 일부분까지 구성된다.In the case of the p-channel LDMOS, the gate region of the polysilicon is composed of a high temperature oxide film and a low temperature insulating layer in the gate channel region and a gate extension region and a part of the low temperature insulating film on the field oxide film in the p-drift region.
여기서 n채널 LDMOS의 경사형 절연막 구조를 구현함으로서 게이트 확장영역의 절연막이 종래의 소자 채널영역의 산화막 두께와 동일한 전력소자에 비해 소자동작시 on 상태에서 고전압에서의 절연파괴 특성을 개선할 수 있다.Here, by implementing the inclined insulating layer structure of the n-channel LDMOS, the dielectric breakdown characteristic at the high voltage can be improved in the on state during the device operation, compared to the power device in which the insulating film in the gate extension region is the same as the oxide film thickness of the conventional device channel region.
또한 저온 절연막공정으로 p채널 LDMOS 공정과 함께 제작이 가능하며, 습식식각을 사용함으로서 박막단차를 줄일수 있는 장점이 있다. 고전압 전력소자로서 종래의 전력소자와 마찬가지로 RESURF(reduced surface field) 효과를 촉진시켜 높은 항복전압이 유지되며, 낮은 on 저항을 얻을수 있다.In addition, the low temperature insulating film process can be manufactured together with the p-channel LDMOS process, and it has the advantage of reducing the thin film step by using wet etching. As a high voltage power device, as in a conventional power device, a high breakdown voltage is maintained by promoting a reduced surface field (RESURF) effect, and a low on resistance can be obtained.
도 3의 (a) 내지 (g)는 본 발명에 의한 경사진 게이트 절연막 구조를 갖는 LDMOS의 바람직한 실시예를 나타낸 것으로, 제조공정을 (a)∼(g)에 단계적으로 기술하였다. 실시예로 설명한 제조공정은 n채널 LDMOS 및 p채널 LDMOS를 동시에 제작할 수 있는 공정이다.3 (a) to (g) show a preferred embodiment of an LDMOS having an inclined gate insulating film structure according to the present invention, and the manufacturing process is described step by step in (a) to (g). The manufacturing process described as an embodiment is a process that can simultaneously produce n-channel LDMOS and p-channel LDMOS.
도 3의 (a)에 도시된 바와 같이, 일반적인 LDMOS 제조공정법을 이용하여 p형 실리콘 기판(1) 위에 낮은 농도의 p 에피층(2)을 형성한 후, 사진전사 및 식각공정, 불순물 이온주입 및 고온 열처리공정등으로 p채널 LDMOS가 형성될 영역에 깊은 n웰(well)(3)을 형성시킨다. 이후, 불순물 농도를 높여 채널영역인 n웰 영역(6)과, p표류영역(4)을 형성하고, n채널 LDMOS 제작을 위해 p웰 영역(7)과 n표류영역(5)을 형성시킨다.As shown in (a) of FIG. 3, after forming a low concentration of the p epi layer 2 on the p-type silicon substrate 1 by using a general LDMOS manufacturing method, a photo transfer, etching process, impurity ions Deep n wells 3 are formed in regions where p-channel LDMOS is to be formed by implantation and high temperature heat treatment processes. Thereafter, the impurity concentration is increased to form the n well region 6 and the p drifting region 4 as the channel region, and the p well region 7 and the n drifting region 5 are formed to fabricate the n-channel LDMOS.
이어서, 완충 산화막(8)을 성장시키고, 질화막(9)을 증착시킨다. 이어서 소자간의 격리 및 표류영역에 필드 산화막을 형성시키기 위해 그 부분을 사진전사공정 및 건식식각으로 질화막(9)을 제거한다.Next, the buffer oxide film 8 is grown, and the nitride film 9 is deposited. Subsequently, in order to form a field oxide film in the isolation and drift region between the elements, the nitride film 9 is removed by photolithography and dry etching.
도 3의 (b)에 도시된 바와 같이, 필드 산화막(10)을 성장시킨 후 질화막(9)과 완충 산화막(8)을 제거하고, 얇은 두께의 산화막을 성장시킨 후 p채널 LDMOS의 문턱전압 조절을 위해 p채널 영역을 제외한 모든 영역을 마스킹하여 n형 불순물으로서 이온주입을 한후, 얇은 산화막을 제거한다. 다시 약 300∼1000Å 두께의 1차 게이트 산화막(11)을 성장시킨다. 이어서 p채널 LDMOS의 두꺼운 게이트 절연막 형성을 위해 저온 절연막(12)을 약 1000∼2000Å 두께로 증착시킨 후, 사진전사공정으로 p채널 LDMOS 영역과 n채널 LDMOS의 게이트 확장부분과 필드산화막의 일부영역을 감광막(14)으로 마스킹한다.As shown in FIG. 3B, after the field oxide film 10 is grown, the nitride film 9 and the buffer oxide film 8 are removed, a thin oxide film is grown, and the threshold voltage of the p-channel LDMOS is controlled. For this purpose, all regions except the p-channel region are masked and ion implanted as n-type impurities, and then the thin oxide film is removed. Again, a primary gate oxide film 11 of about 300 to 1000 microns thick is grown. Subsequently, the low-temperature insulating film 12 is deposited to a thickness of about 1000 to 2000 microseconds to form a thick gate insulating film of the p-channel LDMOS, and then the p-channel LDMOS region, the gate extension portion of the n-channel LDMOS region, and a partial region of the field oxide film are deposited by a photo transfer process. Masked with the photosensitive film 14.
도 3의 (c)에 도시된 바와 같이, 습식식각법을 이용하여 n채널 LDMOS의 저온 절연막(12)을 식각한다. 이때 습식식각 용액은 식각비가 낮은 용액(dilute solution)을 선택한다. 여기서 저온 절연막(12)은 단일 박막이거나 서로 식각비가 다른 다층 절연막을 사용할 수 있다. 결과적으로 n채널 LDMOS의 게이트 확장영역(도 2의 'Le' 영역)은 경사진 절연막 구조를 갖게된다. 이어서 감광막(14)을 제거한후 얇은 두께의 산화막을 성장하고, p채널 LDMOS 영역을 마스킹하여 n채널 LDMOS의 문턱전압을 조절을 위해 n채널 영역을 제외한 모든 영역을 마스킹하여 p형 불순물로서 이온주입을 한후, 감광막을 제거시킨다.As shown in FIG. 3C, the low temperature insulating film 12 of the n-channel LDMOS is etched by using a wet etching method. In this case, the wet etching solution selects a dilute solution having a low etching ratio. Here, the low temperature insulating film 12 may be a single thin film or a multilayer insulating film having different etching ratios from each other. As a result, the gate extension region (the 'Le' region in FIG. 2) of the n-channel LDMOS has an inclined insulating film structure. Subsequently, after removing the photoresist film 14, a thin oxide film is grown, and all regions except the n-channel region are masked to control the threshold voltage of the n-channel LDMOS by masking the p-channel LDMOS region. After that, the photoresist film is removed.
도 3의 (d)에 도시된 바와 같이, 다결정 실리콘(15)을 증착한후 n형 불순물로 도핑(doping)을 한후, p채널 및 n채널 LDMOS의 다결정실리콘 게이트 패턴(15)을 사진전사공정 및 식각공정으로 형성한다.As shown in (d) of FIG. 3, after the polycrystalline silicon 15 is deposited and doped with n-type impurities, the polysilicon gate patterns 15 of the p-channel and n-channel LDMOS are photo transferred. And an etching process.
도 3의 (e)에 도시된 바와 같이, 사진전사공정으로 n채널 LDMOS영역을 감광막(14)으로 마스킹한 후, p채널 LDMOS 영역의 소오스/드레인이 형성될 활성영역상의 두꺼운 산화막을 건식식각한다. 이어서 감광막(14)을 제거하고 얇은 산화막을 성장시킨다.As shown in FIG. 3 (e), after masking the n-channel LDMOS region with the photoresist film 14 by a photolithography process, dry-etch a thick oxide film on the active region where the source / drain of the p-channel LDMOS region is to be formed. . Subsequently, the photosensitive film 14 is removed and a thin oxide film is grown.
도 3의 (f)에 도시된 바와 같이, p채널 LDMOS의 소오스 영역(16,17) 및 드레인 영역(16a), n채널 LDMOS의 소오스 영역(16b,17a) 및 드레인 영역(17b) 형성을 위해 n형 및 p형의 불순물을 이온주입하여 각각 n+영역 및 p+영역을 형성한다. 이어서 열처리 공정을 한후 저온에서 층간 절연막(18)을 증착시킨다.As shown in FIG. 3 (f), the source regions 16 and 17 and the drain region 16a of the p-channel LDMOS, the source regions 16b and 17a and the drain region 17b of the n-channel LDMOS are formed. N-type and p-type impurities are ion implanted to form n + region and p + region, respectively. Subsequently, after the heat treatment process, the interlayer insulating film 18 is deposited at a low temperature.
도 3의 (g)에 도시된 바와 같이, 사진전사공정 및 건식식각공정으로 콘택영역(contact region)을 형성한후 금속박막을 증착시킨다. 이어서 사진전사공정 및 건식식각공정으로 금속배선패턴을 형성하고 열처리공정을 행하면, 본 발명에서 제시한바와 같이 소오스 전극(19), 게이트 전극(20) 및 드레인 전극(21)을 갖는 고전압 전력소자인 n채널 및 p채널 LDMOS가 제작된다.As shown in (g) of FIG. 3, a contact region is formed by a photolithography process and a dry etching process, and then a metal thin film is deposited. Subsequently, when the metal wiring pattern is formed and the heat treatment step is performed by the photo transfer process and the dry etching process, n, which is a high voltage power device having a source electrode 19, a gate electrode 20, and a drain electrode 21, as shown in the present invention. Channel and p-channel LDMOS are fabricated.
본 발명은 고전압 전력소자에서 문제가 되고있는 고전계에 의한 게이트 확장영역에서의 절연막 파괴현상을 해결함으로서 소자의 신뢰성을 높일수 있다. 또한 저온 절연막을 습식 식각함으로서 박막의 단차(step coverage)를 줄일수 있는 잇점이 있으며, n채널 및 p채널 LDMOS 전력소자를 함께 제작할 수 있는 제조공정법이다. 그리고 본 발명을 통해 제작된 전력소자는 향후 PDP 및 FED 구동 IC등에 널리 적용될 수 있다.The present invention can improve the reliability of the device by solving the dielectric breakdown phenomenon in the gate extension region due to the high electric field which is a problem in the high voltage power device. In addition, the wet etching of the low-temperature insulating film has an advantage of reducing the step coverage of the thin film, and is a manufacturing process method for manufacturing the n-channel and p-channel LDMOS power devices together. The power device manufactured through the present invention may be widely applied to PDP and FED driving ICs in the future.
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| US6897117B2 (en) | 2001-08-10 | 2005-05-24 | Sanyo Electric Co., Ltd. | Method of manufacturing semiconductor device |
| JP2006128668A (en) * | 2004-10-27 | 2006-05-18 | Samsung Electronics Co Ltd | High voltage transistor and methods of manufacturing the same |
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| KR100953347B1 (en) | 2007-12-28 | 2010-04-20 | 주식회사 동부하이텍 | LDMOS semiconductor device mask |
| CN104681609B (en) * | 2013-12-03 | 2017-12-05 | 上海华虹宏力半导体制造有限公司 | A kind of n-type LDMOS device and its manufacture method |
| CN104681608B (en) * | 2013-12-03 | 2017-12-05 | 上海华虹宏力半导体制造有限公司 | The n-type LDMOS device and its manufacture method of a kind of high isolation |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US6897117B2 (en) | 2001-08-10 | 2005-05-24 | Sanyo Electric Co., Ltd. | Method of manufacturing semiconductor device |
| KR100508359B1 (en) * | 2001-08-10 | 2005-08-17 | 산요덴키가부시키가이샤 | Semiconductor device and manufacturing method thereof |
| JP2006128668A (en) * | 2004-10-27 | 2006-05-18 | Samsung Electronics Co Ltd | High voltage transistor and methods of manufacturing the same |
| KR100614806B1 (en) * | 2004-10-27 | 2006-08-22 | 삼성전자주식회사 | Transistor with high breakdown voltage and method of manufacturing the same |
| US7446387B2 (en) * | 2004-10-27 | 2008-11-04 | Samsung Electronics Co., Ltd. | High voltage transistor and methods of manufacturing the same |
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