KR101128696B1 - Method for manufacturing mos transistor - Google Patents

Abstract

The present invention is to provide a method for manufacturing a semiconductor device suitable for improving the hot carrier characteristics and reliability of the device, the MOS transistor manufacturing method of the present invention for this purpose is a semiconductor substrate; A gate pattern formed on the semiconductor substrate; A screen oxide layer formed along a profile of the semiconductor substrate and the gate pattern; A first spacer formed on a side of the gate pattern and formed of a high dielectric metal oxide film; A second spacer formed on the first spacer on the side of the gate pattern and formed of a silicon oxide film; And source / drain regions formed in the substrate on both sides of the gate pattern.

Spacer, high-k, LDD, MOS transistor

Description

MOS transistor manufacturing method {METHOD FOR MANUFACTURING MOS TRANSISTOR}

1 is a process cross-sectional view showing a MOS transistor manufacturing method according to the prior art,

2A to 2F are cross-sectional views illustrating a MOS transistor manufacturing method according to an embodiment of the present invention.

DESCRIPTION OF THE REFERENCE NUMERALS

21 semiconductor substrate 22 gate oxide film

23: gate conductive film 24: screen oxide film

25 titanium oxide film 26 LDD region

27 silicon oxide film 28 source / drain regions

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing techniques, and more particularly, to a MOS transistor manufacturing method, and more particularly, to the formation of a light doped drain (LDD) spacer of a highly integrated semiconductor device.

At present, as the degree of integration of semiconductor devices increases, the minimum line width of the gate is reduced from 0.25 µm to 0.1 µm for the purpose of speed improvement and miniaturization of the device. As the gate line width decreases, the threshold voltage decreases rapidly according to the short channel effect, and at the same time, the hot carrier effect occurs severely.

Since the short channel and hot carrier effects are related to the depth of the junction region into which impurities are implanted, a MOS transistor having a shallow depth of the junction region is required. For this purpose, a MOS transistor having a light doped drain (LDD) structure in which impurities are injected at low concentrations in the gate edge portion has emerged.

As the MOS transistor of the LDD structure becomes smaller, it is difficult to adjust the threshold voltage according to the short channel length. Must be reduced. Accordingly, when the impurity concentration in the channel region is increased to increase the concentration of the substrate, the operation of the device is difficult because the threshold voltage becomes too high. have.

1 is a process sectional view showing a MOS transistor manufacturing method according to the prior art.

As shown in FIG. 1, the gate oxide film 12 is grown on the semiconductor substrate 11 on which the device isolation film (not shown) is formed by thermal oxidation.

Subsequently, a polysilicon film is deposited on the gate oxide film by the gate conductive film 13. Next, a mask pattern (not shown) for patterning the gate electrode is formed on the gate conductive film 13, and the gate conductive film 13 and the gate oxide film 12 are sequentially patterned using the mask pattern as an etch barrier. A gate pattern is formed.

Subsequently, in order to recover the etch damage of the semiconductor substrate 11 caused in the patterning process for forming the gate pattern, and to prevent the semiconductor substrate 11 from being damaged due to the source and drain ion implantation. The oxidation process which thermally forms the screen oxide film 14 on it is performed.

Next, low concentration LDD ion implantation is performed to form the LDD region 15.

Subsequently, a spacer CVD oxide film (SiO ₂ ) and a silicon nitride film (Si ₃ N ₄ ) are stacked and formed on the entire surface of the semiconductor substrate 11, and spacer etching is performed to form the LDD spacer 16 on the side of the gate pattern.

Next, high concentration ion implantation is performed to form the source / drain regions 17.

As described above, in the prior art, the LDD spacer is subjected to a strong electric field at the gate edge of the drain. To this end, a double spacer of silicon nitride and silicon oxide is usually formed. As a result, a phenomenon such as hot carrier and short channel effects may occur, thereby degrading reliability and drivability of the device.

The present invention has been proposed to solve the above problems of the prior art, and an object thereof is to provide a MOS transistor manufacturing method suitable for improving hot carrier characteristics and device reliability.

In order to achieve the above object, a MOS transistor of the present invention has a semiconductor substrate, a gate pattern formed on the semiconductor substrate, a screen oxide film formed along the profile of the semiconductor substrate and the gate pattern, and formed on a side of the gate pattern. And a first spacer formed of an all-metal oxide film, a second spacer formed on the first spacer on the side of the gate pattern, and a source / drain region formed in a substrate on both sides of the gate pattern.

In addition, the present invention comprises the steps of forming a gate pattern in which a gate insulating film, a gate conductive film is sequentially stacked on a semiconductor substrate, performing a gate oxidation on the entire surface including the gate pattern to form a screen oxide film, the side of the gate pattern Forming a metal oxide spacer on the screen oxide, forming a low density ion implantation LDD region, forming a silicon oxide spacer on the side of the metal oxide layer, and performing a high concentration ion implantation to form a source / drain It includes a step.

By applying the above structure, a double spacer of a titanium oxide film and a silicon oxide film is used to improve the dielectric constant of the spacer, thereby reducing the electric field at the drain gate edge.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings in order to facilitate a person skilled in the art to easily carry out the technical idea of the present invention. .

2F is a cross-sectional view illustrating a structure of a MOS transistor according to an embodiment of the present invention.

First, as shown in FIG. 2F, the gate patterns 22a and 23a formed on the semiconductor substrate 21 and the screen oxide film 24 and the screen oxide film 24 formed along the profile of the gate patterns 22a and 23a are formed. LDD region 26 and source / drain regions formed in the formed metal oxide spacer 25, the silicon oxide spacer 26 formed on the metal oxide spacer 25, and the semiconductor substrate 21 on both sides of the gate patterns 22a and 23a. It consists of 28.

2A through 2F are cross-sectional views illustrating a method of manufacturing a MOS transistor according to an exemplary embodiment of the present invention, based on the structure described with reference to FIG. 2F.

As shown in FIG. 2A, a gate oxide film 22 having a thickness of 10 kV to 50 kV is grown on the semiconductor substrate 21 on which the device isolation film (not shown) is formed by thermal oxidation.

As shown in FIG. 2B, a gate conductive film 23 is formed on the gate oxide film 22. At this time, a polysilicon film is used as the gate conductive film 23, and a tungsten film or a tungsten silicide film is used in addition to the polysilicon film.

As shown in FIG. 2C, a photoresist pattern (not shown) for patterning the gate electrode is formed on the gate conductive layer 23a, and the gate conductive layer 23a and the gate are formed by using the photoresist pattern as an etching mask. The oxide film 22a is patterned at the same time.

Subsequently, in order to recover the etch damage of the semiconductor substrate 21 caused by the gate patterning etching process and to prevent the underlying structure from being damaged by the source / drain ion implantation, an oxidation process is performed to screen the semiconductor substrate 21. An oxide film 24 is formed.

As shown in FIG. 2D, a 50 μm thick titanium film is formed on the entire surface including the screen oxide film 24, and rapid thermal annealing is performed at a temperature of 900 ° C. to 1000 ° C. FIG. The rapid annealing process is performed in an oxygen atmosphere to oxidize the titanium film so that the titanium oxide film 25 having a high dielectric constant is formed. At this time, the titanium oxide film 25 has a dielectric constant of 40 to 50.

As shown in FIG. 2E, low concentration LDD ions are implanted to form the LDD region 26 under the gate pattern side surface.

Subsequently, a low dielectric constant (˜3.9) CVD oxide film is deposited on the entire surface including the titanium oxide film 25 and spacer etching is performed to form a silicon oxide spacer 27 on the side of the titanium oxide film 25.

As shown in FIG. 2F, high concentration source / drain ions are implanted to form the source / drain region 28 on the side of the LDD region 27.

As described above, by forming a double LDD spacer of a titanium oxide film having a high dielectric constant and a CVD silicon oxide film, an electric field is pushed from the drain edge to the drain, thereby reducing the short channel effect.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

According to the present invention, by forming the LDD spacer as a dual spacer using a titanium oxide film and a CVD oxide film, it is possible to improve the dielectric constant of the spacer to reduce the electric field of the gate edge to obtain the effect of improving the characteristics of the MOSFET.

In addition, the effect of preventing the short channel effect by improving the hot carrier characteristics and the effect of improving the reliability and driving ability of the device can be obtained.

Claims (7)

Semiconductor substrates; A gate pattern formed on the semiconductor substrate; A screen oxide layer formed along a profile of the semiconductor substrate and the gate pattern; A first spacer formed on a side of the gate pattern and formed of a high dielectric metal oxide film; A second spacer formed on the first spacer on the side of the gate pattern and formed of a silicon oxide film; And Source / drain regions formed in the substrate on both sides of the gate pattern Morse transistor comprising a. The method of claim 1, The first spacer is a MOS transistor composed of a titanium oxide film having a thickness of 50 kHz.  Forming a gate pattern in which a gate insulating film and a gate conductive film are sequentially stacked on the semiconductor substrate; Forming a screen oxide layer by performing gate oxidation on the entire surface including the gate pattern; Forming a metal oxide spacer on a screen oxide layer on the side of the gate pattern; Performing low concentration ion implantation to form an LDD region; Forming a silicon oxide spacer on a side of the metal oxide layer; And High concentration ion implantation to form source / drain MOS transistor manufacturing method comprising a. The method of claim 3, wherein The metal oxide film spacer is a MOS transistor manufacturing method using a titanium oxide film. The method of claim 3, wherein The metal oxide film spacer, Forming a metal film on the screen oxide film; And And oxidizing the metal film by performing a rapid heat treatment in an oxygen atmosphere. The method of claim 3, wherein The metal oxide film spacer is a MOS transistor manufacturing method to form a thickness of 50Å. The method of claim 5, The rapid heat treatment is a MOS transistor manufacturing method performed at a temperature of 900 ℃ ~ 1000 ℃.

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